Silicon carbide heterojunction-based cascode mosfet device

Abstract

A silicon carbide heterojunction-based cascode MOSFET device, comprising a substrate (102). A first epitaxial layer (103) is provided on the substrate (102); a first P-type doped region (105), a second P-type doped region (110), a first well region (104), and a second well region (109) are provided on the first epitaxial layer (103); a second epitaxial layer (108) is provided on the top of the first epitaxial layer (103); a third P-type doped region (116), a fourth P-type doped region (117), a third well region (106), and a fourth well region (111) are provided on the second epitaxial layer (108); a first N-type doped region (107) is provided on the third well region (106), and a second N-type doped region (112) is provided on the fourth well region (111); the first epitaxial layer (103) and the second epitaxial layer (108) form a silicon carbide / silicon heterojunction.

Description

A silicon carbide heterojunction cascode MOSFET device Technical Field

[0001] The present invention relates to the technical field of cascode MOSFET, and in particular to a cascode MOSFET device with a silicon carbide heterojunction. Background Art

[0002] In the development of semiconductor technology, the research and development of power silicon devices has become quite mature. However, due to the limitations of the physical properties of silicon devices themselves, they cannot perform well in some extreme scenarios such as high voltage, high temperature, high efficiency and high power density.

[0003] Based on the above issues, research has found that silicon carbide has better physical properties, is more adaptable to high-temperature operation, has a higher blocking voltage, has lower losses, and has faster switching speeds. Therefore, in the semiconductor field, silicon carbide-based devices have gradually gained attention and development. However, silicon carbide MOSFETs still have some shortcomings, such as low channel mobility, poor gate oxide layer reliability, high body diode conduction voltage drop, bipolar degradation, and poor body diode consistency.

[0004] In order to overcome the above problems, it is necessary to optimize the design of silicon carbide MOSFET to achieve silicon carbide MOSFET with better performance.

[0005] Summary of the Invention

[0006] The purpose of the present invention is to provide a silicon carbide heterojunction cascode MOSFET device, the purpose of which is to optimize the design of silicon carbide MOSFET, overcome the defects of existing silicon carbide MOSFET such as low channel mobility and poor gate oxide layer reliability, and improve the performance of silicon carbide MOSFET.

[0007] The embodiments of the present invention are achieved through the following technical solutions:

[0008] The present invention provides a silicon carbide heterojunction cascode MOSFET device.

[0009] The device comprises a substrate, multiple epitaxial layers, multiple well regions, multiple N-type doped regions, multiple P-type doped regions, a source metal, a gate polysilicon, an inner dielectric layer arranged on the top of the device, and a drain metal arranged on the bottom; the first epitaxial layer and the second epitaxial layer form a silicon carbide / silicon heterojunction;

[0010] A first epitaxial layer is provided on the substrate, a first P-type doping region and a second P-type doping region are provided on the left and right sides of the first epitaxial layer, and a first well region and a second well region are provided on the left and right sides of the first epitaxial layer close to the first P-type doping region and the second P-type doping region respectively;

[0011] A second epitaxial layer is arranged on the top of the first epitaxial layer, and a third P-type doping region and a fourth P-type doping region are arranged on the left and right sides of the second epitaxial layer respectively, and the bottom of the third P-type doping region and the bottom of the fourth P-type doping region are in contact with the top of the first P-type doping region and the top of the second P-type doping region respectively; a third well region is arranged on the left side of the second epitaxial layer, close to the third P-type doping region, and a fourth well region is arranged on the right side of the second epitaxial layer, close to the fourth P-type doping region; a first N-type doping region is arranged on the left side of the third well region, close to the third P-type doping region, and a second N-type doping region is arranged on the right side of the fourth well region, close to the fourth P-type doping region.

[0012] Preferably, the first epitaxial layer is an N-type epitaxial layer made of silicon carbide, and the second epitaxial layer is an N-type epitaxial layer made of silicon.

[0013] Preferably, gate polysilicon and an inner dielectric layer wrapping the gate polysilicon are provided on the first N-type doping region, the second N-type doping region, the third well region, the fourth well region and the second epitaxial layer;

[0014] A source metal is disposed on the first N-type doping region, the second N-type doping region, the first P-type doping region, the second P-type doping region and the inner dielectric layer;

[0015] The drain metal is disposed below the substrate.

[0016] Preferably, the first well region, the second well region, the third well region and the fourth well region are all P-type well regions.

[0017] Preferably, the source metal and the drain metal are made of metal.

[0018] Preferably, the center of the top of the first epitaxial layer is a boss structure, and the left and right sides of the top are recessed structures;

[0019] The first well region and the first P-type doping region are arranged in a recessed structure on the left side of the top of the first epitaxial layer, and the second well region and the second P-type doping region are arranged in a recessed structure on the right side of the top of the first epitaxial layer.

[0020] Preferably, the first P-type doping region, the second P-type doping region, the top of the first well region, the top of the second well region and the top of the mesa structure of the first epitaxial layer are located on the same horizontal line.

[0021] Preferably, the top center of the second epitaxial layer is a boss structure;

[0022] The third P-type doping region is set at the leftmost end of the second epitaxial layer, a recess structure is set between the third P-type doping region and the boss, and the third well region is set in the recess structure; the fourth P-type doping region is set at the optimal end of the second epitaxial layer, a recess structure is set between the fourth P-type doping region and the boss, and the fourth well region is set in the recess structure.

[0023] Preferably, the top right side of the third well region is a boss structure, and the left side is a recessed structure, and the first N-type doped region is arranged in the recessed structure at the top of the third well region;

[0024] The left side of the top of the fourth well region is a boss structure, and the right side is a recessed structure. The second N-type doping region is arranged in the recessed structure at the top of the fourth well region.

[0025] Preferably, the top of the first N-type doping region, the top of the second N-type doping region, the top of the platform structure of the third well region, the top of the platform structure of the fourth well region, the top of the third P-type doping region, and the top of the fourth P-type doping region are located on the same horizontal line. The technical solution of the embodiment of the present invention has at least the following advantages and beneficial effects:

[0026] The present invention improves channel mobility by using a heterojunction silicon MOS channel;

[0027] Compared with the higher barrier height between the gate oxide layer and silicon carbide in traditional devices, the barrier height between the gate oxide layer and the second epitaxial layer of the present invention is reduced, solving the problem of poor reliability of the gate oxide layer;

[0028] The structure of the present invention realizes the series connection of silicon PN junction and silicon carbide JFET, thereby forming a lower barrier height and reducing the on-state voltage drop;

[0029] The present invention reduces the bipolar current of the silicon carbide portion through the design of the structure and material of the second epitaxial layer, thereby solving the problem of bipolar degradation;

[0030] The structure of the present invention can reduce the bipolar current of the silicon carbide part and improve the consistency of the body diode performance;

[0031] The present invention has reasonable design, simple structure, high cost performance and is easy to promote and apply. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0033] FIG1 is a schematic structural diagram of a silicon carbide heterojunction cascode MOSFET device provided by an embodiment of the present invention;

[0034] FIG2 is a schematic diagram of an equivalent circuit of a silicon carbide heterojunction cascode MOSFET device provided by an embodiment of the present invention;

[0035] Icon: 101-drain metal, 102-substrate, 103-first epitaxial layer, 104-first well region, 105-first P-type doped region, 106-third well region, 107-first N-type doped region, 108-second epitaxial layer, 109-second well region, 110-second P-type doped region, 111-fourth well region, 112-second N-type doped region, 113-gate polysilicon, 114-internal dielectric layer, 115-source metal, 116-third P-type doped region, 117-fourth P-type doped region. DETAILED DESCRIPTION

[0036] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. It should be understood that the described embodiments are only a portion of the embodiments of the present invention, not all of them. Generally, the components of the embodiments of the present invention described and illustrated in the drawings herein may be arranged and designed in a variety of different configurations.

[0037] In the description of the present invention, it should be noted that if the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside" and the like appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the accompanying drawings, or is the orientation or position relationship in which the product of the application is usually placed when in use. It is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0038] Example 1

[0039] 1 , this embodiment provides a silicon carbide heterojunction cascode MOSFET device, including a substrate 102, multiple epitaxial layers, multiple well regions, multiple N-type doped regions, multiple P-type doped regions, a source metal 115, a gate polysilicon 113, and an inner dielectric layer 114 disposed at the top of the device, and a drain metal 101 disposed at the bottom; the first epitaxial layer 103 and the second epitaxial layer 108 form a silicon carbide / silicon heterojunction;

[0040] A first epitaxial layer 103 is provided on the substrate 102. A first P-type doping region 105 and a second P-type doping region 110 are provided on the left and right sides of the first epitaxial layer 103. A first well region 104 and a second well region 109 are provided on the left and right sides of the first epitaxial layer 103 close to the first P-type doping region 105 and the second P-type doping region 110, respectively.

[0041] A second epitaxial layer 108 is arranged on the top of the first epitaxial layer 103, and a third P-type doping region 116 and a fourth P-type doping region 117 are arranged on the left and right sides of the second epitaxial layer 108 respectively. The bottom of the third P-type doping region 116 and the bottom of the fourth P-type doping region 117 are in contact with the top of the first P-type doping region 105 and the top of the second P-type doping region 110 respectively; a third well region 106 is arranged on the left side of the second epitaxial layer 108, close to the third P-type doping region 116, and a fourth well region 111 is arranged on the right side of the second epitaxial layer 108, close to the fourth P-type doping region 117; a first N-type doping region 107 is arranged on the left side of the third well region 106, close to the third P-type doping region 116, and a second N-type doping region 112 is arranged on the right side of the fourth well region 111, close to the fourth P-type doping region 117.

[0042] First, as a preferred solution of this embodiment, the first epitaxial layer 103 is an N-type epitaxial layer made of silicon carbide, and the second epitaxial layer 108 is an N-type epitaxial layer made of silicon.

[0043] In addition, a gate polysilicon 113 and an inner dielectric layer 114 wrapping the gate polysilicon 113 are disposed on the first N-type doping region 107 , the second N-type doping region 112 , the third well region 106 , the fourth well region 111 , and the second epitaxial layer 108 ;

[0044] A source metal 115 is disposed on the first N-type doping region 107 , the second N-type doping region 112 , the first P-type doping region 105 , the second P-type doping region 110 and the inner dielectric layer 114 ;

[0045] The drain metal 101 is disposed at the bottom of the substrate 102 .

[0046] On the other hand, the first well region 104 , the second well region 109 , the third well region 106 and the fourth well region 111 are all P-type well regions, which are labeled P-Well in FIG. 1 .

[0047] Furthermore, the gate polysilicon 113 is made of polysilicon.

[0048] Finally, the source metal 115 and the drain metal 101 are made of metal.

[0049] It should be noted that in FIG. 1 , P+ represents a P-type doped region, N+ represents an N-type doped region, Well represents a well region, and P-Well represents a P-type well region, and ILD represents an interlayer dielectric layer.

[0050] In the semiconductor field, conventional silicon devices are limited in semiconductor applications by the physical properties of the silicon devices themselves, making it difficult for them to adapt to high-voltage, high-temperature and other scenarios, and thus difficult to fully exert the full performance of the devices. Silicon carbide MOSFETs with excellent physical properties can greatly improve the above problems.

[0051] Therefore, in order to address its defects, this embodiment is improved based on silicon carbide MOSFET, as follows:

[0052] First, the core of this embodiment lies in the setting of a silicon carbide heterojunction.

[0053] The basic principle of SiC MOSFET can be briefly summarized as follows: the current I through the source and drain is controlled by controlling the gate voltage. SD / I DS However, SiC MOSFETs also have some drawbacks, such as low channel mobility, poor gate oxide layer reliability, high body diode forward voltage drop, bipolar degeneration, and poor body diode consistency.

[0054] See Figure 2 for the equivalent circuit diagram of a silicon carbide MOSFET. The equivalent circuit diagram of this device is equivalent to connecting a SiC JFET and a Si MOSFET together, with the gate of the SiC JFET connected to the source of the Si MOSFET. As can be seen from the figure, the voltage from the gate to the source of the SiC JFET is the same magnitude but opposite in sign to the voltage from the drain to the source of the Si MOSFET, that is: V GS，SiC_JFET =-V DS，Si_MOSFET ;

[0055] When the Si MOSFET is turned on, its voltage V DS，Si_MOSFET Approaching 0V, and then V GS，SiC_JFET It also approaches 0 V. Therefore, since the Si MOSFET is a normally-on device, the SiC JFET is also turned on, and then the entire device is turned on.

[0056] When the device needs to be turned off, a 0V or negative gate voltage is applied, and the Si MOSFET is turned off. DS，Si_MOSFET Once the voltage V DS，Si_MOSFET The value of is higher than the threshold voltage of SiC JFET |V TH，SiC_JFET |, then the SiC JFET turns off, after which V DS，Si_MOSFETIt will not continue to grow.

[0057] In the reverse conduction mode, the current first flows through the body diode of the Si MOSFET, and its knee voltage is 0.7V. DS，Si_MOSFET is about -1V, so V GS，SiC_JFET At approximately +1V, the SiC JFET turns on.

[0058] Based on the above principles:

[0059] First, for traditional SiC MOSFETs, during the process of thermal oxidation of SiC to form silicon dioxide, a high density of interface states is generated at the SiO2 / SiC interface. These interface defects lead to low SiC MOSFET channel mobility. However, these interface defects between SiO2 / Si are significantly reduced. In this embodiment, the heterojunction Si MOSFET channel can improve channel mobility.

[0060] Secondly, the SiC MOSFET gate oxide layer, that is, the silicon carbide / silicon dioxide barrier height between the silicon carbide and the gate oxide layer is low, which makes FN tunneling prone. In this embodiment, due to the use of a silicon carbide heterojunction, the silicon / silicon dioxide barrier height at the gate oxide layer is higher, reducing the risk of FN tunneling.

[0061] Furthermore, since the turn-on voltage drop of the silicon carbide body diode before the improvement was as high as 3V, it would cause a higher loss. It can be seen here that we are equivalent to using Si PN junction and SiC JFET in series to form a lower barrier height. Since the turn-on voltage drop can be reduced to 0.7V, the problem of high body diode conduction voltage drop can be solved and the loss can be reduced.

[0062] Moreover, here, the gate is buried in the inner dielectric layer 114, thereby forming a vertical channel. This design can achieve a higher cell density and further optimize the channel mobility, thereby reducing the on-resistance, and further increasing the switching speed and reducing the switching loss.

[0063] In addition, the energy generated by the recombination of carriers in silicon carbide will cause the BPD defect to expand and form a stacking fault defect. During bipolar operation, the energy released by the recombination of electrons and holes causes the stacking defect to diffuse at the BPD, reducing the current conduction capability. The bipolar current of the silicon carbide part in this embodiment is reduced because, under the design of this embodiment, the holes complete more recombination in the second epitaxial layer 108, which is the silicon part, effectively avoiding the problem of the recombination release stacking and diffusion outside the BPD, thus solving the problem of bipolar degradation.

[0064] Finally, the uneven distribution of BPD defects in the SiC body diode leads to uneven conduction capabilities across different devices, which can easily cause gate resonance. This structure reduces the bipolar current in the SiC portion, improving the consistency of body diode performance and resolving the issue of poor body diode consistency.

[0065] Example 2

[0066] This embodiment is based on the technical solution of Embodiment 1 and further illustrates the related connection structure of the first epitaxial layer 103 .

[0067] In this embodiment, the center of the top of the first epitaxial layer 103 is a convex structure, and the left and right sides of the top are concave structures;

[0068] The first well region 104 and the first P-type doping region 105 are arranged in a recessed structure on the top left side of the first epitaxial layer 103 , and the second well region 109 and the second P-type doping region 110 are arranged in a recessed structure on the top right side of the first epitaxial layer 103 .

[0069] As a further preferred embodiment, the first P-type doped region (105), the second P-type doped region (110), the top of the first well region 104, the top of the second well region 109 and the top of the boss structure of the first epitaxial layer 103 are located on the same horizontal line.

[0070] This embodiment provides a detailed description of the specific arrangement within the first epitaxial layer 103, ensuring the basic internal structure, contact, and connection requirements while achieving a good and neat internal arrangement, making the device structure neater and further ensuring its excellent characteristics.

[0071] Example 3

[0072] This embodiment is based on the technical solution of Implementation 1 and further describes the second epitaxial layer 108 and related connection structures.

[0073] As a preferred solution of this embodiment, the top center of the second epitaxial layer 108 is a boss structure;

[0074] The third P-type doping region 116 is set at the leftmost end of the second epitaxial layer 108, a recess structure is set between the third P-type doping region 116 and the boss, and the third well region 106 is set in the recess structure; the fourth P-type doping region 117 is set at the optimal end of the second epitaxial layer 108, a recess structure is set between the fourth P-type doping region 117 and the boss, and the fourth well region 111 is set in the recess structure.

[0075] Secondly, the top right side of the third well region 106 is a boss structure, and the left side is a recessed structure, and the first N-type doping region 107 is disposed in the recessed structure at the top of the third well region 106;

[0076] The left side of the top of the fourth well region 111 is a boss structure, and the right side is a recess structure. The second N-type doping region 112 is disposed in the recess structure at the top of the fourth well region 111 .

[0077] In addition, the top of the first N-type doping region 107, the top of the second N-type doping region 112, the top of the boss structure of the third well region 106, the top of the boss structure of the fourth well region 111, the top of the third P-type doping region 116 and the top of the fourth P-type doping region 117 are located on the same horizontal line.

[0078] This embodiment provides a detailed description of the second epitaxial layer 108 and related connection structures. Similar to Example 2, the basic internal structure, contact, and connection requirements are guaranteed while achieving a good and neat internal arrangement, making the device structure neater and further ensuring its excellent characteristics.

[0079] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A silicon carbide heterojunction cascode MOSFET device, characterized in that: The device comprises a substrate (102), a plurality of epitaxial layers, a plurality of well regions, a plurality of N-type doped regions, a plurality of P-type doped regions, a source metal (115) arranged on the top of the device, a gate polysilicon (113), an inner dielectric layer (114), and a drain metal (101) arranged on the bottom; the first epitaxial layer (103) and the second epitaxial layer (108) form a silicon carbide / silicon heterojunction; A first epitaxial layer (103) is arranged on the substrate (102); a first P-type doping region (105) and a second P-type doping region (110) are arranged on the left and right sides of the first epitaxial layer (103); and a first well region (104) and a second well region (109) are respectively arranged on the left and right sides of the first epitaxial layer (103) close to the first P-type doping region (105) and the second P-type doping region (110); A second epitaxial layer (108) is arranged on the top of the first epitaxial layer (103); a third P-type doping region (116) and a fourth P-type doping region (117) are arranged on the left and right sides of the second epitaxial layer (108); the bottom of the third P-type doping region (116) and the bottom of the fourth P-type doping region (117) are in contact with the top of the first P-type doping region (105) and the top of the second P-type doping region (110) respectively; the left side of the second epitaxial layer (108) is closely connected to the top of the second P-type doping region (110); A third well region (106) is arranged adjacent to the third P-type doping region (116), and a fourth well region (111) is arranged on the right side of the second epitaxial layer (108) adjacent to the fourth P-type doping region (117); a first N-type doping region (107) is arranged on the left side of the third well region (106) adjacent to the third P-type doping region (116), and a second N-type doping region (112) is arranged on the right side of the fourth well region (111) adjacent to the fourth P-type doping region (117).

2. The silicon carbide heterojunction cascode MOSFET device according to claim 1, characterized in that: The first epitaxial layer (103) is an N-type epitaxial layer made of silicon carbide, and the second epitaxial layer (108) is an N-type epitaxial layer made of silicon.

3. The silicon carbide heterojunction cascode MOSFET device according to claim 1, characterized in that: The gate polysilicon (113) and the inner dielectric layer (114) wrapping the gate polysilicon (113) are arranged on the first N-type doping region (107), the second N-type doping region (112), the third well region (106), the fourth well region (111) and the second epitaxial layer (108); A source metal (115) is disposed on the first N-type doping region (107), the second N-type doping region (112), the first P-type doping region (105), the second P-type doping region (110) and the inner dielectric layer (114); The drain metal (101) is arranged below the substrate (102).

4. The silicon carbide heterojunction cascode MOSFET device according to claim 1, characterized in that: The first well region (104), the second well region (109), the third well region (106) and the fourth well region (111) are all P-type well regions.

5. The silicon carbide heterojunction cascode MOSFET device according to claim 1, characterized in that: The source metal (115) and the drain metal (101) are made of metal.

6. The silicon carbide heterojunction cascode MOSFET device according to claim 1, characterized in that: The center of the top of the first epitaxial layer (103) is a boss structure, and the left and right sides of the top are concave structures; The first well region (104) and the first P-type doped region (105) are arranged in a recessed structure on the left side of the top of the first epitaxial layer (103), and the second well region (109) and the second P-type doped region (110) are arranged in a recessed structure on the right side of the top of the first epitaxial layer (103).

7. The silicon carbide heterojunction cascode MOSFET device according to claim 6, characterized in that: The first P-type doped region (105), the second P-type doped region (110), the top of the first well region (104), the top of the second well region (109) and the top of the boss structure of the first epitaxial layer (103) are located on the same horizontal line.

8. The silicon carbide heterojunction cascode MOSFET device according to claim 1, characterized in that: The top center of the second epitaxial layer (108) is a boss structure; The third P-type doping region (116) is arranged at the leftmost end of the second epitaxial layer (108), a recess structure is arranged between the third P-type doping region (116) and the boss, and the third well region (106) is arranged in the recess structure; the fourth P-type doping region (117) is arranged at the optimal end of the second epitaxial layer (108), a recess structure is arranged between the fourth P-type doping region (117) and the boss, and the fourth well region (111) is arranged in the recess structure.

9. The silicon carbide heterojunction cascode MOSFET device according to claim 8, characterized in that: The top right side of the third well region (106) is a boss structure, and the left side is a recessed structure, and the first N-type doping region (107) is arranged in the recessed structure at the top of the third well region (106); The left side of the top of the fourth well region (111) is a boss structure, and the right side is a recessed structure; the second N-type doping region (112) is arranged in the recessed structure at the top of the fourth well region (111).

10. The silicon carbide heterojunction cascode MOSFET device according to claim 9, characterized in that: The top of the first N-type doping region (107), the top of the second N-type doping region (112), the top of the boss structure of the third well region (106), the top of the boss structure of the fourth well region (111), the top of the third P-type doping region (116) and the top of the fourth P-type doping region (117) are located on the same horizontal line.

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