Repair circuit, repair locking method and memory

Abstract

Embodiments of the present disclosure provide a repair circuit, a repair locking method and a memory. The repair circuit comprises: a clock circuit, used for, on the basis of a reset signal, a repair locking signal and a preset clock signal, generating a target clock signal, wherein when the repair locking signal is in an enabled state, the target clock signal is in an invalid state; and a latch circuit, used for, on the basis of the target clock signal, carrying out sampling processing on a preset address signal when the target clock signal is in a valid state, so that the latch circuit outputs a first address signal, and not carrying out sampling processing when the target clock signal is in the invalid state, so that the output of the latch circuit is in a latched state.

Description

Repair circuits, repair locking methods and memory

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure is based on the Chinese patent application with application number 202310900691.X, application date July 20, 2023, and invention name “Repair Circuit, Repair Locking Method and Memory”, and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby introduced into the present disclosure as a reference. Technical Field

[0003] The present disclosure relates to the field of semiconductor technology, and in particular to a repair circuit, a repair locking method, and a memory. Background Art

[0004] During normal use of a memory, some storage rows and / or columns may fail. In order to extend the life of the memory in the event of a failure of a storage row and / or column, a post-package repair (PPR) method is used to repair the storage rows and / or columns of the memory. Specifically, redundant storage rows and / or columns can be used to replace the failed storage rows and / or columns. The PPR method includes soft post-package repair (SPPR) and hard post-package repair (HPPR), where SPPR is a temporary repair and HPPR is a permanent repair.

[0005] Summary of the Invention

[0006] Embodiments of the present disclosure provide a repair circuit, a repair locking method, and a memory.

[0007] In a first aspect, an embodiment of the present disclosure provides a repair circuit, comprising:

[0008] a clock circuit, configured to receive a reset signal, a repair lock signal, and a preset clock signal, and generate a target clock signal according to the reset signal, the repair lock signal, and the preset clock signal; wherein when the repair lock signal is in an enabled state, the target clock signal is disabled;

[0009] a latch circuit configured to receive the target clock signal, sample a preset address signal according to the target clock signal when the target clock signal is in a valid state, and cause the latch circuit to output a first address signal; and not perform the sampling process when the target clock signal is in an invalid state, causing the output of the latch circuit to be in a latched state;

[0010] Wherein, when in an invalid state, the target clock signal has no level flip; when in a valid state, the target clock signal has a level flip.

[0011] In some embodiments, the clock circuit includes a clock control circuit and a first logic circuit, wherein:

[0012] The clock control circuit is configured to receive the reset signal and the repair lock signal, and generate the clock control signal according to the reset signal and the repair lock signal;

[0013] The first logic circuit is used to receive the clock control signal and the preset clock signal, and generate the target clock signal according to the clock control signal and the preset clock signal; wherein: when the clock control signal is in a disabled state, the preset clock signal is output as the target clock signal; when the clock control signal is in an enabled state, the target clock signal is fixed in an invalid state.

[0014] In some embodiments, the clock control circuit includes a first NOT gate and a latch, and the first logic circuit includes a second NOT gate and a first NOR gate; wherein:

[0015] The input end of the first NOT gate is used to receive the repair lock signal, and the output end of the first NOT gate is connected to the first input end of the latch;

[0016] The second input terminal of the latch is used to receive the reset signal; the output terminal of the latch is connected to the first input terminal of the first NOR gate, and is used to output the clock control signal;

[0017] The input end of the second NOT gate is used to receive the preset clock signal, and the output end of the second NOT gate is connected to the second input end of the first NOR gate;

[0018] The output terminal of the first NOR gate is used to output the target clock signal.

[0019] In some embodiments, the latch includes a first NAND gate and a second NAND gate, wherein:

[0020] The first input terminal of the first NAND gate is connected to the output terminal of the first NAND gate, and the first input terminal of the first NAND gate serves as the first input terminal of the latch; the second input terminal of the first NAND gate is connected to the output terminal of the second NAND gate; the output terminal of the first NAND gate serves as the output terminal of the latch, and is used to output the clock control signal;

[0021] The first input end of the second NAND gate is connected to the output end of the first NAND gate; the second input end of the second NAND gate serves as the second input end of the latch, for receiving the reset signal.

[0022] In some embodiments, the repair circuit further includes an input circuit, an enabling circuit, and a matching circuit, wherein:

[0023] The input circuit is configured to receive an activation signal and a current address signal, and sample the current address signal according to the activation signal to obtain a target address signal;

[0024] The enabling circuit is configured to receive the current address signal, the activation signal, the repair signal, and the target clock signal, sample the current address signal according to the activation signal and the repair signal to obtain an initial enabling signal, and sample and latch the initial enabling signal according to the target clock signal to obtain a target enabling signal;

[0025] The matching circuit is used to receive the target address signal, the first address signal and the target enable signal, compare the target address signal and the first address signal to generate a comparison signal, and perform logical processing on the target enable signal and the comparison signal to generate a match signal.

[0026] In some embodiments, the input circuit includes a first sampling circuit, an input terminal of the first sampling circuit is used to receive the current address signal, and a clock terminal of the first sampling circuit is used to receive the activation signal; wherein:

[0027] The first sampling circuit is configured to sample the current address signal according to the activation signal to generate the target address signal when the activation signal is in an enabled state;

[0028] The target address signal includes an n-bit target address, where n is an integer greater than 0.

[0029] In some embodiments, the enabling circuit includes a second logic circuit, a second sampling circuit, and a third sampling circuit; wherein:

[0030] The second logic circuit is configured to receive the activation signal and the repair signal, perform logic processing on the activation signal and the repair signal, and generate a trigger signal; wherein, when both the activation signal and the repair signal are in an enabled state, the trigger signal is in an enabled state;

[0031] The second sampling circuit is configured to receive the trigger signal and the current address signal, sample the current address signal according to the trigger signal, and generate the initial enable signal;

[0032] The third sampling circuit is configured to receive the target clock signal and the initial enable signal, and to sample and latch the initial enable signal to generate the target enable signal when the target clock signal is in a repair state.

[0033] In some embodiments, the second logic circuit includes a first AND gate; wherein:

[0034] The first input terminal of the first AND gate is used to receive the activation signal;

[0035] The second input terminal of the first AND gate is used to receive the repair signal;

[0036] The output terminal of the first AND gate is connected to the clock terminal of the second sampling circuit for outputting the trigger signal.

[0037] In some embodiments, the matching circuit includes a comparison circuit and a third logic circuit; wherein:

[0038] The comparison circuit is configured to receive the target address signal and the first address signal, compare the target address signal with the first address signal, and generate the comparison signal;

[0039] The third logic circuit is used to receive the target enable signal and the comparison signal, and generate the matching signal according to the comparison signal when the target enable signal is in the enabled state; and fix the matching signal in the disabled state when the target enable signal is in the disabled state.

[0040] In some embodiments, the preset address signal includes an n-bit preset address, the first address signal includes an n-bit first address, the comparison signal includes an n-bit comparison sub-signal, the latch circuit includes n sampling sub-circuits, and the comparison circuit includes n comparison sub-circuits; wherein:

[0041] The i-th sampling sub-circuit is configured to receive the target clock signal and the i-th preset address, sample and latch the i-th preset address according to the target clock signal, and generate the i-th first address;

[0042] The i-th comparison sub-circuit is used to receive the i-th target address and the i-th first address, compare the i-th target address with the i-th first address, and generate an i-th comparison sub-signal, where i is an integer greater than 0 and less than or equal to n.

[0043] In some embodiments, the i-th comparison sub-circuit comprises an i-th XNOR gate; wherein:

[0044] The first input terminal of the i-th XNOR gate is connected to the output terminal of the input circuit, and is used for receiving the i-th target address;

[0045] The second input terminal of the i-th XNOR gate is connected to the output terminal of the i-th sampling sub-circuit, and is used to receive the i-th first address;

[0046] The output terminal of the i-th XNOR gate is used to output the i-th comparison sub-signal.

[0047] In some embodiments, the third logic circuit includes a second AND gate, wherein the second AND gate includes a first input terminal and n second input terminals; wherein:

[0048] The first input terminal of the second AND gate is used to receive the target enable signal;

[0049] The i-th second input terminal of the second AND gate is used to receive the i-th comparison sub-signal;

[0050] The output terminal of the second AND gate is used to output the matching signal.

[0051] In some embodiments, the repair signal includes a soft-encapsulated repair signal; and the preset clock signal is generated according to the repair signal and an initial clock signal.

[0052] In a second aspect, an embodiment of the present disclosure provides a method for repairing a lock, comprising:

[0053] receiving a reset signal, a repair lock signal, and a preset clock signal through a clock circuit, and generating a target clock signal according to the reset signal, the repair lock signal, and the preset clock signal; wherein when the repair lock signal is in an enabled state, the target clock signal is disabled;

[0054] receiving the target clock signal through a latch circuit, sampling a preset address signal according to the target clock signal when the target clock signal is in a valid state, so that the latch circuit outputs a first address signal; and not performing the sampling process when the target clock signal is in an invalid state, so that the output of the latch circuit is in a latched state;

[0055] Wherein, when in an invalid state, the target clock signal has no level flip; when in a valid state, the target clock signal has a level flip.

[0056] In a third aspect, an embodiment of the present disclosure provides a memory comprising a repair circuit as described in any one of the first aspects.

[0057] The present disclosure provides a repair circuit, a repair lock method, and a memory. The repair circuit includes: a clock circuit for receiving a reset signal, a repair lock signal, and a preset clock signal, and generating a target clock signal based on the reset signal, the repair lock signal, and the preset clock signal; wherein, when the repair lock signal is in an enabled state, the target clock signal is disabled; a latch circuit for receiving the target clock signal and, when the target clock signal is in an enabled state, sampling a preset address signal based on the target clock signal, causing the latch circuit to output a first address signal; and, when the target clock signal is in an disabled state, not performing sampling, causing the output of the latch circuit to be in a latched state; wherein, when the target clock signal is in an disabled state, the target clock signal does not undergo a level flip; and when the target clock signal is in an enabled state, the target clock signal undergoes a level flip. In this way, the repair lock signal is used to control the clock circuit to generate the target clock signal. When repair lock is required, the target clock signal is disabled, thereby preventing the latch circuit from sampling and maintaining it in a latched state. Ultimately, the repair lock function is achieved without making significant circuit modifications, meeting standard requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] FIG1 is a schematic diagram of the structure of an SPPR circuit provided by an embodiment of the present disclosure;

[0059] FIG2 is a schematic diagram of the structure of a repair circuit provided by an embodiment of the present disclosure;

[0060] FIG3 is a schematic diagram of the composition structure of another repair circuit provided by an embodiment of the present disclosure;

[0061] FIG4 is a detailed structural diagram of a repair circuit provided by an embodiment of the present disclosure;

[0062] FIG5 is a schematic diagram of a signal timing sequence provided by an embodiment of the present disclosure;

[0063] FIG6 is a flow chart of a repair and undo method provided by an embodiment of the present disclosure;

[0064] FIG7 is a schematic diagram of the composition structure of a memory provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0065] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It should be understood that the specific embodiments described herein are only used to illustrate the relevant disclosure and are not intended to limit the disclosure. It should also be noted that for ease of description, only the portions relevant to the relevant disclosure are shown in the drawings.

[0066] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0067] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0068] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0069] Before further explaining the embodiments of the present disclosure in detail, the nouns and terms involved in the embodiments of the present disclosure are explained first. The nouns and terms involved in the embodiments of the present disclosure are subject to the following interpretations:

[0070] Post Package Repair (PPR)

[0071] Soft Post Package Repair (SPPR);

[0072] Hard Post Package Repair (HPPR);

[0073] Dynamic Random Access Memory (DRAM);

[0074] D flip-flop (DFF);

[0075] Standard (SPEC);

[0076] Activation (ACT);

[0077] Row Address (RA);

[0078] Double Data Rate (DDR).

[0079] Referring to Figure 1 , a schematic diagram illustrating the structure of an SPPR circuit according to an embodiment of the present disclosure is shown. As shown in Figure 1 , the SPPR circuit 10 includes an AND gate A1, a flip-flop DFF_1, a flip-flop DFF_2, a fuse latch X, n fuse latches (fuse latch 0 to fuse latch n-1), n ​​XNOR gates (XNOR gate X0 to XN-1), and an AND gate A2. Where n is an integer greater than 0.

[0080] It should be noted that a memory (such as a DRAM) includes a memory array and a redundant memory array. When a row in the memory array fails, a redundant row in the redundant memory array can be used to replace the failed row and resume operation. This replacement can be non-permanent (SPPR) or permanent (HPPR). In the embodiments of this disclosure, the focus is on SPPR.

[0081] As shown in Figure 1 , fuse latches 0 through n-1 are used to latch the addresses FzRA0 through FzRAn-1 (collectively, FzRA<0:n-1>) of the failed row. Address FzRA<0:n-1> can be sent to fuse latches 0 through n-1 by another circuit or device. Alternatively, as shown in Figure 1 , the input D of each fuse latch is connected to the output of flip-flop DFF_2 . Flip-flop DFF_2 samples the address signal corresponding to the failed row to obtain address FzRA<0:n-1>, which is then sent to fuse latches 0 through n-1 for latching.

[0082] The flip-flop DFF_1 is used to sample the address RA of the accessed row according to the activation signal ACT to obtain n-bit address sampling signals RA0 to RAn-1 (collectively denoted as RA<0:n-1>). The address RA comes from the activation signal ACT, that is, the address RA is the address information carried by the activation signal ACT.

[0083] AND gate A1 performs an AND logic operation on the activation signal ACT and the post-soft package repair signal SPPR. The output signal of AND gate A1 serves as the clock signal for flip-flop DFF_2. DFF_2 samples the address RA and generates the enable signal EN only when both the activation signal ACT and the post-soft package repair signal SPPR are enabled.

[0084] As shown in Figure 1, the input terminal of each fuse latch is represented by D, and the output terminal is represented by Q. Fuse latch X samples the enable signal EN according to the latch clock signal LatClk, generating a repair enable signal FzEN, which is sent to AND gate A2. Fuse latch i-1 samples the address FzRA i-1 according to the latch clock signal LatClk, outputs the sampled signal from the output terminal Q, and sends it to the XNOR gate Xi-1. Here, i is an integer greater than 0 and less than or equal to n. The latch clock signal LatClk is generated based on the post-soft package repair signal SPPR. That is, when the post-soft package repair signal SPPR is enabled, the latch clock signal LatClk is valid, allowing fuse latch X and fuse latches 0 through n-1 to sample the signal received at the input terminal D according to the latch clock signal LatClk.

[0085] The EXCLUSIVE-OR gate Xi-1 compares the address RA i-1 output by the flip-flop DFF_1 with the signal sampled and latched by the fuse latch i-1 from the address FzRA i-1. If the two are the same, the EXCLUSIVE-OR gate Xi-1 outputs a logic 1; if the two are different, the EXCLUSIVE-OR gate Xi-1 outputs a logic 0. The output signal of each EXCLUSIVE-OR gate Xi-1 is transmitted to the AND gate A2, which also receives the address enable signal FzEN output by the fuse latch X.

[0086] Thus, if every FzRA i-1 and RA i-1 match (i.e., the two signals received by each XNOR gate Xi i-1 are identical), the outputs of all n XNOR gates are logic 1, indicating that the row corresponding to address RA is the failed row. Simultaneously, if the signal output by fuse latch X is also logic 1, a repair operation is required. Consequently, the match signal Ma output by AND gate A2 is logic 1, indicating that the redundant row should be used instead of the failed row to ensure normal operation of the memory.

[0087] It should also be noted that the addresses FzRA<0:n-1> of the failed rows latched by Fuse Latch 0 through Fuse Latch n-1 are not fixed but are variable. For example, Fuse Latch 0 through Fuse Latch n-1 latch the address FzRA<0:n-1> corresponding to the first failed row. After the first failed row is repaired, Fuse Latch 0 through Fuse Latch n-1 can also latch the address FzRA<0:n-1> corresponding to the second failed row.

[0088] That is, in the SPPR circuit 10 shown in FIG1 , the SPPR command can be used to generate a latch clock signal LatClk. This latch clock signal LatClk can be sent to the fuse latch of the corresponding memory bank (Bank) to retain the repaired failed row address FzRA 0 to FzRA n-1. Subsequently, when the chip activates the row address, it will be compared with the retained failed row address FzRA 0 to FzRA n-1. If a match is successful, the row decoder will access the redundant row instead of the failed row. In addition, the fuse latch X retains the fuse enable information (EN). Therefore, only when EN = logic 1 is the retained address valid and address matching is performed when activated. Otherwise, the Ma signal will always remain at a low level (logic 0).

[0089] The SPPR Lock SPEC standard was released later than SPPR. How to integrate SPPR lock into SPPR circuits while meeting the standard is a problem that needs to be solved.

[0090] Based on this, an embodiment of the present disclosure provides a repair circuit, comprising: a clock circuit for receiving a reset signal, a repair lock signal, and a preset clock signal, and generating a target clock signal based on the reset signal, the repair lock signal, and the preset clock signal; wherein the target clock signal is in an inactive state while the repair lock signal is in an enabled state; a latch circuit for receiving the target clock signal and, when the target clock signal is in an active state, sampling a preset address signal based on the target clock signal, causing the latch circuit to output a first address signal; and, when the target clock signal is in an inactive state, not performing sampling, causing the output of the latch circuit to be in a latched state; wherein, when the target clock signal is in the inactive state, the target clock signal does not undergo a level flip; and when the target clock signal is in the active state, the target clock signal undergoes a level flip. In this way, the repair lock signal is used to control the clock circuit to generate the target clock signal. When repair lock is required, the target clock signal is in an inactive state, thereby preventing the latch circuit from sampling and maintaining it in a latched state. Ultimately, the repair lock function is achieved without making significant circuit modifications, meeting standard requirements.

[0091] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0092] In one embodiment of the present disclosure, referring to FIG2 , a schematic diagram of the structure of a repair circuit provided by the present disclosure is shown. As shown in FIG2 , the repair circuit 20 includes:

[0093] The clock circuit 21 is configured to receive a reset signal, a repair lock signal, and a preset clock signal, and generate a target clock signal based on the reset signal, the repair lock signal, and the preset clock signal; wherein, when the repair lock signal is enabled, the target clock signal is disabled;

[0094] The latch circuit 22 is configured to receive a target clock signal, sample a preset address signal according to the target clock signal when the target clock signal is in a valid state, and cause the latch circuit 22 to output a first address signal; and not perform sampling when the target clock signal is in an invalid state, causing the output of the latch circuit 22 to be in a latched state.

[0095] When the target clock signal is in an invalid state, there is no level flip in the target clock signal; when the target clock signal is in a valid state, there is a level flip in the target clock signal.

[0096] It should be noted that the repair circuit 20 may be an SPPR circuit, and correspondingly, the repair lock signal is a signal indicating that the SPPR resource is locked (which may be denoted as SPPR Lock CMD). The disclosed embodiment improves the SPPR circuit 10 shown in FIG1 , and adds an SPPR lock function without significantly changing the SPPR circuit 10 to meet the requirements of the standard.

[0097] In this embodiment, SPPR is a method for quickly but temporarily repairing the row address of each bank group (storage structure such as bank group or bank) on a memory device (such as DDR5 DRAM), compared with HPPR, which takes longer but can permanently repair the row address.

[0098] SPPR locking allows SPPR resources to be locked in place, and locking operations can be performed on SPPR resources separately. In this way, the SPPR locking function can lock a specific SPPR resource in its current position and does not allow another SPPR operation or SPPR revocation operation to be performed on the resource. More specifically, as shown in Figure 2, the latch circuit 22 can latch a preset address signal, sample and latch the preset address signal, and generate a first address signal. The preset address signal is the address of the failed row, that is, in the SPPR, the latch circuit 22 is used to latch the address of the failed row; and the preset address signal is not fixed, but variable. For example, the latch circuit 22 latches the preset address signal corresponding to the first failed row and outputs the corresponding first address signal. After the first failed row is repaired, the latch circuit 22 can also latch the preset address signal corresponding to the second failed row and output the corresponding first address signal. The repair lock (mainly referring to SPPR lock in the embodiment of the present disclosure) function is: during the SPPR latching period, the latch circuit 22 only latches a specific preset address signal and outputs the corresponding first address signal, without latching other subsequent address signals.

[0099] To implement the SPPR locking function, as shown in FIG2 , the embodiment of the present disclosure adds a clock circuit 21 to the repair circuit 20, and the clock circuit 21 is connected to the latch circuit 22. The repair lock signal is used to indicate whether the repair circuit 20 has entered the repair lock state. If the repair lock signal is in the enabled state, it indicates that the repair circuit 20 has entered the repair lock state. If the repair lock signal is in the disabled state, it indicates that the repair circuit 20 does not enter the repair lock state and operates normally. The preset clock signal is a clock signal that controls the latch circuit 22 to perform sampling when the repair lock function does not exist, for example: the latch clock signal LatClk in the SPPR circuit 10 shown in FIG1 . The reset signal is used to reset the clock circuit 21 when repair lock is not required.

[0100] It should also be noted that the repair lock signal controls the repair circuit 20 in the following manner: when the repair lock signal is in the non-enabled state, there is no need to perform repair lock, and the preset clock signal is output as the target clock signal; at this time, the level state of the target clock signal will change, and there will be a level flip, so that the latch circuit 22 can sample the preset address signal according to the target clock signal to obtain a first address signal; when the preset address signal changes, the latch circuit 22 can sample the changed preset address signal according to the target clock signal to generate a new first address signal.

[0101] When the repair lock signal is in the enabled state, repair lock needs to be performed, and the new preset address signal is not latched. The preset clock signal has no effect on the target clock signal, and the target clock signal is always in an invalid state; at this time, the level state of the target clock signal is fixed, the level state does not change, and the level flip does not occur, so that the latch circuit 22 cannot sample the preset address signal, and the first address signal it outputs is the state it previously latched. Even if the preset address signal changes, since the target clock signal is in a fixed level state, the latch circuit 22 cannot sample and will not generate a new first address signal, thereby realizing the repair lock function.

[0102] In this way, the embodiment of the present disclosure adds a clock circuit 21 to the SPPR circuit. When the repair lock signal is in the enabled state, the clock circuit 21 controls the target clock signal to be in the invalid state, so that the latch circuit 22 cannot sample the preset address signal according to the target clock signal, thereby realizing the repair lock function without making too many changes to the circuit.

[0103] Based on Figure 2, refer to Figure 3, which shows a schematic diagram of the composition structure of another repair circuit provided by an embodiment of the present disclosure. As shown in Figure 3, in some embodiments, the repair circuit 20 further includes an input circuit 23, an enabling circuit 24 and a matching circuit 25, wherein:

[0104] The input circuit 23 is used to receive the activation signal and the current address signal, and sample the current address signal according to the activation signal to obtain the target address signal;

[0105] The enabling circuit 24 is configured to receive a current address signal, an activation signal, a repair signal, and a target clock signal, sample the current address signal according to the activation signal and the repair signal to obtain an initial enabling signal, and sample and latch the initial enabling signal according to the target clock signal to obtain a target enabling signal;

[0106] The matching circuit 25 is configured to receive the target address signal, the first address signal and the target enable signal, compare the target address signal with the first address signal to generate a comparison signal, and perform logic processing on the target enable signal and the comparison signal to generate a match signal.

[0107] It should be noted that the activation signal is used to activate the corresponding storage address in the memory (such as a storage unit, row, column, memory bank, etc., this embodiment takes a row as an example), and the current address signal is used to locate the storage address. In other words, the activation signal and the current address signal correspond to each other.

[0108] The input circuit 23 is a circuit with sampling and latching functions. When receiving the activation signal and the current address signal, if the activation signal and the current address signal are valid signals, that is, the activation signal and the current address signal can successfully locate the row (or storage row) in the storage array, then the input circuit 23 will sample the current address signal according to the activation signal to obtain the target address signal.

[0109] The activation signal and the current address signal are also transmitted to the enable circuit 24, which also receives the repair signal. In this embodiment, the repair signal can be an SPPR signal. The enable circuit 24 is also a circuit with sampling and latching functions. In this way, when the repair signal is in the enabled state, the repair circuit 20 enters the repair working state. If the activation signal and the current address signal are valid signals, the enable circuit 24 samples the current address signal according to the activation signal to generate an initial enable signal, and the initial enable signal is in the enabled state; further, if the repair lock signal is in the non-enabled state, the target clock signal is in the valid state, and the enable circuit 24 samples and latches the initial enable signal according to the target clock signal to generate a target enable signal in the enabled state and sends it to the matching circuit 25; if the repair lock signal is in the enabled state, the target clock signal is in the invalid state. At this time, the enable circuit 24 cannot sample the initial enable signal, so that the target enable signal will maintain its previous state.

[0110] In this way, on the one hand, the target clock signal is sent to the latch circuit 22 to control whether the preset address signal is sampled and latched, and the latch circuit 22 can be in a latched state when the target clock signal is in an invalid state. Even if the preset address signal changes, the first address signal will not change, thereby realizing the repair latch function; on the other hand, the target clock signal is also sent to the enable circuit 24 to control whether the initial enable signal is sampled and latched. When the target clock signal is in an invalid state, the initial enable signal will not be sampled, so that the target enable signal is fixed in the previous state.

[0111] For the matching circuit 25, when the target clock signal is in the valid state, it compares the first address signal with the target address signal. If the first address signal and the target address signal are the same, the generated comparison signal is at one level, indicating that the row corresponding to the current address signal is the failed row corresponding to the preset address signal. If the first address signal and the target address signal are different, the generated comparison signal is at another level, indicating that the row corresponding to the current address signal is not the failed row. Then, the target enable signal performs logical control. Only when the target enable signal is in the enabled state, the matching signal is output according to the comparison result. Otherwise, the matching signal will maintain a fixed level (disabled state). If the current address signal corresponds to the failed row, the redundant row will replace the failed row to operate. Otherwise, the row corresponding to the current address signal operates normally.

[0112] It should also be noted that in the embodiment of the present disclosure, a high-level logic 1 is used as an enabled state and a low-level logic 0 is used as a disabled state. However, a high-level logic 1 may be used as a disabled state and a low-level logic 0 may be used as an enabled state. This is not limited to the above and is set in combination with the circuit.

[0113] In a specific circuit implementation, see FIG4 , which shows a detailed structural diagram of a repair circuit provided by an embodiment of the present disclosure. As shown in FIG4 , the input circuit 23 includes a first sampling circuit 231 . The input terminal of the first sampling circuit 231 is used to receive the current address signal RA, and the clock terminal of the first sampling circuit 231 is used to receive the activation signal ACT.

[0114] The first sampling circuit 231 is configured to sample the current address signal RA according to the activation signal ACT to generate a target address signal RA<0:n-1> when the activation signal ACT is in an enabled state;

[0115] The target address signal RA<0:n-1> includes an n-bit target address RA i-1, where n is an integer greater than 0, and i is an integer greater than 0 and less than or equal to n.

[0116] It should be noted that in the embodiment of the present disclosure, the first sampling circuit 231 can be implemented by a DFF (or other device with sampling latch and other functions). Therefore, as shown in Figure 4, the first sampling circuit 231 is represented by DFF_1. The input terminal and clock terminal of the first sampling circuit 231 serve as the two input terminals of the input circuit 23, respectively, and the output terminal of the first sampling circuit 231 serves as the output terminal of the input circuit 23.

[0117] Wherein, RA represents the current address signal, and ACT represents the activation signal. When the activation signal ACT is in the enabled state, it indicates that it carries valid address information, that is, the current address signal RA is valid and can indicate a row in the memory array (here, the row address is used as an example; in other embodiments, it can also be a specific memory cell, column address, or even a memory bank, etc.). When the activation signal ACT is switched from the disabled state to the enabled state, a rising edge can be formed to trigger the first sampling circuit 231, so that the first sampling circuit 231 samples the current address signal RA according to the activation signal ACT to obtain the target address signal RA<0:n-1>. The target address signal RA<0:n-1> includes an n-bit target address: RA0 to RAn-1.

[0118] Correspondingly, the current address signal may include an n-bit current address, and the first sampling circuit 231 may include n DFFs, each DFF receiving the activation signal ACT and a current address, performing sampling according to the activation signal ACT and the current address to generate a corresponding target address.

[0119] As shown in FIG4 , the clock circuit 21 includes a clock control circuit 211 and a first logic circuit 212 , wherein:

[0120] The clock control circuit 211 is configured to receive a reset signal Reset_n and a repair lock signal SPPR Lock, and generate a clock control signal Clk Lock according to the reset signal Reset_n and the repair lock signal SPPR Lock;

[0121] The first logic circuit 212 is configured to receive the clock control signal Clk Lock and the preset clock signal Clk1, and generate a target clock signal Clk2 based on the clock control signal Clk Lock and the preset clock signal Clk1. When the clock control signal Clk Lock is in a disabled state, the preset clock signal Clk1 is output as the target clock signal Clk2; when the clock control signal Clk Lock is in an enabled state, the target clock signal Clk2 is disabled.

[0122] It should be noted that, as shown in FIG4 , since this embodiment is mainly for SPPR, the repair lock signal can be recorded as SPPR Lock, Reset_n represents the reset signal, Clk Lock represents the clock control signal, Clk1 represents the preset clock signal, and Clk2 represents the target clock signal.

[0123] When the repair lock signal SPPR Lock is in the enabled state, the clock control circuit 211 latches the state of the repair lock signal SPPR Lock, so that the clock control signal Clk Lock output by the clock control circuit 211 is in the enabled state until the reset signal Reset_n resets the clock control signal Clk Lock to the initial state.

[0124] One input terminal of the first logic circuit 212 is connected to the output terminal of the clock control circuit 211 for receiving the clock control signal Clk Lock. The other input terminal of the first logic circuit 212 receives the preset clock signal Clk1. When the clock control signal Clk Lock is in the disabled state, the state of the latch circuit 22 is not locked. The first logic circuit 212 outputs the preset clock signal Clk1 as the target clock signal Clk2. At this time, if the preset clock signal Clk1 is in the valid state, the target clock signal Clk2 is also in the valid state, so that the latch circuit 22 can normally perform the sampling function according to the target clock signal Clk2. When the clock control signal Clk Lock is in the enabled state, the state of the latch circuit 22 is locked. The first logic circuit 212 blocks the preset clock signal Clk1. At this time, regardless of the state of the preset clock signal Clk1, the target clock signal Clk2 is always in the invalid state. As a result, the latch circuit 22 cannot perform the sampling function according to the target clock signal Clk2 and its state is locked.

[0125] Specifically, as shown in FIG4 , the clock control circuit 211 includes a first NOT gate N1 and a latch LAT, and the first logic circuit 212 includes a second NOT gate N2 and a first NOR gate XO; wherein:

[0126] An input end of the first NOT gate N1 is used to receive a repair lock signal SPPR Lock, and an output end of the first NOT gate N1 is connected to a first input end of the latch LAT;

[0127] The second input terminal of the latch LAT is used to receive the reset signal Reset_n; the output terminal of the latch LAT is connected to the first input terminal of the first NOR gate XO, and is used to output the clock control signal Clk Lock;

[0128] The input end of the second NOT gate N2 is used to receive the preset clock signal Clk1, and the output end of the second NOT gate N2 is connected to the second input end of the first NOR gate XO;

[0129] The output terminal of the first NOR gate XO is used to output the target clock signal Clk2.

[0130] Taking the latch LAT as an example, as shown in FIG4 , the latch LAT includes a first NAND gate NA1 and a second NAND gate NA2 , wherein:

[0131] A first input terminal of the first NAND gate NA1 is connected to an output terminal of the first NOT gate N1, and the first input terminal of the first NAND gate NA1 serves as a first input terminal of the latch LAT; a second input terminal of the first NAND gate NA1 is connected to an output terminal of the second NAND gate NA2; and an output terminal of the first NAND gate NA1 serves as an output terminal of the latch LAT, for outputting a clock control signal Clk Lock;

[0132] A first input terminal of the second NAND gate NA2 is connected to the output terminal of the first NAND gate NA1 ; a second input terminal of the second NAND gate NA2 serves as a second input terminal of the latch LAT, for receiving the reset signal Reset_n.

[0133] It should be noted that in the example shown in FIG4 , the reset signal Reset_n is a signal that is valid at a low level (logic 0). When Reset_n is low, the output of the latch LAT is reset to an initial state. During normal operation of the circuit, Reset_n is high (logic 1).

[0134] During the period when Reset_n is high, if the repair lock signal SPPR Lock is in the enabled state (logic 1), the signal output by the first NOT gate N1 is logic 0, and the signal received by the first input terminal of the latch NA1 is logic 0, so the clock control signal Clk Lock output by the latch LAT is in the enabled state (logic 1). At this time, for the NOR gate XO, one input terminal is connected to the output terminal of the latch LAT, receiving the clock control signal Clk Lock in the enabled state, and its other input terminal is connected to the output terminal of the second NOT gate N2, receiving the inverted signal of the preset clock signal Clk1. Since the clock control signal Clk Lock is logic 1, regardless of the state of the preset clock signal Clk1, the target clock signal Clk2 output by the NOR gate XO is always logic 0 and is in an invalid state.

[0135] During the period when Reset_n is high, if the repair lock signal SPPR Lock is in the disabled state (logic 0), the signal output by the first NOT gate N1 is logic 1, and the signal received at the first input terminal of the latch NA1 is logic 1. The clock control signal output by the latch LAT maintains its previous state until Reset_n becomes low, resetting the clock control signal Clk Lock. In this case, if the clock control signal Clk Lock remains at logic 1, the output of the NOR gate XO is consistent with the description in the previous paragraph; if the clock control signal Clk Lock remains at logic 0, the target clock signal Clk2 output by the NOR gate XO has the opposite level state of the signal received at its second input terminal, that is, the same level state as the preset clock signal Clk1.

[0136] In this embodiment, the preset clock signal Clk1 can be generated by performing a logical operation on the repair signal SPPR and the initial clock signal. Here, the initial clock signal can be a system clock or other signal, and the preset clock signal Clk1 can be generated by performing a logical AND operation on the repair signal SPPR and the initial clock signal. Therefore, the preset clock signal Clk1 can also be referred to as SPPR Clk. When the repair signal SPPR is enabled, the preset clock signal Clk1 generates a short pulse, which serves as the sampling clock for the latch circuit 22 and the enable circuit 24.

[0137] It should also be noted that the first logic circuit 212 can also be implemented using a third NOT gate and a third AND gate. In this case, the third NOT gate is connected to the output of the clock control circuit 211, and the output of the third NOT gate is connected to the first input of the third AND gate. The second input of the third AND gate is used to receive the preset clock signal Clk1, and the output of the third AND gate is used to output the target clock signal Clk2. This can also achieve the same functions as the first logic circuit 212 shown in FIG. A detailed description thereof will not be repeated here.

[0138] In this way, when the repair circuit 20 is performing a repair operation, if it is necessary to enter the repair lock state, it is only necessary to enable the repair lock signal SPPR Lock. The clock control circuit 211 will latch the enable state, so that the clock control signal Clk Lock is enabled, and then control the target clock signal Clk2 to be in an invalid state. As a result, the enabling circuit 24 and the latch circuit 22 cannot perform the sampling operation, and the SPPR lock is achieved until the reset signal Reset_n resets the clock control signal Clk Lock.

[0139] As shown in FIG4 , the enabling circuit 24 includes a second logic circuit 241 , a second sampling circuit 242 , and a third sampling circuit 243 ; wherein:

[0140] The second logic circuit 241 is configured to receive the activation signal ACT and the repair signal SPPR, perform logic processing on the activation signal ACT and the repair signal SPPR, and generate a trigger signal; wherein, when both the activation signal ACT and the repair signal SPPR are in an enabled state, the trigger signal is in an enabled state;

[0141] The second sampling circuit 242 is configured to receive a trigger signal and a current address signal RA, sample the current address signal RA according to the trigger signal, and generate an initial enable signal EN;

[0142] The third sampling circuit 243 is configured to receive the target clock signal Clk2 and the initial enable signal EN, and when the target clock signal Clk2 is in an active state, sample and latch the initial enable signal EN to generate a target enable signal FzEN.

[0143] It should be noted that, as shown in FIG4 , in the embodiment of the present disclosure, the second sampling circuit 242 can be implemented by a DFF (or other device with sampling and latching functions), and the third sampling circuit 243 is a circuit with sampling and latching functions. The third sampling circuit 243 samples and latches the initial enable signal EN according to the target clock signal Clk2 to obtain the target enable signal FzEN. The third sampling circuit 243 can be implemented by a fuse latch, etc., and the repair signal can be a repair signal after soft packaging. Therefore, as shown in FIG4 , the second sampling circuit 242 is represented by DFF_2, the third sampling circuit 243 is represented by fuse latch X, the repair signal is represented by SPPR, EN represents the initial enable signal, and FzEN represents the target enable signal.

[0144] Specifically, as shown in FIG4 , the second logic circuit 241 includes a first AND gate A1 ; wherein:

[0145] The first input terminal of the first AND gate A1 is used to receive the activation signal ACT;

[0146] The second input terminal of the first AND gate A1 is used to receive the repair signal SPPR;

[0147] The output terminal of the first AND gate A1 is connected to the clock terminal of the second sampling circuit 242 for outputting a trigger signal.

[0148] It should be noted that, as shown in FIG4 , the first input terminal and the second input terminal of the first AND gate A1 and the clock terminal of the third sampling circuit 243 serve as the three input terminals of the enabling circuit 24 , and the output terminal of the third sampling circuit 243 serves as the output terminal of the enabling circuit 24 .

[0149] The second logic circuit 241 is used to perform an AND logic operation on the activation signal ACT and the repair signal SPPR. The second logic circuit 241 can be implemented by an AND gate A1. In this way, when the activation signal ACT and the repair signal SPPR are both in the enabled state (logic 1), the trigger signal output by the first AND gate A1 is also in the enabled state; otherwise, the trigger signal is in the disabled state.

[0150] When the trigger signal transitions from the disabled state to the enabled state, a rising edge is generated, triggering the second sampling circuit 242. The second sampling circuit 242 can then sample and latch the current address signal RA according to the trigger signal, obtaining an initial enable signal EN and sending it to the third sampling circuit 243. Here, when the second sampling circuit 242 is sampling, if the current address signal RA can effectively indicate a row in the memory array, the second sampling circuit 242 can output the initial enable signal EN in the enabled state; otherwise, the initial enable signal EN is in the disabled state.

[0151] The input terminal D of the fuse latch X is connected to the output terminal of DFF_2 to receive the initial enable signal EN. The clock terminal of the fuse latch X is connected to the output terminal of the clock circuit 21 (i.e., the output terminal of the first NOR gate XO) to receive the target clock signal Clk2. Thus, during the SPPR lock period, the target clock signal Clk2 is in an invalid state, so the fuse latch X cannot sample the initial enable signal EN. The target enable signal FzEN will maintain the state before the target clock signal Clk2 became invalid.

[0152] As shown in FIG4 , the matching circuit 25 includes a comparison circuit 251 and a third logic circuit 252 .

[0153] The comparison circuit 251 is configured to receive the target address signal RA<0:n-1> and the first address signal FA<0:n-1>, compare the target address signal RA<0:n-1> with the first address signal FA<0:n-1>, and generate a comparison signal Com<0:n-1>.

[0154] The third logic circuit 252 is configured to receive the target enable signal FzEN and the comparison signal Com<0:n-1>, and to generate a match signal Ma according to the comparison signal Com<0:n-1> when the target enable signal FzEN is in the enabled state; and to fix the match signal Ma in the disabled state when the target enable signal FzEN is in the disabled state.

[0155] It should be noted that the target enable signal FzEN is used to control whether the match signal Ma is generated based on the comparison signal Com<0:n-1>. That is, when the target enable signal FzEN is in the enabled state, the repair circuit 20 performs the repair operation normally. If the target address signal RA<0:n-1> and the first address signal FA<0:n-1> are the same, indicating that the row corresponding to the current address signal RA is the failed row corresponding to the preset address signal FzRA<0:n-1>, the match signal Ma is enabled, indicating that the redundant row is used to replace the failed row. If the target address signal RA<0:n-1> and the first address signal FA<0:n-1> are different, indicating that the row corresponding to the current address signal RA is not the failed row corresponding to the preset address signal FzRA<0:n-1>, the match signal Ma is disabled, indicating that the row corresponding to the current address signal RA is operating normally.

[0156] When the target enable signal FzEN is in the disabled state, no matter what the comparison result between the target address signal RA<0:n-1> and the first address signal FA<0:n-1> is, the match signal Ma is in the disabled state, and the repair circuit 20 does not perform the repair operation.

[0157] As shown in FIG4 , the latch circuit 22 and the comparison circuit 251 include the preset address signal FzRA<0:n-1> including an n-bit preset address FzRA i-1, the first address signal FA<0:n-1> including an n-bit first address FA i-1, and the comparison signal Com<0:n-1> including an n-bit comparison sub-signal Com i-1. The latch circuit 22 includes n sampling sub-circuits 221, and the comparison circuit 251 includes n comparison sub-circuits 2511.

[0158] The i-th sampling sub-circuit 221 is configured to receive the target clock signal Clk2 and the i-th preset address FzRA i-1, sample and latch the i-th preset address FzRA i-1 according to the target clock signal Clk2, and generate the i-th first address FA i-1;

[0159] The i-th comparison sub-circuit 2511 is used to receive the i-th target address RA i-1 and the i-th first address FA i-1, compare the i-th target address RA i-1 with the i-th first address FA i-1, and generate the i-th comparison sub-signal Com i-1, where i is an integer greater than 0 and less than or equal to n.

[0160] It should be noted that, as shown in Figure 4, the sampling sub-circuit 221 is a circuit with sampling and latching functions. The input terminal D of the i-th sampling sub-circuit 221 receives the i-th preset address FzRA i-1, the clock terminal of each sampling sub-circuit 221 receives the target clock signal Clk2, and the output terminal Q of the i-th sampling sub-circuit 221 outputs the i-th first address FA i-1.

[0161] The i-th sampling subcircuit 221 samples and latches the corresponding i-th preset address FzRA i-1 according to the target clock signal Clk2, thereby obtaining the corresponding i-th first address FA i-1. The sampling subcircuit 221 may be a fuse latch. In FIG4 , the fuse latch in the i-th sampling subcircuit 221 is denoted as fuse latch i-1, and the n fuse latches in the latch circuit 22 are denoted as fuse latch 0 through fuse latch n-1, respectively.

[0162] The comparison sub-circuit 2511 is a circuit with a comparison function. The i-th comparison sub-circuit 2511 receives the i-th target address RA i-1 and the i-th first address FA i-1. When the i-th target address RA i-1 and the i-th first address FA i-1 are the same, the comparison sub-signal Com i-1 output by the i-th comparison sub-circuit 2511 is a first value. When the i-th target address RA i-1 and the i-th first address FA i-1 are different, the comparison sub-signal Com i-1 output by the i-th comparison sub-circuit 2511 is a second value.

[0163] The first value may be a high-level logic 1, and the second value may be a low-level logic 0; or the first value may be a low-level logic 0, and the second value may be a high-level logic 1, which is not specifically limited.

[0164] As shown in FIG4 , for the comparison circuit 251 and the third logic circuit 252 , in one implementation, the i-th comparison sub-circuit 2511 includes the i-th XNOR gate Xi-1; wherein:

[0165] The first input terminal of the i-th XNOR gate Xi-1 is connected to the output terminal of the input circuit 23 for receiving the i-th target address RA i-1;

[0166] The second input terminal of the i-th XNOR gate Xi-1 is connected to the output terminal of the i-th sampling sub-circuit 221, and is used to receive the i-th first address FA i-1;

[0167] The output terminal of the i-th XNOR gate Xi-1 is used to output the i-th comparison sub-signal Com i-1.

[0168] The third logic circuit 252 includes a second AND gate A2, which includes a first input terminal and n second input terminals; wherein:

[0169] The first input terminal of the second AND gate A2 is used to receive the target enable signal FzEN;

[0170] The i-th second input terminal of the second AND gate A2 is used to receive the i-th comparison sub-signal Com i-1;

[0171] The output terminal of the second AND gate A2 is used to output a matching signal Ma.

[0172] It should be noted that, as shown in FIG4 , taking the first sampling sub-circuit 221 and the first comparison sub-circuit 2511 as an example, the output terminal Q of the fuse latch 0 is connected to the second input terminal of the X-OR gate X0, and the first input terminal of the X-OR gate X0 is connected to the output terminal of the input circuit 23. Thus, the first input terminal and the second input terminal of the X-OR gate X0 receive the first target address RA0 and the first first address FA0, respectively. If the first first address FA0 and the first target address RA0 are the same, the first comparison sub-signal Com0 output by the X-OR gate X0 is logic 1. If the first first address RA10 and the first target address RA0 are different, the first comparison sub-signal Com0 output by the X-OR gate X0 is logic 0.

[0173] The same applies to the remaining sampling sub-circuit 221 and comparison sub-circuit 2511 , which will not be described in detail here.

[0174] It should also be noted that, for the comparison circuit 251 and the third logic circuit 252, in another implementation, the i-th comparison sub-circuit includes the i-th XOR gate; wherein:

[0175] A first input terminal of the i-th XOR gate is connected to the output terminal of the input circuit for receiving the i-th target address;

[0176] The second input terminal of the i-th XOR gate is connected to the output terminal of the i-th sampling sub-circuit, and is used to receive the i-th first address;

[0177] The output terminal of the i-th XOR gate is used to output the i-th comparison sub-signal.

[0178] The third logic circuit includes a third NAND gate, and the third NAND gate includes a first input terminal and n second input terminals; wherein:

[0179] The first input terminal of the third NAND gate is used to receive the target enable signal;

[0180] The i-th second input terminal of the third NAND gate is used to receive the i-th comparison sub-signal;

[0181] The output terminal of the third NAND gate is used for outputting a matching signal.

[0182] It should be noted that the comparison sub-circuit can also be implemented by an XOR gate. In this case, the third logic circuit is implemented by a NAND gate, which can also achieve the same function as FIG4 , and will not be described in detail here.

[0183] Based on the circuit shown in FIG4 , refer to FIG5 , which shows a signal timing diagram provided by an embodiment of the present disclosure. As shown in FIG5 , a high-level logic 1 represents an enabled state, and a low-level logic 2 represents a disabled state. During the period when the repair signal SPPR is in the enabled state, after the repair lock signal SPPR Lock becomes the enabled state, the enabled state of the repair lock signal SPPR Lock is latched. Thus, after the repair lock signal SPPR Lock becomes the enabled state and before the reset signal Reset_n becomes the low-level state to reset the circuit (due to the influence of the device, there is a certain delay), the clock control signal Clk Lock is in the enabled state. During this period, the preset clock signal Clk1 is in the invalid state, and the target clock signal Clk2 is also in the invalid state (it can be understood that since the clock control signal Clk Lock is in the enabled state, even if the preset clock signal Clk1 is in the valid state, the target clock signal Clk2 is still in the invalid state). Therefore, the address signal latched by the latch circuit 22 is the first address signal Pre FA<0:n-1> obtained by sampling and latching the previous preset address signal; after the circuit is reset, and the repair lock signal SPPR Lock becomes the enabled state and before the reset signal Reset_n becomes the low-level state to reset the circuit, there is a certain delay. Lock is in the disabled state, and the circuit performs the repair operation normally. After the rising edge of the preset clock signal Clk1 arrives, the target clock signal Clk2 is correspondingly in the valid state, and the latch circuit 22 samples and latches the new preset address signal to obtain a new first address signal FA<0:n-1> (due to the influence of the device, there is a certain delay).

[0184] 5 , between the clock control signal Clk Lock becoming enabled and the rising edge of the preset clock signal Clk1 , the target enable signal FzEN is in a disabled state, so that the matching signal Ma is fixed in a disabled state.

[0185] The simulation results show that the repair circuit 20 can realize the repair operation and the repair locking function.

[0186] In short, the disclosed embodiments relate to DRAM, and more specifically, to SPPR design. Using this solution, SPPR lock can be applied to existing DDR5 products. Since SPPR Lock SPEC was released later than SPPR, it was necessary to add this new functionality to the existing SPPR functionality without making too many structural and logical changes that would affect the existing SPPR. This solution introduces a method for implementing the SPPR lock functionality and adapting it to current SPPR designs.

[0187] The disclosed embodiment combines SPPR with SPPR lock to implement a "lock" function without making too many changes to the current design, thereby reducing the risk of changes and resource consumption. Specifically: on the one hand, the repair signal SPPR and the repair lock signal SPPR Lock are combined to generate the target clock signal Clk2; on the other hand, when performing SPPR lock, "Clk Lock" is latched to a high level to block subsequent target clock signals Clk2 until reset by the reset signal Reset_n. This solution introduces a simple but efficient design to implement the SPPR lock function of DDR5, which can meet SPEC requirements with limited circuit implementation, thereby reducing design time and size costs.

[0188] In another embodiment of the present disclosure, referring to FIG6 , a flowchart of a method for repairing a lock provided by an embodiment of the present disclosure is shown. As shown in FIG6 , the method may include:

[0189] S601: Receive a reset signal, a repair lock signal and a preset clock signal through a clock circuit, and generate a target clock signal according to the reset signal, the repair lock signal and the preset clock signal; wherein, when the repair lock signal is in an enabled state, the target clock signal is disabled.

[0190] S602: Receive a target clock signal through a latch circuit, and when the target clock signal is in a valid state, sample the preset address signal according to the target clock signal, so that the latch circuit outputs a first address signal; and when the target clock signal is in an invalid state, do not perform sampling processing, so that the output of the latch circuit is in a latched state.

[0191] When the target clock signal is in an invalid state, there is no level flip in the target clock signal; when the target clock signal is in a valid state, there is a level flip in the target clock signal.

[0192] It should be noted that the repair locking method provided in the embodiment of the present disclosure is applied to the repair circuit 20 in the aforementioned embodiment. For details not disclosed in this embodiment, please refer to the description of the aforementioned embodiment for understanding, and no further details will be given here.

[0193] In another embodiment of the present disclosure, referring to Figure 7, a schematic diagram of the composition structure of a memory provided by an embodiment of the present disclosure is shown. As shown in Figure 7, the memory 70 at least includes the repair circuit 20 in the aforementioned embodiment.

[0194] It should be noted that the memory 70 can be a semiconductor memory such as DRAM. For DRAM, it can not only comply with memory specifications such as DDR, DDR2, DDR3, DDR4, DDR5, DDR6, but also comply with memory specifications such as LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5, LPDDR6, etc., without any limitation here.

[0195] Since the memory 70 includes the repair circuit 20, it can implement a repair locking function, meeting standard requirements.

[0196] The above description is merely a preferred embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure.

[0197] It should be noted that, in this disclosure, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0198] The serial numbers of the above-mentioned embodiments of the present disclosure are for description only and do not represent the advantages or disadvantages of the embodiments.

[0199] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0200] The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0201] The features disclosed in several method or device embodiments provided in this disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0202] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims. Industrial Applicability

[0203] The disclosed embodiment utilizes a repair lock signal to control a clock circuit to generate a target clock signal. When repair lock is required, the target clock signal is placed in an invalid state, so that the latch circuit cannot perform sampling and remains in a latched state. Ultimately, the repair lock function is achieved without making too many changes to the circuit, thereby meeting the requirements of the standard.

Claims

1. A repair circuit (20), comprising: A clock circuit (21) is used to receive a reset signal (Reset_n), a repair lock signal (SPPR Lock) and a preset clock signal (Clk1), and generate a target clock signal (Clk2) according to the reset signal (Reset_n), the repair lock signal (SPPR Lock) and the preset clock signal (Clk1); wherein when the repair lock signal (SPPR Lock) is in an enabled state, the target clock signal (Clk2) is in an invalid state; A latch circuit (22) is used to receive the target clock signal (Clk2), and when the target clock signal (Clk2) is in a valid state, perform sampling processing on a preset address signal (FzRA<0:n-1>) according to the target clock signal (Clk2), so that the latch circuit (22) outputs a first address signal (FA<0:n-1>); and when the target clock signal (Clk2) is in an invalid state, do not perform the sampling processing, so that the output of the latch circuit (22) is in a latched state; When in an invalid state, the target clock signal (Clk2) has no level flip; when in a valid state, the target clock signal (Clk2) has a level flip.

2. The repair circuit (20) according to claim 1, wherein: The clock circuit (21) comprises a clock control circuit (211) and a first logic circuit (212), wherein: The clock control circuit (211) is used to receive the reset signal (Reset_n) and the repair lock signal (SPPR Lock), and generate a clock control signal (Clk Lock) according to the reset signal (Reset_n) and the repair lock signal (SPPR Lock); The first logic circuit (212) is used to receive the clock control signal (Clk Lock) and the preset clock signal (Clk1), and generate the target clock signal (Clk2) according to the clock control signal (Clk Lock) and the preset clock signal (Clk1); wherein: when the clock control signal (Clk Lock) is in a disabled state, the preset clock signal (Clk1) is output as the target clock signal (Clk2); and when the clock control signal (Clk Lock) is in an enabled state, the target clock signal (Clk2) is fixed in an invalid state.

3. The repair circuit (20) according to claim 2, wherein: The clock control circuit (211) comprises a first NOT gate (N1) and a latch (LAT), and the first logic circuit (212) comprises a second NOT gate (N2) and a first NOR gate (XO); wherein: The input end of the first NOT gate (N1) is used to receive the repair lock signal (SPPR Lock), and the output end of the first NOT gate (N1) is connected to the first input end of the latch (LAT); The second input end of the latch (LAT) is used to receive the reset signal (Reset_n); the output end of the latch (LAT) is connected to the first input end of the first NOR gate (XO) to output the clock control signal (Clk Lock); The input end of the second NOT gate (N2) is used to receive the preset clock signal (Clk1), and the output end of the second NOT gate (N2) is connected to the second input end of the first NOR gate (XO); The output terminal of the first NOR gate (XO) is used to output the target clock signal (Clk2).

4. The repair circuit (20) according to claim 3, wherein: The latch (LAT) comprises a first NAND gate (NA1) and a second NAND gate (NA2), wherein: The first input end of the first NAND gate (NA1) is connected to the output end of the first NOT gate (N1), and the first input end of the first NAND gate (NA1) serves as the first input end of the latch (LAT); The second input end of the first NAND gate (NA1) is connected to the output end of the second NAND gate (NA2); the output end of the first NAND gate (NA1) serves as the output end of the latch (LAT) for outputting the clock control signal (Clk Lock); The first input end of the second NAND gate (NA2) is connected to the output end of the first NAND gate (NA1); the second input end of the second NAND gate (NA2) serves as the second input end of the latch (LAT) for receiving the reset signal (Reset_n).

5. The repair circuit (20) according to any one of claims 1 to 4, wherein: The repair circuit (20) further comprises an input circuit (23), an enabling circuit (24) and a matching circuit (25), wherein: The input circuit (23) is used to receive an activation signal (ACT) and a current address signal (RA), and to sample the current address signal (RA) according to the activation signal (ACT) to obtain a target address signal (RA<0:n-1>); The enabling circuit (24) is used to receive the current address signal (RA), the activation signal (ACT), the repair signal (SPPR) and the target clock signal (Clk2), sample the current address signal (RA) according to the activation signal (ACT) and the repair signal (SPPR) to obtain an initial enabling signal (EN), sample and latch the initial enabling signal (EN) according to the target clock signal (Clk2) to obtain a target enabling signal (FzEN); The matching circuit (25) is used to receive the target address signal (RA<0:n-1>), the first address signal (FA<0:n-1>) and the target enable signal (FzEN), compare the target address signal (RA<0:n-1>) and the first address signal (FA<0:n-1>) to generate a comparison signal (Com<0:n-1>), and perform logic processing on the target enable signal (FzEN) and the comparison signal (Com<0:n-1>) to generate a match signal (Ma).

6. The repair circuit (20) according to claim 5, wherein: The input circuit (23) comprises a first sampling circuit (231), the input end of the first sampling circuit (231) is used to receive the current address signal (RA), and the clock end of the first sampling circuit (231) is used to receive the activation signal (ACT); wherein: The first sampling circuit (231) is used for sampling the current address signal (RA) according to the activation signal (ACT) to generate the target address signal (RA<0:n-1>) when the activation signal (ACT) is in an enabled state; The target address signal (RA<0:n-1>) includes an n-bit target address, where n is an integer greater than 0.

7. The repair circuit (20) according to claim 5 or 6, wherein: The enabling circuit (24) comprises a second logic circuit (241), a second sampling circuit (242) and a third sampling circuit (243); wherein: The second logic circuit (241) is used to receive the activation signal (ACT) and the repair signal (SPPR), perform logic processing on the activation signal (ACT) and the repair signal (SPPR), and generate a trigger signal; wherein, when the activation signal (ACT) and the repair signal (SPPR) are both in an enabled state, the trigger signal is in an enabled state; The second sampling circuit (242) is used to receive the trigger signal and the current address signal (RA), sample the current address signal (RA) according to the trigger signal, and generate the initial enable signal (EN); The third sampling circuit (243) is used to receive the target clock signal (Clk2) and the initial enable signal (EN), and when the target clock signal (Clk2) is in a repair state, The initial enable signal (EN) is sampled and latched to generate the target enable signal (FzEN).

8. The repair circuit (20) according to claim 7, wherein: The second logic circuit (241) comprises a first AND gate (A1); wherein: The first input terminal of the first AND gate (A1) is used to receive the activation signal (ACT); The second input terminal of the first AND gate (A1) is used to receive the repair signal (SPPR); The output end of the first AND gate (A1) is connected to the clock end of the second sampling circuit (242) for outputting the trigger signal.

9. The repair circuit (20) according to any one of claims 5 to 8, wherein: The matching circuit (25) comprises a comparison circuit (251) and a third logic circuit (252); wherein: The comparison circuit (251) is used to receive the target address signal (RA<0:n-1>) and the first address signal (FA<0:n-1>), compare the target address signal (RA<0:n-1>) and the first address signal (FA<0:n-1>), and generate the comparison signal (Com<0:n-1>); The third logic circuit (252) is used to receive the target enable signal (FzEN) and the comparison signal (Com<0:n-1>), and when the target enable signal (FzEN) is in an enabled state, generate the match signal (Ma) according to the comparison signal (Com<0:n-1>); when the target enable signal (FzEN) is in a disabled state, fix the match signal (Ma) in a disabled state.

10. The repair circuit (20) according to claim 9, wherein: The preset address signal (FzRA<0:n-1>) includes an n-bit preset address (FzRA i-1), the first address signal (FA<0:n-1>) includes an n-bit first address (FA i-1), the comparison signal (Com<0:n-1>) includes an n-bit comparison sub-signal (Com i-1), the latch circuit (22) includes n sampling sub-circuits (221), and the comparison circuit (251) includes n comparison sub-circuits (2511); wherein: The i-th sampling subcircuit (221) is used to receive the target clock signal (Clk2) and the i-th preset address (FzRA i-1), sample and latch the i-th preset address (FzRA i-1) according to the target clock signal (Clk2), and generate the i-th first address (FA i-1); The i-th comparison sub-circuit (2511) is used to receive the i-th target address (RA i-1) and the i-th first address (FA i-1), compare the i-th target address (RA i-1) with the i-th first address (FA i-1), and generate the i-th comparison sub-signal (Com i-1), where i is an integer greater than 0 and less than or equal to n.

11. The repair circuit (20) according to claim 10, wherein: The i-th comparison subcircuit (2511) comprises an i-th XNOR gate (X i-1); wherein: The first input terminal of the i-th XNOR gate (X i-1) is connected to the output terminal of the input circuit (23) and is used to receive the i-th target address (RA i-1); The second input end of the i-th XNOR gate (X i-1) is connected to the output end of the i-th sampling subcircuit (221) for receiving the i-th first address (FA i-1); The output terminal of the i-th XNOR gate (X i-1) is used to output the i-th comparison sub-signal (Com i-1).

12. The repair circuit (20) according to claim 10 or 11, wherein: The third logic circuit (252) comprises a second AND gate (A2), wherein the second AND gate (A2) comprises a first input terminal and n second input terminals; wherein: The first input terminal of the second AND gate (A2) is used to receive the target enable signal (FzEN); The i-th second input terminal of the second AND gate (A2) is used to receive the i-th comparison sub-signal (Com i-1); The output end of the second AND gate (A2) is used to output the matching signal (Ma).

13. The repair circuit (20) according to any one of claims 5 to 12, wherein: The repair signal (SPPR) includes a soft-packaged repair signal; the preset clock signal (Clk1) is generated according to the repair signal (SPPR) and an initial clock signal.

14. A method for repairing a lock, comprising: Receiving a reset signal (Reset_n), a repair lock signal (SPPR Lock) and a preset clock signal (Clk1) through a clock circuit (21), and generating a target clock signal (Clk2) according to the reset signal (Reset_n), the repair lock signal (SPPR Lock) and the preset clock signal (Clk1); wherein when the repair lock signal (SPPR Lock) is in an enabled state, the target clock signal (Clk2) is in an invalid state; The target clock signal (Clk2) is received through a latch circuit (22); when the target clock signal (Clk2) is in a valid state, a preset address signal (FzRA<0:n-1>) is sampled according to the target clock signal (Clk2), so that the latch circuit (22) outputs a first address signal (FA<0:n-1>); and when the target clock signal (Clk2) is in an invalid state, the sampling process is not performed, so that the output of the latch circuit (22) is in a latched state; When in an invalid state, the target clock signal (Clk2) has no level flip; when in a valid state, the target clock signal (Clk2) has a level flip.

15. A memory (70) comprising the repair circuit (20) according to any one of claims 1 to 13.

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