Light detection device

Abstract

[Problem] To provide a light detection device capable of suppressing an increase in dark current. [Solution] A light detection device according to one embodiment of the present disclosure comprises: a first compound semiconductor layer (214) that photoelectrically converts incident light; a second compound semiconductor layer (213) that is laminated on the first compound semiconductor layer (214); and a third compound semiconductor layer (212) that faces the first compound semiconductor layer (214) across the second compound semiconductor layer (213). The composition of the second compound semiconductor layer (213) is different from the compositions of the first compound semiconductor layer (214) and the third compound semiconductor layer (212). The concentration of first conductivity type impurities contained in the third compound semiconductor layer (212) is higher than the concentration of first conductivity type impurities contained in the first compound semiconductor layer (214).

Description

Photodetector

[0001] The present disclosure relates to a light detection device.

[0002] Photodetectors using compound semiconductors such as InGaAs for the photoelectric conversion section are known. During the manufacturing process of such photodetectors, contaminants made of metal elements may adhere to the compound semiconductor. In this case, if the contaminants diffuse into the compound semiconductor during the heat treatment process, the dark current increases.

[0003] Japanese Patent Application Laid-Open No. 2020-113809

[0004] The present disclosure provides a photodetector capable of suppressing an increase in dark current.

[0005] A photodetector according to an embodiment of the present disclosure includes a first compound semiconductor layer that photoelectrically converts incident light, a second compound semiconductor layer stacked on the first compound semiconductor layer, and a third compound semiconductor layer facing the first compound semiconductor layer with the second compound semiconductor layer sandwiched therebetween. The second compound semiconductor layer has a different composition from the first compound semiconductor layer and the third compound semiconductor layer. The third compound semiconductor layer contains a first conductivity type impurity at a higher concentration than the first conductivity type impurity at a higher concentration.

[0006] The second compound semiconductor layer may be disposed below the first compound semiconductor layer.

[0007] The second compound semiconductor layer may be disposed above the first compound semiconductor layer.

[0008] The first compound semiconductor layer and the third compound semiconductor layer may contain InGaAs, and the second compound semiconductor layer may contain InP.

[0009] The first compound semiconductor layer and the third compound semiconductor layer may contain InGaP, and the second compound semiconductor layer may contain GaAs.

[0010] Furthermore, the first conductivity type impurity is an N-type impurity, and the concentration of the N-type impurity contained in the third compound semiconductor layer is 3×10 １９ / cm ３ It may be more than that.

[0011] The third compound semiconductor layer may have a thickness of 100 nm or more and 500 nm or less.

[0012] The semiconductor device may further include a second conductivity type impurity region provided between the first compound semiconductor layer and an electrode.

[0013] The semiconductor device may further include a second conductivity type impurity region provided between the first compound semiconductor layer and the third compound semiconductor layer.

[0014] The semiconductor device may further include an insulating film provided directly on the second compound semiconductor layer.

[0015] The first conductivity type impurity may be silicon (Si) or carbon (C).

[0016] The second conductivity type impurity region may contain zinc (Zn).

[0017] 1 is a block diagram showing a schematic configuration of a photodetector according to a first embodiment; FIG. 2 is a circuit diagram showing an example configuration of a pixel according to the first embodiment; FIG. 3 is a cross-sectional view showing the structure of a photoelectric conversion unit according to the first embodiment; FIG. 4 is a cross-sectional view showing a step of forming a compound semiconductor layer on the uppermost layer of a wafer; FIG. 5 is a cross-sectional view showing a step of forming a bonding layer; FIG. 6 is a cross-sectional view showing a step of bonding a wafer and a semiconductor substrate; FIG. 7 is a cross-sectional view showing a planarization step; FIG. 8 is a plan view showing a trimming step; FIG. 9 is a cross-sectional view showing a trimming step; FIG. 10 is a cross-sectional view showing a step of forming an insulating film; FIG. 11 is a cross-sectional view showing a step of forming an opening in an insulating film; FIG. 12 is a cross-sectional view showing the structure of a photoelectric conversion unit according to a comparative example; FIG. 13 is a cross-sectional view showing a step of forming a compound semiconductor layer according to a comparative example; FIG. 14 is a cross-sectional view showing a step of forming an impurity region according to a comparative example; FIG. 15 is a cross-sectional view showing the structure of a photoelectric conversion unit according to a second embodiment; FIG. 16 is a cross-sectional view showing a step of forming a compound semiconductor layer on a buffer layer; FIG. 17 is a cross-sectional view showing a step of stacking compound semiconductor layers; FIG. 18 is a cross-sectional view showing a step of forming a bonding layer; FIG. 19 is a cross-sectional view showing a step of bonding a wafer and a semiconductor substrate; FIG. 19 is a cross-sectional view showing a planarization step; FIG. 19 is a cross-sectional view showing a trimming step; FIG. 19 is a cross-sectional view showing a step of forming an insulating film; FIG. 19 is a cross-sectional view showing a step of forming a first resist on an insulating film; Fig. 1 is a cross-sectional view showing a step of forming a second resist on an insulating film. Fig. 2 is a plan view showing a step of forming an opening in an insulating film. Fig. 3 is a cross-sectional view showing a step of forming an opening in an insulating film. Fig. 4 is a cross-sectional view showing a step of forming an impurity region. Fig. 5 is a cross-sectional view showing a step of forming an opening in an insulating film according to a comparative example. Fig. 6 is a cross-sectional view showing the movement of a contaminant element 300.

[0018] Hereinafter, an embodiment of a light detection device according to the present disclosure will be described with reference to the drawings. The following description will focus on the main components of the light detection device, but the light detection device may include components and functions that are not shown or described. The following description does not exclude components and functions that are not shown or described.

[0019] First Embodiment Fig. 1 is a block diagram showing a schematic configuration of a photodetector according to a first embodiment. The photodetector 1 shown in Fig. 1 can be applied to, for example, a SWIR (Short Wavelength Infrared) sensor capable of photoelectric conversion of light in the short-wave infrared region. The photodetector 1 includes a pixel array 3, a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, and a control circuit 8.

[0020] A plurality of pixels 2 are arranged in a matrix in the pixel array 3. The configuration of the pixel 2 will be described later.

[0021] The vertical drive circuit 4 is configured with, for example, a shift register. The vertical drive circuit 4 drives the pixels 2 row by row by supplying signals for driving the pixels 2 to predetermined pixel drive wirings 10. That is, the vertical drive circuit 4 selectively scans each pixel 2 in the pixel array 3 row by row in the vertical direction. Through this selective scanning, a pixel signal generated in each pixel 2 according to the amount of incident light received is input to the column signal processing circuit 5 via the vertical signal line 9.

[0022] The column signal processing circuit 5 is arranged for each pixel column. The column signal processing circuit 5 performs signal processing such as noise removal on pixel signals output from one row of pixels 2 for each column. For example, the column signal processing circuit 5 performs signal processing such as CDS (Correlated Double Sampling) to remove fixed pattern noise specific to the pixel and AD conversion.

[0023] The horizontal drive circuit 6 is configured by, for example, a shift register. The horizontal drive circuit 6 sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 5 in turn. This sequential selection causes pixel signals to be output from each of the column signal processing circuits 5 to the horizontal signal line 11.

[0024] The output circuit 7 processes and outputs pixel signals sequentially supplied from each of the column signal processing circuits 5 via horizontal signal lines 11. The output circuit 7 may perform only buffering, or may perform black level adjustment, column variation correction, various digital signal processing, etc. The input / output terminal 13 exchanges signals with the outside.

[0025] The control circuit 8 receives an input clock and data instructing the operation mode and the like, and outputs data such as internal information of the photodetector 1. That is, the control circuit 8 generates clock signals and control signals that serve as references for the operations of the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc., based on the vertical synchronization signal, horizontal synchronization signal, and master clock. The control circuit 8 then outputs the generated clock signals and control signals to the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc.

[0026] 2 is a circuit diagram showing an example of the configuration of the pixel 2. The pixel 2 shown in FIG.

[0027] The photoelectric conversion unit 21 generates electric charges (signal charges) according to the amount of light received. The photoelectric conversion unit 21 is a photodiode using a compound semiconductor such as InGaAs. A predetermined bias voltage Va is applied to the cathode of the photoelectric conversion unit 21. A capacitive element 22, a reset transistor 23, and an amplifying transistor 24 are connected to the anode of the photoelectric conversion unit 21. The structure of the photoelectric conversion unit 21 will be described later.

[0028] The capacitance element 22 accumulates the charge generated by the photoelectric conversion unit 21. The capacitance element 22 can be configured to include at least one of a PN junction capacitance, a MOS capacitance, and a wiring capacitance, for example.

[0029] When the reset transistor 23 is turned on by a reset signal RST, the charge stored in the capacitance element 22 is discharged to the source (ground), thereby resetting the potential of the capacitance element 22 .

[0030] The amplification transistor 24 outputs a pixel signal corresponding to the accumulated potential of the capacitance element 22. That is, the amplification transistor 24 forms a source follower circuit together with a load MOS (not shown) serving as a constant current source connected via the vertical signal line 9, and a pixel signal indicating a level corresponding to the charge accumulated in the capacitance element 22 is output from the amplification transistor 24 to the column signal processing circuit 5 via the selection transistor 25.

[0031] The selection transistor 25 is turned on when the pixel 2 is selected by the selection signal SEL, and outputs a pixel signal of the pixel 2 to the column signal processing circuit 5 via the vertical signal line 9. The signal lines through which the transfer signal TRX, the selection signal SEL, and the reset signal RST are transmitted correspond to the pixel drive wiring 10 in FIG.

[0032] 3 is a cross-sectional view showing the structure of the photoelectric conversion unit 21 according to the first embodiment. The photoelectric conversion unit 21 according to this embodiment includes a semiconductor substrate 210, a bonding layer 211, compound semiconductor layers 212 to 215, an impurity region 216, an insulating film 217, and an electrode 218. In this embodiment, the compound semiconductor layer 214 corresponds to the first compound semiconductor layer. The compound semiconductor layer 213 corresponds to the second compound semiconductor layer. The compound semiconductor layer 212 corresponds to the third compound semiconductor layer.

[0033] The semiconductor substrate 210 is made of, for example, a silicon substrate. In this embodiment, an insulating film made of an insulating material such as silicon nitride (SiN) is formed on the top and bottom surfaces of the semiconductor substrate 210. A bonding layer 211 is provided on the semiconductor substrate 210.

[0034] The bonding layer 211 bonds the stack of compound semiconductor layers 212 to 215 to the semiconductor substrate 210. The bonding layer 211 is made of, for example, TEOS(Si(OC ２ H ５ ) ４ The bonding layer 211 has a thickness of about 450 nm. The compound semiconductor layer 212 is provided on the bonding layer 211.

[0035] The material of the compound semiconductor layer 212 is selected depending on the compound contained in the compound semiconductor layer 214. When the compound semiconductor layer 214 is an InGaAs layer, the compound semiconductor layer 212 is an N layer having a high concentration of N-type impurities (first conductivity type impurities). ＋ When the compound semiconductor layer 214 is an InGaP layer, the compound semiconductor layer 212 is an N type impurity layer having a high concentration. ＋ The compound semiconductor layer 212 is an InGaP layer. The concentration of N-type impurities contained in the compound semiconductor layer 214 is higher than the concentration of N-type impurities contained in the compound semiconductor layer 212 .

[0036] The N-type impurities contained in the compound semiconductor layer 212 include, for example, silicon (Si) or carbon (C). From the viewpoint of preventing the diffusion of contaminant elements into the compound semiconductor layer 214, the concentration of the N-type impurities contained in the compound semiconductor layer 212 is set to 3×10 １９ / cm ３ The above is preferable. On the compound semiconductor layer 212, a compound semiconductor layer 213 is provided.

[0037] The compound semiconductor layer 213 is made of a material that is lattice-matched to the compound semiconductor layer 214. Therefore, the composition of the compound semiconductor layer 213 is different from the composition of the compound semiconductor layer 214. For example, if the compound semiconductor layer 214 is an InGaAs layer, the compound semiconductor layer 213 is an InP layer. Also, if the compound semiconductor layer 214 is an InGaP layer, the compound semiconductor layer 212 is a GaAs layer. The thickness of the compound semiconductor layer 213 is about 20 nm. The compound semiconductor layer 214 is provided on the compound semiconductor layer 213.

[0038] The compound semiconductor layer 214 converts incident light into electricity. As described above, the compound semiconductor layer 214 is made of an N-type compound semiconductor capable of photoelectric conversion, such as InGaAs or InGaP. The thickness of the compound semiconductor layer 214 is about 3 μm. The compound semiconductor layer 215 is provided on the compound semiconductor layer 214.

[0039] The material of the compound semiconductor layer 215 is the same as the material of the compound semiconductor layer 213. That is, the compound semiconductor layer 215 is, for example, an InP layer or a GaAs layer. The thickness of the compound semiconductor layer 215 is about 30 nm.

[0040] The impurity region 216 is formed in the compound semiconductor layer 215 so as to be located between the compound semiconductor layer 214 and the electrode 218. The impurity region 216 reduces the contact resistance between the compound semiconductor layer 214 and the electrode 218. The impurity region 216 contains a P-type impurity (a second conductivity type impurity) such as zinc (Zn). This P-type impurity may diffuse not only into the compound semiconductor layer 215 but also into the compound semiconductor layer 214.

[0041] The insulating film 217 is a protective film that covers the stack of compound semiconductor layers 212 to 215. The insulating film 217 is made of, for example, TEOS, silicon oxide (SiO ２ ), or made of insulating materials such as silicon nitride.

[0042] The electrode 218 functions as an anode electrode that outputs the charge generated by photoelectric conversion in the compound semiconductor layer 214 .

[0043] Hereinafter, a manufacturing process for the photoelectric conversion section 21 according to the first embodiment configured as described above will be described with reference to FIGS.

[0044] 4, a compound semiconductor layer 212 is formed on the top layer of a wafer 220. A compound semiconductor substrate 221 is provided on the bottom layer of the wafer 220. The compound semiconductor substrate 221 is, for example, an N-type semiconductor substrate containing N-type impurities. － The compound semiconductor substrate 221 is an InP substrate, and a buffer layer 222 is laminated on the compound semiconductor substrate 221 .

[0045] The buffer layer 222 is, for example, an N-type impurity layer containing a low concentration of N-type impurities. －The buffer layer 222 is an InP layer. The buffer layer 222 has a thickness of about 300 nm. A stopper layer 223 is stacked on the buffer layer 222. The stopper layer 223 is, for example, an undoped InGaAs layer. The stopper layer 223 has a thickness of about 100 nm. The compound semiconductor layer 215, the compound semiconductor layer 214, the compound semiconductor layer 213, and the compound semiconductor layer 212 described above are stacked in this order on the stopper layer 223. The compound semiconductor layer 212 can be formed by epitaxial growth on an undoped InGaAs layer (not shown) having a thickness of about 20 nm, for example.

[0046] 5, a bonding layer 211 is formed on the compound semiconductor layer 212. The bonding layer 211 can be formed by, for example, CVD (Chemical Vapor Deposition).

[0047] 6, a wafer 220 is bonded to the semiconductor substrate 210 using a bonding layer 211. At this time, the wafer 220 shown in FIG.

[0048] 7, a planarization process is performed to remove the compound semiconductor substrate 221 and the buffer layer 222. The planarization process can be performed by, for example, CMP (Chemical Mechanical Polishing). At this time, the stopper layer 223 functions as a stopper for CMP.

[0049] 8A and 8B, a trimming process is performed to form the compound semiconductor layers 212 to 215 into a chip shape, and the stopper layer 223 is removed at this time.

[0050] 9, an insulating film 217 is formed so as to cover the compound semiconductor layers 212 to 215 formed into chip shapes. The insulating film 217 can be formed by, for example, CVD.

[0051] 10 , a portion of the insulating film 217 is removed to form an opening 230 that exposes the compound semiconductor layer 215. The opening 230 can be formed by, for example, RIE (Reactive Ion Etching). Subsequently, a P-type impurity such as zinc is injected into the compound semiconductor layer 215 through the opening 230 and thermally diffused. This forms a P-type impurity region 216.

[0052] 3, a metal such as aluminum or tungsten is filled into the opening 230 to form the electrode 218. This completes the photoelectric conversion section 21.

[0053] Here, a comparative example to be compared with this embodiment will be described.

[0054] 11 is a cross-sectional view showing the structure of a photoelectric conversion unit 21a according to a comparative example. In FIG. 11, the same components as those in the photoelectric conversion unit 21 according to the first embodiment described above are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0055] The photoelectric conversion unit 21a according to this comparative example differs from the photoelectric conversion unit 21 according to the first embodiment in that it has a compound semiconductor layer 212a instead of the compound semiconductor layer 212. The N-type impurity concentration of the compound semiconductor layer 212a is the same as the N-type impurity concentration of the compound semiconductor layer 214 and is lower than the N-type impurity concentration of the compound semiconductor layer 212.

[0056] The photoelectric conversion unit 21a according to this comparative example can be manufactured by the same manufacturing process as the photoelectric conversion unit 21 described above.

[0057] 12 is a cross-sectional view showing a process for forming a compound semiconductor layer 212a according to a comparative example. The compound semiconductor layer 212a is formed on the top layer of the wafer 220, similar to the compound semiconductor layer 212. At this time, contaminant elements 300 made of metal elements may adhere to the surface of the compound semiconductor layer 212a.

[0058] 13 is a cross-sectional view showing a process for forming the impurity region 216 according to the comparative example. The contaminant element 300 attached to the surface of the compound semiconductor layer 212a may diffuse from the compound semiconductor layer 212a through the compound semiconductor layer 213 to the compound semiconductor layer 214, depending on the temperature of the heat treatment for forming the impurity region 216. If the impurity region 216 is included in the compound semiconductor layer 214, the dark current increases.

[0059] On the other hand, in the photoelectric conversion unit 21 according to this embodiment, a compound semiconductor layer 212 containing a high concentration of N-type impurities is provided instead of the compound semiconductor layer 212a. Therefore, even if a contaminant element 300 adheres to the surface of the compound semiconductor layer 212 as shown in Fig. 4, the adhered contaminant element 300 segregates at the interface between the compound semiconductor layer 212 and the compound semiconductor layer 213 as shown in Fig. 10. Therefore, even if a heat treatment is performed to form the impurity region 216, the contaminant element 300 does not diffuse into the compound semiconductor layer 214.

[0060] Therefore, according to this embodiment, it is possible to suppress an increase in dark current.

[0061] In this embodiment, the compound semiconductor layer 212 is made of N ＋ InGaAs layer or N ＋ The compound semiconductor layer 212 may be made of, but is not limited to, an InGaP layer. For example, if the thermal expansion coefficient of the compound semiconductor layer 212 is larger than that of the compound semiconductor layer 213, micro-strain occurs at the interface between the compound semiconductor layer 212 and the compound semiconductor layer 213. Therefore, the contaminant element 300 can be gettered by this micro-strain. As a result, the diffusion of the contaminant element 300 into the compound semiconductor layer 214 can be prevented, making it possible to suppress an increase in dark current.

[0062] Furthermore, if the metal solid solubility of the compound semiconductor layer 212 is higher than that of the compound semiconductor layer 213, the contaminant element 300 is more likely to dissolve into the compound semiconductor layer 212. In this case, the contaminant element 300 is less likely to diffuse into the compound semiconductor layer 213. As a result, the diffusion of the contaminant element 300 into the compound semiconductor layer 214 can be avoided, making it possible to suppress an increase in dark current. However, if the thickness of the compound semiconductor layer 212 is thinner than 100 nm, the amount of dissolution of the contaminant element 300 may be insufficient. Therefore, the thickness of the compound semiconductor layer 212 is preferably 100 nm or greater.

[0063] Second Embodiment Fig. 14 is a cross-sectional view showing the structure of a photoelectric conversion unit according to a second embodiment. In Fig. 14, the same components as those in the photoelectric conversion unit 21 according to the first embodiment described above are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0064] In the photoelectric conversion unit 21b according to this embodiment, a compound semiconductor layer 212b is provided instead of the compound semiconductor layer 212. The compound semiconductor layer 212b is, for example, a non-doped InGaAs layer. The thickness of the compound semiconductor layer 212b is about 20 nm.

[0065] The photoelectric conversion unit 21b according to this embodiment further includes a compound semiconductor layer 219. The compound semiconductor layer 219 is provided between the impurity region 216 and the electrode 218. In this embodiment, the compound semiconductor layer 219 corresponds to the third compound semiconductor layer. The compound semiconductor layer 15 corresponds to the second compound semiconductor layer.

[0066] The material of the compound semiconductor layer 219 is selected depending on the compound contained in the compound semiconductor layer 214. When the compound semiconductor layer 214 is an InGaAs layer, the compound semiconductor layer 219 is an N layer containing N-type impurities. ＋ When the compound semiconductor layer 214 is an InGaP layer, the compound semiconductor layer 219 is an N layer containing an N-type impurity. ＋ The compound semiconductor layer 219 is an InGaP layer. The N-type impurity in the compound semiconductor layer 219 includes, for example, silicon (Si) or carbon (C). The concentration of the N-type impurity in the compound semiconductor layer 219 is 3×10 １９ / cm ３ That's all.

[0067] Hereinafter, a manufacturing process for the photoelectric conversion unit 21b according to the second embodiment configured as described above will be described with reference to FIGS.

[0068] 15, a compound semiconductor layer 219 is formed on a buffer layer 222. The compound semiconductor layer 219 can be formed by epitaxial growth, for example. The buffer layer 222 is formed on a compound semiconductor substrate 221, as in the first embodiment.

[0069] Next, as shown in FIG. 16, a compound semiconductor layer 215, a compound semiconductor layer 214, a compound semiconductor layer 213, and a compound semiconductor layer 212b are stacked in this order on the compound semiconductor layer 219.

[0070] 17, the bonding layer 211 is formed on the compound semiconductor layer 212b. The bonding layer 211 can be formed by, for example, CVD, as in the first embodiment.

[0071] 18, a wafer 220 is bonded to the semiconductor substrate 210 using a bonding layer 211. At this time, the wafer 220 shown in FIG.

[0072] 19, a planarization process is performed to remove the compound semiconductor substrate 221 and the buffer layer 222. The planarization process can be performed by, for example, CMP, as in the first embodiment.

[0073] Next, as shown in FIG. 20, a trimming process is performed to shape the compound semiconductor layers 212b to 219 into a chip shape.

[0074] 21, an insulating film 217 is formed so as to cover the compound semiconductor layers 212b to 219 formed into chip shapes. The insulating film 217 can be formed by, for example, CVD, as in the first embodiment.

[0075] Next, as shown in FIG. 22, a first resist 240 is formed on the insulating film 217 in order to pattern the compound semiconductor layer 219 .

[0076] Next, as shown in FIG. 23, an etching process is performed using the first resist 240 as a mask to remove the portions not covered by the first resist 240.

[0077] Next, as shown in FIG. 24, the exposed portion of the compound semiconductor layer 215 exposed by the above etching process is covered again with an insulating film 217.

[0078] 25, a second resist 241 is formed on the insulating film 217. The second resist 241 is patterned so as to form an opening that exposes the compound semiconductor layer 219.

[0079] 26A and 26B , an etching process is performed using the second resist 241 as a mask to remove the insulating film 217 that is not covered with the second resist 241. As a result, an opening 250 that exposes the compound semiconductor layer 219 is formed.

[0080] 27, P-type impurities such as zinc are injected into compound semiconductor layer 215 through opening 250 and thermally diffused. This forms impurity region 216. The conductivity type of impurity region 216 is P-type. The conductivity type of compound semiconductor layer 219 is N-type. Therefore, if compound semiconductor layer 219 were to exist in the region outside opening 250, a strong electric field would be generated in the oblique direction.

[0081] 26A and 26B , however, in this embodiment, the compound semiconductor layer 219 is not present in the region outside the opening 250. In other words, the insulating film 217 is provided directly above the non-diffusion region of the compound semiconductor layer 215, which is not provided with the impurity region 216. This makes it possible to avoid the generation of a strong electric field.

[0082] 14, a metal such as aluminum or tungsten is filled into the opening 250 to form the electrode 218. This completes the photoelectric conversion section 21b.

[0083] Here, a case where the contaminant element 300 adheres to the photoelectric conversion unit 21b according to this embodiment and the photoelectric conversion unit 21a according to the comparative example described above in a manufacturing process different from that of the first embodiment described above will be described.

[0084] 28 is a cross-sectional view showing a process of forming an opening 230 in an insulating film 217 according to a comparative example. As shown in FIG. 28 , a contaminant element 300 made of a metal element may adhere to the surface of the compound semiconductor layer 215 exposed by the formation of the opening 230. In this comparative example, the metal solid solubility of the compound semiconductor layer 214 disposed below the compound semiconductor layer 215 is higher than the metal solid solubility of the compound semiconductor layer 215. Therefore, the contaminant element 300 is more likely to dissolve in the compound semiconductor layer 214 than in the compound semiconductor layer 215.

[0085] As a result, as shown in FIG. 29, the contaminant element 300 moves from the compound semiconductor layer 215 to the compound semiconductor layer 214, resulting in an increase in dark current.

[0086] On the other hand, in this embodiment, as shown in Fig. 26B , the compound semiconductor layer 219 is exposed from the opening 250. Therefore, the contaminant element 300 adheres to the surface of the compound semiconductor layer 219. However, the metal solid solubility of the compound semiconductor layer 219 is higher than that of the compound semiconductor layer 215. Therefore, the contaminant element 300 dissolves into the compound semiconductor layer 219 and does not diffuse into the compound semiconductor layer 214, as shown in Fig. 27 .

[0087] Therefore, according to this embodiment, an increase in dark current can be suppressed.

[0088] In this embodiment, the compound semiconductor layer 219 is made of N ＋ InGaAs layer or N ＋ The compound semiconductor layer 219 may be made of, but is not limited to, an InGaP layer. For example, if the thermal expansion coefficient of the compound semiconductor layer 219 is larger than that of the compound semiconductor layer 215, micro-strain occurs at the interface between the compound semiconductor layer 219 and the compound semiconductor layer 215. Therefore, the contaminant element 300 can be gettered by this micro-strain. As a result, the diffusion of the contaminant element 300 into the compound semiconductor layer 214 can be prevented, making it possible to suppress an increase in dark current.

[0089] Furthermore, in this embodiment, the metal solid solubility of the compound semiconductor layer 219 is higher than that of the compound semiconductor layer 215, so the contaminant element 300 is more likely to dissolve into the compound semiconductor layer 219. However, if the thickness of the compound semiconductor layer 219 is thinner than 100 nm, the amount of dissolution of the contaminant element 300 may be insufficient. Furthermore, if the thickness of the compound semiconductor layer 219 is thicker than 500 nm, there is a possibility that metal diffusion in the impurity region 216 will be hindered. Therefore, the thickness of the compound semiconductor layer 219 is preferably 100 nm or more and 500 nm or less.

[0090] The present technology can be configured as follows:

[0091] (1) A photodetector comprising: a first compound semiconductor layer that photoelectrically converts incident light; a second compound semiconductor layer stacked on the first compound semiconductor layer; and a third compound semiconductor layer facing the first compound semiconductor layer with the second compound semiconductor layer interposed therebetween, wherein the second compound semiconductor layer has a composition different from the compositions of the first compound semiconductor layer and the third compound semiconductor layer, and the third compound semiconductor layer contains a first conductivity type impurity at a higher concentration than the first conductivity type impurity at a higher concentration.

[0092] (2) The photodetector according to (1), wherein the second compound semiconductor layer is disposed below the first compound semiconductor layer.

[0093] (3) The photodetector according to (1), wherein the second compound semiconductor layer is disposed above the first compound semiconductor layer.

[0094] (4) The photodetector according to any one of (1) to (3), wherein the first compound semiconductor layer and the third compound semiconductor layer contain InGaAs, and the second compound semiconductor layer contains InP.

[0095] (5) The photodetector according to any one of (1) to (3), wherein the first compound semiconductor layer and the third compound semiconductor layer contain InGaP, and the second compound semiconductor layer contains GaAs.

[0096] (6) The first conductivity type impurity is an N-type impurity, and the concentration of the N-type impurity contained in the third compound semiconductor layer is 3×10 １９ / cm ３ The photodetector according to any one of (1) to (5) above.

[0097] (7) The photodetector according to any one of (1) to (6), wherein the thickness of the third compound semiconductor layer is 100 nm or more and 500 nm or less.

[0098] (8) The photodetector according to (2), further comprising a second conductivity type impurity region provided between the first compound semiconductor layer and an electrode.

[0099] (9) The photodetector according to (3), further comprising a second conductivity type impurity region provided between the first compound semiconductor layer and the third compound semiconductor layer.

[0100] (10) The photodetector according to (9), further comprising an insulating film provided directly on the second compound semiconductor layer.

[0101] (11) The photodetector according to any one of (1) to (10), wherein the first conductivity type impurity is silicon (Si) or carbon (C).

[0102] (12) The photodetector according to (8) or (10), wherein the second conductivity type impurity region contains zinc (Zn).

[0103] 1: Photodetector 212: Compound semiconductor layer (third compound semiconductor layer) 213: Compound semiconductor layer (second compound semiconductor layer) 214: Compound semiconductor layer (first compound semiconductor layer) 215: Compound semiconductor layer (second compound semiconductor layer) 219: Compound semiconductor layer (third compound semiconductor layer) 216: Impurity region 217: Insulating film

Claims

1. A photodetector comprising: a first compound semiconductor layer that converts incident light into electricity; a second compound semiconductor layer laminated on said first compound semiconductor layer; and a third compound semiconductor layer facing said first compound semiconductor layer with the second compound semiconductor layer interposed therebetween, wherein the composition of said second compound semiconductor layer is different from the compositions of said first compound semiconductor layer and said third compound semiconductor layer, and a concentration of a first conductivity type impurity contained in said third compound semiconductor layer is higher than a concentration of a first conductivity type impurity contained in said first compound semiconductor layer.

2. The photodetector device according to claim 1, wherein the second compound semiconductor layer is disposed below the first compound semiconductor layer.

3. The photodetector device according to claim 1, wherein the second compound semiconductor layer is disposed above the first compound semiconductor layer.

4. The photodetector device according to claim 1, wherein the first compound semiconductor layer and the third compound semiconductor layer contain InGaAs, and the second compound semiconductor layer contains InP.

5. The photodetector device according to claim 1, wherein the first compound semiconductor layer and the third compound semiconductor layer contain InGaP, and the second compound semiconductor layer contains GaAs.

6. The first conductive type impurity is an N-type impurity, and the concentration of the N-type impurity contained in the third compound semiconductor layer is 3×10 １９ / cm ３ The photodetector according to claim 1 .

7. The photodetector according to claim 1, wherein the third compound semiconductor layer has a thickness of 100 nm or more and 500 nm or less.

8. The photodetector according to claim 2, further comprising an impurity region of a second conductivity type provided between said first compound semiconductor layer and an electrode.

9. The photodetector according to claim 3, further comprising a second conductivity type impurity region provided between said first compound semiconductor layer and said third compound semiconductor layer.

10. The photodetector device according to claim 9, further comprising an insulating film provided directly on said second compound semiconductor layer.

11. The photodetector device according to claim 1, wherein the first conductivity type impurity is silicon (Si) or carbon (C).

12. The photodetector device according to claim 8, wherein the second conductivity type impurity region contains zinc (Zn).

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