Semiconductor substrate, semiconductor device, and method for manufacturing same

Abstract

A semiconductor device according to one embodiment of the present invention involves: a step for forming, by an epitaxial growth method and on a first silicon carbide layer, a second silicon carbide layer which has a lower first conductivity type impurity concentration than the first silicon carbide layer, in which the first conductivity type impurity concentration is 1×1014-1×1017 atoms / cm3 <sp / >, and which has a film thickness of 0.001-0.1 µm; a step for forming, by an epitaxial growth method and on the second silicon carbide layer, a third silicon carbide layer which has a first conductivity type impurity concentration of not less than 5×1017 atoms / cm3 but less than 1×1020 atoms / cm3, and which has a film thickness of 0.5-20 µm; a step for forming, by an epitaxial growth method and on the third silicon carbide layer, a fourth silicon carbide layer which has a lower first conductivity type impurity concentration than the third silicon carbide layer; and a step for heating the first silicon carbide layer, the second silicon carbide layer, the third silicon carbide layer, and the fourth silicon carbide layer.

Description

Semiconductor substrate, semiconductor device and manufacturing method thereof

[0001] FIELD Embodiments of the present invention relate to a semiconductor substrate, a semiconductor device, and a method for manufacturing the same.

[0002] Silicon carbide (SiC) is expected to be a material for next-generation semiconductor devices. Compared to silicon (Si), silicon carbide has approximately three times the band gap, ten times the breakdown field strength, and three times the thermal conductivity. Therefore, the use of SiC can realize semiconductor devices that are low-loss and capable of operating at high temperatures.

[0003] JP 2009-088223 A

[0004] Fuji Electric Technical Report 2017 vol. 90 no. 4

[0005] The problem to be solved by the present invention is to provide a semiconductor substrate with few defects and low on-resistance, a semiconductor device, and a method for manufacturing the same.

[0006] In the method for manufacturing a semiconductor substrate according to the embodiment, a silicon carbide layer having a first conductivity type impurity concentration lower than that of the first silicon carbide layer and having a first conductivity type impurity concentration of 1×10 １４ atoms / cm ３ That's 1 x 10 １７ atoms / cm ３ forming a second silicon carbide layer having a thickness of 0.001 μm or more and 0.1 μm or less by epitaxial growth; and depositing a silicon carbide layer having a first conductivity type impurity concentration of 5×10 on the second silicon carbide layer. １７ atoms / cm ３ That's 1 x 10 ２０ atoms / cm ３ forming, by epitaxial growth, a third silicon carbide layer having a thickness of 0.5 μm or more and 20 μm or less; forming, on the third silicon carbide layer, by epitaxial growth, a fourth silicon carbide layer having a first conductivity type impurity concentration lower than that of the third silicon carbide layer; and performing heat treatment on the first silicon carbide layer, the second silicon carbide layer, the third silicon carbide layer and the fourth silicon carbide layer.

[0007] According to the present invention, it is possible to provide a semiconductor substrate with few defects and low on-resistance, a semiconductor device, and a method for manufacturing the same.

[0008] FIG. 1 is a schematic cross-sectional view of a semiconductor substrate and a semiconductor device of a first embodiment. FIG. 2 is a schematic cross-sectional view showing a manufacturing process of a semiconductor substrate and a semiconductor device of a first embodiment. FIG. 3 is a schematic cross-sectional view showing a manufacturing process of a semiconductor substrate and a semiconductor device of a first embodiment. FIG. 4 is a flowchart of a manufacturing process of a semiconductor substrate and a semiconductor device of a first embodiment. FIG. 5 is a schematic cross-sectional view of a semiconductor substrate and a semiconductor device of a second embodiment. FIG. 6 is a schematic cross-sectional view showing a manufacturing process of a semiconductor substrate and a semiconductor device of a second embodiment. FIG. 7 is a flowchart of a manufacturing process of a semiconductor substrate and a semiconductor device of a second embodiment. FIG. 8 is a schematic cross-sectional view of a semiconductor substrate and a semiconductor device of a third embodiment. FIG. 9 is a flowchart of a manufacturing process of a semiconductor substrate and a semiconductor device of a third embodiment. FIG. 10 is a schematic cross-sectional view of a semiconductor device and a semiconductor device of a fourth embodiment. FIG. 11 is a schematic cross-sectional view of a semiconductor device and a semiconductor device of a fifth embodiment.

[0009] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same components will be denoted by the same reference numerals, and the description of components that have already been described will be omitted as appropriate.

[0010] In the following description, n ＋ , n, n － and p ＋ , p, p － When the notations are used, these notations represent the relative levels of impurity concentration in each conductivity type. ＋ has a relatively higher n-type impurity concentration than n, － indicates that the n-type impurity concentration is relatively lower than that of n. ＋ The p-type impurity concentration is relatively higher than that of p － indicates that the p-type impurity concentration is relatively lower than that of p. ＋ type, n － The type is simply n-type, p ＋ type, p － The type may also be simply referred to as p-type.

[0011] The impurity concentration can be measured, for example, by SIMS (Secondary Ion Mass Spectrometry). The relative level of the impurity concentration can also be determined from the level of the carrier concentration obtained, for example, by SCM (Scanning Capacitance Microscopy). The distance, such as the depth of the impurity region, can be determined, for example, by SIMS. The distance, such as the width and depth of the impurity region, can also be determined, for example, from an SCM image.

[0012] Defects can be evaluated by, for example, KOH etching, reflection X-ray topography, transmission X-ray topography, TEM (Transmission Electron Microscope), or photoluminescence imaging.

[0013] Hereinafter, the first conductivity type will be referred to as n-type, and the second conductivity type will be referred to as p-type.

[0014] In this specification, in order to indicate the positional relationship of parts, etc., the upward direction of the drawing will be described as "up" and the downward direction of the drawing will be described as "down." In this specification, the concepts of "up" and "down" do not necessarily refer to the direction of gravity.

[0015] First Embodiment A method for manufacturing a semiconductor substrate according to the present embodiment includes forming a first silicon carbide layer on a first silicon carbide layer, the first silicon carbide layer having a first conductivity type impurity concentration lower than that of the first silicon carbide layer and having a first conductivity type impurity concentration of 1×10 １４ atoms / cm ３ That's 1 x 10 １７ atoms / cm ３ forming a second silicon carbide layer having a thickness of 0.001 μm or more and 0.1 μm or less by epitaxial growth; and depositing a silicon carbide layer having a first conductivity type impurity concentration of 5×10 on the second silicon carbide layer. １７ atoms / cm ３ That's 1 x 10 ２０ atoms / cm ３forming, by epitaxial growth, a third silicon carbide layer having a thickness of 0.5 μm or more and 20 μm or less; forming, on the third silicon carbide layer, by epitaxial growth, a fourth silicon carbide layer having a first conductivity type impurity concentration lower than that of the third silicon carbide layer; and performing heat treatment on the first silicon carbide layer, the second silicon carbide layer, the third silicon carbide layer and the fourth silicon carbide layer.

[0016] The method for manufacturing the semiconductor device of this embodiment includes the steps of forming a ninth silicon carbide layer of the second conductivity type on the fourth silicon carbide layer of the semiconductor substrate of this embodiment, forming a first electrode below the first silicon carbide layer, and forming a second electrode on the ninth silicon carbide layer.

[0017] The semiconductor substrate of this embodiment includes a first silicon carbide layer and a first conductivity type impurity layer having a concentration of 1×10 １７ cm －３ atoms / cm ３ That's 1 x 10 １９ cm －３ atoms / cm ３ a fifth silicon carbide layer having a first conductivity type impurity concentration of less than 5×10; and a silicon carbide layer provided on the fifth silicon carbide layer and having a first conductivity type impurity concentration of less than 5×10 １７ cm －３ atoms / cm ３ That's 1 x 10 ２０ cm －３ atoms / cm ３ and a fourth silicon carbide layer provided on the third silicon carbide layer and having a first conductivity type impurity concentration lower than that of the third silicon carbide layer, wherein in a region including the first silicon carbide layer and the fifth silicon carbide layer, in a direction from the first silicon carbide layer toward the fifth silicon carbide layer, the concentration gradient of the first conductivity type impurity is different from the concentration gradient of an impurity different from the first conductivity type impurity.

[0018] The semiconductor substrate of this embodiment also includes a first silicon carbide layer and a silicon carbide layer provided on the first silicon carbide layer, the first conductivity type impurity concentration of which is 1×10 １７ cm －３ atoms / cm ３ That's 1 x 10 １９ cm －３ atoms / cm３ a fifth silicon carbide layer having a first conductivity type impurity concentration of less than 5×10; and a silicon carbide layer provided on the fifth silicon carbide layer and having a first conductivity type impurity concentration of less than 5×10 １７ cm －３ atoms / cm ３ That's 1 x 10 ２０ cm －３ atoms / cm ３ a third silicon carbide layer having a thickness of 0.5 μm or more and 20 μm or less, and a fourth silicon carbide layer provided on the third silicon carbide layer and having a first conductivity type impurity concentration lower than that of the third silicon carbide layer, wherein the first silicon carbide layer has a BPD (Basal plane dislocation) density of 10 / cm ２ or more, and the BPD density of the third silicon carbide layer and the fourth silicon carbide layer is 0.1 pieces / cm ２ The following is the result.

[0019] 1A and 1B are schematic cross-sectional views of a semiconductor substrate 100 and a semiconductor device 200 according to this embodiment. Fig. 1A is a schematic cross-sectional view of the semiconductor substrate 100 and the semiconductor device 200 according to this embodiment. Fig. 1B is a schematic view showing the impurity concentration in the Z direction of the semiconductor device 200.

[0020] The semiconductor substrate 100 includes a first silicon carbide layer 4 , a fifth silicon carbide layer 12 , a third silicon carbide layer 8 , and a fourth silicon carbide layer 10 .

[0021] The semiconductor device 200 includes a semiconductor substrate 100 , a first electrode 60 , a ninth silicon carbide layer 20 , and a second electrode 62 .

[0022] The semiconductor device 200 of this embodiment is a PIN diode.

[0023] Here, an X direction, a Y direction perpendicular to the X direction, and a Z direction perpendicular to the X and Y directions are defined. The first silicon carbide layer 4, the fifth silicon carbide layer 12, the third silicon carbide layer 8, and the fourth silicon carbide layer 10 are arranged parallel to each other in the XY plane. The Z direction is the direction in which the first electrode 60, the first silicon carbide layer 4, the fifth silicon carbide layer 12, the third silicon carbide layer 8, the fourth silicon carbide layer 10, and the second electrode 62 are stacked. The Z direction is the direction from the first electrode 60 to the second electrode 62.

[0024] n ＋The first silicon carbide layer 4 is doped with n-type impurities at a concentration of, for example, 1×10 １８ atoms / cm ３ 1x10 or more １９ atoms / cm ３ The following is included. The n-type impurity is, for example, N (nitrogen). However, the n-type impurity may be, for example, P (phosphorus). Furthermore, the n-type impurity may be both N (nitrogen) and P (phosphorus). The first silicon carbide layer 4 is, for example, a silicon carbide layer formed by epitaxial growth using a CVD (Chemical Vapor Deposition) method on a substrate such as a silicon carbide substrate (not shown in FIGS. 1A-B). However, the first silicon carbide layer 4 may also be, for example, a silicon carbide substrate. The first silicon carbide layer 4 is, for example, a cathode layer of a PIN diode.

[0025] The n-type fifth silicon carbide layer 12 is provided on the first silicon carbide layer 4. The fifth silicon carbide layer 12 is doped with an n-type impurity at a concentration of, for example, 1×10 １７ atoms / cm ３ 1x10 or more １９ atoms / cm ３ Alternatively, the n-type impurity concentration of the fifth silicon carbide layer 12 is equal to or less than half of the n-type impurity concentration of the first silicon carbide layer 4 or the n-type impurity concentration of the third silicon carbide layer 8. The film thickness of the fifth silicon carbide layer 12 is preferably, for example, not less than 0.001 μm and not more than 0.1 μm.

[0026] n ＋ The third silicon carbide layer 8 is provided on the fifth silicon carbide layer 12. The third silicon carbide layer 8 is doped with, for example, 5×10 n-type impurities. １７ atoms / cm ３ 1x10 or more ２０ atoms / cm ３ The third silicon carbide layer 8 has a film thickness of, for example, 0.5 μm or more and 20 μm or less. The third silicon carbide layer 8 is a layer for promoting recombination of holes and electrons so that holes do not reach the silicon carbide substrate, etc., during bipolar current conduction in the semiconductor device 200, for example.

[0027] The fifth silicon carbide layer 12 is formed, for example, by forming a second silicon carbide layer 6 (described later) on the first silicon carbide layer 4, forming a third silicon carbide layer 8 on the second silicon carbide layer 6, and then diffusing n-type impurities from the first silicon carbide layer 4 and the third silicon carbide layer 8 into the second silicon carbide layer 6 by impurity diffusion using heat treatment.

[0028] The third silicon carbide layer 8 is, for example, a silicon carbide layer formed on the second silicon carbide layer 6 (described later) by epitaxial growth using a CVD method.

[0029] In epitaxial growth using CVD, the n-type impurity concentration of each silicon carbide layer is adjusted by the flow rate of the impurity gas (e.g., nitrogen), and the n-type impurity concentration near the interface of each silicon carbide layer has a concentration gradient depending on the time of changing the flow rate. However, the concentration gradient also changes during impurity diffusion using subsequent heat treatment. The concentration gradient generally becomes gentler after heat treatment. In addition to n-type impurities, unintended impurities from parts inside the furnace of the epitaxial growth apparatus may be mixed in. Examples include Al (aluminum), B (boron), P (phosphorus), Fe (iron), Cr (chromium), Ni (nickel), Zn (zinc), and Ta (tantalum). The diffusion coefficient of impurities in SiC varies depending on the element. Therefore, the concentration gradient of n-type impurities resulting from impurity diffusion using heat treatment differs from the concentration gradient of unintended impurities other than the n-type impurity.

[0030] 1B is merely an example, and it goes without saying that the impurity concentrations of the semiconductor substrate 100 and the semiconductor device 200 of this embodiment are not limited to those shown in FIG.

[0031] n － The fourth silicon carbide layer 10 is provided on the third silicon carbide layer 8. The fourth silicon carbide layer 10 is doped with, for example, an n-type impurity at a concentration of 1×10 １５ atoms / cm ３ 5x10 or more １６ atoms / cm ３The n-type impurity concentration of the fourth silicon carbide layer 10 is lower than the impurity concentration of the third silicon carbide layer 8. The film thickness of the fourth silicon carbide layer 10 is, for example, not less than 4 μm and not more than 50 μm.

[0032] The BPD density of the first silicon carbide layer 4 is 10 / cm ２ The BPD density of the fifth silicon carbide layer 12, the third silicon carbide layer 8, and the fourth silicon carbide layer 10 is 0.1 pieces / cm ２ The following is the result.

[0033] The p-type ninth silicon carbide layer 20 is provided on the fourth silicon carbide layer 10. The ninth silicon carbide layer 20 is doped with, for example, a p-type impurity of 1×10 １７ atoms / cm ３ 1x10 or more ２０ atoms / cm ３ The p-type impurity is, for example, Al (aluminum). The ninth silicon carbide layer 20 has a thickness of, for example, 0.1 μm or more and 2.0 μm or less. The ninth silicon carbide layer 20 is, for example, an anode layer of a PIN diode.

[0034] The first electrode 60 is provided under the first silicon carbide layer 4. The first electrode 60 is in contact with, for example, the first silicon carbide layer 4. The first electrode 60 contains, for example, a metal or a metal semiconductor compound. The first electrode 60 contains, for example, Ni (nickel). Note that Ni contained in the first electrode 60 reacts with the first silicon carbide layer 4 to form NiSi or Ni ２ A layer containing Si (nickel silicide) may be formed. The first electrode 60 may be made of NiSi or Ni ２ A layer containing Ti (titanium), Ni (nickel), Ag (silver), or Au (gold) may be provided below the layer containing Si. The first electrode 60 is a cathode electrode.

[0035] The second electrode 62 is provided on the ninth silicon carbide layer 20. The second electrode 62 is in contact with, for example, the ninth silicon carbide layer 20. The second electrode 62 has, for example, a stacked structure of a barrier metal layer containing Ti (titanium) in contact with the ninth silicon carbide layer 20 and a metal layer containing Al (aluminum) provided on the barrier metal layer. Furthermore, the second electrode 62 may have, for example, a layer containing a metal silicide such as NiSi in a portion in contact with the ninth silicon carbide layer 20.

[0036] 2A-B and 3A-B are schematic cross-sectional views showing the manufacturing process of the semiconductor substrate 100 and the semiconductor device 200 of this embodiment. Fig. 4 is a flowchart of the manufacturing process of the semiconductor substrate 100 and the semiconductor device 200 of this embodiment.

[0037] First, on the first silicon carbide layer 4, an n-type impurity layer having a concentration of 1×10 was epitaxially grown by CVD (Chemical Vapor Deposition). １４ atoms / cm ３ That's 1 x 10 １７ atoms / cm ３ The second silicon carbide layer 6 is formed to a thickness of 0.001 μm or more and 0.1 μm or less (S102 in FIG. 4). The n-type impurity concentration of the second silicon carbide layer 6 is lower than the n-type impurity concentration of the first silicon carbide layer 4. For example, SiH ４ , C (carbon) raw material is C ３ H ８ or C ２ H ２ , N (nitrogen) as an n-type dopant, and H as a carrier gas. ２ (hydrogen) are used, respectively.

[0038] The second silicon carbide layer 6 is a layer for converting, for example, BPDs of SiC into TEDs (Threading Edge Dislocations).

[0039] Next, n-type impurities are doped onto the second silicon carbide layer 6 by epitaxial growth using a CVD (Chemical Vapor Deposition) method.１７ atoms / cm ３ 1x10 or more ２０ atoms / cm ３ A third silicon carbide layer 8 having a thickness of 0.5 μm or more and 20 μm or less is formed (S104 in FIG. 4).

[0040] Next, on the third silicon carbide layer 8, a first conductivity type impurity layer having a first conductivity type impurity concentration of, for example, 1×10 is epitaxially grown by CVD (Chemical Vapor Deposition). １５ cm －３ atoms / cm ３ 5x10 or more １６ cm －３ atoms / cm ３ A fourth silicon carbide layer 10 having a thickness of 4 μm or more and 50 μm or less is formed (FIGS. 2A and 2B, S106 in FIG. 4).

[0041] Next, a silicon carbide layer having an n-type impurity concentration of 1×10 １７ atoms / cm ３ 1x10 or more １９ atoms / cm ３ A fifth silicon carbide layer 12 having a thickness less than 100 nm is formed. The fifth silicon carbide layer 12 is formed by, for example, a heat treatment to diffuse impurities from the first silicon carbide layer 4 and the third silicon carbide layer 8 into the second silicon carbide layer 6. Specifically, the first silicon carbide layer 4, the second silicon carbide layer 6, the third silicon carbide layer 8, and the fourth silicon carbide layer 10 are heated, for example, at a temperature range of 1100°C to 1700°C for 30 minutes or longer. As a result, n-type impurities are diffused from the first silicon carbide layer 4 and the third silicon carbide layer 8, which have a relatively high n-type impurity concentration, to the second silicon carbide layer 6, which has a relatively low n-type impurity concentration, thereby increasing the n-type impurity concentration of the second silicon carbide layer 6. Therefore, the fifth silicon carbide layer 12 can be formed between the first silicon carbide layer 4 and the third silicon carbide layer 8. In this way, the semiconductor substrate 100 of this embodiment is obtained. (Figures 3A-B, S108 in Figure 4).

[0042] The distance that the n-type impurity diffuses varies depending on the heat treatment conditions. For example, when the n-type impurity is N (nitrogen), it diffuses by about 50 nm after heat treatment at 1300°C for 1 hour. The distance that the n-type impurity diffuses can be further increased by adjusting the heat treatment temperature and time. For example, the n-type impurity concentration in the fifth silicon carbide layer 12 can be set to about 1 / 10 to 1 / 2 of that in the first silicon carbide layer 4 and the third silicon carbide layer 8.

[0043] Next, on the fourth silicon carbide layer 10, for example, a p-type impurity of 1×10 is deposited by epitaxial growth using a CVD (Chemical Vapor Deposition) method. １７ atoms / cm ３ 1x10 or more ２０ atoms / cm ３ The p-type ninth silicon carbide layer 20 is formed to a thickness of 0.1 μm to 2.0 μm, and contains the following: ３ ) ３ Al is used.

[0044] Next, the first electrode 60 is formed under the first silicon carbide layer 4. Furthermore, the second electrode 62 is formed on the ninth silicon carbide layer 20. In this way, the semiconductor device 200 of this embodiment is obtained.

[0045] The impurity diffusion step using heat treatment and the epitaxial growth step may be performed in the same apparatus, or the impurity diffusion step using heat treatment and the epitaxial growth step may be performed in separate apparatuses.

[0046] Next, the effects of the semiconductor substrate and semiconductor device of this embodiment will be described.

[0047] When a semiconductor substrate is manufactured by forming a silicon carbide layer on a silicon carbide layer including a silicon carbide substrate, dislocations and stacking faults occur in the formed silicon carbide layer due to dislocations in the silicon carbide substrate or damage to the silicon carbide substrate during the substrate processing process, etc. When a semiconductor device is manufactured using such a semiconductor substrate, this causes a decrease in the yield of the semiconductor device, which is a problem.

[0048] Among dislocations in a silicon carbide substrate, BPDs expand into stacking faults during bipolar current conduction, causing fluctuations in device characteristics. One possible method for suppressing this is to provide a silicon carbide layer with a high impurity concentration between the silicon carbide substrate and the drift layer so that holes do not reach the silicon carbide substrate during bipolar current conduction. However, because BPDs are easily inherited from the silicon carbide substrate to the silicon carbide layer with a high impurity concentration, there is a problem in that holes reach the inherited BPDs and the BPDs expand into stacking faults.

[0049] Another approach to reducing BPDs is to provide a silicon carbide layer with a low impurity concentration between the silicon carbide substrate and the drift layer to convert BPDs to TEDs. This is because TEDs have a smaller effect on device characteristics than BPDs. However, providing a silicon carbide layer with a low impurity concentration increases the device resistance.

[0050] Therefore, in the method for manufacturing a semiconductor substrate according to the present embodiment, a silicon carbide layer having a first conductivity type impurity concentration lower than that of the first silicon carbide layer and having a first conductivity type impurity concentration of 1×10 １４ atoms / cm ３ That's 1 x 10 １７ atoms / cm ３ forming a second silicon carbide layer having a thickness of 0.001 μm or more and 0.1 μm or less by epitaxial growth; and depositing a silicon carbide layer having a first conductivity type impurity concentration of 5×10 on the second silicon carbide layer. １７ atoms / cm ３ That's 1 x 10 ２０ atoms / cm ３ forming, by epitaxial growth, a third silicon carbide layer having a thickness of 0.5 μm or more and 20 μm or less; forming, on the third silicon carbide layer, by epitaxial growth, a fourth silicon carbide layer having a first conductivity type impurity concentration lower than that of the third silicon carbide layer; and performing heat treatment on the first silicon carbide layer, the second silicon carbide layer, the third silicon carbide layer and the fourth silicon carbide layer.

[0051] By providing the second silicon carbide layer 6 , the BPD in the first silicon carbide layer 4 is converted to TED with high efficiency in the layer above the first silicon carbide layer 4 .

[0052] Furthermore, the provision of the third silicon carbide layer 8 promotes the recombination of holes and electrons, thereby preventing the holes from reaching the first silicon carbide layer 4. This makes it possible to suppress the expansion of BPDs into stacking faults.

[0053] Furthermore, impurity diffusion from the first silicon carbide layer 4 and the third silicon carbide layer 8 into the second silicon carbide layer 6 forms a fifth silicon carbide layer 12 having a higher n-type impurity concentration than the second silicon carbide layer 6. The second silicon carbide layer 6 has a thin film thickness of 0.1 μm or less. Therefore, impurity diffusion from the first silicon carbide layer 4 and the third silicon carbide layer 8 into the second silicon carbide layer 6 is sufficiently carried out, thereby suppressing an increase in the resistance of the semiconductor substrate 100. Furthermore, if the film thickness of the second silicon carbide layer 6 is 0.001 μm or more, BPD in the first silicon carbide layer 4 can be converted to TED.

[0054] For example, the BPD density of the first silicon carbide layer 4 is 10 / cm ２ or more, the BPD densities of the fifth silicon carbide layer 12, the third silicon carbide layer 8, and the fourth silicon carbide layer 10 are set to 0.1 pieces / cm ２ It is possible to do the following:

[0055] The second silicon carbide layer 6 and the third silicon carbide layer 8 are preferably formed by epitaxial growth, because it is difficult to diffuse impurities introduced by ion implantation using heat treatment.

[0056] According to this embodiment, it is possible to provide a semiconductor substrate with few defects and low on-resistance, a semiconductor device, and a method for manufacturing the same.

[0057] Second Embodiment A method for manufacturing a semiconductor substrate according to the present embodiment includes the steps of: forming a first conductivity type impurity layer having a concentration of 5×10 on the second silicon carbide layer after the step of forming a second silicon carbide layer and before the step of forming a third silicon carbide layer; １７ atoms / cm ３ That's 1 x 10 ２０ atoms / cm ３forming a sixth silicon carbide layer having a thickness of 0.5 μm or more and 20 μm or less by epitaxial growth; and depositing a silicon carbide layer having a first conductivity type impurity concentration of 1×10 on the sixth silicon carbide layer. １４ atoms / cm ３ That's 1 x 10 １７ atoms / cm ３ The method for manufacturing a semiconductor substrate according to the first embodiment differs from the method for manufacturing a semiconductor substrate according to the first embodiment in that it further includes a step of forming a seventh silicon carbide layer having a thickness of 0.001 μm or more and 0.1 μm or less by epitaxial growth.

[0058] Here, the description of the contents that overlap with the first embodiment will be omitted.

[0059] 5A and 5B are schematic cross-sectional views of the semiconductor substrate 110 and the semiconductor device 210 of this embodiment.

[0060] The sixth silicon carbide layer 14 is provided between the fifth silicon carbide layer 12 and the third silicon carbide layer 8. The sixth silicon carbide layer 14 is doped with, for example, an n-type impurity at a concentration of 5×10 １７ atoms / cm ３ That's 1 x 10 ２０ atoms / cm ３ The sixth silicon carbide layer 14 has a film thickness of 0.5 μm or more and 20 μm or less. The sixth silicon carbide layer 14 is a layer for promoting recombination of holes and electrons so that holes do not reach the silicon carbide substrate or the like when, for example, bipolar current is applied to the semiconductor device 200.

[0061] The eighth silicon carbide layer 18 is provided between the sixth silicon carbide layer 14 and the third silicon carbide layer 8. The eighth silicon carbide layer 18 is doped with, for example, an n-type impurity at a concentration of 1×10 １７ atoms / cm ３ That's 1 x 10 １９ atoms / cm ３Alternatively, the n-type impurity concentration of the eighth silicon carbide layer 18 is half or less of the n-type impurity concentration of the sixth silicon carbide layer 14 or the n-type impurity concentration of the third silicon carbide layer 8. Note that the n-type impurity concentration of the fifth silicon carbide layer 12 in this embodiment may be half or less of the n-type impurity concentration of the first silicon carbide layer 4 or the n-type impurity concentration of the sixth silicon carbide layer 14. The film thickness of the eighth silicon carbide layer 18 is 0.001 μm or more and 0.1 μm.

[0062] 6A and 6B are schematic cross-sectional views showing the manufacturing process of the semiconductor substrate 110 and the semiconductor device 210 of this embodiment. Fig. 7 is a schematic cross-sectional view showing the manufacturing process of the semiconductor substrate 110 and the semiconductor device 210 of this embodiment.

[0063] In the method for manufacturing the semiconductor substrate 110 of this embodiment, the second silicon carbide layer 6 is formed on the first silicon carbide layer 4 (S202 in FIG. 7 ), the sixth silicon carbide layer 14 is formed on the second silicon carbide layer 6 (S204 in FIG. 7 ), the seventh silicon carbide layer 16 is formed on the sixth silicon carbide layer 14 (S206 in FIG. 7 ), the third silicon carbide layer 8 is formed on the seventh silicon carbide layer 16 (S208 in FIG. 7 ), and the fourth silicon carbide layer 10 is formed on the third silicon carbide layer 8 (S210 in FIG. 7 ). Next, by impurity diffusion using a heat treatment, the fifth silicon carbide layer 12 is formed between the first silicon carbide layer 4 and the sixth silicon carbide layer 14, and the eighth silicon carbide layer 18 is formed between the sixth silicon carbide layer 14 and the third silicon carbide layer 8 (S212 in FIG. 7 ).

[0064] In the present embodiment, the use of the second silicon carbide layer 6 and the seventh silicon carbide layer 16 can be considered as using a plurality of second silicon carbide layers 6. Therefore, the conversion efficiency from BPD to TED can be improved.

[0065] Consider the case where the first silicon carbide layer 4 is a silicon carbide substrate. In this case, the variation in the n-type impurity concentration in the silicon carbide substrate is very large. Therefore, when n-type impurities are diffused from the first silicon carbide layer 4, which is a silicon carbide substrate, to the second silicon carbide layer 6, the variation in the XY plane of the resistance of the fifth silicon carbide layer 12 increases. Furthermore, the variation in the XY plane of the BPD conversion efficiency increases. In this embodiment, the n-type impurity diffusion from the sixth silicon carbide layer 14 to the second silicon carbide layer 6 is considered to have smaller variation in the plane than the n-type impurity diffusion from the first silicon carbide layer 4, which is a silicon carbide substrate, to the second silicon carbide layer 6. Furthermore, it is considered that the n-type impurity diffusion from the sixth silicon carbide layer 14 to the seventh silicon carbide layer 16 and the n-type impurity diffusion from the third silicon carbide layer 8 to the seventh silicon carbide layer 16 have smaller in-plane variations than the n-type impurity diffusion from the first silicon carbide layer 4, which is a silicon carbide substrate, to the second silicon carbide layer 6. This makes it possible to reduce the XY in-plane variations in the resistance component and the XY in-plane variations in the BPD conversion efficiency.

[0066] Furthermore, for example, by reducing the film thicknesses of the second silicon carbide layer 6 and the seventh silicon carbide layer 16, it is possible to sufficiently increase the n-type impurity concentrations in the fifth silicon carbide layer 12 and the eighth silicon carbide layer 18 even if the heat treatment temperature for impurity diffusion is lowered or the heat treatment time is shortened. This makes it possible to more easily manufacture the semiconductor substrate 110 and the semiconductor device 210.

[0067] Furthermore, if the n-type impurity concentration of the second silicon carbide layer 6 is too low, the difference in n-type impurity concentration between the first silicon carbide layer 4 or the third silicon carbide layer 8 and the second silicon carbide layer 6 is too large, which may cause stress associated with the difference in lattice constant with the first silicon carbide layer 4 or the third silicon carbide layer 8, resulting in new dislocations. Therefore, for example, the n-type impurity concentration of the second silicon carbide layer 6 is set to, for example, 1×10 １６ atoms / cm ３ That's 1 x 10 １８ atoms / cm ３ In addition to the second silicon carbide layer 6, for example, an n-type impurity density of 1×10 １６ atoms / cm ３ That's 1 x 10 １８ atoms / cm３ It is conceivable to use the seventh silicon carbide layer 16 having the following structure: This allows for a difference in lattice constant, so that the BPD conversion efficiency can be improved while suppressing the generation of new dislocations.

[0068] This embodiment also makes it possible to provide a semiconductor substrate with few defects and low on-resistance, a semiconductor device, and a method for manufacturing the same.

[0069] Third Embodiment A semiconductor substrate of this embodiment differs from the semiconductor substrates of the first and second embodiments in that it further includes a silicon carbide substrate 2 and has a first silicon carbide layer 4 provided on the silicon carbide substrate 2.

[0070] The semiconductor device of this embodiment differs from the semiconductor substrates of the first and second embodiments in that a silicon carbide substrate 2 is provided between a first electrode 60 and a first silicon carbide layer 4 .

[0071] The method for manufacturing a semiconductor substrate of this embodiment differs from the methods for manufacturing a semiconductor substrate of the first and second embodiments in that it further includes a step of forming a first silicon carbide layer 4 by epitaxial growth on a silicon carbide substrate 2 before the step of forming a second silicon carbide layer 6. The method for manufacturing a semiconductor substrate of this embodiment corresponds to the case in the first embodiment where the first silicon carbide layer 4 is formed on a silicon carbide substrate 2 by epitaxial growth.

[0072] Here, descriptions of contents that overlap with the first and second embodiments will be omitted.

[0073] 8A-B are schematic cross-sectional views of the semiconductor substrate 120 and semiconductor device 220 of this embodiment. FIG. 9 is a flowchart of the manufacturing process of the semiconductor substrate 120 and semiconductor device 220 of this embodiment. When the flowchart shown in FIG. 9 is compared with the flowchart shown in FIG. 4, it is different in that FIG. 9 includes a step of "forming a first silicon carbide layer on a silicon carbide substrate" (302 in FIG. 9). In addition, S304, S306, S308, and S310 in FIG. 9 are the same steps as S102, S104, S106, and S108 in FIG. 4, respectively.

[0074] The variation in the n-type impurity concentration within the silicon carbide substrate 2 is very large. Therefore, if the n-type impurity is directly diffused from the silicon carbide substrate 2 into the second silicon carbide layer 6, the variation in the resistance of the fifth silicon carbide layer 12 within the substrate surface will be large. Also, the variation in the BPD conversion efficiency within the substrate surface will be large. In this embodiment, by providing the first silicon carbide layer 4 between the silicon carbide substrate 2 and the second silicon carbide layer 6, these variations can be reduced.

[0075] This embodiment also makes it possible to provide a semiconductor substrate with few defects and low on-resistance, a semiconductor device, and a method for manufacturing the same.

[0076] (Fourth embodiment) A semiconductor device of this embodiment includes: a ninth silicon carbide layer of a second conductivity type provided on a fourth silicon carbide layer of a semiconductor substrate; a tenth silicon carbide layer of a first conductivity type provided on the ninth silicon carbide layer; a third electrode provided on the ninth silicon carbide layer via a first insulating film in a trench extending from the tenth silicon carbide layer to the fourth silicon carbide layer; a second insulating film provided on the third electrode; and a second electrode provided on the tenth silicon carbide layer and the second insulating film.

[0077] The method for manufacturing a semiconductor device of this embodiment includes the steps of: forming a ninth silicon carbide layer of a second conductivity type on a fourth silicon carbide layer of a semiconductor substrate; forming a tenth silicon carbide layer of a first conductivity type on the ninth silicon carbide layer; forming a trench that extends from the tenth silicon carbide layer to the fourth silicon carbide layer; forming a first insulating film in the trench; forming a third electrode in the trench that is provided on the ninth silicon carbide layer via the first insulating film; forming a second insulating film on the third electrode; and forming a second electrode on the tenth silicon carbide layer and the second insulating film.

[0078] Here, descriptions of contents that overlap with the first to third embodiments will be omitted.

[0079] FIG. 10 is a schematic cross-sectional view of the semiconductor device of this embodiment.

[0080] The semiconductor device of this embodiment is a trench type MOSFET.

[0081] The p-type ninth silicon carbide layer 20 is provided on the fourth silicon carbide layer 10. The ninth silicon carbide layer 20 functions as a base of the MOSFET. Ninth silicon carbide layers 20a, 20b, and 20c are illustrated in FIG.

[0082] The n-type tenth silicon carbide layer 40 is provided on the ninth silicon carbide layer 20. The tenth silicon carbide layer 40 functions as the source of the MOSFET. 7 illustrates the tenth silicon carbide layer 40a, the tenth silicon carbide layer 40b, the tenth silicon carbide layer 40c, and the tenth silicon carbide layer 40d.

[0083] The trench 70 extends from the tenth silicon carbide layer 40 to the fourth silicon carbide layer 10. A trench 70a and a trench 70b are shown in FIG.

[0084] The first insulating film 72 is provided in the trench 70. The first insulating film 72 is a gate insulating film of the MOSFET. The first insulating film 72 includes an insulating material such as silicon oxide. FIG. 7 illustrates a first insulating film 72a and a first insulating film 72b.

[0085] The third electrode 74 is provided in the trench 70, facing the ninth silicon carbide layer 20, with the first insulating film 72 interposed between them. The third electrode 74 is a gate electrode of the MOSFET. The third electrode 74 includes, for example, a conductive material such as conductive polysilicon containing impurities. FIG. 7 illustrates the third electrode 74a and the third electrode 74b.

[0086] The second insulating film 76 is provided on the third electrode 74. The second insulating film 76 includes an insulating material such as silicon oxide. In FIG. 7, the second insulating film 76a and the second insulating film 76b are illustrated.

[0087] p ＋ The eleventh silicon carbide layer 42 is provided on the ninth silicon carbide layer 20. The p-type impurity concentration of the eleventh silicon carbide layer 42 is higher than that of the ninth silicon carbide layer 20. The eleventh silicon carbide layer 42 is a contact region of the MOSFET. FIG. 7 illustrates the eleventh silicon carbide layer 42 a, the eleventh silicon carbide layer 42 b, and the eleventh silicon carbide layer 42 c.

[0088] The second electrode 62 is provided on the tenth silicon carbide layer 40 and the second insulating film 76. The second electrode 62 is a source electrode of the MOSFET.

[0089] The first electrode 60 is a drain electrode of the MOSFET.

[0090] Since a semiconductor substrate with few defects and low on-resistance is used, this embodiment also makes it possible to provide a semiconductor device with few defects and low on-resistance and a method for manufacturing the same.

[0091] Fifth Embodiment A semiconductor device of this embodiment includes a ninth silicon carbide layer of a second conductivity type provided on a fourth silicon carbide layer of a semiconductor substrate, a tenth silicon carbide layer of a first conductivity type provided on the ninth silicon carbide layer, a third electrode provided on the ninth silicon carbide layer, a first insulating film provided between the ninth silicon carbide layer and the third electrode, a second electrode provided on the tenth silicon carbide layer and the third electrode, and a second insulating film provided between the second electrode and the third electrode.

[0092] The method for manufacturing a semiconductor device of this embodiment further includes the steps of forming a ninth silicon carbide layer of a second conductivity type on the fourth silicon carbide layer of the semiconductor substrate of any of the first to third embodiments, forming a tenth silicon carbide layer of a first conductivity type on the ninth silicon carbide layer, forming a first insulating film on the ninth silicon carbide layer, forming a third electrode on the first insulating film, forming a second insulating film on the third electrode, and forming a second electrode on the third electrode, the second insulating film, and the tenth silicon carbide layer.

[0093] Here, descriptions of contents that overlap with the first to third embodiments will be omitted.

[0094] FIG. 11 is a schematic cross-sectional view of a semiconductor device 400 according to this embodiment.

[0095] The semiconductor device of this embodiment is a planar type MOSFET.

[0096] The p-type ninth silicon carbide layer 20 is provided on the fourth silicon carbide layer 10. The ninth silicon carbide layer 20 functions as a base of the MOSFET. The ninth silicon carbide layer 20 a and the ninth silicon carbide layer 20 b are illustrated in Fig. 8. The ninth silicon carbide layer 20 a and the ninth silicon carbide layer 20 b are provided, for example, spaced apart from each other.

[0097] The n-type tenth silicon carbide layer 40 is provided on the ninth silicon carbide layer 20. The tenth silicon carbide layer 40 functions as the source of the MOSFET. The tenth silicon carbide layer 40a and the tenth silicon carbide layer 40b are illustrated in FIG. 8 . The tenth silicon carbide layer 40a and the tenth silicon carbide layer 40b are provided, for example, spaced apart from each other.

[0098] The third electrode 74 is provided on the ninth silicon carbide layer 20 a and the ninth silicon carbide layer 20 b. The third electrode 74 is a gate electrode of the MOSFET. The third electrode 74 includes a conductive material such as conductive polysilicon containing impurities.

[0099] The first insulating film 72 is provided between the ninth silicon carbide layer 20 and the third electrode 74. The first insulating film 72 is a gate insulating film of the MOSFET. The first insulating film 72 includes an insulator such as silicon oxide, for example.

[0100] The second electrode 62 is provided on the tenth silicon carbide layer 40 and the third electrode 74. The second electrode 62 is a source electrode of the MOSFET.

[0101] The second insulating film 76 is provided between the second electrode 62 and the third electrode 74. The second insulating film 76 includes an insulating material such as silicon oxide.

[0102] The first electrode 60 is a drain electrode of the MOSFET.

[0103] Since a semiconductor substrate with few defects and low on-resistance is used, this embodiment also makes it possible to provide a semiconductor device with few defects and low on-resistance and a method for manufacturing the same.

[0104] Although several embodiments and examples of the present invention have been described, these embodiments and examples are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims.

[0105] The above-described embodiments can be summarized as the following technical solutions: (Technical Solution 1) A silicon carbide layer having a first conductivity type impurity concentration lower than that of the first silicon carbide layer and having a first conductivity type impurity concentration of 1×10 １４ atoms / cm ３ That's 1 x 10 １７ atoms / cm ３ forming a second silicon carbide layer having a thickness of 0.001 μm or more and 0.1 μm or less by epitaxial growth on the second silicon carbide layer; １７ atoms / cm ３ That's 1 x 10 ２０ atoms / cm ３ a step of forming, by epitaxial growth, a third silicon carbide layer having a thickness of 0.5 μm or more and 20 μm or less, and a thickness of less than 10 μm; a step of forming, by epitaxial growth, a fourth silicon carbide layer on the third silicon carbide layer, the fourth silicon carbide layer having a first conductivity type impurity concentration lower than that of the third silicon carbide layer, and a step of performing heat treatment on the first silicon carbide layer, the second silicon carbide layer, the third silicon carbide layer, and the fourth silicon carbide layer. (Technical Solution 2) In the step of performing heat treatment on the first silicon carbide layer, the second silicon carbide layer, the third silicon carbide layer, and the fourth silicon carbide layer, １７ atoms / cm ３ That's 1 x 10 １８ atoms / cm ３The method for manufacturing a semiconductor substrate according to Technical Idea 1, further comprising forming a fifth silicon carbide layer having a first conductivity type impurity concentration of 5×10 on the second silicon carbide layer after the step of forming the second silicon carbide layer and before the step of forming the third silicon carbide layer. １７ atoms / cm ３ That's 1 x 10 ２０ atoms / cm ３ forming a sixth silicon carbide layer having a thickness of 0.5 μm or more and 20 μm or less by epitaxial growth on the sixth silicon carbide layer; １４ atoms / cm ３ That's 1 x 10 １７ atoms / cm ３ (Technical Solution 4) The method for manufacturing a semiconductor substrate according to any one of Technical Solutions 1 to 3, further comprising: forming the first silicon carbide layer on a silicon carbide substrate by epitaxial growth before the step of forming the second silicon carbide layer. (Technical Solution 5) The method for manufacturing a semiconductor substrate according to Technical Solution 1 or Technical Solution 2, further comprising: forming the first silicon carbide layer on a silicon carbide substrate by epitaxial growth before the step of forming the second silicon carbide layer. (Technical Solution 6) The method for manufacturing a semiconductor substrate according to Technical Solution 1 or Technical Solution 2, further comprising: forming the first silicon carbide layer on a silicon carbide substrate by epitaxial growth before the step of forming the second silicon carbide layer. １７ atoms / cm ３ That's 1 x 10 １９ atoms / cm ３The method for manufacturing a semiconductor substrate according to any one of Technical Schemes 1 to 4, which is as follows: (Technical Scheme 6) A method for manufacturing a semiconductor device, further comprising the steps of: forming a ninth silicon carbide layer of a second conductivity type on the fourth silicon carbide layer of the semiconductor substrate according to any one of Technical Schemes 1 to 5; forming a first electrode below the first silicon carbide layer; and forming a second electrode on the ninth silicon carbide layer. (Technical proposal 7) A method for manufacturing a semiconductor device further comprising the steps of: forming a ninth silicon carbide layer of a second conductivity type on the fourth silicon carbide layer of the semiconductor substrate described in any one of Technical proposals 1 to 5; forming a tenth silicon carbide layer of a first conductivity type on the ninth silicon carbide layer; forming a first electrode below the first silicon carbide layer; forming a trench that extends from the tenth silicon carbide layer to the fourth silicon carbide layer; forming a first insulating film in the trench; forming a third electrode in the trench, the third electrode being provided on the ninth silicon carbide layer via the first insulating film; and forming a second electrode on the tenth silicon carbide layer. (Technical proposal 8) A method for manufacturing a semiconductor device, further comprising the steps of: forming a ninth silicon carbide layer of a second conductivity type on the fourth silicon carbide layer of the semiconductor substrate according to any one of Technical proposals 1 to 5; forming a tenth silicon carbide layer of a first conductivity type on the ninth silicon carbide layer; forming a first insulating film on the ninth silicon carbide layer; forming a third electrode on the first insulating film; forming a second insulating film on the third electrode; and forming a second electrode on the third electrode, the second insulating film, and the tenth silicon carbide layer. (Technical proposal 9) A first silicon carbide layer; and １７ cm －３ atoms / cm ３ That's 1 x 10 １９ cm －３ atoms / cm ３ a fifth silicon carbide layer provided on the fifth silicon carbide layer, the fifth silicon carbide layer having a first conductivity type impurity concentration of less than 5×10 １７ cm －３ atoms / cm ３ That's 1 x 10２０ cm －３ atoms / cm ３ a third silicon carbide layer having a thickness of 0.5 μm or more and 20 μm or less, and a fourth silicon carbide layer provided on the third silicon carbide layer and having a first conductivity type impurity concentration lower than that of the third silicon carbide layer, wherein in a region including the first silicon carbide layer and the fifth silicon carbide layer, a concentration gradient of the first conductivity type impurity is different from a concentration gradient of an impurity different from the first conductivity type impurity. (Technical Solution 10) A first silicon carbide layer; and a fourth silicon carbide layer provided on the first silicon carbide layer and having a first conductivity type impurity concentration of 1×10 １７ cm －３ atoms / cm ３ That's 1 x 10 １９ cm －３ atoms / cm ３ a fifth silicon carbide layer provided on the fifth silicon carbide layer, the fifth silicon carbide layer having a first conductivity type impurity concentration of less than 5×10 １７ cm －３ atoms / cm ３ That's 1 x 10 ２０ cm －３ atoms / cm ３ a third silicon carbide layer having a thickness of 0.5 μm or more and 20 μm or less, and a fourth silicon carbide layer provided on the third silicon carbide layer and having a first conductivity type impurity concentration lower than that of the third silicon carbide layer, wherein the BPD density of the first silicon carbide layer is 10 / cm ２ or above, wherein the BPD density of the third silicon carbide layer and the fourth silicon carbide layer is 0.1 count / cm ２ A semiconductor substrate.

[0106] 2: Silicon carbide substrate 4: First silicon carbide layer 6: Second silicon carbide layer 8: Third silicon carbide layer 10: Fourth silicon carbide layer 12: Fifth silicon carbide layer 14: Sixth silicon carbide layer 16: Seventh silicon carbide layer 18: Eighth silicon carbide layer 20: Ninth silicon carbide layer 20a: Ninth silicon carbide layer 20b: Ninth silicon carbide layer 20c: Ninth silicon carbide layer 40: Tenth silicon carbide layer 42: Eleventh silicon carbide layer 60: First electrode 62: Second electrode 70: Trench 72: First insulating film 74: Third electrode 76: Second insulating film 100: Semiconductor substrate 110: Semiconductor substrate 120 : Semiconductor substrate 200 : Semiconductor device 210 : Semiconductor device 220 : Semiconductor device 400 : Semiconductor device

Claims

1. A first silicon carbide layer is provided on the first silicon carbide layer. The first silicon carbide layer has a first conductivity type impurity concentration lower than that of the first silicon carbide layer and a first conductivity type impurity concentration of 1×10 １４ atoms / cm ３ That's 1 x 10 １７ atoms / cm ３ forming a second silicon carbide layer having a thickness of 0.001 μm or more and 0.1 μm or less by epitaxial growth on the second silicon carbide layer; １７ atoms / cm ３ That's 1 x 10 ２０ atoms / cm ３ forming a third silicon carbide layer having a thickness of 0.5 μm or more and 20 μm or less by epitaxial growth; forming a fourth silicon carbide layer having a first conductivity type impurity concentration lower than that of the third silicon carbide layer by epitaxial growth on the third silicon carbide layer; and performing a heat treatment of the first silicon carbide layer, the second silicon carbide layer, the third silicon carbide layer and the fourth silicon carbide layer.

2. In the step of performing the heat treatment on the first silicon carbide layer, the second silicon carbide layer, the third silicon carbide layer, and the fourth silicon carbide layer, a first conductive type impurity concentration of 1×10 １７ atoms / cm ３ That's 1 x 10 １８ atoms / cm ３ The method for manufacturing a semiconductor substrate according to claim 1 , further comprising forming a fifth silicon carbide layer having the following:

3. After the step of forming the second silicon carbide layer and before the step of forming the third silicon carbide layer, a first conductive type impurity having a concentration of 5×10 is formed on the second silicon carbide layer. １７ atoms / cm ３ That's 1 x 10 ２０ atoms / cm ３ forming a sixth silicon carbide layer having a thickness of 0.5 μm or more and 20 μm or less by epitaxial growth on the sixth silicon carbide layer; １４ atoms / cm ３ That's 1 x 10 １７ atoms / cm ３ forming a seventh silicon carbide layer having a thickness of 0.001 μm or more and 0.1 μm or less by epitaxial growth.

4. The method for manufacturing a semiconductor substrate according to claim 1, further comprising the step of forming the first silicon carbide layer on a silicon carbide substrate by epitaxial growth prior to the step of forming the second silicon carbide layer.

5. The first silicon carbide layer has a first conductivity type impurity concentration of 5×10 １７ atoms / cm ３ That's 1 x 10 １９ atoms / cm ３ The method for manufacturing a semiconductor substrate according to claim 1 , wherein:

6. A method for manufacturing a semiconductor device, further comprising the steps of: forming a ninth silicon carbide layer of a second conductivity type on the fourth silicon carbide layer of the semiconductor substrate according to claim 1; forming a first electrode under the first silicon carbide layer; and forming a second electrode on the ninth silicon carbide layer.

7. A method for manufacturing a semiconductor device, further comprising the steps of: forming a ninth silicon carbide layer of a second conductivity type on the fourth silicon carbide layer of the semiconductor substrate described in claim 1; forming a tenth silicon carbide layer of a first conductivity type on the ninth silicon carbide layer; forming a first electrode under the first silicon carbide layer; forming a trench extending from the tenth silicon carbide layer to the fourth silicon carbide layer; forming a first insulating film in the trench; forming a third electrode in the trench, the third electrode being provided on the ninth silicon carbide layer via the first insulating film; and forming a second electrode on the tenth silicon carbide layer.

8. A method for manufacturing a semiconductor device, further comprising the steps of: forming a ninth silicon carbide layer of a second conductivity type on the fourth silicon carbide layer of the semiconductor substrate described in claim 1; forming a tenth silicon carbide layer of a first conductivity type on the ninth silicon carbide layer; forming a first insulating film on the ninth silicon carbide layer; forming a third electrode on the first insulating film; forming a second insulating film on the third electrode; and forming a second electrode on the third electrode, the second insulating film and the tenth silicon carbide layer.

9. A first silicon carbide layer; and a first conductive type impurity having a concentration of 1×10 １７ cm －３ atoms / cm ３ That's 1 x 10 １９ cm －３ atoms / cm ３ a fifth silicon carbide layer provided on the fifth silicon carbide layer, the fifth silicon carbide layer having a first conductivity type impurity concentration of less than 5×10 １７ cm －３ atoms / cm ３ That's 1 x 10 ２０ cm －３ atoms / cm ３ a third silicon carbide layer having a thickness of 0.5 μm or more and 20 μm or less; and a fourth silicon carbide layer provided on the third silicon carbide layer and having a first conductivity type impurity concentration lower than that of the third silicon carbide layer, wherein in a region including the first silicon carbide layer and the fifth silicon carbide layer, a concentration gradient of the first conductivity type impurity is different from a concentration gradient of an impurity different from the first conductivity type impurity in a direction from the first silicon carbide layer to the fifth silicon carbide layer.

10. A first silicon carbide layer; and a first conductive type impurity having a concentration of 1×10 １７ cm －３ atoms / cm ３ That's 1 x 10 １９ cm －３ atoms / cm ３ a fifth silicon carbide layer provided on the fifth silicon carbide layer, the fifth silicon carbide layer having a first conductivity type impurity concentration of less than 5×10 １７ cm －３ atoms / cm ３ That's 1 x 10 ２０ cm －３ atoms / cm ３ a third silicon carbide layer having a thickness of 0.5 μm or more and 20 μm or less; and a fourth silicon carbide layer provided on the third silicon carbide layer and having a first conductivity type impurity concentration lower than that of the third silicon carbide layer, wherein the BPD density of the first silicon carbide layer is 10 / cm ２ and wherein the BPD density of the third silicon carbide layer and the fourth silicon carbide layer is 0.1 pieces / cm ２ A semiconductor substrate.

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