Wafer planarization method

Abstract

A wafer planarization method according to an embodiment of the present invention comprises the steps of: coating a wafer with a coating material; preparing a template, which is fixed to an upper chuck and is coated with a release agent; inserting the wafer and the upper chuck into a chamber, and pressing the coating material on the wafer with the template in a vacuum atmosphere; and releasing the vacuum in the chamber in the vacuum atmosphere and unloading the upper chuck from the wafer.

Description

Wafer planarization method

[0001] The present invention relates to a wafer flattening method, and more particularly, to a wafer flattening method using an imprint method.

[0002] As demand for ultra-high-density semiconductors grows, the development of new process technologies and related equipment requires competitiveness. Furthermore, the semiconductor industry is continuously striving to reduce manufacturing costs by reducing defects and the number of processes involved in the manufacturing process.

[0003] Planarization techniques are useful in the manufacture of semiconductor devices. For example, the process for creating semiconductor devices involves repeatedly adding and removing material to and from a substrate.

[0004] This process can produce laminated substrates with irregular height variations (i.e., topography), and the more layers added, the greater the substrate height variation.

[0005] Height variations negatively impact the ability to add additional layers to a laminated substrate. Separately, semiconductor substrates (e.g., silicon wafers) themselves are not always perfectly flat and may contain initial surface height variations (i.e., topography).

[0006] One way to address this problem is to flatten the substrate between lamination steps.

[0007] When coating a stepped substrate using a conventional spin coating method, a difference in coating thickness occurs between the stepped and non-stepped areas. This difference in coating thickness can lead to a "Not Open" defect in subsequent processes.

[0008] To solve these problems, processes such as coating, CMP (Chemical Mechanical Polishing), and cleaning are being added to reduce the lower film step, but this ultimately leads to an increase in manufacturing costs, which is causing a decrease in cost competitiveness.

[0009] Another method for improving flatness is to utilize imprinting lithography technology. This relatively simplified process ensures productivity and price competitiveness.

[0010] Republic of Korea Patent Publication No. 2022-0028124 (published on March 8, 2022), titled "Planarization Process, Device, and Method for Manufacturing Articles," describes a wafer planarization process. The patent utilizes a fluid distributor to deposit droplets of a planarization material onto the wafer, and then hardens the material using UV curing.

[0011] However, this process makes it difficult to precisely control the amount of droplets injected from the fluid dispenser and predict the thickness of the deposits on the wafer. Furthermore, for UV curing, the top plate must be constructed of a material that is transparent to UV light.

[0012] An object of the present invention is to provide a method for performing wafer planarization through an imprinting lithography process.

[0013] In addition, the purpose is to provide a wafer flattening method that can improve productivity through a simpler process than the existing process.

[0014] A wafer planarization method according to an embodiment of the present invention includes a step of coating a wafer with a coating material, a step of preparing a template fixed to an upper chuck and coated with a release agent, a step of placing the wafer and the upper chuck into a chamber and pressing the coating material on the wafer with the template in a vacuum atmosphere, and a step of releasing the vacuum in the chamber in a vacuum atmosphere and unloading the upper chuck from the wafer.

[0015] The step of coating the above wafer with a coating material includes a step of spin-coating SOC (Spin On Carbon) onto the wafer.

[0016] The step of preparing a template coated with a release agent and fixed to the upper chuck includes a step of coating trichloro silane on the template.

[0017] In addition, the step of coating trichlorosilane on the template includes the steps of preparing a solution by dissolving 0.1 (vol%) of HDFS in N-Haxane (normal nucleic acid), the step of adding the template to the solution and causing a reaction, the step of washing the template in which the reaction has occurred with n-Haxane and then with DI water, the step of ultrasonically cleaning with HFE solution, and the step of washing with DI water and removing surface moisture with N2 gas.

[0018] Additionally, the step of placing the wafer and the upper chuck into the chamber and pressing the coating material on the wafer as a template in a vacuum atmosphere includes the step of heating the SOC to the glass transition temperature.

[0019] In particular, the glass transition temperature may be 100°C to 200°C.

[0020] Additionally, the step of unloading the upper chuck from the wafer according to an embodiment of the present invention includes the step of lifting the edge of the template within the chamber while releasing the vacuum to separate the coating material and the template.

[0021] In addition, the wafer flattening method according to an embodiment of the present invention further includes a step of heating the wafer to 400°C after the step of separating the coating material and the template.

[0022] According to a wafer flattening method according to an embodiment of the present invention, flattening of a wafer is possible through a simple process.

[0023] Additionally, process time is shortened, improving productivity.

[0024] In addition, stable process performance is possible because deformation of the flattening material does not occur when separating the wafer from the upper chuck after pressing it.

[0025] In addition, since the process of performing conventional flattening can be utilized, existing process equipment and materials can be utilized.

[0026] Further scope of the applicability of the present invention will become apparent from the detailed description below. However, since various modifications and variations within the spirit and scope of the present invention will become apparent to those skilled in the art, it should be understood that the detailed description and specific examples, such as preferred embodiments of the present invention, are given by way of example only.

[0027] Figure 1 is a conceptual diagram of a wafer flattening method according to an embodiment of the present invention.

[0028] Figure 2 is a flowchart of a wafer flattening method according to an embodiment of the present invention.

[0029] Figure 3 shows the results of an experiment to determine the uniformity of a quartz glass template and whether the template is damaged according to the pressure applied to the wafer.

[0030] Figure 4 shows the results of testing the degree of insolubility according to the type of solvent and the concentration of trichlorosilane added according to an embodiment of the present invention.

[0031] Figure 5 is a flowchart of a method for coating trichlorosilane on a template according to an embodiment of the present invention.

[0032] Specific structural or functional descriptions of embodiments according to the concept of the present invention disclosed in this specification are merely illustrative for the purpose of explaining embodiments according to the concept of the present invention, and embodiments according to the concept of the present invention may be implemented in various forms and are not limited to the embodiments described in this specification.

[0033] While terms such as "first" or "second" may be used to describe various components, these components should not be limited by these terms. These terms are only intended to distinguish one component from another. For example, a first component may be referred to as a "second component," and similarly, a second component may be referred to as a "first component," without departing from the scope of the present invention.

[0034] When a component is referred to as being "connected" or "connected" to another component, it should be understood that it may be directly connected or connected to that other component, but that there may be other components in between. Conversely, when a component is referred to as being "directly connected" or "directly connected" to another component, it should be understood that there are no other components in between. Other expressions that describe the relationship between components, such as "between" and "directly between" or "adjacent to" and "directly adjacent to", should be interpreted similarly.

[0035] The terminology used herein is merely used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this specification, it should be understood that the terms "comprises" or "has" indicate the presence of a feature, number, step, operation, component, part, or combination thereof described in this specification, but do not exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0036] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings attached to this specification.

[0037] Figure 1 is a conceptual diagram of a wafer flattening method according to an embodiment of the present invention.

[0038] Figure 2 is a flowchart of a wafer flattening method according to an embodiment of the present invention.

[0039] As illustrated in FIGS. 1 and 2, a wafer planarization method according to an embodiment of the present invention includes a step (S100) of coating a wafer (100) with a coating material (110), a step (S200) of preparing a template (300) fixed to an upper chuck (200) and coated with a release agent (310), a step (S300) of putting the wafer (100) and the upper chuck (200) into a chamber (400) and pressing the coating material (110) on the wafer (100) with the template (300) in a vacuum atmosphere, and a step (S400) of releasing the vacuum in the chamber (400) in the vacuum atmosphere and unloading the upper chuck (200) from the wafer (100).

[0040] The step (S100) of coating a wafer (100) with a coating material (110) is a step of spin-coating the coating material (110) on the upper surface of the wafer (100), as illustrated in FIG. 1. The coating material (110) is a SOC (Spin On Carbon hardmask), which is a coating material (110) that is mainly applied by spin-coating in a process where the flatness of the lower film is an issue.

[0041] As a coating material (110) according to an embodiment of the present invention, it is preferable that the SOC has a characteristic of improving flowability by making the polymer chain long, maintaining low viscosity for a long time with a material having a high BP (boiling point), and improving flatness by self-leveling when heated by lowering the glass transition temperature.

[0042] Table 1 below shows the results of evaluating a wafer (100) when spray-coated or slit-coated with a coating material (110) as in the aforementioned Korean Patent Publication No. 2022-0028124.

[0043] Development Results of Classification Evaluation ContentsSpray CoatingConformal Coating characteristics are further strengthenedFailure to remove stepsSlit CoatingMassive shrinkage occurs during bakingFailure to remove steps

[0044] As shown in Table 1, in the case of spray coating and slit coating, the step formed on the wafer (100) failed to be removed. As shown in FIGS. 1 and 2, the step (S200) of preparing a template (300) fixed to an upper chuck (200) and coated with a release agent (310) is a step of fixing the template (300) to the upper chuck (200) prepared in advance and coating the template (300) with a release agent (310).

[0045] The template (300) may be quartz glass, and it is preferable that the uniformity have a flatness of 0.3㎛ or less.

[0046] Figure 3 shows the results of an experiment on the uniformity of quartz glass, which is a template (300), and whether the template (300) is damaged according to the pressure applied to the wafer (100).

[0047] As shown in Fig. 3, when the quartz glass uniformity was 0.3㎛, it was found that there was no SOC surface damage due to pressure, and it was also found that there was an anisotropic characteristic.

[0048] However, when the Quartz glass uniformity was 3㎛, it was found that as the pressure increased, there was SOC surface damage (circular mark), and it was found that there was no anomaly characteristic in that an external force was applied when separating from the wafer (100).

[0049] In the step (S200) of preparing a template (300) coated with a release agent (310) according to an embodiment of the present invention, the release agent (310) includes trichlorosilane. More specifically, trichlorosilane is dissolved using a solvent, THF (L-5,6,7,8-tetrahydrofolic acid).

[0050] Figure 4 shows the results of testing the degree of insolubility according to the type of solvent and the concentration of trichlorosilane added according to an embodiment of the present invention.

[0051] As shown in Fig. 4, when 1 wt% trichlorosilane was added to THF, it was found to be dissolved without generating haze, and when trichlorosilane was added to PGMEA, it was found that haze was generated at all concentrations of 1%, 3%, and 10%.

[0052] In addition, it was found that a slight haze occurred even when 3% and 10% trichlorosilane were added to THF, and thus, the release agent (310) with 1% trichlorosilane added to THF exhibited the most ideal characteristics.

[0053] Figure 5 is a flowchart of a method for coating trichlorosilane on a template (300) according to an embodiment of the present invention.

[0054] As shown in FIG. 5, the step (S200) of coating trichlorosilane on a template (300) includes the steps of preparing a solution by dissolving 0.1 (vol%) of HDFS in N-Haxane (normal nucleic acid) (S210), the step of adding the template (300) to the solution and reacting it (S220), the step of washing the template (300) in which the reaction has occurred with n-Haxane and then washing it with DI water (S230), the step of ultrasonically cleaning it with an HFE solution (S240), and the step of washing it with DI water and removing surface moisture with N2 gas (S250).

[0055] After the step (S200) of preparing a template (300), as shown in FIGS. 1 and 2, a method of flattening a wafer (100) is to place the wafer (100) and the upper chuck (200) into a chamber (400) and press the coating material (110) on the wafer (100) with the template (300) in a vacuum atmosphere. As shown in FIG. 1, the chamber (400) is sealed by placing the wafer (100) at the bottom of the chamfer and placing the upper chuck (200) on top. In the sealed state, air inside the chamber (400) is removed to create a vacuum state.

[0056] When placed in a vacuum, the upper chuck (200) equipped with the template (300) is lowered toward the wafer (100) to pressurize the coating material (110) coated on the wafer (100). In addition, in the pressurized state, the SOC coated on the wafer (100) is heated to a glass transition temperature of 100°C to 200°C.

[0057] By heating the SOC, which is a coating material (110) coated on the upper surface of the wafer (100), to the glass transition temperature, the viscosity of the SOC is reduced. The SOC, with improved flowability, spreads while filling the pattern on the surface of the wafer (100).

[0058] Next, as shown in FIGS. 1 and 2, the step (S400) of releasing the vacuum in the vacuum atmosphere chamber (400) and unloading the upper chuck (200) from the wafer (100) is a step in which the upper chuck (200) is raised so that the template (300) is separated from the SOC.

[0059] During this process, the temperature of the SOC decreases and the viscosity increases.

[0060] The step (S400) of unloading the upper chuck (200) from the wafer (100) includes a step of lifting the edge of the template (300) inside the chamber (400) while releasing the vacuum to separate the coating material (110) and the template (300). That is, when the edge of the template (300) is physically lifted, the incoming air seeps in to separate the template (300) and the coating material (110), and as the upper chuck (200) rises, the template (300) is naturally separated from the coating material (110).

[0061] Next, as illustrated in FIGS. 1 and 2, the wafer (100) flattening method according to the embodiment of the present invention further includes a step (S500) of heating the wafer (100) to 400°C with a heater (500).

[0062] This is a process of heating a wafer (100) that has been flattened by a coating material (110) so that the polymers in the coating material (110) undergo a cross-linking reaction with each other and change into a single carbon lump.

[0063] Before undergoing this cross-linking process, the coating material (110) is a polymer, and after undergoing the cross-linking process, it becomes a large carbon lump with unlimited molecular weight to form a hard layer.

[0064] By performing a wafer planarization process according to an embodiment of the present invention, wafer planarization can be achieved through a relatively simple process, thereby reducing process time and improving productivity. Furthermore, a highly reliable wafer planarization method can be provided by utilizing a coating material and release agent optimized for a planarization process utilizing an imprinting process.

[0065]

[0066] The present invention is susceptible to various modifications and embodiments. Specific embodiments are illustrated in the drawings and described in detail in the detailed description. However, this is not intended to limit the present invention to specific embodiments, but rather to encompass all modifications, equivalents, and alternatives falling within the spirit and technical scope of the present invention.

Claims

1. As a wafer flattening method, (a) a step of coating a wafer with a coating material; (b) a step of preparing a template fixed to the upper chuck and coated with a release agent; (c) a step of placing the wafer and the upper chuck into a chamber and pressing the coating material on the wafer with a template in a vacuum atmosphere; and (d) A wafer flattening method characterized by including a step of releasing the vacuum in a vacuum atmosphere chamber and unloading the upper chuck from the wafer.

2. In paragraph 1, The above step (a) A wafer planarization method comprising a step of spin-coating SOC (Spin On Carbon) on a wafer.

3. In paragraph 1, Step (b) above A wafer planarization method comprising a step of coating trichlorosilane on a template.

4. In paragraph 3, The step of coating trichlorosilane on the above template is A step of preparing a solution by dissolving 0.1 (vol%) of HDFS in N-Haxane (normal nucleic acid); A step of adding a template to the above solution and causing a reaction; A step of washing the template in which the above reaction has been performed with n-Haxane and then with DI water; Step of ultrasonic cleaning with HFE solution; and A wafer planarization method characterized by including a step of washing with DI water and removing surface moisture with N2 gas.

5. In paragraph 2, Step (c) above A wafer planarization method characterized by comprising a step of heating the above SOC to a glass transition temperature.

6. In paragraph 5, A wafer flattening method, characterized in that the glass transition temperature is 100°C to 200°C.

7. In paragraph 1, The above step (d) A wafer planarization method comprising a step of lifting an edge of a template within a chamber while releasing a vacuum to separate the coating material and the template.

8. In paragraph 1, After step (d) above, A wafer flattening method, characterized in that it further comprises a step of heating the wafer to 400°C.

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