Integrated optoelectronic module

Abstract

A method for fabricating optoelectronic modules (42a, 42b, 42c, 42d, 42e) includes designating an array of module locations (24) on a wafer substrate (20) and forming respective electrical connection terminals (26) on the wafer substrate at each of the module locations. In each module location, at least two optoelectronic semiconductor components (28, 30) are placed on the wafer substrate in mutual optical alignment and are connected electrically to the respective electrical connection terminals. Lids (38) are fixed to the wafer substrate over the optoelectronic semiconductor components at the array of modulate locations. After fixing the lids, the wafer substrate is diced to singulate the optoelectronic modules.

Description

[0001] INTEGRATED OPTOELECTRONIC MODULE

[0002] CROSS-REFERENCE TO RELATED APPLICATION

[0003] This application claims the benefit of U.S. Provisional Patent Application 63 / 514,395, filed July 19, 2023, which is incorporated herein by reference.

[0004] FIELD

[0005] The present invention relates generally to integrated optoelectronic devices, and particularly to integration of devices incorporating multiple optoelectronic and photonic technologies.

[0006] BACKGROUND

[0007] Silicon photonic integrated circuits (PICs) are commonly used in optical transmitter and transceiver arrays. Some active optoelectronic components, however, such as semiconductor lasers and semiconductor optical amplifiers (SOAs), comprise IILV semiconductor compounds (such as GaAs or InP). These components are typically fabricated on a III-V wafer. After fabrication, the III-V wafer is diced to produce singulated III-V chiplets, which are then aligned and mounted in the appropriate locations on the silicon PIC. The PIC may also be connected to one or more electronic integrated circuits (EICs), such as complementary metal-oxide semiconductor (CMOS) chips, to drive, control, and process signals output by the optoelectronic components on the PIC.

[0008] Multi-chip PIC assemblies are described, for example, in PCT International Publications WO 2023 / 076132, WO 2023 / 034465, and WO 2023 / 023106, whose disclosures are incorporated herein by reference. Specifically, WO 2023 / 076132 describes a scheme in which an optoelectronic device includes a carrier substrate and a photonic integrated circuit (PIC). The PIC includes a PIC substrate, having a first side mounted on the carrier substrate, first electrical connection pads disposed on a second side of the PIC substrate, opposite the first side, optical waveguides disposed on the PIC substrate, and electrical conductors disposed on the PIC substrate and connecting to one or more of the first electrical connection pads. At least one electronic integrated circuit includes a semiconductor substrate having a third side mounted on the second side of the PIC substrate, second electrical connection pads disposed on the semiconductor substrate in electrical communication with the first electrical connection pads, and one or more electronic circuit components disposed on the semiconductor substrate and connected electrically to the second electrical connection pads. The terms “optical radiation” and “light” are used synonymously in the present description and in the claims to refer to electromagnetic radiation in any or all of the visible, infrared, and ultraviolet spectral ranges.

[0009] SUMMARY

[0010] Embodiments of the present invention that are described hereinbelow provide improved integrated optoelectronic devices and methods for their fabrication.

[0011] There is therefore provided, in accordance with an embodiment of the invention, a method for fabricating optoelectronic modules. The method includes designating an array of module locations on a wafer substrate and forming respective electrical connection terminals on the wafer substrate at each of the module locations. In each module location, at least two optoelectronic semiconductor components are placed on the wafer substrate in mutual optical alignment and are connected electrically to the respective electrical connection terminals. Lids are fixed to the wafer substrate over the optoelectronic semiconductor components at the array of modulate locations. After fixing the lids, the wafer substrate is diced to singulate the optoelectronic modules.

[0012] In some embodiments, the wafer substrate includes a semiconductor wafer. In a disclosed embodiment, the method includes forming electrical traces on the semiconductor wafer to define a redistribution layer, which connects the optoelectronic semiconductor components to the electrical connection terminals.

[0013] Alternatively, the wafer substrate includes a dielectric material.

[0014] In some embodiments, the method includes fixing a respective thermo-electric cooler in each module location, wherein at least one of the optoelectronic semiconductor components is mounted on the thermo-electric cooler. In a disclosed embodiment, designating the array of module locations includes forming a respective cavity in the wafer substrate in each module location, and wherein fixing the respective thermo-electric cooler includes mounting the respective thermo-electric cooler in the respective cavity.

[0015] In some embodiments, forming the respective electrical connection terminals includes forming ball grid arrays. Alternatively or additionally, forming the respective electrical connection terminals includes forming wire bond pads.

[0016] In some embodiments, the at least two optoelectronic components are placed on an upper side of the wafer substrate, and forming the respective electrical connection terminals includes forming the electrical connection terminals on the upper side of the wafer substrate. In a disclosed embodiment, the electrical connection terminals are disposed outside an area of the wafer substrate that is covered by the lids.

[0017] Alternatively, the at least two optoelectronic components are placed on an upper side of the wafer substrate, and forming the respective electrical connection terminals includes forming the electrical connection terminals on a lower side of the wafer substrate, opposite the upper side, and forming vias through the wafer substrate to connect the optoelectronic components to the electrical connection terminals.

[0018] In a disclosed embodiment, placing the at least two optoelectronic semiconductor components includes aligning the at least two optoelectronic semiconductor components on the wafer substrate using an active alignment process. Additionally or alternatively, placing the at least two optoelectronic semiconductor components includes coupling the optoelectronic semiconductor components together using a coupling technique selected from a list of techniques consisting of butt coupling, lens coupling, fiber coupling, and optical wire bonding.

[0019] In some embodiments, the at least two optoelectronic semiconductor components include at least one silicon photonic integrated circuit (PIC). Additionally or alternatively, the at least two optoelectronic semiconductor components further include at least one active optical component including a III-V semiconductor compound.

[0020] In a disclosed embodiment, coupling at least one electronic integrated circuit to at least one of the optoelectronic semiconductor components in each module location.

[0021] Additionally or alternatively, fixing the lids includes sealing the lids hermetically to the wafer substrate.

[0022] In some embodiments, the lids each include a metal case with a transparent window aligned with at least one of the optoelectronic semiconductor components. Alternatively or additionally, the lids include a semiconductor material.

[0023] There is also provided, in accordance with an embodiment of the invention, an article of manufacture, including a wafer substrate, on which an array of module locations is defined. Respective electrical connection terminals are disposed on the wafer substrate at each of the module locations. At least two optoelectronic semiconductor components are disposed on the wafer substrate in each module location, in mutual optical alignment. Conductors connect the optoelectronic semiconductor components electrically to the respective electrical connection terminals. Lids are fixed to the wafer substrate over the optoelectronic semiconductor components at the array of modulate locations. There is additionally provided, in accordance with an embodiment of the invention, an optoelectronic module, which is fabricated by dicing the article of manufacture described above.

[0024] The present invention will be more fully understood from the following detailed description of the embodiments thereof, taken together with the drawings in which:

[0025] BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Fig. 1 is a schematic pictorial illustration of a semiconductor wafer on which multiple integrated optoelectronic modules are assembled, in accordance with an embodiment of the invention;

[0027] Fig. 2 is a schematic pictorial illustration of an assembled array of integrated optoelectronic modules, in accordance with an embodiment of the invention; and

[0028] Figs. 3A, 3B, 3C, 3D and 3E are schematic sectional views of integrated optoelectronic modules, in accordance with embodiments of the invention.

[0029] DETAILED DESCRIPTION

[0030] Assembly of multi-chip optoelectronic modules typically involves multiple steps of picking, placing, and aligning optical and optoelectronics components and connecting them to associated electronics. Such processes can be laborious and costly.

[0031] Embodiments of the present invention that are described herein provide methods for waferlevel assembly, testing, and co-packaging of modules comprising photonic and electronic integrated circuits, as well as integrated devices that are manufactured by such methods. The modules may include both active and passive optoelectronic components and optical elements. The wafer-level assembly operations extend from placing and aligning optoelectronic components on the wafer substrate and making electrical connections between the components and connection terminals on the substrate, through fixing lids over the components in each module. Performing the operations at the wafer level simplifies the processes of component placement and alignment and eliminates the need to align each module individually. The wafer is diced to singulate the modules only after all components have been assembled and capped with the lids.

[0032] The present methods may be applied, for example, in assembling optical engines for sensing application, such as the sorts of assemblies described in the above-mentioned PCT publications. Alternatively, these methods may be adapted, mutatis mutandis, for use in assembly of various other types of multi-component optoelectronic modules.

[0033] Thus, the present embodiments provide a method for fabricating optoelectronic modules in which an array of module locations is designated on a wafer substrate. Respective electrical connection terminals are formed on the wafer substrate at each of the module locations. At least two optoelectronic semiconductor components are placed on the wafer substrate at each module location in mutual optical alignment, using passive or active alignment as appropriate. The optoelectronic semiconductor components are coupled electrically to the respective electrical connection terminals, either directly or through one or more electronic integrated circuits, which may also be incorporated in each of the modules. After assembling the components on the wafer substrates, lids are fixed to the wafer substrate at the array of module locations over the optoelectronic semiconductor components. After fixing the lids, the wafer substrate is diced to singulate the optoelectronic modules.

[0034] Fig. 1 is a schematic pictorial illustration of a wafer substrate 20 on which module components 22 are assembled at an array of module locations 24, in accordance with an embodiment of the invention. In the present embodiment, wafer substrate 20 comprises a semiconductor wafer, such as a silicon wafer. Alternatively, wafer substrate 20 may comprise a dielectric material, such as glass, aluminum nitride, or alumina, for example. Electrical connection terminals 26 are formed on wafer substrate 20 at each of module locations 24. Electrical traces on the wafer substrate (as shown in Figs. 3A-3E) define a redistribution layer, which connects module components 22 in each module location 24 to electrical connection terminals 26.

[0035] Components 22 comprise at least two optoelectronic semiconductor components placed on wafer substrate 20 in each module location 24 in mutual optical alignment. In the present example, components 22 comprise multiple silicon PICs 28 and an active optical component 30, such as a semiconductor laser, comprising a III-V semiconductor compound. Active optical component 30 is aligned with PICs 28 with the assistance of one or more microlenses 32. Alternatively or additionally, the optoelectronic semiconductor components may be coupled together on substrate 20 using other methods, such as butt coupling, fiber coupling, or optical wire bonding, for example using 3D printing techniques. The alignment may be carried out using either passive or active alignment techniques, which are performed at the wafer level shown in Fig. 1. For active alignment, for example, an electrical drive signal may be applied to active component 30, causing it to emit light, and the signals output by detectors in PICs 28 may be measured while manipulating microlenses 32.

[0036] Components 22 of each module also comprise electronic integrated circuits (EICs) 34, 36, which are connected to the optoelectronic semiconductor components at each module location 24. In the pictured example, EIC 34 is mounted on one of PICs 28, in the manner described in the above-mentioned PCT publication WO 2023 / 076132, while EIC 36 is mounted directly on wafer substrate 20. As noted above, PICs 28, active optical component 30, and EICs 34 and 36 are connected electrically to respective electrical connection terminals 26, typically by electrical traces on substrate 20.

[0037] The optoelectronic modules on wafer substrate 20 may serve a wide range of purposes. For example, the optoelectronic and optical components may be used to condition, transmit and receive multiple beams of light as channels of a multi-channel transmitter or transceiver system, for example as described in described in the above-mentioned PCT publication WO 2023 / 023106. These details of the modules and components, however, are beyond the scope of the present description.

[0038] After all components 22 have been placed, connected, and aligned on wafer substrate 20, lids 38 are fixed to the wafer substrate over the components at module location 24. Lids 38 may comprise substantially any suitable material, such as a metal, semiconductor, or dielectric material, or a combination of materials. Various different types of lids are shown in Figs. 3A-3E. Lids 38 may be hermetically sealed to wafer substrate 20. After the lids have been fixed in place, wafer substrate 20 is diced to singulate the optoelectronic modules.

[0039] Fig. 2 is a schematic pictorial illustration of an assembled array 40 of integrated optoelectronic modules 42, in accordance with an embodiment of the invention. Array 40 is an article of manufacture that is fabricated by the methods described above with reference to Fig. 1 and includes the components shown in Fig. 1 (most of which are hidden by lids 38 in Fig. 2).

[0040] After lids 38 have been fixed in place, wafer substrate 20 is diced to singulate optoelectronic modules 42. In this embodiment, electrical connection terminals 26 are formed on the same side of wafer substrate 20 as the components of modules 42 (referred to here arbitrarily as the “upper side”), outside the areas that are covered by lids 38. Electrical connection terminals 26 may comprise ball grid arrays of solder bumps, in which case modules 42 can be mounted on a rigid or flexible printed circuit substrate in a flip-chip configuration. (For this purpose, a hole may be cut in the printed circuit substrate to accommodate lid 38). Alternatively, electrical connection terminals 26 may be wire-bonded to corresponding pads on the printed circuit substrate. Further alternatively, the electrical connection terminals may be formed on the lower side of wafer substrate 20, for example as shown in Fig. 3E.

[0041] Fig. 3A is a schematic sectional view of an integrated optoelectronic module 42a, in accordance with an embodiment of the invention. Module 42a, as well as the modules shown in Figs. 3B-3E, is an example of the types of modules 42 that can be produced in and then singulated from array 40, using the techniques described above. In these simplified views, only a single PIC 28 is shown as an example of components 22.

[0042] In module 42a, as well as in the modules described below, wafer substrate 20 comprises silicon, with electrical traces 44 defining a redistribution layer and connecting PIC 28 to solder ball terminals 26a and / or wire bond terminal pads 26b. PIC 28 is connected to traces 44 by wire bonds 46. Alternatively, PIC 28 may be configured as a flip-chip device, with terminals soldered to pads (not shown) on substrate 20.

[0043] Lid 38 comprises a metal case 48 with a transparent window 50, which is aligned with at least one of the optoelectronic semiconductor components to allow light to enter and / or exit module 42a. Window 50 may comprise glass, silicon, plastic, or any other suitable material that is transparent in the spectral range of interest. Optionally, window 50 can be integrated with one or more additional optical elements (not shown), such as a transparent conductive layer (for example indium tin oxide - ITO), a diffractive optical element or metalens, a circulator, a beam displacer, or a waveplate.

[0044] Fig. 3B is a schematic sectional view of an integrated optoelectronic module 42b, in accordance with another embodiment of the invention. Elements in this figure and in the figures that follow that are similar to corresponding elements in Fig. 3 A are labeled with the same indicator numbers, and repetition of the descriptions of these elements are omitted for the sake of brevity.

[0045] In addition to the elements in Fig. 3A, module 42b comprises a thermo-electric cooler 60. A silicon optical bench 62 is mounted over and bonded to cooler 60, and an optoelectronic semiconductor component is mounted on the silicon optical bench. In the pictured example, PIC 28 is mounted over cooler 60; but alternatively or additionally, active optical component 30 may be cooled in this fashion. Thermo-electric coolers 60 and silicon optical benches 62 are assembled at the wafer level in each module location prior to capping and dicing of modules 42b.

[0046] Fig. 3C is a schematic sectional view of an integrated optoelectronic module 42c, in accordance with yet another embodiment of the invention. This embodiment is similar to the embodiment of Fig. 3B, except that a respective cavity 64 is formed in wafer substrate 20 in each module location. The respective thermo-electric cooler 60 is mounted in the respective cavity to lower the module profde and improve heat dissipation.

[0047] Fig. 3D is a schematic sectional view of an integrated optoelectronic module 42d, in accordance with an alternative embodiment of the invention. In place of the metal lids of the preceding embodiments, module 42d has a lid 66 comprising a semiconductor material, such as silicon. Lid 66 comprises a transparent cap 68, which may likewise comprise a semiconductor material or alternatively, glass or another suitable dielectric material.

[0048] Fig. 3E is a schematic sectional view of an integrated optoelectronic module 42e, in accordance with a further embodiment of the invention. In contrast to the preceding embodiments, while the optoelectronic components of module 42e, such as PIC 28, are placed on the upper side of wafer substrate 20, electrical connection terminals 70 are formed on the opposite, lower side of the wafer substrate. Vias 72, such as through-silicon vias (TSVs), pass through wafer substrate 20 and connect electrical traces 44 to electrical connection terminals 70, thus connecting the terminals to the optoelectronic components. The embodiments described above are cited by way of example, and the present invention is not limited to what has been particularly shown and described hereinabove. Rather, the scope of the present invention includes both combinations and subcombinations of the various features described hereinabove, as well as variations and modifications thereof which would occur to persons skilled in the art upon reading the foregoing description and which are not disclosed in the prior art.

Claims

CLAIMS1. A method for fabricating optoelectronic modules, the method comprising: designating an array of module locations on a wafer substrate; forming respective electrical connection terminals on the wafer substrate at each of the module locations; in each module location, placing at least two optoelectronic semiconductor components on the wafer substrate in mutual optical alignment and connecting the optoelectronic semiconductor components electrically to the respective electrical connection terminals; fixing lids to the wafer substrate over the optoelectronic semiconductor components at the array of modulate locations; and after fixing the lids, dicing the wafer substrate to singulate the optoelectronic modules.

2. The method according to claim 1, wherein the wafer substrate comprises a semiconductor wafer.

3. The method according to claim 2, and comprising forming electrical traces on the semiconductor wafer to define a redistribution layer, which connects the optoelectronic semiconductor components to the electrical connection terminals.

4. The method according to claim 1, wherein the wafer substrate comprises a dielectric material.

5. The method according to claim 1 , and comprising fixing a respective thermo-electric cooler in each module location, wherein at least one of the optoelectronic semiconductor components is mounted on the thermo-electric cooler.

6. The method according to claim 5, wherein designating the array of module locations comprises forming a respective cavity in the wafer substrate in each module location, and wherein fixing the respective thermo-electric cooler comprises mounting the respective thermo-electric cooler in the respective cavity.

7. The method according to claim 1, wherein forming the respective electrical connection terminals comprises forming ball grid arrays.

8. The method according to claim 1, wherein forming the respective electrical connection terminals comprises forming wire bond pads.

9. The method according to any of claims 1-8, wherein the at least two optoelectronic components are placed on an upper side of the wafer substrate, and wherein forming the respective electrical connection terminals comprises forming the electrical connection terminals on the upper side of the wafer substrate.

10. The method according to claim 9, wherein the electrical connection terminals are disposed outside an area of the wafer substrate that is covered by the lids.

11. The method according to any of claims 1-8, wherein the at least two optoelectronic components are placed on an upper side of the wafer substrate, and wherein forming the respective electrical connection terminals comprises forming the electrical connection terminals on a lower side of the wafer substrate, opposite the upper side, and forming vias through the wafer substrate to connect the optoelectronic components to the electrical connection terminals.

12. The method according to any of claims 1-8, wherein placing the at least two optoelectronic semiconductor components comprises aligning the at least two optoelectronic semiconductor components on the wafer substrate using an active alignment process.

13. The method according to any of claims 1 -8, wherein placing the at least two optoelectronic semiconductor components comprises coupling the optoelectronic semiconductor components together using a coupling technique selected from a list of techniques consisting of butt coupling, lens coupling, fiber coupling, and optical wire bonding.

14. The method according to any of claims 1-8, wherein the at least two optoelectronic semiconductor components comprise at least one silicon photonic integrated circuit (PIC).

15. The method according to claim 14, wherein the at least two optoelectronic semiconductor components further comprise at least one active optical component comprising a III-V semiconductor compound.

16. The method according to any of claims 1-8, and comprising coupling at least one electronic integrated circuit to at least one of the optoelectronic semiconductor components in each module location.

17. The method according to any of claims 1-8, wherein fixing the lids comprises sealing the lids hermetically to the wafer substrate.

18. The method according to any of claims 1-8, wherein the lids each comprise a metal case with a transparent window aligned with at least one of the optoelectronic semiconductor components.

19. The method according to any of claims 1-8, wherein the lids comprise a semiconductor material.

20. An article of manufacture, comprising: a wafer substrate, on which an array of module locations is defined; respective electrical connection terminals disposed on the wafer substrate at each of the module locations; at least two optoelectronic semiconductor components disposed on the wafer substrate in each module location, in mutual optical alignment; conductors connecting the optoelectronic semiconductor components electrically to the respective electrical connection terminals; and lids fixed to the wafer substrate over the optoelectronic semiconductor components at the array of modulate locations.

21. The article according to claim 20, wherein the wafer substrate comprises a semiconductor wafer.

22. The article according to claim 21, and comprising electrical traces disposed on the semiconductor wafer to define a redistribution layer, which connects the optoelectronic semiconductor components to the electrical connection terminals.

23. The article according to claim 20, wherein the wafer substrate comprises a dielectric material.

24. The article according to claim 20, and comprising a respective thermo-electric cooler in each module location, wherein at least one of the optoelectronic semiconductor components is mounted on the thermo-electric cooler.

25. The article according to claim 24, wherein a respective cavity is formed in the wafer substrate in each module location, and wherein the respective thermo-electric cooler is mounted in the respective cavity.

26. The article according to claim 20, wherein the electrical connection terminals comprise ball grid arrays.

27. The article according to claim 20, wherein the electrical connection terminals comprise wire bond pads.

28. The article according to claim 20, wherein the at least two optoelectronic components are placed on an upper side of the wafer substrate, and wherein the electrical connection terminals are disposed on the upper side of the wafer substrate.

29. The article according to claim 28, wherein the electrical connection terminals are disposed outside an area of the wafer substrate that is covered by the lids.

30. The article according to claim 20, wherein the at least two optoelectronic components are placed on an upper side of the wafer substrate, and wherein the electrical connection terminals are disposed on a lower side of the wafer substrate, opposite the upper side, and are connected by vias through the wafer substrate to the optoelectronic components.

31. The article according to claim 20, wherein the at least two optoelectronic semiconductor components are aligned on the wafer substrate using an active alignment process.

32. The article according to claim 20, wherein the optoelectronic semiconductor components are coupled together using a coupling technique selected from a list of techniques consisting of butt coupling, lens coupling, fiber coupling, and optical wire bonding.

33. The article according to claim 20, wherein the at least two optoelectronic semiconductor components comprise at least one silicon photonic integrated circuit (PIC).

34. The article according to claim 33, wherein the at least two optoelectronic semiconductor components further comprise at least one active optical component comprising a III-V semiconductor compound.

35. The article according to claim 20, and comprising at least one electronic integrated circuit coupled to at least one of the optoelectronic semiconductor components in each module location.

36. The article according to claim 20, wherein the lids are sealed hermetically to the wafer substrate.

37. The article according to claim 20, wherein the lids each comprise a metal case with a transparent window aligned with at least one of the optoelectronic semiconductor components.

38. The article according to claim 20, wherein the lids comprise a semiconductor material.

39. An optoelectronic module, which is fabricated by dicing the article of any of claims 20-38 after fixing the lids.

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