Method for manufacturing semiconductor device, semiconductor device, and vehicle

Abstract

This method for manufacturing a semiconductor device in which a base material is bonded to a heat dissipation member is configured so that the shape of sealing resin can be more favorably maintained. The manufacturing method comprises a first step, a second step, and a third step. In the first step, a base material having an insulating layer and an electroconductive layer positioned on one first-direction side of the insulating layer is bonded to the heat dissipation member. In the second step, a semiconductor element is bonded to the electroconductive layer. In the third step, sealing resin covering the semiconductor element is formed. In the first step, the base material is bonded to the heat dissipation member such that the insulating layer is positioned between the heat dissipation member and the electroconductive layer. The third step is performed after each of the first step and the second step is completed.

Description

Semiconductor device manufacturing method, semiconductor device and vehicle

[0001] The present disclosure relates to a method for manufacturing a semiconductor device, a semiconductor device obtained by the manufacturing method, and a vehicle equipped with the semiconductor device.

[0002] Conventionally, semiconductor devices equipped with semiconductor elements (such as MOSFETs and IGBTs) having switching functions have been widely known and are primarily used for power conversion. Patent Document 1 discloses an example of such a semiconductor device. The semiconductor device disclosed in this document includes a substrate (a heat sink in Patent Document 1) on which the semiconductor elements are mounted, a sealing resin (a sealing body in Patent Document 1) that covers a portion of the substrate and the semiconductor elements, and a heat dissipation member (a heat dissipation fin in Patent Document 1) that faces the substrate. The sealing resin is attached to the heat dissipation member via screws. This improves the heat dissipation performance of the semiconductor device.

[0003] In addition to the semiconductor device disclosed in Patent Document 1, a semiconductor device in which a substrate is bonded to a heat dissipation member via a bonding layer is also considered. In such a semiconductor device, the work of attaching a sealing resin to a heat dissipation member is not required. However, when attempting to bond the substrate to the heat dissipation member after forming the sealing resin, there is a concern that the sealing resin may lose its shape if the temperature at which the bonding layer is formed is relatively high.

[0004] International Publication No. 2019 / 239997

[0005] [Summary] An object of the present disclosure is to provide an improved semiconductor device compared to conventional semiconductor devices. In particular, in view of the above circumstances, an object of the present disclosure is to provide a method for manufacturing a semiconductor device in which a base material is bonded to a heat dissipation member, and which is capable of better maintaining the shape of the sealing resin.

[0006] A first aspect of the present disclosure provides a method for manufacturing a semiconductor device, comprising: a first step of bonding a substrate having an insulating layer and a conductive layer located on one side of the insulating layer in a first direction to a heat dissipation member; a second step of bonding a semiconductor element to the conductive layer; and a third step of forming a sealing resin to cover the semiconductor element. In the first step, the substrate is bonded to the heat dissipation member so that the insulating layer is located between the heat dissipation member and the conductive layer. The third step is performed after the first and second steps are completed.

[0007] A second aspect of the present disclosure provides a semiconductor device comprising: a heat dissipation member having a main surface facing one side of a first direction and an end surface facing a direction perpendicular to the first direction; a substrate having a conductive layer and bonded to the main surface; a semiconductor element bonded to the conductive layer; and a sealing resin covering the substrate and the semiconductor element. The substrate has an insulating layer located between the main surface and the conductive layer. The sealing resin is in contact with the main surface. The end surface is exposed from the sealing resin.

[0008] A vehicle provided by a third aspect of the present disclosure includes a drive source and a semiconductor device, the semiconductor device being electrically connected to the drive source, the semiconductor device being the semiconductor device provided by the second aspect of the present disclosure.

[0009] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0010] FIG. 1 is a perspective view of a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a plan view of the semiconductor device shown in FIG. 1. FIG. 3 is a right side view of the semiconductor device shown in FIG. 1. FIG. 4 is a front view of the semiconductor device shown in FIG. 1. FIG. 5 is a rear view of the semiconductor device shown in FIG. 1. FIG. 6 is a bottom view of the semiconductor device shown in FIG. 1. FIG. 7 is a plan view corresponding to FIG. 2, taken through the sealing resin and omitting the illustration of the heat dissipation member. FIG. 8 is a plan view corresponding to FIG. 2, taken through the sealing resin and omitting the illustration of the second conductive member and the heat dissipation member. FIG. 9 is a plan view corresponding to FIG. 2, taken through the sealing resin and omitting the illustration of the first conductive member, the second conductive member, and the heat dissipation member. FIG. 10 is a cross-sectional view taken along line X-X in FIG. 7. FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 7. FIG. 12 is a partially enlarged view of the first semiconductor element and its periphery shown in FIG. 11. FIG. 13 is a partially enlarged view of the second semiconductor element and its periphery shown in FIG. 11 . FIG. 14 is a cross-sectional view taken along line XIV-XIV in FIG. 7 . FIG. 15 is a cross-sectional view taken along line XV-XV in FIG. 7 . FIG. 16 is a partially enlarged view of FIG. 10 . FIG. 17 is a cross-sectional view of a semiconductor device according to a first modified example of the first embodiment of the present disclosure, corresponding to FIG. 11 . FIG. 18 is a partially enlarged cross-sectional view of a semiconductor device according to a second modified example of the first embodiment of the present disclosure, corresponding to FIG. 16 . FIG. 19 is a cross-sectional view illustrating a manufacturing process of the semiconductor device shown in FIG. 1 . FIG. 20 is a cross-sectional view illustrating a manufacturing process of the semiconductor device shown in FIG. 1 . FIG. 21 is a cross-sectional view illustrating a manufacturing process of the semiconductor device shown in FIG. 1 . FIG. 22 is a cross-sectional view illustrating a manufacturing process of the semiconductor device shown in FIG. 1 . FIG. 23 is a cross-sectional view illustrating a manufacturing process of the semiconductor device shown in FIG. 17 . FIG. 24 is a cross-sectional view illustrating a manufacturing process of the semiconductor device shown in FIG. 17 . FIG. 25 is a schematic diagram of a vehicle equipped with the semiconductor device shown in FIG. 1 . FIG. 26 is a plan view of a semiconductor device according to a second embodiment of the present disclosure. Fig. 27 is a cross-sectional view of the semiconductor device shown in Fig. 26 and corresponds to Fig. 10. Fig. 28 is a cross-sectional view of the semiconductor device shown in Fig. 26 and corresponds to Fig. 11. Fig. 29 is a partially enlarged cross-sectional view illustrating a manufacturing process of the semiconductor device shown in Fig. 26. Fig. 30 is a plan view of a semiconductor device according to a third embodiment of the present disclosure.FIG. 31 is a cross-sectional view of the semiconductor device shown in FIG. 30 and corresponds to FIG. 11 . FIG. 32 is a cross-sectional view of a semiconductor device according to a modified example of the third embodiment of the present disclosure and corresponds to FIG. 31 . FIG. 33 is a cross-sectional view illustrating a manufacturing process of the semiconductor device shown in FIG. 30 . FIG. 34 is a plan view of a semiconductor device according to a fourth embodiment of the present disclosure. FIG. 35 is a cross-sectional view of the semiconductor device shown in FIG. 34 and corresponds to FIG. 10 . FIG. 36 is a cross-sectional view of the semiconductor device shown in FIG. 34 and corresponds to FIG. 11 . FIG. 37 is a cross-sectional view illustrating a manufacturing process of the semiconductor device shown in FIG. 34 . FIG. 38 is a cross-sectional view illustrating a manufacturing process of the semiconductor device shown in FIG. 34 . FIG. 39 is a plan view of a semiconductor device according to a fifth embodiment of the present disclosure. FIG. 40 is a cross-sectional view of the semiconductor device shown in FIG. 39 and corresponds to FIG. 10 . FIG. 41 is a cross-sectional view of the semiconductor device shown in FIG. 39 and corresponds to FIG. 11 . FIG. 42 is a cross-sectional view illustrating a manufacturing process of the semiconductor device shown in FIG. 39 . FIG. 43 is a cross-sectional view illustrating a manufacturing process of the semiconductor device shown in FIG. 39 .

[0011] DETAILED DESCRIPTION The present disclosure will be described in detail with reference to the accompanying drawings.

[0012] First Embodiment: A semiconductor device A10 according to a first embodiment of the present disclosure will be described with reference to Figures 1 to 16. The semiconductor device A10 includes a substrate 11, a first bonding layer 19, a first power terminal 13, two second power terminals 14, two third power terminals 15, a plurality of semiconductor elements 20, a first conductive member 31, a second conductive member 32, a second bonding layer 39, a sealing resin 50, and a heat dissipation member 70. The semiconductor device A10 further includes a first signal terminal 161, a second signal terminal 162, a third signal terminal 171, a fourth signal terminal 172, two fifth signal terminals 181, two sixth signal terminals 182, two thermistors 23, a first wiring 61, and a second wiring 62. For ease of understanding, Figures 7 to 9 show perspective views through the sealing resin 50 and omit the heat dissipation member 70. 7 to 9, the transmitted sealing resin 50 is indicated by an imaginary line (two-dot chain line). For ease of understanding, the second conductive member 32 is also omitted from illustration in Fig. 8. For ease of understanding, the first conductive member 31 and the second conductive member 32 are also omitted from illustration in Fig. 9.

[0013] In the description of the semiconductor device A10, for convenience, the normal direction to a main surface 711 of a heat dissipation member 70 (described later) is referred to as the "first direction z." The direction perpendicular to the first direction z is referred to as the "second direction x." The direction perpendicular to both the first direction z and the second direction x is referred to as the "third direction y."

[0014] The semiconductor device A10 converts DC power input to the first power terminal 13 and the two second power terminals 14 into AC power using a plurality of semiconductor elements 20. The converted AC power is input from each of the two third power terminals 15 to a power supply target such as a motor.

[0015] The heat dissipation member 70 is used to cool the semiconductor device A 10. The heat dissipation member 70 contains metal. The heat dissipation member 70 is made of a material containing, for example, aluminum (Al).

[0016] 3 to 5, the heat dissipation member 70 has a base 71, a main surface 711, multiple end surfaces 712, and a heat dissipation portion 72. The base 71 is flat. The main surface 711 and the multiple end surfaces 712 are included in the base 71. The main surface 711 faces one side in the first direction z. In the semiconductor device A10, a portion of the main surface 711 is exposed from the sealing resin 50. Each of the multiple end surfaces 712 faces in a direction perpendicular to the first direction z. Each of the multiple end surfaces 712 is exposed from the sealing resin 50.

[0017] 3 to 5, the heat dissipation portion 72 is connected to the base portion 71. The heat dissipation portion 72 protrudes from the base portion 71 on the side opposite to the side toward which the main surface 711 faces in the first direction z. In the semiconductor device A10, the heat dissipation portion 72 has a rectangular parallelepiped shape. Alternatively, the heat dissipation portion 72 may be a plurality of fins arranged in a direction perpendicular to the first direction z. As shown in FIG. 6, the heat dissipation portion 72 is located inward from the periphery 501 of the sealing resin 50 when viewed in the first direction z.

[0018] 6 , 10 , 11 , 14 , and 15 , the base 71 of the heat dissipation member 70 is provided with an engaging portion 73 recessed from the main surface 711. A portion of the sealing resin 50 is accommodated in the engaging portion 73.

[0019] 16 , the heat dissipation member 70 has an inner circumferential surface 713 that is connected to the main surface 711 and defines the engagement portion 73. The inner circumferential surface 713 is included in the base portion 71. The sealing resin 50 is in contact with the inner circumferential surface 713.

[0020] As shown in FIGS. 10 , 11 , 14 , and 15 , the sealing resin 50 covers the substrate 11, the first conductive layer 121, the second conductive layer 122, the multiple semiconductor elements 20, the first conductive member 31, and the second conductive member 32. The sealing resin 50 also covers a portion of each of the first power terminal 13, the third power terminal 15, and the second power terminal 14. The sealing resin 50 has electrical insulation properties. The sealing resin 50 is made of a material containing, for example, black epoxy resin. As shown in FIG. 2 , the sealing resin 50 is located inward from the periphery 701 of the heat dissipation member 70 when viewed in the first direction z. As shown in FIGS. 3 to 5 , the sealing resin 50 has a top surface 51, a bottom surface 52, a first side surface 53, a second side surface 54, and multiple recesses 55.

[0021] 10 , 11 , 14 , and 15 , top surface 51 faces the side where first conductive layer 121 and second conductive layer 122 are located with base material 11 as the reference in first direction z. That is, top surface 51 faces the same side as main surface 711 of heat dissipation member 70 in first direction z. Bottom surface 52 faces the side opposite top surface 51 in first direction z. As shown in FIGS. 10 , 11 , 14 , and 15 , bottom surface 52 is in contact with main surface 711.

[0022] 3 and 4, the first side surface 53 and the second side surface 54 are spaced apart from each other in the second direction x. The first side surface 53 and the second side surface 54 face in opposite directions from each other in the second direction x.

[0023] 2, 4, and 5, each of the multiple recesses 55 is recessed from the top surface 51 and either the first side surface 53 or the second side surface 54. The multiple recesses 55 include a first recess 55A, two second recesses 55B, and two third recesses 55C. The first recess 55A and the two second recesses 55B are each connected to the first side surface 53. In the third direction y, the first recess 55A is located between the two second recesses 55B. The two third recesses 55C are connected to the second side surface 54. The two third recesses 55C are spaced apart from each other in the third direction y.

[0024] As shown in FIGS. 10 , 11 , 14 , and 15 , the base material 11 is bonded to the main surface 711 of the heat dissipation member 70. In the semiconductor device A10, the base material 11 is formed, for example, from a DBC (Direct Bonded Copper) substrate. The base material 11 has an insulating layer 111, a metal layer 112, a first conductive layer 121, and a second conductive layer 122. The base material 11 is covered with a sealing resin 50.

[0025] 10 , 11 , 14 , and 15 , the metal layer 112 is bonded to the main surface 711 of the heat dissipation member 70. The metal layer 112 contains copper (Cu). When viewed in the first direction z, the metal layer 112 is located inward from the periphery 111A of the insulating layer 111.

[0026] As shown in Figures 10, 11, 14, and 15, the insulating layer 111 is located between the metal layer 112 and the first and second conductive layers 121 and 122 in the first direction z. That is, the insulating layer 111 is located between the main surface 711 of the heat dissipation member 70 and the first and second conductive layers 121 and 122. The metal layer 112 is also bonded to the insulating layer 111. The insulating layer 111 is made of a material with relatively high thermal conductivity. The insulating layer 111 is made of ceramics containing aluminum nitride (AlN), for example. The insulating layer 111 may be made of an insulating resin sheet instead of ceramics.

[0027] As shown in FIGS. 10 , 11 , 14 , and 15 , the first conductive layer 121 and the second conductive layer 122 are located on the opposite side of the insulating layer 111 from the metal layer 112. Each of the first conductive layer 121 and the second conductive layer 122 is bonded to the insulating layer 111. As shown in FIGS. 8 and 9 , each of the first conductive layer 121 and the second conductive layer 122 is located inward from the periphery 111A of the insulating layer 111. Each of the first conductive layer 121 and the second conductive layer 122 contains copper. The first conductive layer 121 and the second conductive layer 122 are spaced apart from each other in the second direction x. The dimension of each of the first conductive layer 121 and the second conductive layer 122 in the first direction z is greater than the dimension of the insulating layer 111 in the first direction z. The first conductive layer 121 has a first mounting surface 121A that faces the same side as the main surface 711 of the heat dissipation member 70 in the first direction z. The first mounting surface 121A faces the multiple semiconductor elements 20. The second conductive layer 122 has a second mounting surface 122A that faces the same side as the first mounting surface 121A in the first direction z.

[0028] As shown in FIGS. 10 , 11 , 14 , and 15 , the first bonding layer 19 bonds the main surface 711 of the heat dissipation member 70 to the metal layer 112. The first bonding layer 19 is covered with a sealing resin 50. The first bonding layer 19 contains a metal. The first bonding layer 19 is a sintered body of metal particles containing silver (Ag) or the like. Alternatively, the first bonding layer 19 may be a minute metal layer (hereinafter referred to as a “solid-phase diffusion layer”) located at the bonding interface formed by solid-phase diffusion. Furthermore, the first bonding layer 19 may be a metal layer formed by brazing using silver or the like. The glass transition point of the sealing resin 50 is lower than the melting point of the first bonding layer 19.

[0029] As shown in FIGS. 7 to 9 , each of the plurality of semiconductor elements 20 is mounted on either the first conductive layer 121 or the second conductive layer 122. The plurality of semiconductor elements 20 are, for example, MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). Alternatively, the plurality of semiconductor elements 20 may be switching elements such as IGBTs (Insulated Gate Bipolar Transistors) or diodes. In the description of the semiconductor device A10, the plurality of semiconductor elements 20 are n-channel MOSFETs with a vertical structure. The plurality of semiconductor elements 20 include a compound semiconductor substrate. The compound semiconductor substrate includes silicon carbide (SiC).

[0030] 9 , in the semiconductor device A10, the multiple semiconductor elements 20 include multiple first semiconductor elements 21 and multiple second semiconductor elements 22. The structure of each of the multiple second semiconductor elements 22 is the same as the structure of each of the multiple first semiconductor elements 21. The multiple first semiconductor elements 21 are mounted on a first mounting surface 121A of a first conductive layer 121. The multiple first semiconductor elements 21 are arranged along the third direction y. The multiple second semiconductor elements 22 are mounted on a second mounting surface 122A of a second conductive layer 122. The multiple second semiconductor elements 22 are arranged along the third direction y.

[0031] As shown in FIGS. 9 and 12, each of the plurality of first semiconductor elements 21 has a first electrode 211 , a second electrode 212 , a first gate electrode 213 and a first detection electrode 214 .

[0032] 12 , the first electrode 211 faces the first mounting surface 121A of the first conductive layer 121. A current corresponding to the power before being converted by the first semiconductor element 21 flows through the first electrode 211. In other words, the first electrode 211 corresponds to the drain electrode of the first semiconductor element 21. The first electrode 211 is conductively bonded to the first mounting surface 121A via the first bonding layer 19. As a result, the first electrode 211 of each of the multiple first semiconductor elements 21 is electrically connected to the first conductive layer 121.

[0033] 12 , the second electrode 212 is located on the opposite side of the first conductive layer 121 from the side facing the first mounting surface 121A in the first direction z. Therefore, the first electrode 211 and the second electrode 212 are located on opposite sides of each other in the first direction z. A current corresponding to the power converted by the first semiconductor element 21 flows through the second electrode 212. In other words, the second electrode 212 corresponds to the source electrode of the first semiconductor element 21.

[0034] 12 , the first gate electrode 213 is located on the opposite side of the first conductive layer 121 in the first direction z from the side facing the first mounting surface 121A. Therefore, the first gate electrode 213 is located on the same side as the second electrode 212 in the first direction z. A gate voltage for driving the first semiconductor element 21 is applied to the first gate electrode 213. As shown in FIG. 9 , the area of ​​the first gate electrode 213 is smaller than the area of ​​the second electrode 212 when viewed in the first direction z.

[0035] 9 , the first detection electrode 214 is located on the same side as the second electrode 212 and the first gate electrode 213 in the first direction z. The first detection electrode 214 is located adjacent to the first gate electrode 213 in the third direction y. A voltage equivalent to the voltage applied to the second electrode 212 is applied to the first detection electrode 214. When viewed in the first direction z, the area of ​​the first detection electrode 214 is equal to (or approximately equal to) the area of ​​the first gate electrode 213.

[0036] As shown in FIGS. 9 and 13 , each of the plurality of second semiconductor elements 22 has a third electrode 221 , a fourth electrode 222 , a second gate electrode 223 and a second detection electrode 224 .

[0037] 13 , the third electrode 221 faces the second mounting surface 122A of the second conductive layer 122. A current corresponding to the power before being converted by the second semiconductor element 22 flows through the third electrode 221. In other words, the third electrode 221 corresponds to the drain electrode of the second semiconductor element 22. The third electrode 221 is conductively bonded to the second mounting surface 122A via the first bonding layer 19. As a result, the third electrode 221 of each of the multiple second semiconductor elements 22 is electrically connected to the second conductive layer 122.

[0038] 13 , the fourth electrode 222 is located on the opposite side of the second conductive layer 122 from the side facing the second mounting surface 122A in the first direction z. Therefore, the third electrode 221 and the fourth electrode 222 are located on opposite sides of each other in the first direction z. A current corresponding to the power converted by the second semiconductor element 22 flows through the fourth electrode 222. In other words, the fourth electrode 222 corresponds to the source electrode of the second semiconductor element 22.

[0039] 13 , the second gate electrode 223 is located on the opposite side of the second conductive layer 122 in the first direction z from the side facing the second mounting surface 122A. Therefore, the second gate electrode 223 is located on the same side as the fourth electrode 222 in the first direction z. A gate voltage for driving the second semiconductor element 22 is applied to the second gate electrode 223. As shown in FIG. 9 , the area of ​​the second gate electrode 223 is smaller than the area of ​​the fourth electrode 222 when viewed in the first direction z.

[0040] 9 , the second detection electrode 224 is located on the same side as the fourth electrode 222 and the second gate electrode 223 in the first direction z. The second detection electrode 224 is located on both sides of the second gate electrode 223 in the third direction y. A voltage equivalent to the voltage applied to the fourth electrode 222 is applied to the second detection electrode 224. When viewed in the first direction z, the area of ​​the second detection electrode 224 is equal to (or approximately equal to) the area of ​​the second gate electrode 223.

[0041] As shown in FIG. 9 , the first power terminal 13 is located on the opposite side of the second semiconductor elements 22 from the first semiconductor elements 21 in the second direction x. The first power terminal 13 is disposed on the substrate 11. The first power terminal 13 is conductively bonded to the first conductive layer 121. This electrically connects the first power terminal 13 to the first electrodes 211 of the first semiconductor elements 21 via the first conductive layer 121. The first power terminal 13 is a P terminal (positive electrode) to which DC power to be converted is input. As shown in FIG. 2 , the first power terminal 13 is exposed from the top surface 51 of the sealing resin 50. As viewed in the first direction z, the first power terminal 13 is surrounded by a periphery 501 of the sealing resin 50 and is located inward from the periphery of the top surface 51. As shown in FIG. 11 , the first power terminal 13 has a first connection surface 131 exposed from the sealing resin 50. The first connecting surface 131 faces the same side as the main surface 711 of the heat dissipation member 70 in the first direction z. As shown in Figures 5 and 11, in the semiconductor device A10, the first connecting surface 131 is accommodated in a first recess 55A among the multiple recesses 55 in the sealing resin 50. In addition to the configuration of the first power terminal 13 in the semiconductor device A10, the first power terminal 13 may be configured to protrude from the first side surface 53 of the sealing resin 50 in the second direction x.

[0042] As shown in FIG. 9 , each of the two second power terminals 14 is located on the same side as the first power terminal 13 in the second direction x with respect to the multiple first semiconductor elements 21. The two second power terminals 14 are disposed on the substrate 11. Each of the two second power terminals 14 is disposed on the insulating layer 111. Each of the two second power terminals 14 is electrically connected to the fourth electrodes 222 of each of the multiple second semiconductor elements 22. The two second power terminals 14 are N terminals (negative electrodes) to which DC power to be converted is input. The second power terminals 14 are spaced apart from each other in the third direction y. The first power terminal 13 is located between the two second power terminals 14 in the third direction y. As shown in FIG. 2 , each of the two second power terminals 14 is exposed from the top surface 51 of the sealing resin 50. As viewed in the first direction z, each of the two second power terminals 14 is surrounded by a periphery 501 of the sealing resin 50 and is located inward from the periphery of the top surface 51. As shown in FIG. 10 , each of the two second power terminals 14 has a second connection surface 141 exposed from the sealing resin 50. The second connection surface 141 faces the same side as the main surface 711 of the heat dissipation member 70 in the first direction z. As shown in FIGS. 5 and 10 , in the semiconductor device A10, the two second connection surfaces 141 are individually accommodated in two second recesses 55B among the multiple recesses 55 in the sealing resin 50. In addition to the configuration of two second power terminals 14 in the semiconductor device A10, a configuration in which two second power terminals 14 each protrude from the first side surface 53 of the sealing resin 50 in the second direction x may also be used.

[0043] As shown in FIG. 9 , each of the two third power terminals 15 is located on the opposite side of the first power terminal 13 and the two second power terminals 14 in the second direction x with respect to the plurality of semiconductor elements 20. The two third power terminals 15 are disposed on the substrate 11. Each of the two third power terminals 15 is conductively bonded to the second conductive layer 122. As a result, each of the two third power terminals 15 is electrically connected to the third electrodes 221 of the plurality of second semiconductor elements 22 via the second conductive layer 122. AC power converted by the plurality of semiconductor elements 20 is output from each of the two third power terminals 15. In the semiconductor device A10, the two third power terminals 15 are spaced apart from each other in the third direction y. As shown in FIG. 2 , each of the two third power terminals 15 is exposed from the top surface 51 of the sealing resin 50. As viewed in the first direction z, each of the two third power terminals 15 is surrounded by a periphery 501 of the sealing resin 50 and is located inward from the periphery of the top surface 51. As shown in FIG. 10 , each of the two third power terminals 15 has a third connection surface 151 exposed from the sealing resin 50. The third connection surface 151 faces the same side as the main surface 711 of the heat dissipation member 70 in the first direction z. As shown in FIGS. 4 and 10 , in the semiconductor device A10, the two third connection surfaces 151 are individually accommodated in two third recesses 55C among the multiple recesses 55 in the sealing resin 50. In addition to the configuration of two third power terminals 15 in the semiconductor device A10, a configuration of two third power terminals 15 each protruding from the second side surface 54 of the sealing resin 50 in the second direction x may also be used.

[0044] 12 , the first wiring 61 is bonded to a first mounting surface 121A of the first conductive layer 121. The first wiring 61 is located on the opposite side of the plurality of second semiconductor elements 22 from the plurality of first semiconductor elements 21 in the second direction x. The first wiring 61 is electrically connected to the plurality of first semiconductor elements 21 and the first conductive layer 121. As shown in FIGS. 9 and 12 , the first wiring 61 has a first mounting layer 611, a first metal layer 612, two first gate wiring layers 613, a first detection wiring layer 614, a first temperature detection wiring layer 615, and a second detection wiring layer 616.

[0045] 9 , the first mounting layer 611 includes two first gate wiring layers 613, a first detection wiring layer 614, two first temperature detection wiring layers 615, and a second detection wiring layer 616. The first mounting layer 611 is an insulator. The first mounting layer 611 is made of, for example, ceramics. Alternatively, the first mounting layer 611 may be made of an insulating resin sheet.

[0046] As shown in FIG. 12 , the first metal layer 612 is located on the side facing the first mounting surface 121A of the first conductive layer 121 relative to the first mounting layer 611 in the first direction z. The first metal layer 612 is bonded to the first mounting layer 611. The first metal layer 612 contains copper. The first metal layer 612 is bonded to the first mounting surface 121A via a second bonding layer 39. The second bonding layer 39 contains a metal. The second bonding layer 39 is solder. Therefore, the second bonding layer 39 contains tin (Sn). Alternatively, the second bonding layer 39 may be a sintered body of metal particles containing silver (Ag) or the like. The glass transition point of the sealing resin 50 is lower than the melting point of the second bonding layer 39. Furthermore, if the second bonding layer 39 is solder, the melting point of the second bonding layer 39 is lower than the melting point of the first bonding layer 19.

[0047] 9 and 12 , the two first gate wiring layers 613 are located on the opposite side of the first mounting layer 611 from the first metal layer 612. The two first gate wiring layers 613 are bonded to the first mounting layer 611. Of the two first gate wiring layers 613, one of the first gate wiring layers 613 is conductively bonded to a plurality of first wires 41. The plurality of first wires 41 are individually conductively bonded to the first gate electrodes 213 of the plurality of first semiconductor elements 21. Furthermore, a plurality of sixth wires 46 are conductively bonded to each of the two first gate wiring layers 613. As a result, each of the two first gate wiring layers 613 is electrically connected to the first gate electrodes 213 of the plurality of first semiconductor elements 21.

[0048] 9 and 12 , the first detection wiring layer 614 is located on the opposite side of the first metal layer 612 with respect to the first mounting layer 611. The first detection wiring layer 614 is bonded to the first mounting layer 611. A plurality of second wires 42 are conductively bonded to the first detection wiring layer 614. Furthermore, the plurality of second wires 42 are individually conductively bonded to the first detection electrodes 214 of the plurality of first semiconductor elements 21. As a result, the first detection wiring layer 614 is electrically connected to the first detection electrodes 214 of the plurality of first semiconductor elements 21.

[0049] 9 , the two first temperature detection wiring layers 615 are located on the opposite side of the first mounting layer 611 from the first metal layer 612. The two first temperature detection wiring layers 615 are bonded to the first mounting layer 611. The two first temperature detection wiring layers 615 are adjacent to each other in the third direction y.

[0050] 9, the second detection wiring layer 616 is located on the opposite side of the first mounting layer 611 from the first metal layer 612. The second detection wiring layer 616 is bonded to the first mounting layer 611.

[0051] 13 , the second wiring 62 is bonded to the second mounting surface 122A of the second conductive layer 122. The second wiring 62 is located on the opposite side of the second semiconductor elements 22 from the first semiconductor elements 21 in the second direction x. The second wiring 62 is electrically connected to the second semiconductor elements 22 and the second conductive layer 122. As shown in FIGS. 9 and 13 , the second wiring 62 includes a second mounting layer 621, a second metal layer 622, two second gate wiring layers 623, a third detection wiring layer 624, two second temperature detection wiring layers 625, and a fourth detection wiring layer 626.

[0052] 9 , the second mounting layer 621 includes two second gate wiring layers 623, a third detection wiring layer 624, two second temperature detection wiring layers 625, and a fourth detection wiring layer 626. The second mounting layer 621 is an insulator. The second mounting layer 621 is made of, for example, ceramics. Alternatively, the second mounting layer 621 may be made of an insulating resin sheet.

[0053] 13 , the second metal layer 622 is located on a side of the second conductive layer 122 facing the second mounting surface 122A with respect to the second mounting layer 621 in the first direction z. The second metal layer 622 is bonded to the second mounting layer 621. The second metal layer 622 contains copper. The second metal layer 622 is bonded to the second mounting surface 122A via the second bonding layer 39.

[0054] 9 and 13 , the two second gate wiring layers 623 are located on the opposite side of the second metal layer 622 with respect to the second mounting layer 621. The two second gate wiring layers 623 are bonded to the second mounting layer 621. A plurality of fourth wires 44 are conductively bonded to one of the two second gate wiring layers 623. The plurality of fourth wires 44 are individually conductively bonded to the second gate electrodes 223 of the second semiconductor elements 22. Furthermore, a plurality of seventh wires 47 are conductively bonded to each of the two second gate wiring layers 623. As a result, each of the two second gate wiring layers 623 is electrically connected to the second gate electrodes 223 of the second semiconductor elements 22.

[0055] 9 and 13 , the third detection wiring layer 624 is located on the opposite side of the second metal layer 622 with respect to the second mounting layer 621. The third detection wiring layer 624 is bonded to the second mounting layer 621. A plurality of fifth wires 45 are conductively bonded to the third detection wiring layer 624. Furthermore, the plurality of fifth wires 45 are individually conductively bonded to the second detection electrodes 224 of the plurality of second semiconductor elements 22. As a result, the third detection wiring layer 624 is electrically connected to the second detection electrodes 224 of the plurality of second semiconductor elements 22.

[0056] 9 , the two second temperature detection wiring layers 625 are located on the opposite side of the second mounting layer 621 from the second metal layer 622. The two second temperature detection wiring layers 625 are bonded to the second mounting layer 621. The two second temperature detection wiring layers 625 are adjacent to each other in the third direction y.

[0057] 9, the fourth detection wiring layer 626 is located on the opposite side of the second mounting layer 621 from the second metal layer 622. The fourth detection wiring layer 626 is bonded to the second mounting layer 621.

[0058] As shown in FIGS. 12 and 13 , each of the multiple sleeves 63 is conductively bonded to either the first wiring 61 or the second wiring 62 via a second bonding layer 39. The second bonding layer 39 is, for example, solder. The multiple sleeves 63 are made of a conductive material such as metal. Each of the multiple sleeves 63 has a cylindrical shape extending in the first direction z. As shown in FIGS. 2 and 11 , each of the multiple sleeves 63 has an end surface 631 that faces the same side as the first mounting surface 121A of the first conductive layer 121 in the first direction z. The end surface 631 is exposed from the top surface 51 of the sealing resin 50, which will be described later.

[0059] 8 and 9, one of the two thermistors 23 is conductively joined to two first temperature detection wiring layers 615 of the first wiring 61. The other of the two thermistors 23 is conductively joined to two second temperature detection wiring layers 625 of the second wiring 62. The two thermistors 23 are used as temperature detection sensors for the semiconductor device A10.

[0060] As shown in FIG. 3 , each of the first signal terminal 161, the second signal terminal 162, the third signal terminal 171, the fourth signal terminal 172, the two fifth signal terminals 181, and the two sixth signal terminals 182 is formed by a metal pin extending in the first direction z. These terminals protrude from the top surface 51 of the sealing resin 50 (described later). Furthermore, these terminals are individually press-fitted into a plurality of sleeves 63. As a result, each of these terminals is supported by one of the plurality of sleeves 63 and is electrically connected to one of the first wiring 61 and the second wiring 62.

[0061] 9 , the first signal terminal 161 is press-fitted into one of the multiple sleeves 63 that is conductively joined to one of the two first gate wiring layers 613 of the first wiring 61. This allows the first signal terminal 161 to be electrically connected to the first gate electrodes 213 of the multiple first semiconductor elements 21 via the two first gate wiring layers 613. A gate voltage for driving the multiple first semiconductor elements 21 is applied to the first signal terminal 161.

[0062] 9 and 11 , the second signal terminal 162 is press-fitted into one of the multiple sleeves 63 that is conductively joined to one of the two second gate wiring layers 623 of the second wiring 62. This allows the second signal terminal 162 to be electrically connected to the second gate electrodes 223 of the multiple second semiconductor elements 22 via the two second gate wiring layers 623. A gate voltage for driving the multiple second semiconductor elements 22 is applied to the second signal terminal 162.

[0063] As shown in Fig. 2 , the third signal terminal 171 is located adjacent to the first signal terminal 161 in the third direction y. As shown in Figs. 9 and 11 , the third signal terminal 171 is press-fitted into one of the multiple sleeves 63 that is conductively joined to the first detection wiring layer 614 of the first wiring 61. This allows the third signal terminal 171 to be electrically connected to the first detection electrodes 214 of each of the multiple first semiconductor elements 21 via the first detection wiring layer 614. A voltage equivalent to the voltage applied to the first detection electrodes 214 of each of the multiple first semiconductor elements 21 is applied to the third signal terminal 171.

[0064] As shown in Fig. 2 , the fourth signal terminal 172 is located adjacent to the second signal terminal 162 in the third direction y. As shown in Fig. 9 , the fourth signal terminal 172 is press-fitted into one of the multiple sleeves 63 that is conductively joined to the third detection wiring layer 624 of the second wiring 62. This allows the fourth signal terminal 172 to be electrically connected to the second detection electrodes 224 of each of the multiple second semiconductor elements 22 via the third detection wiring layer 624. A voltage equivalent to the voltage applied to the second detection electrodes 224 of each of the multiple second semiconductor elements 22 is applied to the fourth signal terminal 172.

[0065] As shown in Fig. 2 , the two fifth signal terminals 181 are located on the opposite side of the third signal terminal 171 from the first signal terminal 161 in the third direction y. The two fifth signal terminals 181 are adjacent to each other in the third direction y. As shown in Fig. 9 , the two fifth signal terminals 181 are individually press-fitted into two of the multiple sleeves 63 that are individually conductively joined to the two first temperature detection wiring layers 615 of the first wiring 61. As a result, the two fifth signal terminals 181 are electrically connected to the two thermistors 23 that are conductively joined to the two first temperature detection wiring layers 615 of the two thermistors 23.

[0066] As shown in Fig. 2 , the two sixth signal terminals 182 are located on the opposite side of the second signal terminal 162 from the fourth signal terminal 172 in the third direction y. The two sixth signal terminals 182 are adjacent to each other in the third direction y. As shown in Fig. 9 , the two sixth signal terminals 182 are individually press-fitted into two of the multiple sleeves 63 that are individually conductively joined to the two second temperature detection wiring layers 625 of the second wiring 62. As a result, the two sixth signal terminals 182 are electrically connected to the two thermistors 23 that are conductively joined to the two second temperature detection wiring layers 625 of the two thermistors 23.

[0067] As shown in FIGS. 8 and 12 , the first conductive member 31 is conductively bonded to the second electrodes 212 of the plurality of first semiconductor elements 21 and the second mounting surface 122A of the second conductive layer 122. As a result, the second electrodes 212 of the plurality of first semiconductor elements 21 are electrically connected to the second conductive layer 122. The first conductive member 31 contains copper. The first conductive member 31 is a metal clip. As shown in FIG. 5 , the first conductive member 31 has a main portion 311, a plurality of first bonding portions 312, a plurality of first connecting portions 313, a second bonding portion 314, and a second connecting portion 315.

[0068] The main portion 311 forms a main portion of the first conductive member 31. As shown in Fig. 8 , the main portion 311 extends in the third direction y. The main portion 311 straddles between the first conductive layer 121 and the second conductive layer 122.

[0069] 8 and 12 , the multiple first bonding portions 312 are individually bonded to the second electrodes 212 of the multiple first semiconductor elements 21. Each of the multiple first bonding portions 312 faces the second electrode 212 of one of the multiple first semiconductor elements 21.

[0070] 8 and 12 , the multiple first connecting portions 313 are connected to the main portion 311 and the multiple first bonding portions 312. The multiple first connecting portions 313 are spaced apart from one another in the third direction y. As viewed in the third direction y, the multiple first connecting portions 313 are inclined in a direction away from the first mounting surface 121A of the first conductive layer 121 as they extend from the multiple first bonding portions 312 toward the main portion 311.

[0071] 8 and 11 , the second bonding portion 314 is bonded to the second mounting surface 122A of the second conductive layer 122. The second bonding portion 314 faces the second mounting surface 122A. The second bonding portion 314 extends in the third direction y. The dimension of the second bonding portion 314 in the third direction y is equal to the dimension of the main portion 311 in the third direction y.

[0072] 8 and 11 , the second connecting portion 315 is connected to the main portion 311 and the second joint portion 314. When viewed in the third direction y, the second connecting portion 315 is inclined in a direction away from the second mounting surface 122A of the second conductive layer 122 as it extends from the second joint portion 314 toward the main portion 311. The dimension of the second connecting portion 315 in the third direction y is equal to the dimension of the main portion 311 in the third direction y.

[0073] 12 , a second bonding layer 39 is located between the second electrode 212 of each of the multiple first semiconductor elements 21 and each of the multiple first bonding portions 312. The second bonding layer 39 electrically conductively bonds each of the multiple first bonding portions 312 to the second electrode 212 of each of the multiple first semiconductor elements 21. The second bonding layer 39 is, for example, solder. As shown in FIG. 11 , the second bonding layer 39 is located between the second mounting surface 122A of the second conductive layer 122 and the second bonding portion 314. The second bonding layer 39 electrically conductively bonds the second mounting surface 122A to the second bonding portion 314.

[0074] As shown in Figures 7 and 13, the second conductive member 32 is conductively joined to the second electrodes 212 of the multiple second semiconductor elements 22 and the two second power terminals 14. As a result, the second electrodes 212 of the multiple second semiconductor elements 22 are electrically connected to the second power terminals 14. The second conductive member 32 contains copper. The second conductive member 32 is a metal clip. As shown in Figure 7, the second conductive member 32 has two main portions 321, multiple third joint portions 322, multiple third connecting portions 323, multiple intermediate portions 326, and a cross beam portion 327.

[0075] As shown in Fig. 7 , the two main portions 321 are spaced apart from each other in the third direction y. The two main portions 321 extend in the second direction x. As shown in Fig. 10 , the two main portions 321 are arranged parallel to the first mounting surface 121A of the first conductive layer 121 and the second mounting surface 122A of the second conductive layer 122. The two main portions 321 are spaced apart from the first mounting surface 121A and the second mounting surface 122A more than the main portion 311 of the first conductive member 31.

[0076] 7 , the intermediate portions 326 are spaced apart from one another in the third direction y and are located between the two main portions 321 in the third direction y. The intermediate portions 326 extend in the second direction x. The dimension of each of the intermediate portions 326 in the second direction x is smaller than the dimension of each of the two main portions 321 in the second direction x.

[0077] 13 , the multiple third bonding portions 322 are individually bonded to the second electrodes 212 of the multiple second semiconductor elements 22. Each of the multiple third bonding portions 322 faces the fourth electrode 222 of one of the multiple second semiconductor elements 22.

[0078] 7 and 15 , the multiple third connecting portions 323 are connected to both sides of the multiple third joint portions 322 in the third direction y. Furthermore, the multiple third connecting portions 323 are connected to either of the two main portions 321 and the multiple intermediate portions 326. When viewed in the second direction x, each of the multiple third connecting portions 323 is inclined in a direction away from the second mounting surface 122A of the second conductive layer 122 as it moves from either of the multiple third joint portions 322 toward either of the two main portions 321 or the multiple intermediate portions 326.

[0079] As shown in Fig. 7 , the cross beam portion 327 extends in the third direction y. As shown in Fig. 15 , when viewed in the first direction z, the cross beam portion 327 includes regions that overlap with each of the multiple first joint portions 312 of the first conductive member 31. Both sides of the cross beam portion 327 in the third direction y are individually connected to the two main portions 321.

[0080] 13 , a second bonding layer 39 is located between the fourth electrode 222 of each of the second semiconductor elements 22 and each of the third bonding portions 322. The second bonding layer 39 electrically conductively bonds each of the third bonding portions 322 to the fourth electrode 222 of each of the second semiconductor elements 22. As shown in FIG. 10 , a second bonding layer 39 is located between two second power terminals 14 and two main portions 321. The second bonding layer 39 electrically conductively bonds each of the second power terminals 14 to the two main portions 321.

[0081] Next, a semiconductor device A11 according to a first modification of the first embodiment of the present disclosure will be described with reference to Fig. 17. Fig. 17 corresponds to Fig. 11 showing the semiconductor device A10. In the semiconductor device A11, the configuration relating to the conductive bonding of each of the plurality of semiconductor elements 20 to either the first conductive layer 121 or the second conductive layer 122 differs from that of the semiconductor device A10.

[0082] 17 , the first electrodes 211 of the plurality of first semiconductor elements 21 are conductively bonded to the first mounting surface 121A of the first conductive layer 121 via the second bonding layer 39. The third electrodes 221 of the plurality of second semiconductor elements 22 are conductively bonded to the second mounting surface 122A of the second conductive layer 122 via the second bonding layer 39.

[0083] Next, a semiconductor device A12 according to a second modified example of the first embodiment of the present disclosure will be described with reference to Fig. 18. Fig. 18 corresponds to Fig. 16 showing the semiconductor device A10. In the semiconductor device A12, the configuration of the engagement portion 73 of the heat dissipation member 70 is different from that of the semiconductor device A10.

[0084] 18, the engaging portion 73 protrudes from the main surface 711 of the heat dissipation member 70. The engaging portion 73 is recessed into the sealing resin 50.

[0085] Next, an example of a method for manufacturing the semiconductor device A10 will be described with reference to Figures 19 to 22. Figures 19 to 22 correspond to Figure 10 showing the semiconductor device A10.

[0086] First, as shown in Figure 19, the first conductive layer 121 and the second conductive layer 122 are each bonded to one side of the insulating layer 111 in the first direction z. At the same time, the metal layer 112 is bonded to the other side of the insulating layer 111 in the first direction z. Then, the first power terminal 13 is conductively bonded to the first conductive layer 121 (see Figure 11). Each of the two second power terminals 14 is placed on the insulating layer 111. Each of the two third power terminals 15 is conductively bonded to the second conductive layer 122. This step is performed at least before the fourth step P4 described below.

[0087] Next, as shown in FIG. 20 , a first process P1 is performed to bond the base material 11 to the heat dissipation member 70. In the first process P1, the metal layer 112 is bonded to the main surface 711 of the heat dissipation member 70 via a first bonding layer 19. The temperature for forming the first bonding layer 19 in the first process P1 is, for example, 200° C. or higher and 600° C. or lower. Thereafter, a second process P2 is performed to conductively bond each of the multiple semiconductor elements 20 to either the first conductive layer 121 or the second conductive layer 122. In the manufacturing method of the semiconductor device A10, the second process P2 is performed simultaneously with the first process P1. Each of the multiple semiconductor elements 20 is conductively bonded to either the first conductive layer 121 or the second conductive layer 122 via the first bonding layer 19. The first bonding layer 19 is formed by sintering metal particles containing silver or the like. Alternatively, the first bonding layer 19 may be a solid-state bonding layer. When forming the solid-phase bonding layer, pressure is applied to the base material 11 and each of the plurality of semiconductor elements 20 in the direction opposite to the main surface 711 of the heat dissipation member 70 in the first direction z.

[0088] Next, as shown in FIG. 21 , a fourth process P4 is performed to conductively bond the first conductive member 31 and the second conductive member 32. In the fourth process P4, the first conductive member 31 is conductively bonded to each of the plurality of first semiconductor elements 21 and the second conductive layer 122 via the second bonding layer 39. Additionally, the second conductive member 32 is conductively bonded to each of the plurality of second semiconductor elements 22 and the two second power terminals 14 via the second bonding layer 39. In the fourth process P4, the first wiring 61, to which the thermistor 23 and the plurality of sleeves 63 are conductively bonded, is bonded to the first conductive layer 121 via the second bonding layer 39 (see FIG. 11 ). Additionally, the second wiring 62, to which the thermistor 23 and the plurality of sleeves 63 are conductively bonded, is bonded to the second conductive layer 122 via the second bonding layer 39 (see FIG. 11 ). Furthermore, although not shown in the drawings, in the fourth process P4, the plurality of first wires 41, the plurality of second wires 42, the plurality of fourth wires 44, the plurality of fifth wires 45, the plurality of sixth wires 46, and the plurality of seventh wires 47 are formed. The temperature at which the second bonding layer 39 is formed in the fourth process P4 is, for example, about 260° C. The second bonding layer 39 is formed by melting solder by reflow and then solidifying the solder.

[0089] Next, as shown in FIG. 22 , a third process P3 is performed to form a sealing resin 50 that covers the semiconductor elements 20. In the third process P3, the base material 11, the first conductive member 31, and the second conductive member 32 are covered with the sealing resin 50. The sealing resin 50 is formed by transfer molding. The third process P3 is performed after the first process P1, the second process P2, and the fourth process P4 are completed. The temperature at which the sealing resin 50 is formed in the third process P3 is, for example, approximately 180° C. Therefore, the temperature at which the sealing resin 50 is formed in the third process P3 is lower than the temperature at which the first bonding layer 19 is formed in the first process P1 and the temperature at which the second bonding layer 39 is formed in the fourth process P4. In the third process P3, the bottom surface 52 of the sealing resin 50 is brought into contact with the main surface 711 of the heat dissipation member 70. Additionally, each of the multiple end surfaces 712 of the heat dissipation member 70 is exposed from the sealing resin 50. Furthermore, when viewed in the first direction z, the sealing resin 50 is positioned inward from the periphery 701 of the heat dissipation member 70 .

[0090] 22 , in the third process P3, the first power terminal 13, the two second power terminals 14, and the two third power terminals 15 are exposed from the top surface 51 of the sealing resin 50. Furthermore, the sealing resin 50 is caused to sink into the engagement portion 73 provided on the heat dissipation member 70.

[0091] Finally, the first signal terminal 161, the second signal terminal 162, the third signal terminal 171, the fourth signal terminal 172, the two fifth signal terminals 181, and the two sixth signal terminals 182 are individually inserted into the multiple sleeves 63. This causes these signal terminals to protrude from the top surface 51 of the sealing resin 50. This process is performed after the third process P3 is completed. Through the above processes, the semiconductor device A10 is obtained.

[0092] Next, an example of a method for manufacturing the semiconductor device A11 will be described with reference to Figures 23 and 24. Figures 23 and 24 correspond to Figure 10, which shows the semiconductor device A10. The method for manufacturing the semiconductor device A11 differs from the method for manufacturing the semiconductor device A10 in the order of the first step P1, the second step P2, and the fourth step P4.

[0093] After the step shown in Fig. 19 is completed, a first step P1 shown in Fig. 23 is performed. After the first step P1 is completed, a second step P2 and a fourth step P4 are simultaneously performed as shown in Fig. 24. Each of the multiple semiconductor elements 20 is conductively bonded to either the first conductive layer 121 or the second conductive layer 122 via the second bonding layer 39. After the second step P2 and the fourth step P4 are completed, a third step P3 shown in Fig. 22 is performed.

[0094] Next, a vehicle B equipped with the semiconductor device A10 will be described with reference to Fig. 25. The vehicle B is, for example, an electric vehicle (EV).

[0095] As shown in Fig. 25, vehicle B includes an on-board charger 81, a storage battery 82, and a drive system 83. Power is supplied to the on-board charger 81 wirelessly from a power supply facility (not shown) installed outdoors. Alternatively, power may be supplied from the power supply facility to the on-board charger 81 via a wired connection. The on-board charger 81 is configured with a step-up DC-DC converter. The voltage of the power supplied to the on-board charger 81 is stepped up by the converter and then supplied to the storage battery 82. The stepped-up voltage is, for example, 600 V.

[0096] The drive system 83 drives the vehicle B. The drive system 83 includes an inverter 831 and a drive source 832. The semiconductor device A10 constitutes part of the inverter 831. Power stored in the storage battery 82 is supplied to the inverter 831. The power supplied from the storage battery 82 to the inverter 831 is DC power. Alternatively, unlike the power system shown in FIG. 25 , a step-up DC-DC converter may be further provided between the storage battery 82 and the inverter 831. The inverter 831 converts DC power into AC power. The inverter 831 including the semiconductor device A10 is connected to the drive source 832. The drive source 832 includes an AC motor and a transmission. When the AC power converted by the inverter 831 is supplied to the drive source 832, the AC motor rotates and the rotation is transmitted to the transmission. The transmission appropriately reduces the rotation speed transmitted from the AC motor and then rotates the drive shaft of the vehicle B. This drives vehicle B. To drive vehicle B, it is necessary to freely control the rotation speed of the AC motor based on information such as the amount of accelerator pedal fluctuation. Therefore, semiconductor device A10 in inverter 831 is necessary to output AC power whose frequency has been appropriately changed to correspond to the required rotation speed of the AC motor.

[0097] Next, the effects of the manufacturing method of the semiconductor device A10 will be described.

[0098] The manufacturing method of the semiconductor device A10 includes a first process P1, a second process P2, and a third process P3. In the first process P1, a base material 11 having an insulating layer 111, a first conductive layer 121, and a second conductive layer 122 is bonded to a heat dissipation member 70. In the second process P2, a semiconductor element 20 is bonded to either the first conductive layer 121 or the second conductive layer 122. In the third process P3, a sealing resin 50 is formed to cover the semiconductor element 20. In the first process P1, the base material 11 is bonded to the heat dissipation member 70 so that the insulating layer 111 is positioned between the heat dissipation member 70 and the first conductive layer 121 and the second conductive layer 122. The third process P3 is performed after the first process P1 and the second process P2 are completed. With this configuration, since the first step P1 is completed at the time of the third step P3, the semiconductor device A10 being manufactured after the third step P3 is not placed in an environment with a temperature higher than the temperature at which the sealing resin 50 is formed. Therefore, with this configuration, the shape of the sealing resin 50 can be maintained better in the manufacturing method of the semiconductor device A10 in which the base material 11 is bonded to the heat dissipation member 70.

[0099] In the first process P1, the base material 11 is bonded to the main surface 711 of the heat dissipation member 70 via the first bonding layer 19. The temperature at which the sealing resin 50 is formed in the third process P3 is lower than the temperature at which the first bonding layer 19 is formed in the first process P1. By adopting this configuration, melting of the first bonding layer 19 can be prevented when the sealing resin 50 is formed.

[0100] The manufacturing method of the semiconductor device A10 further includes a fourth process P4 in which the second conductive member 32 is conductively bonded to the semiconductor element 20 (second semiconductor element 22) via the second bonding layer 39. The fourth process P4 is performed before the third process P3. The temperature at which the sealing resin 50 is formed in the third process P3 is lower than the temperature at which the second bonding layer 39 is formed in the fourth process P4. This configuration prevents the second bonding layer 39 from melting when the sealing resin 50 is formed.

[0101] In the third process P3, the sealing resin 50 is brought into contact with the main surface 711 of the heat dissipation member 70. At the same time, the base material 11 is covered with the sealing resin 50, and an end surface 712 of the heat dissipation member 70 is exposed from the sealing resin 50. Furthermore, when viewed in the first direction z, the sealing resin 50 is positioned inward from the periphery 701 of the heat dissipation member 70. By adopting this configuration, when forming the sealing resin 50 in the third process P3, the molding die can be pressed against the heat dissipation member 70 without any gaps. This further improves the molding state of the sealing resin 50.

[0102] The semiconductor device A10 further includes a first power terminal 13 electrically connected to the semiconductor element 20 (first semiconductor element 21). The first power terminal 13 is exposed from a top surface 51 of the sealing resin 50. When viewed in the first direction z, the first power terminal 13 is located inward from the periphery of the top surface 51. This configuration ensures a longer creepage distance (the distance along the surface of the sealing resin 50) from the first power terminal 13 to the heat dissipation member 70. This makes it possible to further improve the dielectric strength voltage of the semiconductor device A10.

[0103] The heat dissipation member 70 has an engagement portion 73 recessed from the main surface 711. In the third process P3, the sealing resin 50 is caused to sink into the engagement portion 73. This configuration allows the sealing resin 50 to exhibit an anchoring effect with respect to the heat dissipation member 70. This makes it possible to prevent the sealing resin 50 from peeling off from the main surface 711.

[0104] The semiconductor device A10 further includes a first signal terminal 161 that is electrically connected to the semiconductor element 20 (first semiconductor element 21). The first signal terminal 161 protrudes from the top surface 51 of the sealing resin 50. This configuration makes it possible to ensure a longer creepage distance from the first signal terminal 161 to the heat dissipation member 70.

[0105] Second Embodiment: A semiconductor device A20 according to a second embodiment of the present disclosure will be described with reference to Figures 26 to 28. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are designated by the same reference numerals, and duplicated descriptions will be omitted. Here, Figure 27 corresponds to Figure 10, which shows the semiconductor device A10. Figure 28 corresponds to Figure 11, which shows the semiconductor device A10.

[0106] In the semiconductor device A20, the configurations of the first power terminal 13, the two second power terminals 14, the two third power terminals 15, and the sealing resin 50 are different from those of the semiconductor device A10.

[0107] 26 to 28 , the first power terminal 13, the two second power terminals 14, and the two third power terminals 15 each protrude from a top surface 51 of the sealing resin 50. The sealing resin 50 does not have a plurality of recesses 55. The first connection surface 131 of the first power terminal 13, the second connection surface 141 of each of the two second power terminals 14, and the third connection surface 151 of each of the two third power terminals 15 are located on the opposite side of the top surface 51 from the bottom surface 52 of the sealing resin 50 in the first direction z.

[0108] Next, an example of a method for manufacturing the semiconductor device A20 will be described with reference to Fig. 29. Fig. 29 corresponds to a partially enlarged view of Fig. 28 showing the semiconductor device A20.

[0109] The method for manufacturing the semiconductor device A20 differs from the method for manufacturing the semiconductor device A10 in the third step P3.

[0110] 29 , in third process P3, after forming the sealing resin 50, a portion of the sealing resin 50 located on one side in the first direction z is removed by a technique such as wet blasting. Through this process, the first power terminal 13, the two second power terminals 14, and the two third power terminals 15 each protrude from the top surface 51 of the sealing resin 50. Furthermore, the surface roughness of the top surface 51 of the sealing resin 50 is greater than the surface roughness of the first side surface 53 of the sealing resin 50.

[0111] Next, the effects of the manufacturing method of the semiconductor device A20 will be described.

[0112] The manufacturing method of the semiconductor device A20 includes a first process P1, a second process P2, and a third process P3. In the first process P1, the base material 11 having the insulating layer 111, the first conductive layer 121, and the second conductive layer 122 is bonded to the heat dissipation member 70. In the second process P2, the semiconductor element 20 is bonded to either the first conductive layer 121 or the second conductive layer 122. In the third process P3, the sealing resin 50 covering the semiconductor element 20 is formed. In the first process P1, the base material 11 is bonded to the heat dissipation member 70 so that the insulating layer 111 is positioned between the heat dissipation member 70 and the first conductive layer 121 and the second conductive layer 122. The third process P3 is performed after the first process P1 and the second process P2 are completed. Therefore, according to this configuration, even in the manufacturing method of the semiconductor device A20 in which the base material 11 is bonded to the heat dissipation member 70, the shape of the sealing resin 50 can be more properly maintained. Furthermore, the method for manufacturing the semiconductor device A20 has the same configuration as the method for manufacturing the semiconductor device A10, and thus achieves the same effects as the method for manufacturing the semiconductor device A10.

[0113] In the semiconductor device A20, a portion of the first power terminal 13 protrudes from the top surface 51 of the sealing resin 50. This configuration makes it easier to connect an external connection member such as a bus bar to the first connection surface 131 of the first power terminal 13.

[0114] In the above case, the surface roughness of the top surface 51 of the sealing resin 50 is greater than the surface roughness of the first side surface 53 of the sealing resin 50. By adopting this configuration, in the third step P3, it is possible to prevent the first power terminal 13 from interfering with the molding die while allowing a portion of the first power terminal 13 to protrude from the top surface 51.

[0115] Third Embodiment: A semiconductor device A30 according to a third embodiment of the present disclosure will be described with reference to Figures 30 and 31. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are given the same reference numerals, and duplicated descriptions will be omitted. Here, Figure 31 corresponds to Figure 11, which shows the semiconductor device A10.

[0116] The semiconductor device A30 differs from the semiconductor device A10 in that it further includes a protective layer 79.

[0117] 30 and 31 , the protective layer 79 covers a portion of the main surface 711 of the heat dissipation member 70. The protective layer 79 is an insulator. The protective layer 79 is made of a material containing at least one of a resin and a ceramic. When viewed in the first direction z, the protective layer 79 is located outward of the sealing resin 50.

[0118] Next, a semiconductor device A31 according to a modification of the third embodiment of the present disclosure will be described with reference to Fig. 32. Fig. 32 corresponds to Fig. 31 showing the semiconductor device A30. In the semiconductor device A31, the configuration of the protective layer 79 is different from that of the semiconductor device A30.

[0119] 32 , a portion of the protective layer 79 is located between the main surface 711 of the heat dissipation member 70 and the sealing resin 50 in the first direction z. As viewed in the first direction z, the protective layer 79 is located outward of the metal layer 112 and overlaps the insulating layer 111. In the semiconductor device A31, the heat dissipation member 70 does not have an engaging portion 73.

[0120] Next, an example of a method for manufacturing the semiconductor device A30 will be described with reference to Fig. 33. Fig. 33 corresponds to Fig. 10 showing the semiconductor device A10.

[0121] The method for manufacturing the semiconductor device A30 further includes a fifth step P5 in addition to the method for manufacturing the semiconductor device A10.

[0122] After the third step P3 shown in FIG. 22 is completed, a fifth step P5 is performed to form a protective layer 79 that covers a portion of the main surface 711 of the heat dissipation member 70, as shown in FIG. 33 . In the fifth step P5, the protective layer 79 is formed so as to be positioned outward from the sealing resin 50 when viewed in the first direction z. Here, the fifth step P5 may be performed before the third step P3. By performing this procedure, the semiconductor device A31 can be obtained. In the fifth step P5 based on this procedure, the protective layer 79 is formed so as to be positioned outward from the metal layer 112 when viewed in the first direction z.

[0123] Next, the effects of the manufacturing method of the semiconductor device A30 will be described.

[0124] The manufacturing method of the semiconductor device A30 includes a first process P1, a second process P2, and a third process P3. In the first process P1, the base material 11 having the insulating layer 111, the first conductive layer 121, and the second conductive layer 122 is bonded to the heat dissipation member 70. In the second process P2, the semiconductor element 20 is bonded to either the first conductive layer 121 or the second conductive layer 122. In the third process P3, the sealing resin 50 covering the semiconductor element 20 is formed. In the first process P1, the base material 11 is bonded to the heat dissipation member 70 so that the insulating layer 111 is positioned between the heat dissipation member 70 and the first conductive layer 121 and the second conductive layer 122. The third process P3 is performed after the first process P1 and the second process P2 are completed. Therefore, according to this configuration, even in the manufacturing method of the semiconductor device A30 in which the base material 11 is bonded to the heat dissipation member 70, the shape of the sealing resin 50 can be more properly maintained. Furthermore, the method for manufacturing the semiconductor device A30 has the same configuration as the method for manufacturing the semiconductor device A10, and thus achieves the same effects as the method for manufacturing the semiconductor device A10.

[0125] The manufacturing method of the semiconductor device A30 further includes a fifth process P5 of forming a protective layer 79, which is an insulator and covers a portion of the main surface 711 of the heat dissipation member 70. In the fifth process P5, the protective layer 79 is formed so as to be located outward of the sealing resin 50 as viewed in the first direction z. Here, when an external connection member such as a bus bar is connected to the first connection surface 131 of the first power terminal 13, the external connection member overlaps the main surface 711 as viewed in the first direction z. Therefore, by adopting this configuration, it is possible to suppress a decrease in the dielectric strength voltage of the semiconductor device A30 due to the connection of the external connection member.

[0126] The protective layer 79 includes a resin. In the semiconductor device A31, a portion of the protective layer 79 is located between the main surface 711 of the heat dissipation member 70 and the sealing resin 50 in the first direction z. With this configuration, the affinity between the protective layer 79 and the sealing resin 50 is relatively high, and therefore peeling of the sealing resin 50 from the main surface 711 can be suppressed.

[0127] Fourth Embodiment: A semiconductor device A40 according to a fourth embodiment of the present disclosure will be described with reference to FIGS. 34 to 36. In these figures, elements that are the same as or similar to those of the semiconductor device A10 and the semiconductor device A30 described above are designated by the same reference numerals, and duplicated descriptions will be omitted. Here, FIG. 35 corresponds to FIG. 10, which shows the semiconductor device A10. FIG. 36 corresponds to FIG. 11, which shows the semiconductor device A10.

[0128] The semiconductor device A40 differs from the semiconductor device A30 in that it further includes a frame 59 and in the configuration of the sealing resin 50.

[0129] As shown in FIGS. 34 to 36 , the frame body 59 surrounds the base material 11 in the first direction z. The frame body 59 is bonded to the main surface 711 of the heat dissipation member 70. The sealing resin 50 is housed in an area surrounded by the frame body 59. The frame body 59 is an insulator. The frame body 59 is made of a material containing at least one of resin and ceramics. The Young's modulus of the sealing resin 50 is lower than that of the frame body 59. In this case, the sealing resin 50 is made of a material containing, for example, silicone.

[0130] 35 and 36 , the frame body 59 has a frame surface 591 that faces the same side as the main surface 711 of the heat dissipation member 70 in the first direction z. The top surface 51 of the sealing resin 50 is located between the main surface 711 and the frame surface 591 in the first direction z. The first power terminal 13, the two second power terminals 14, and the two third power terminals 15 each protrude from the top surface 51 of the sealing resin 50. The sealing resin 50 does not have a plurality of recesses 55. The first connection surface 131 of the first power terminal 13, the second connection surface 141 of each of the two second power terminals 14, and the third connection surface 151 of each of the two third power terminals 15 are located on the opposite side of the top surface 51 from the bottom surface 52 of the sealing resin 50 in the first direction z.

[0131] Next, an example of a method for manufacturing the semiconductor device A40 will be described with reference to Figures 37 and 38. Each of Figures 37 and 38 corresponds to Figure 35 showing the semiconductor device A40.

[0132] The method for manufacturing the semiconductor device A40 differs from the method for manufacturing the semiconductor device A30 in the third step P3.

[0133] As shown in FIG. 37 , in the third process P3, before forming the sealing resin 50, a frame 59 that surrounds the base material 11 in the first direction z is bonded to the main surface 711 of the heat dissipation member 70. The fifth process P5 is performed simultaneously with the process of bonding the frame 59 to the main surface 711. Thereafter, as shown in FIG. 38 , the sealing resin 50 is formed. In the third process P3, the sealing resin 50 is contained in an area surrounded by the frame 59. To form the sealing resin 50, the uncured sealing resin 50 is injected into the area using a dispenser. In the third process P3, the sealing resin 50 is formed so that the top surface 51 of the sealing resin 50 is located between the main surface 711 and the frame surface 591 of the frame 59 in the first direction z. Additionally, the first power terminal 13, the two second power terminals 14, and the two third power terminals 15 are each made to protrude from the top surface 51.

[0134] Next, the effects of the manufacturing method of the semiconductor device A40 will be described.

[0135] The manufacturing method of the semiconductor device A40 includes a first process P1, a second process P2, and a third process P3. In the first process P1, the base material 11 having the insulating layer 111, the first conductive layer 121, and the second conductive layer 122 is bonded to the heat dissipation member 70. In the second process P2, the semiconductor element 20 is bonded to either the first conductive layer 121 or the second conductive layer 122. In the third process P3, the sealing resin 50 covering the semiconductor element 20 is formed. In the first process P1, the base material 11 is bonded to the heat dissipation member 70 so that the insulating layer 111 is positioned between the heat dissipation member 70 and the first conductive layer 121 and the second conductive layer 122. The third process P3 is performed after the first process P1 and the second process P2 are completed. Therefore, according to this configuration, even in the manufacturing method of the semiconductor device A40 in which the base material 11 is bonded to the heat dissipation member 70, the shape of the sealing resin 50 can be more properly maintained. Furthermore, the method for manufacturing the semiconductor device A40 has the same configuration as the method for manufacturing the semiconductor device A10, and thus achieves the same effects as the method for manufacturing the semiconductor device A10.

[0136] In the manufacturing method of semiconductor device A40, third process P3 includes a process of bonding frame 59 surrounding base material 11 to main surface 711 of heat dissipation member 70 before forming sealing resin 50. In third process P3, sealing resin 50 is contained in the area surrounded by frame 59. By adopting this configuration, the temperature for forming sealing resin 50 can be set lower than the temperature (approximately 180°C) required for transfer molding.

[0137] Fifth Embodiment: A semiconductor device A50 according to a fifth embodiment of the present disclosure will be described with reference to FIGS. 39 to 41. In these figures, elements that are the same as or similar to those in the semiconductor device A10 and the semiconductor device A30 described above are designated by the same reference numerals, and duplicated descriptions will be omitted. Here, FIG. 40 corresponds to FIG. 10, which shows the semiconductor device A10. FIG. 41 corresponds to FIG. 11, which shows the semiconductor device A10.

[0138] The semiconductor device A50 differs from the semiconductor device A30 in that it further includes a dam 58 and in the configuration of the sealing resin 50.

[0139] 39 to 41 , the dam body 58 surrounds the base material 11 in the first direction z. The dam body 58 contacts the main surface 711 of the heat dissipation member 70. The sealing resin 50 is contained in the area surrounded by the dam body 58. The dam body 58 is made of a material containing resin, similar to the sealing resin 50.

[0140] As shown in Figures 40 and 41 , the dam body 58 has an end surface 581 that faces the same side as the main surface 711 of the heat dissipation member 70 in the first direction z. The top surface 51 of the sealing resin 50 is located between the main surface 711 and the end surface 581 in the first direction z. The end surface 581 is convex in the first direction z. The first power terminal 13, the two second power terminals 14, and the two third power terminals 15 each protrude from the top surface 51 of the sealing resin 50. The sealing resin 50 does not have multiple recesses 55. The first connecting surface 131 of the first power terminal 13, the second connecting surface 141 of each of the two second power terminals 14, and the third connecting surface 151 of each of the two third power terminals 15 are located on the opposite side of the top surface 51 from the bottom surface 52 of the sealing resin 50 in the first direction z.

[0141] Next, an example of a method for manufacturing the semiconductor device A50 will be described with reference to Figures 42 and 43. Each of Figures 42 and 43 corresponds to Figure 40 showing the semiconductor device A50.

[0142] The method for manufacturing the semiconductor device A50 differs from the method for manufacturing the semiconductor device A30 in the third step P3.

[0143] As shown in FIG. 42 , in the third process P3, before forming the sealing resin 50, a dam 58 that surrounds the base material 11 in the first direction z is formed on the main surface 711 of the heat dissipation member 70. The dam 58 is formed by applying an uncured resin material to the main surface 711 and then curing the resin material. The fifth process P5 is performed simultaneously with the process of forming the dam 58. Thereafter, as shown in FIG. 43 , the sealing resin 50 is formed. In the third process P3, the sealing resin 50 is contained in a region surrounded by the dam 58. To form the sealing resin 50, the uncured sealing resin 50 is poured into the region and then cured. In this case, the viscosity of the sealing resin 50 before curing is different from the viscosity of the dam 58 before curing. In the third process P3, the sealing resin 50 is formed so that the top surface 51 of the sealing resin 50 is located between the main surface 711 and the end surface 581 of the dam body 58 in the first direction z. Additionally, the first power terminal 13, the two second power terminals 14, and the two third power terminals 15 are each made to protrude from the top surface 51.

[0144] Next, the effects of the manufacturing method of the semiconductor device A50 will be described.

[0145] The manufacturing method of the semiconductor device A50 includes a first process P1, a second process P2, and a third process P3. In the first process P1, the base material 11 having the insulating layer 111, the first conductive layer 121, and the second conductive layer 122 is bonded to the heat dissipation member 70. In the second process P2, the semiconductor element 20 is bonded to either the first conductive layer 121 or the second conductive layer 122. In the third process P3, the sealing resin 50 covering the semiconductor element 20 is formed. In the first process P1, the base material 11 is bonded to the heat dissipation member 70 so that the insulating layer 111 is positioned between the heat dissipation member 70 and the first conductive layer 121 and the second conductive layer 122. The third process P3 is performed after the first process P1 and the second process P2 are completed. Therefore, according to this configuration, even in the manufacturing method of the semiconductor device A50 in which the base material 11 is bonded to the heat dissipation member 70, the shape of the sealing resin 50 can be more properly maintained. Furthermore, the method for manufacturing the semiconductor device A50 has the same configuration as the method for manufacturing the semiconductor device A10, and thus achieves the same effects as the method for manufacturing the semiconductor device A10.

[0146] The present disclosure is not limited to the above-described embodiment, and the specific configuration of each part of the present disclosure can be freely modified in various ways.

[0147] The present disclosure includes embodiments described in the following supplementary notes. Supplementary note 1. A method for manufacturing a semiconductor device, comprising: a first step of bonding a base material having an insulating layer and a conductive layer located on one side of the insulating layer in a first direction to a heat dissipation member; a second step of bonding a semiconductor element to the conductive layer; and a third step of forming a sealing resin covering the semiconductor element, wherein in the first step, the base material is bonded to the heat dissipation member so that the insulating layer is located between the heat dissipation member and the conductive layer, and the third step is performed after each of the first step and the second step is completed. Supplementary note 2. The method for manufacturing a semiconductor device according to Supplementary note 1, wherein in the third step, the sealing resin contacts the main surface, the base material is covered by the sealing resin, and the end surface is exposed from the sealing resin. Supplementary note 3. Appendix 2, wherein in the third step, the sealing resin is positioned inward from the periphery of the heat dissipation member when viewed in the first direction. Appendix 4. Appendix 2, wherein in the first step, the base is bonded to the main surface via a first bonding layer, and the temperature at which the sealing resin is formed in the third step is lower than the temperature at which the first bonding layer is formed in the first step. Appendix 5. Appendix 4, wherein the base has a metal layer positioned on the opposite side of the insulating layer from the conductive layer, and the metal layer is bonded to the base in the first step. Appendix 6. Appendix 5, wherein in the first step, pressure is applied to the base in a direction facing the main surface in the first direction. Appendix 7. The method for manufacturing a semiconductor device according to any one of Appendix 4 to 6, further comprising a fourth step of conductively bonding a conductive member to the semiconductor element via a second bonding layer, the fourth step being performed before the third step, the conductive member being covered with the sealing resin in the third step, and the temperature at which the sealing resin is formed in the third step being lower than the temperature at which the second bonding layer is formed in the fourth step. Appendix 8. The method for manufacturing a semiconductor device according to Appendix 7, wherein the melting point of the second bonding layer is lower than the melting point of the first bonding layer.Appendix 9. The method for manufacturing a semiconductor device according to Appendix 8, further comprising the step of arranging a power terminal electrically connected to the semiconductor element, wherein the step of arranging the power terminal is performed before the fourth step, and wherein a portion of the power terminal is covered with the sealing resin in the third step. Appendix 10. The method for manufacturing a semiconductor device according to Appendix 9, wherein the second step conductively bonds the semiconductor element to the conductive layer. Appendix 11. The method for manufacturing a semiconductor device according to Appendix 10, wherein the power terminal includes a first power terminal and a second power terminal spaced apart from each other, wherein the step of arranging the power terminals conductively bonds the first power terminal to the conductive layer and arranges the second power terminal on the insulating layer, and wherein the fourth step conductively bonds the conductive member to the second power terminal via the second bonding layer. Appendix 12. The method for manufacturing a semiconductor device according to Appendix 11, wherein the second step is performed simultaneously with the first step, and wherein the second step conductively bonds the semiconductor element to the conductive layer via the first bonding layer. Appendix 13. The method for manufacturing a semiconductor device according to Appendix 11, wherein the second step is performed simultaneously with the fourth step, and wherein the second step conductively bonds the semiconductor element to the conductive layer via the second bonding layer. Appendix 14. The method for manufacturing a semiconductor device according to Appendix 11, wherein the sealing resin has a top surface facing the same side as the main surface in the first direction, and wherein the power terminal is exposed from the top surface in the third step. Appendix 15. The method for manufacturing a semiconductor device according to Appendix 14, wherein the heat dissipation member is provided with an engagement portion recessed from the main surface, and wherein the sealing resin is recessed into the engagement portion in the third step. Appendix 16. The method for manufacturing a semiconductor device according to Appendix 14, further comprising a fifth step of forming a protective layer that covers a portion of the main surface and is an insulator. Appendix 17. The method for manufacturing a semiconductor device according to Appendix 16, wherein in the fifth step, the protective layer is formed so as to be positioned outward of the sealing resin when viewed in the first direction. Appendix 18. Supplementary Note 5: The method for manufacturing a semiconductor device according to Supplementary Note 5, wherein the first bonding layer is a sintered body of metal particles containing silver. Supplementary Note 19: The method for manufacturing a semiconductor device according to Supplementary Note 6, wherein the first bonding layer is a solid-phase diffusion layer. Supplementary Note 20: The method for manufacturing a semiconductor device according to Supplementary Note 8, wherein the second bonding layer contains tin.Appendix 21. The method for manufacturing a semiconductor device according to Appendix 14, wherein in the third step, the power terminal is caused to protrude from the top surface. Appendix 22. The method for manufacturing a semiconductor device according to Appendix 21, wherein the third step includes a step of bonding a frame body surrounding the base to the main surface before forming the sealing resin, and wherein in the third step, the sealing resin is contained in an area surrounded by the frame body. Appendix 23. The method for manufacturing a semiconductor device according to Appendix 22, wherein the frame body is an insulator. Appendix 24. The method for manufacturing a semiconductor device according to Appendix 23, wherein the Young's modulus of the sealing resin is lower than that of the frame body. Appendix 25. The method for manufacturing a semiconductor device according to Appendix 23, wherein the frame body has a frame surface facing the same side as the main surface in the first direction, and wherein in the third step, the sealing resin is formed so that the top surface is located between the main surface and the frame surface in the first direction. Appendix 26. Appendix 27. The method for manufacturing a semiconductor device according to Appendix 16, further comprising the step of arranging a signal terminal electrically connected to the semiconductor element, wherein the step of arranging the signal terminal is performed after the third step, and wherein the step of arranging the signal terminal causes the signal terminal to protrude from the top surface. Appendix 27. The method for manufacturing a semiconductor device according to Appendix 16, wherein the protective layer includes a resin. Appendix 28. A semiconductor device comprising: a heat dissipation member having a main surface facing one side in a first direction and an end surface facing a direction perpendicular to the first direction; a base having a conductive layer and bonded to the main surface; a semiconductor element bonded to the conductive layer; and a sealing resin covering the base and the semiconductor element, wherein the base has an insulating layer positioned between the main surface and the conductive layer, the sealing resin is in contact with the main surface, and the end surface is exposed from the sealing resin. Appendix 29. The semiconductor device according to Appendix 28, wherein the sealing resin is positioned inward from a periphery of the heat dissipation member when viewed in the first direction. Appendix 30. 30. The semiconductor device of claim 29, further comprising a power terminal electrically connected to the semiconductor element, wherein the sealing resin has a top surface facing the same side as the main surface in the first direction, and the power terminal is exposed from the top surface.Appendix 31. The semiconductor device according to Appendix 30, wherein the heat dissipation member has an engaging portion recessed from the main surface, and a portion of the sealing resin is accommodated in the engaging portion. Appendix 32. The semiconductor device according to Appendix 30 or 31, wherein the base has a metal layer located between the main surface and the insulating layer, and the metal layer is bonded to the main surface. Appendix 33. The semiconductor device according to Appendix 32, wherein, as viewed in the first direction, the conductive layer and the metal layer are each located inward from a periphery of the insulating layer. Appendix 34. The semiconductor device according to Appendix 33, further comprising a conductive member conductively bonded to the semiconductor element, and the semiconductor element is conductively bonded to the conductive layer. Appendix 35. The semiconductor device according to Appendix 34, wherein the power terminal includes a first power terminal conductively bonded to the conductive layer and a second power terminal disposed on the insulating layer, and the conductive member is conductively bonded to the second power terminal. Appendix 36. Appendix 35. The semiconductor device according to Appendix 35, further comprising a first bonding layer bonding the main surface and the metal layer, and a second bonding layer bonding the semiconductor element and the conductive member, wherein the glass transition point of the sealing resin is lower than the melting points of the first bonding layer and the second bonding layer. Appendix 37. The semiconductor device according to Appendix 36, wherein the melting point of the second bonding layer is lower than the melting point of the first metal layer. Appendix 38. The semiconductor device according to Appendix 37, further comprising a protective layer covering a portion of the main surface and being an insulator. Appendix 39. The semiconductor device according to Appendix 38, wherein a portion of the protective layer is located between the main surface and the sealing resin in the first direction. Appendix 40. The semiconductor device according to Appendix 38, further comprising a frame bonded to the main surface and surrounding the base, wherein the sealing resin is contained in a region surrounded by the frame. Appendix 41. A vehicle comprising: a drive source; and a semiconductor device according to any one of appendices 28 to 40, wherein the semiconductor device is electrically connected to the drive source.

[0148] A10, A20, A30, A40: semiconductor device B: vehicle 11: substrate 111: insulating layer 111A: periphery 112: metal layer 121: first conductive layer 121A: first mounting surface 122: second conductive layer 122A: second mounting surface 13: first power terminal 131: first connecting surface 14: second power terminal 141: second connecting surface 15: third power terminal 151: third connecting surface 161: first signal terminal 162: second signal terminal 171: third signal terminal 172: fourth signal terminal 181: fifth signal terminal 182: sixth signal terminal 19: first bonding layer 20: semiconductor element 21: first semiconductor element 211: first electrode 212: second electrode 213: first gate electrode 214: First detection electrode 22: Second semiconductor element 221: Third electrode 222: Fourth electrode 223: Second gate electrode 224: Second detection electrode 23: Thermistor 31: First conductive member 311: Main body 312: First bonding portion 313: First connecting portion 314: Second bonding portion 315: Second connecting portion 32: Second conductive member 321: Main body 322: Third bonding portion 323: Third connecting portion 324: Fourth bonding portion 325: Fourth connecting portion 326: Middle portion 327: Horizontal beam portion 39: Second bonding layer 41-42, 44-47: First and second wires,Fourth to seventh wires 50: Sealing resin 501: Periphery 51: Top surface 52: Bottom surface 53: First side surface 54: Second side surface 55: Recesses 55A to 55C: First to third recesses 58: Weir 581: End surface 59: Frame 591: Frame surface 61: First wiring 611: First mounting layer 612: First metal layer 613: First gate wiring layer 614: First detection wiring layer 615: First temperature detection wiring layer 616: Second detection wiring layer 62: Second wiring 621: Second mounting layer 622: Second metal layer 623: Second gate wiring layer 624: Third detection wiring layer 625: Second temperature detection wiring layer 626: Fourth detection wiring layer 63: Sleeve 631: End surface 70: Heat dissipation member 701: Periphery 71: Base 711: Main surface 712: End surface 713: Inner circumferential surface 72: Heat dissipation portion 73: Engagement portion 79: Protective layer 81: On-board charger 82: Storage battery 83: Drive system 831: Inverter 832: Drive source P1 to P5: 1st to 5th steps z: 1st direction x: 2nd direction y: 3rd direction,

Claims

1. A method for manufacturing a semiconductor device, comprising: a first step of bonding a substrate having an insulating layer and a conductive layer located on one side of the insulating layer in a first direction to a heat dissipation member; a second step of bonding a semiconductor element to the conductive layer; and a third step of forming an encapsulating resin covering the semiconductor element, wherein in the first step, the substrate is bonded to the heat dissipation member such that the insulating layer is located between the heat dissipation member and the conductive layer, and the third step is performed after each of the first step and the second step has been completed.

2. The method for manufacturing a semiconductor device as described in claim 1, wherein the heat dissipation member has a main surface facing the base material and an end surface facing a direction perpendicular to the first direction, and in the third step, the sealing resin contacts the main surface, the base material is covered with the sealing resin, and the end surface is exposed from the sealing resin.

3. A method for manufacturing a semiconductor device as described in claim 2, wherein in the third step, the sealing resin is positioned inward from the periphery of the heat dissipation component when viewed in the first direction.

4. The method for manufacturing a semiconductor device according to claim 2, wherein in the first step, the base material is bonded to the main surface via a first bonding layer, and the temperature at which the sealing resin is formed in the third step is lower than the temperature at which the first bonding layer is formed in the first step.

5. The method for manufacturing a semiconductor device according to claim 4, wherein the base material has a metal layer located on the opposite side of the insulating layer to the conductive layer, and in the first step, the metal layer is bonded to the base material.

6. A method for manufacturing a semiconductor device according to claim 5, wherein in the first step, a pressure is applied to the base material in a direction opposite to the main surface in the first direction.

7. A method for manufacturing a semiconductor device as described in any one of claims 4 to 6, further comprising a fourth step of conductively bonding a conductive member to the semiconductor element via a second bonding layer, the fourth step being performed before the third step, the conductive member being covered with the sealing resin in the third step, and the temperature at which the sealing resin is formed in the third step being lower than the temperature at which the second bonding layer is formed in the fourth step.

8. The method for manufacturing a semiconductor device according to claim 7, wherein the melting point of the second bonding layer is lower than the melting point of the first bonding layer.

9. The method for manufacturing a semiconductor device according to claim 8, further comprising the step of arranging a power terminal conductive to the semiconductor element, the step of arranging the power terminal being performed before the fourth step, and in the third step, a portion of the power terminal is covered with the sealing resin.

10. The method for manufacturing a semiconductor device according to claim 9, wherein in the second step, the semiconductor element is conductively bonded to the conductive layer.

11. The method for manufacturing a semiconductor device as described in claim 10, wherein the power terminal includes a first power terminal and a second power terminal spaced apart from each other, the step of arranging the power terminals comprises conductively joining the first power terminal to the conductive layer and arranging the second power terminal on the insulating layer, and the fourth step comprises conductively joining the conductive member to the second power terminal via the second bonding layer.

12. The method for manufacturing a semiconductor device according to claim 11, wherein the second step is performed simultaneously with the first step, and in the second step, the semiconductor element is conductively bonded to the conductive layer via the first bonding layer.

13. The method for manufacturing a semiconductor device according to claim 11, wherein the second step is performed simultaneously with the fourth step, and in the second step, the semiconductor element is conductively bonded to the conductive layer via the second bonding layer.

14. The method for manufacturing a semiconductor device according to claim 11, wherein the sealing resin has a top surface facing the same side as the main surface in the first direction, and in the third step, the power terminal is exposed from the top surface.

15. The method for manufacturing a semiconductor device according to claim 14, wherein the heat dissipation member is provided with an engagement portion recessed from the main surface, and in the third step, the sealing resin is caused to sink into the engagement portion.

16. The method for manufacturing a semiconductor device according to claim 14, further comprising a fifth step of forming a protective layer which covers a portion of the main surface and is an insulator.

17. The method for manufacturing a semiconductor device according to claim 16, wherein in the fifth step, the protective layer is formed so as to be positioned outward from the sealing resin when viewed in the first direction.

18. A semiconductor device comprising: a heat dissipation member having a main surface facing one side of a first direction and an end surface facing a direction perpendicular to the first direction; a substrate having a conductive layer and bonded to the main surface; a semiconductor element bonded to the conductive layer; and a sealing resin covering the substrate and the semiconductor element, wherein the substrate has an insulating layer located between the main surface and the conductive layer, the sealing resin is in contact with the main surface, and the end surface is exposed from the sealing resin.

19. The semiconductor device according to claim 18, wherein the sealing resin is located inward from the periphery of the heat dissipation member when viewed in the first direction.

20. A vehicle comprising: a driving source; and the semiconductor device according to claim 18 or 19, wherein the semiconductor device is electrically connected to the driving source.

Images