Semiconductor device, power supply device, and vehicle

Abstract

The pattern (2, 2A, 2B, 2C) of the semiconductor device (100, 100A, 100B, 100C) has a first node (21, 21a, 21b, 21c) formed on an outer peripheral part and configured to be connected to a first potential, and has a second node (22, 22b, 22c) insulated from the first node (21, 21a, 21b, 21c) and configured so that a second potential different from the first potential is applied. The first node (21, 21a, 21b, 21c) and the second node (22, 22b, 22c) are configured such that at least a portion thereof faces each other.

Description

Semiconductor device, power supply device and vehicle

[0001] The present invention relates to a semiconductor device, and to a power supply device and a vehicle using the semiconductor device.

[0002] 2. Description of the Related Art In semiconductor devices, radiation noise may occur in response to switching of switching elements, etc. Such noise is also called EMI (Electro-Magnetic Interference).

[0003] If the level of EMI emitted by a semiconductor device is high, it can have a negative effect on other electronic devices, so regulatory limits are set for electronic devices. Electronic devices that house electronic components for EMI countermeasures in the semiconductor device package are known (see, for example, Patent Document 1).

[0004] Japanese Patent Application Laid-Open No. 2018-14793

[0005] [Summary] There is an increasing demand for miniaturization of semiconductor devices, but miniaturization is difficult when electronic components for EMI countermeasures are housed in the package of the semiconductor device.

[0006] A semiconductor device according to one aspect of the present disclosure has a structure in which a pattern is formed, the pattern having a first node formed on an outer periphery in a plan view and configured to be connected to a first potential, and a second node arranged insulated from the first node and configured to be applied with a second potential different from the first potential, the first node and the second node being configured to at least partially face each other.

[0007] FIG. 1 is a schematic layout diagram of a semiconductor device. FIG. 2 is an enlarged cross-sectional view of a pattern of the semiconductor device. FIG. 3 is an equivalent circuit diagram of the semiconductor device. FIG. 4 is a schematic layout diagram of a semiconductor device of a first modified example. FIG. 5 is an equivalent circuit diagram of the semiconductor device shown in FIG. 4. FIG. 6 is a schematic layout diagram of a semiconductor device of a second modified example. FIG. 7 is a schematic cross-sectional view of a semiconductor device of a third modified example. FIG. 8 is a diagram showing the external appearance of a vehicle.

[0008] [Detailed Description] In this specification, a MOS (Metal Oxide Semiconductor) field effect transistor refers to a transistor whose gate structure is composed of at least three layers: a layer made of a conductor or a semiconductor such as polysilicon with a low resistance value, an insulating layer, and a P-channel, N-channel, or intrinsic semiconductor layer. In other words, the gate structure of a MOS field effect transistor is not limited to a three-layer structure of a metal, an oxide, and a semiconductor.

[0009] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In this specification, when it is stated that members are connected to each other, this includes not only a mechanical connection but also an electrical connection, in other words, a state in which electricity flows. Therefore, "connect" includes "electrically connected."

[0010] <Semiconductor Device 100> Fig. 1 is a schematic layout diagram of the semiconductor device 100. Fig. 2 is an enlarged cross-sectional view of a pattern 2 of the semiconductor device 100. The semiconductor device 100 is a power supply device. The semiconductor device 100 has a substrate 1, a pattern 2, and a plurality of electronic components 3. The semiconductor device 100 is housed in a single package. Housed in a package means that the semiconductor device is viewed from the outside as a single component, and may include being molded with resin and housed in a metal or resin case. The form of the package is not particularly limited.

[0011] The electronic components 3 perform a predetermined operation when a voltage is applied. Examples of the multiple electronic components 3 include power MOS transistors, IGBTs (Insulated Gate Bipolar Transistors), inverters, and controllers. The semiconductor device 100 is a power supply device in this embodiment. The semiconductor device 100 includes electronic components 3 that can configure a circuit that can output an output voltage Vout by stepping up or stepping down an input voltage Vin. In addition, the electronic components 3 may be a functional integrated circuit (IC) that can perform a predetermined function by combining the above electronic components.

[0012] 2, the substrate 1 is a rectangular plate in a plan view, and an end surface in the thickness direction is a component mounting surface. In this embodiment, the thickness direction of the substrate 1 is the vertical direction in which gravity acts, and the substrate 1 will be described as having an upper surface 11 and a lower surface 12. The upper surface 11 and the lower surface 12 do not limit the directions of the semiconductor device 100 when in use. Patterns 2 are formed on the upper surface 11 and the lower surface 12 of the substrate 1.

[0013] The pattern 2 is, for example, a pattern wiring formed on the surface of the substrate 1. Here, the pattern 2 is described as being formed on the upper surface 11 of the substrate 1. The pattern 2 may be formed on both sides of the substrate 1, or the substrate 1 may be a multilayer substrate with a pattern formed on each layer.

[0014] In addition, in a plan view, the pattern 2 has a first node 21, a second node 22, and a third node 23. In a plan view, the first node 21 is formed along the outer periphery. The first node 21 is connected to a ground potential GND, which is a first potential.

[0015] The second node 22 is formed outside the first node 21 on the outer periphery of the substrate 1 in a plan view. The second node 22 is connected to a second potential Ea different from the first potential. The second potential Ea is a potential capable of supplying a control voltage Vcc that operates the electronic component 3, and is one of power supply potentials. To explain further, when the electronic component 3 operates using the ground potential GND as a reference potential, the second potential Ea can be said to be a potential higher than the ground potential GND by the control voltage Vcc or more.

[0016] The third node 23 is disposed inside the first node 21 of the substrate 1 in a plan view. The third node 23 connects a plurality of electronic components 3 to form a circuit. In other words, the electronic components 3 are connected by the third node 23 to form a circuit that performs a predetermined operation in the semiconductor device 100. The third node 23 has a portion that is connected to both the first node 21 and the second node 22.

[0017] In the semiconductor device 100, the first node 21 connected to the ground potential GND is arranged outside the circuit formed by connecting the electronic component 3 to the third node 23. Therefore, a high voltage due to an external ESD (Electro-Static Discharge) flows from the first node 21 to the ground potential GND. This makes it possible to prevent a high voltage from being applied to the third node 23 and an internal circuit formed by the electronic device, even if ESD occurs in the semiconductor device 100.

[0018] As shown in FIG. 2 , the second node 22 and the first node 21 face each other across a gap 20 in a direction along the upper surface 11 of the substrate 1. The second node 22 is disposed outside the first node 21. As a result, the first node 21 and the second node 22 form a capacitor C (see FIG. 3 described later). Note that the gap 20 may be empty space, or a material with a high dielectric constant may be disposed therein. For example, when packaging is performed by molding with resin, the resin used for the package is filled into the gap 20.

[0019] 3 is an equivalent circuit diagram of the semiconductor device 100. In the circuit diagram shown in FIG. 3, a first node 21 forms part of the ground line Lg and is connected to the ground potential GND. A second node 22 forms part of the control power supply line Lcc and is connected to a second potential Ea for supplying a control voltage Vcc to the electronic component 3. The control power supply line Lcc is connected to the ground line Lg via a capacitor C. That is, the control power supply line Lcc is connected to the ground potential GND via the capacitor C. The electronic component 3 is also provided with an input line Lin through which an input voltage Vin is input and an output line Lout through which an output voltage Vout is output. The semiconductor device 100 outputs an output voltage Vout by stepping up or stepping down the input voltage Vin input from the input line Lin.

[0020] The second node 22, which is the control power supply line Lcc, is connected to the electronic component 3 directly or indirectly via the third node 23. As a result, the control voltage Vcc is applied to the connected electronic component 3. The control power supply line Lcc is also connected to the ground potential GND via the capacitor C. As a result, the capacitor C functions as a noise filter. For example, noise due to EMI (Electro-Magnetic Interference) may be superimposed on the control voltage Vcc via the second node 22 and input to the semiconductor device 100. Even in such cases, the noise is removed by the capacitor C. As a result, the influence of noise on the internal circuitry of the semiconductor device 100 can be suppressed.

[0021] That is, in the semiconductor device 100, the first node 21 and the second node 22 of the pattern 2 can form a capacitor C. Therefore, in the semiconductor device 100, the influence of noise from outside the semiconductor device 100 is reduced without providing a separate capacitor for noise removal outside the circuit.

[0022] In the present embodiment, the first node 21 is connected to the ground potential GND, but the present invention is not limited to this. The first node 21 may be connected to a reference potential of the electronic component 3 in the semiconductor device 100. The reference potential is a potential lower than the second potential Ea. In this way, a capacitor C is formed between the first node 21 and the second node 22, making it possible to remove noise input via the second node 22.

[0023] Furthermore, although the second node 22 is configured to be connected to the second potential Ea, this is not limiting. A wide variety of configurations can be adopted in which the second node 22 is connected to a potential at which a signal (or voltage) that is susceptible to noise superposition is input or output, and which is different from the potential at the first node 21. Examples of such a line include lines through which an output voltage, a reset signal, etc. are input or output. The second node 22 may also be configured to be a line other than these.

[0024] In either case, noise input to or output from the second node 22 is removed by the capacitor C formed by the first node 21 and the second node 22. As described above, since the capacitor C for removing noise is formed by the first node 21 and the second node 22 of the pattern 2 arranged on the substrate 1, the package of the semiconductor device 100 can be made smaller than when an EMI countermeasure component is attached.

[0025] <First Modification> Fig. 4 is a schematic layout diagram of a semiconductor device 100A of a first modification. Fig. 5 is an equivalent circuit diagram of the semiconductor device 100A shown in Fig. 4. In the semiconductor device 100A shown in Fig. 4, the first node 21a will be described by dividing it into a first region 21r1, a second region 21r2, and a third region 21r3. Also, the semiconductor device 100A differs from the semiconductor device 100 in that the pattern 2A has a fourth node 24 and a fifth node 25 in addition to the second node 22. Other parts of the semiconductor device 100A have the same configuration as the semiconductor device 100.

[0026] Therefore, the same reference numerals are used to designate the same parts of the semiconductor device 100A as those of the semiconductor device 100, and detailed descriptions of the same parts will be omitted. The second node 22, the fourth node 24, and the fifth node 25 have the same configuration, except that they are connected to different potentials. Therefore, the second node 22, the fourth node 24, and the fifth node 25 are interchangeable with each other. In other words, the fourth node 24 and the fifth node 25 can be considered as other examples of the second node 22.

[0027] The first node 21a is formed such that the first region 21r1, the second region 21r2, and the third region 21r3 are integrally formed and connected to the ground potential GND. That is, the first region 21r1, the second region 21r2, and the third region 21r3 are all at the ground potential GND. The second node 22 is disposed outside the first region 21r1 in a planar view, facing the first region 21r1 across the gap 20a1. Similarly, the fourth node 24 is disposed outside the second region 21r2 in a planar view, facing the second region 21r2 across the gap 20a2. Furthermore, the fifth node 25 is disposed outside the third region 21r3 in a planar view, facing the third region 21r3 across the gap 20a3.

[0028] 4, the second node 22 is connected to a second potential Ea and constitutes a part of the control power supply line Lcc. The fourth node 24 is connected to a terminal from which the output voltage Vout of the electronic component 3 is output and constitutes a part of the output line Lout. The output voltage Vout is a voltage supplied from the semiconductor device 100A to an external device. Therefore, the output potential Eao of the output line Lout including the fourth node 24 is higher than the ground potential GND.

[0029] The fifth node 25 is connected to the power supply potential Eai and forms part of the input line Lin that inputs the input voltage Vin to the electronic component 3. The electronic component 3 steps up or steps down the input voltage Vin to output the output voltage Vout. The electronic component 3 operates using the ground potential GND as a reference potential, and the power supply potential Eai is higher than the ground potential GND.

[0030] As described above, the second node 22 and the first region 21r1 of the first node 21a, which face each other across the gap 20a1, are at different potentials. Therefore, as shown in FIG. 5 , the second node 22 and the first region 21a1 of the first node 21a form a capacitor Ca1. Furthermore, the fourth node 24 and the second region 21r2 of the first node 21a, which face each other across the gap 20a2, form a capacitor Ca2. Furthermore, the fifth node 25 and the third region 21r3 of the first node 21a, which face each other across the gap 20a3, form a capacitor Ca3.

[0031] The capacitor Ca1, which is formed by the second node 22 and the first region 21r1 of the first node 21, operates as a noise filter. The capacitor Ca1 removes noise that is input together with the control voltage Vcc supplied via the second node 22.

[0032] Furthermore, the capacitor Ca2 formed by the fourth node 24 and the second region 21r2 of the first node 21 operates as a smoothing capacitor. The semiconductor device 100A may include, for example, an electronic component 3 that forms a step-up circuit or a step-down circuit using a switching element to convert the input voltage Vin to the output voltage Vout. The switching element converts voltage by switching at high speed, and generates noise (switching noise) during switching operations. The switching noise is included in the output voltage Vout, but is removed by the capacitor Ca2. In other words, the influence of noise generated inside the semiconductor device 100A on the outside can be suppressed.

[0033] Furthermore, the capacitor Ca3 formed by the fifth node 25 and the third region 21r3 of the first node 21 operates as a noise filter. The semiconductor device 100A is supplied with an input voltage Vin from the power supply potential Eai. At this time, the input voltage Vin may contain noise. The capacitor Ca3 operates as a noise filter, thereby removing the noise contained in the input voltage Vin. As a result, the input voltage Vin from which the noise has been removed is input, thereby removing the influence of external noise contained in the input voltage Vin.

[0034] As in the semiconductor device 100A shown above, the first node 21 connected to the ground potential GND may be divided into multiple regions, and the lines through which input or output (voltage, signal) flow may be arranged with gaps between the respective regions, i.e., so as to form capacitors. This allows the semiconductor device 100A to be made smaller than when a capacitor for removing noise is provided on each line.

[0035] In addition, the potentials to which the second node 22, the fourth node 24, and the fifth node 25 constituting the capacitor are connected can be widely any potential to which signals or voltages that are prone to noise superposition are input or output, in addition to the configuration in which they are connected to the potentials described above.

[0036] <Second Modification> Fig. 6 is an enlarged layout diagram of a semiconductor device 100B according to a second modification. Fig. 6 is an enlarged view of the opposing portions of the first node 21b and the second node 22b of the pattern 2B of the semiconductor device 100B. In the semiconductor device 100B shown in Fig. 6, the shape of the opposing portions of the first node 21b and the second node 22b of the pattern 2B is different from that of the semiconductor device 100. Other than this, the semiconductor device 100B is substantially the same as the semiconductor device 100, and the substantially same parts are denoted by the same reference numerals and detailed description of the same parts will be omitted.

[0037] 6, the first node 21b has a plurality of first protrusions 211 that protrude outward. The first protrusions 211 are arranged at intervals in a direction intersecting the protruding direction. The second node 22b, which is disposed outside the first node 21b, has a plurality of second protrusions 221 that protrude inward.

[0038] 6, the first protrusions 211 and the second protrusions 221 are arranged alternately with gaps 20b between them. By arranging the first protrusions 211 and the second protrusions 221 alternately in this manner, the first protrusions 211 and the second protrusions 221 form a capacitor. By configuring the first protrusions 211 and the second protrusions 221 in this manner, the area where the first node 21b and the second node 22b face each other becomes larger. This means that the capacitance of the capacitor formed by the first node 21b and the second node 22b can be increased. This increases the amount of noise that can be removed.

[0039] <Third Modification> Figure 7 is a schematic cross-sectional view of a semiconductor device 100C of a third modification. In the semiconductor device 100C shown in Figure 7, the substrate 1C is a multi-layer substrate, and patterns are formed on each layer. Other parts of the semiconductor device 100C have the same configuration as the semiconductor device 100. Therefore, parts of the semiconductor device 100C that are substantially the same as those of the semiconductor device 100 are given the same reference numerals, and detailed descriptions of the same parts will be omitted.

[0040] 7 , in the semiconductor device 100C, the substrate 1C is a multilayer substrate. The substrate 1C is configured by stacking three layers, namely, a first layer 101, a second layer 102, and a third layer 103, from the top. The pattern 2C has a first pattern 201, a second pattern 202, and a third pattern 203 formed on the first layer 101, the second layer 102, and the third layer 103, respectively. The first pattern 201 is formed on the upper surface of the first layer 101, the second pattern 202 is formed on the upper surface of the second layer 102, and the third pattern 203 is formed on the upper surface of the third layer 103.

[0041] The first node 21c has a first layer portion 21c1 formed in the first pattern 201 and a second layer portion 21c2 formed in the second pattern 202. The first layer portion 21c1 and the second layer portion 21c2 of the first node 21c are connected by a via 26.

[0042] The second node 22c has a first layer portion 22c1 formed in the first pattern 201, a second layer portion 22c2 formed in the second pattern 202, and a third layer portion 22c3 formed in the third layer portion 22c3. The first layer portion 22c1 and the second layer portion 22c2, and the second layer portion 22c2 and the third layer portion 22c3 of the second node 22c are connected by vias 26, respectively.

[0043] The first layer portion 21c1 and the second layer portion 21c2 of the first node 21c and the first layer portion 22c1 and the second layer portion 22c2 of the second node 22c face each other across a gap 20c in a direction perpendicular to the stacking direction (vertical direction) of the substrate 1C. As a result, the first layer portion 21c1 and the second layer portion 21c2 of the first node 21c and the first layer portion 22c1 and the second layer portion 22c2 of the second node 22c form a capacitor Cc1 (shown by a two-dot chain line in FIG. 7).

[0044] Furthermore, the third layer portion 22c3 of the second node 22c extends below the second layer portion 21c2 of the first node 21c. As a result, the third layer portion 22c3 of the second node 22c is arranged alongside the second layer portion 21c2 of the first node 21c in the stacking direction (vertical direction) of the substrate 1C, with the second layer 102 of the substrate 1C interposed therebetween. As a result, the second layer portion 21c2 of the first node 21c and the third layer portion 22c3 of the second node 22c form a capacitor Cc2 (shown by a two-dot chain line in FIG. 7 ).

[0045] The first node 21c and the second node 22c constitute a capacitor Cc having a capacitance obtained by connecting capacitors Cc1 and Cc2 in parallel. In other words, by using a multi-layer substrate 1C, the first node 21c and the second node 22c can be arranged in the stacking direction of the substrate 1C, and the capacitance of the capacitor Cc constituted by the first node 21c and the second node 22c can be increased.

[0046] In this modification, the first node 21c and the second node 22c are configured to have both portions that face each other in a direction perpendicular to the stacking direction and portions that are arranged side by side in the stacking direction, but this is not limiting. The first node 21c and the second node 22c may be arranged side by side only in the stacking direction. In this case, the first node 21c may be arranged on one side of a single-layer double-sided board, and the second node 22c may be arranged on the other side.

[0047] <Application to Vehicle> Fig. 8 is a diagram showing the appearance of a vehicle 200. A vehicle 200 of this configuration example is equipped with various electronic devices that operate by receiving power supply from a battery.

[0048] Vehicle 200 includes not only engine vehicles but also electric vehicles (battery electric vehicles (BEVs), hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs / PHVs), or xEVs such as fuel cell electric vehicles (FCEVs / FCVs)).

[0049] The semiconductor devices 100, 100A, 100B, and 100C described above can be incorporated into a power supply device that supplies power to electronic devices mounted on the vehicle 200. They can also be incorporated into the electronic devices themselves. Furthermore, they can also be incorporated into an inverter device that controls a motor that is a power source for an electric vehicle.

[0050] <Others> The above-described embodiments should be considered to be illustrative in all respects and not restrictive, and the technical scope of the present disclosure is indicated by the claims rather than the description of the above-described embodiments, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0051] <Additional Notes> The semiconductor devices (100, 100A, 100B, 100C) described above have a configuration in which a pattern (2) is formed. The pattern (2, 2A, 2B, 2C) has first nodes (21, 21a, 21b, 21c) formed on the periphery in a plan view and configured to be connected to a first potential, and second nodes (22, 22b, 22c) arranged insulated from the first nodes (21, 21a, 21b, 21c) and configured to be applied with a second potential different from the first potential. The first nodes (21, 21a, 21b, 21c) and the second nodes (22, 22b, 22c) are configured to be at least partially opposed to each other (first configuration).

[0052] While there is a growing demand for miniaturization of semiconductor devices, it is difficult to miniaturize the package of the semiconductor device when electronic components for EMS countermeasures are attached. According to the first configuration, a capacitor for EMS countermeasures can be configured using the first node and the second node of the semiconductor device pattern, which simplifies the configuration of the semiconductor device compared to a configuration in which a separate electronic component is attached. As a result, the package of the semiconductor device can be miniaturized.

[0053] In the semiconductor device (100, 100A, 100B, 100C) of the first configuration, the second node (22, 22b, 22c) is configured to be positioned outward in a planar view from the first node (21, 21a, 21b, 21c), (second configuration).

[0054] In the semiconductor device (100C) of the first or second configuration, the pattern (2C) is formed by stacking multiple layers, and is configured to have portions (21c2, 22c3) formed in layers different from the first node (21c) and the second node (22c) and facing each other in the stacking direction (third configuration).

[0055] In the semiconductor device (100B) of any one of the first to third configurations, the first node (21b) has a plurality of first protrusions (211) configured to extend toward the second node (22b). The second node (22b) has a plurality of second protrusions (221) configured to extend toward the first node (21b). The first protrusions (21b) and second protrusions (22b) are alternately arranged, and adjacent first protrusions (21b) and second protrusions (22b) have opposing portions (fourth configuration).

[0056] In the semiconductor device (100, 100A, 100B, 100C) having any of the first to fourth configurations, the first node (21, 21a, 21b, 21c) is configured to be connected to a ground potential (BND) (fifth configuration).

[0057] In the semiconductor device (100, 100A, 100B, 100C) having any of the first to fifth configurations, the second node (22, 22b, 22c) is configured to be connected to a power supply potential (Ea) (sixth configuration).

[0058] In the semiconductor device (100B) having any one of the first to sixth configurations, the second node (24) is configured to be connected to the output potential (Eao) (seventh configuration).

[0059] The power supply device (100, 100A, 100B, 100C) has a semiconductor device (100, 100A, 100B, 100C) having any one of the first to seventh configurations (eighth configuration).

[0060] This is a configuration (ninth configuration) that includes an electric vehicle (200) that includes the power supply device (100, 100A, 100B, 100C) of the eighth configuration.

[0061] 1, 1C Substrate 11 Upper surface 12 Lower surface 2, 2A, 2B, 2C Pattern 20, 20a1, 20a2, 20a3, 20b, 20c Gap 21, 21a, 21b, 21c First node 21c1 First layer portion 21c2 Second layer portion 21r1 First region 21r2 Second region 21r3 Third region 211 First protrusion 22, 22b, 22c Second node 22c1 First layer portion 22c2 Second layer portion 22c3 Third layer portion 221 Second protrusion 23 Third node 24 Fourth node 25 Fifth node 3 Electronic component 100, 100A, 100B, 100C Semiconductor device 101 First layer 102 Second layer 103 Third layer 200 Vehicle 201 First pattern 202 Second pattern 203 Third pattern C, Ca1, Ca2, Ca3, Cc, Cc1, Cc2 Capacitors

Claims

1. A semiconductor device having a pattern formed thereon, the pattern having: a first node formed on the outer periphery in a planar view and configured to be connected to a first potential; and a second node arranged insulated from the first node and configured to be applied with a second potential different from the first potential, the first node and the second node being configured to face each other at least partially.

2. The semiconductor device according to claim 1, wherein the second node is configured to be positioned outward from the first node in a plan view.

3. A semiconductor device according to claim 1 or 2, wherein the pattern is formed by stacking a plurality of layers, and the first node and the second node are formed in different layers and have portions that face each other in the stacking direction.

4. A semiconductor device as described in any one of claims 1 to 3, wherein the first node has a plurality of first protrusions configured to extend toward the second node, the second node has a plurality of second protrusions configured to extend toward the first node, and the first protrusions and the second protrusions are arranged alternately and have portions where adjacent first protrusions and second protrusions face each other.

5. The semiconductor device according to claim 1, wherein the first node is configured to be connected to a ground potential.

6. A semiconductor device according to claim 1, wherein the second node is configured to be connected to a power supply potential.

7. The semiconductor device according to claim 1, wherein the second node is configured to be connected to an output potential.

8. A power supply device comprising the semiconductor device according to any one of claims 1 to 7.

9. A vehicle having the power supply device according to claim 8.

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