Semiconductor device

Abstract

A base layer (12) is an ion implantation layer. A second base layer (12b) has a peak position (P2), in which the impurity concentration becomes maximum, between an emitter region (17) and a barrier region (16) and at a depth that is different from those of the boundary with the emitter region (17) and the boundary with the barrier region (16). A stabilization layer (19) of a first conductivity type is formed together with a contact region (18) at a surface layer part of the second base layer (12b) in an FWD region (2). A first electrode (22) is electrically connected to the contact region (18) and the stabilization layer (19) in the FWD region (2).

Description

Semiconductor Devices CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based on Japanese Patent Application No. 2023-121047, filed on July 25, 2023, the contents of which are incorporated herein by reference.

[0002] The present disclosure relates to a semiconductor device in which an insulated gate bipolar transistor (hereinafter referred to as an IGBT) element having an insulated gate structure and a free wheel diode (hereinafter referred to as an FWD) element are formed on a common semiconductor substrate.

[0003] Semiconductor devices including an IGBT element have been proposed (see, for example, Patent Document 1). Specifically, in this semiconductor device, a P-type base layer is disposed on an N-type drift layer, and an N-type emitter region is formed in a surface layer of the base layer. In this semiconductor device, an N-type barrier region is disposed within the base layer, dividing the base layer in the thickness direction, to prevent holes (i.e., carriers) from flowing from the drift layer to the base layer when the IGBT region is in an on-state. In this semiconductor device, the base layer is formed as an ion-implanted layer into which P-type impurities are ion-implanted. Specifically, the base layer is configured as follows: the portion of the base layer facing the drift layer is defined as a first base layer, and the portion of the base layer opposite the first base layer across the barrier region is defined as a second base layer. That is, the first base layer is formed so that a first peak position, where the P-type impurity concentration is maximum, is located between the barrier region and the drift layer. The second base layer is formed so that a second peak position, where the P-type impurity concentration is maximum, is located between the emitter region and the barrier region. The first peak position is adjusted to a position different from the boundary with the barrier region or the drift layer, for example, to a position approximately in the center between the barrier region and the drift layer, and the second peak position is adjusted to a position different from the boundary with the emitter region or the barrier region, for example, to a position approximately in the center between the emitter region and the barrier region.

[0004] JP 2010-103326 A

[0005] The present inventors are currently investigating a semiconductor device with a so-called RC (reverse conducting)-IGBT structure in which an IGBT element and an FWD element are formed on a common semiconductor substrate. The inventors are also considering a configuration in which the base layer of the FWD element has the same structure as that of the IGBT element in order to simplify the manufacturing process. In this semiconductor device, the base layer, emitter region, and the like are formed on one side of the semiconductor substrate.

[0006] In this case, when the second peak position of the second base layer is adjusted as described above, the base layer is formed of an ion-implanted layer, and therefore the impurity concentration in the portion of the second base layer that forms one surface of the semiconductor substrate is gradually reduced from the second peak position, and the impurity concentration is likely to vary, which may result in variations in the forward voltage of the FWD element.

[0007] An object of the present disclosure is to provide a semiconductor device capable of suppressing variations in forward voltage.

[0008] According to one aspect of the present disclosure, a semiconductor device has an IGBT region and an FWD region, and includes: a drift layer of a first conductivity type; a base layer of a second conductivity type formed on the drift layer; a collector layer of the second conductivity type formed on a side of the drift layer opposite to the base layer side in the IGBT region; and a cathode layer of the first conductivity type formed on a side of the drift layer opposite to the base layer side in the FWD region, the semiconductor substrate having a surface facing the base layer as one side and a surface facing the collector layer and the cathode layer as the other side; a barrier region of the first conductivity type formed in the base layer and dividing the base layer into a first base layer on the drift layer side and a second base layer on the one side of the semiconductor substrate; a gate insulating film formed on a wall surface of a trench that penetrates the base layer and barrier region of the IGBT region to reach the drift layer; and a gate electrode formed on the gate insulating film. the second base layer has a peak position where the impurity concentration is maximum at a depth different from the boundary with the emitter region and the boundary with the barrier region, and a stabilization layer of the first conductivity type is formed in the surface layer portion of the second base layer in the BT region and in contact with the trench; a contact region of a second conductivity type formed in the surface layer portion of the base layer in the FWD region and having a higher impurity concentration than the base layer; a first electrode disposed on one surface side of the semiconductor substrate and electrically connected to the emitter region and the contact region; and a second electrode disposed on the other surface side of the semiconductor substrate and electrically connected to the collector layer and the cathode layer, wherein the base layer is an ion-implanted layer, and the second base layer is between the emitter region and the barrier region and has a peak position where the impurity concentration is maximum at a depth different from the boundary with the emitter region and the boundary with the barrier region, and a stabilization layer of the first conductivity type is formed in the surface layer portion of the second base layer in the FWD region together with the contact region, and the first electrode is electrically connected to the contact region and the stabilization layer in the FWD region.

[0009] According to this, in the FWD region, one surface of the semiconductor substrate connected to the first electrode includes a stabilization layer of the first conductivity type, and the first electrode is electrically connected to the contact region and the stabilization layer. Therefore, compared to when the one surface of the semiconductor substrate in the FWD region is configured only by the contact region and the second base layer, the proportion of the second base layer, which is prone to variations in impurity concentration, on the one surface of the semiconductor substrate can be reduced, and variations in the forward voltage of the FWD element can be suppressed.

[0010] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and the specific components described in the embodiments described below.

[0011] 1 is a cross-sectional view of a semiconductor device in a first embodiment. FIG. 2 is a plan view of the semiconductor device shown in FIG. 1. FIG. 3 is a perspective cross-sectional view of an FWD element. FIG. 4 is a diagram showing the relationship between the depth of a semiconductor substrate and the impurity concentration of P-type impurities. FIG. 5 is a diagram showing the relationship between the forward voltage and forward current in an FWD element, and the surface concentration of a stabilization layer. FIG. 6 is a plan view of a semiconductor device in a second embodiment. FIG. 7 is a diagram showing the relationship between the collector-emitter voltage and collector current in an IGBT element, and the surface concentration of a stabilization layer. FIG. 8 is a diagram showing the relationship between the gate-emitter voltage and collector current in an IGBT element, and the peak position of the stabilization layer.

[0012] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. In the following embodiments, identical or equivalent parts will be denoted by the same reference numerals.

[0013] 1 to 4, a semiconductor device according to a first embodiment will be described. The semiconductor device according to the present embodiment is suitable for use as a power switching element used in a power supply circuit such as an inverter or a DC / DC converter.

[0014] The semiconductor device is configured by forming an IGBT region 1 that functions as an IGBT element, and an FWD region 2 that is adjacent to the IGBT region 1 and functions as an FWD element. That is, the semiconductor device of this embodiment is an RC-IGBT in which the IGBT region 1 and the FWD region 2 are formed in a common semiconductor substrate 10, which will be described later. Note that, as will be described more specifically later, in this embodiment, the portion on the collector layer 24 located on the other surface 10b of the semiconductor substrate 10 is the IGBT region 1, and the portion on the cathode layer 25 located on the other surface 10b of the semiconductor substrate 10 is the FWD region 2.

[0015] The semiconductor device is －The semiconductor substrate 10 has a P-type drift layer 11. A P-type base layer 12 is formed on the drift layer 11. Hereinafter, the surface of the semiconductor substrate 10 facing the base layer 12 will be referred to as one surface 10a, and the surface of the semiconductor substrate 10 opposite to the one surface 10a will be referred to as the other surface 10b. The semiconductor substrate 10 is formed of, for example, a silicon substrate.

[0016] A plurality of trenches 13 are formed in the semiconductor substrate 10 so as to penetrate the base layer 12 from the one surface 10a side to reach the drift layer 11. As a result, the base layer 12 is separated into a plurality of layers by the trenches 13. In this embodiment, the plurality of trenches 13 are formed in each of the IGBT region 1 and the FWD region 2. In this embodiment, the plurality of trenches 13 are formed in a stripe shape with their longitudinal direction extending in a direction intersecting the arrangement direction of the IGBT region 1 and the FWD region 2 (i.e., the depth direction in the paper in FIG. 1 ). Hereinafter, the longitudinal direction of the trenches 13 will be simply referred to as the longitudinal direction, and in FIG. 2 , the vertical direction in the paper is the longitudinal direction. The distance between adjacent trenches 13 (i.e., the pitch distance) is, for example, approximately 2 μm.

[0017] Each trench 13 is filled with a gate insulating film 14 formed to cover the wall surface of each trench 13, and a gate electrode 15 made of polysilicon or the like formed on this gate insulating film 14. This forms a trench gate structure.

[0018] The gate electrode 15 disposed in the trench 13 formed in the IGBT region 1 is connected to a drive circuit (not shown) via a gate wiring (not shown). A predetermined pulse-like gate voltage is applied to the gate electrode 15. The gate electrode 15 disposed in the trench 13 formed in the FWD region 2 is electrically connected to an upper electrode 22 (described later) and is maintained at a predetermined potential.

[0019] An N-type barrier region 16 having a higher impurity concentration than the drift layer 11 is formed in the base layer 12 so as to divide the base layer 12 in the depth direction of the semiconductor substrate 10. Hereinafter, the portion of the base layer 12 on the drift layer 11 side will also be referred to as a first base layer 12a, and the portion of the base layer 12 on the one surface 10a side of the semiconductor substrate 10 will also be referred to as a second base layer 12b. The base layer 12 in the IGBT region 1 and the base layer 12 in the FWD region 2 have the same configuration.

[0020] The surface layer of the second base layer 12b is made of N, which has a higher impurity concentration than the drift layer 11 in the IGBT region 1. ＋ The P type emitter region 17 and the base layer 12 have a higher impurity concentration. ＋ In the present embodiment, the emitter region 17 and the contact region 18 are formed such that a portion of the surface layer of the second base layer 12b remains. That is, the emitter region 17 and the contact region 18 are formed such that one surface 10a of the semiconductor substrate 10 in the IGBT region 1 includes the second base layer 12b, the emitter region 17, and the contact region 18. In the present embodiment, the emitter region 17 and the contact region 18 are formed in the IGBT region 1 between adjacent trenches 13 so that the contact region 18, the emitter region 17, the contact region 18, and the second base layer 12b are repeatedly arranged in this order along the longitudinal direction.

[0021] In addition, the surface layer of the base layer 12 is made of P, which has a higher impurity concentration than the base layer 12 in the FWD region 2. ＋In the FWD region 2, an N-type contact region 18 is formed. The contact region 18 in the FWD region 2 has the same configuration as the contact region 18 in the IGBT region 1. Furthermore, an N-type stabilization layer 19 is formed in the surface layer portion of the base layer 12 in the FWD region 2. In this embodiment, the one surface 10a of the semiconductor substrate 10 in the FWD region 2 is composed of the contact region 18 and the stabilization layer 19. That is, in the FWD region 2 of this embodiment, the stabilization layer 19 is formed in the entire region of the one surface 10a of the semiconductor substrate 10, except for the region where the contact region 18 is formed.

[0022] In this embodiment, the length of the contact region 18 along the longitudinal direction in the FWD region 2 is shorter than the length of the contact region 18 along the longitudinal direction in the IGBT region 1. However, the length of the contact region 18 along the longitudinal direction in the FWD region 2 and the length of the contact region 18 along the longitudinal direction in the IGBT region 1 can be changed as appropriate. For example, in the FWD region 2, the longer the length of the contact region 18 along the longitudinal direction, the smaller the forward voltage Vf when the FWD element operates as a diode.

[0023] In this embodiment, the first base layer 12a and the second base layer 12b are ion-implanted layers formed by ion-implanting P-type impurities into the semiconductor substrate 10 and diffusing the P-type impurities. The second base layer 12b is formed so that a second peak position P2, where the impurity concentration is maximum, is located between the emitter region 17 and the barrier region 16, as shown in Fig. 4. The first base layer 12a is formed so that a first peak position P1, where the impurity concentration is maximum, is located between the barrier region 16 and the drift layer 11.

[0024] 4 shows the relationship between the P-type impurity concentration along line IV-IV in FIG. 1 and the depth from the surface 10a of the semiconductor substrate 10. The first peak position P1 is adjusted to a position different from the boundary between the first base layer 12a and the barrier region 16 or the drift layer 11, for example, to a position approximately centered between the barrier region 16 and the drift layer 11. The second peak position P2 is adjusted to a position different from the boundary between the second base layer 12b and the emitter region 17 or the barrier region 16, for example, to a position approximately centered between the emitter region 17 and the barrier region 16. By forming the first base layer 12a and the second base layer 12b in this manner, even if the thickness (i.e., position) of the emitter region 17 or the thickness (i.e., position) of the barrier region 16 changes slightly due to manufacturing errors, etc., the maximum values ​​of the impurity concentrations of the first base layer 12a and the second base layer 12b will be at the respective peak positions P1 and P2. Therefore, fluctuations in the threshold voltage Vth can be suppressed. Although not shown, the emitter region 17, the barrier region 16, and the drift layer 11 are made to be N-type as a whole by making the corresponding portions have an N-type impurity concentration higher than the P-type impurity concentration.

[0025] An interlayer insulating film 21 made of BPSG (abbreviation of borophosphosilicate glass) or the like is formed on one surface 10a of the semiconductor substrate 10. In the interlayer insulating film 21, contact holes 21a are formed to expose the emitter region 17, the contact region 18, and the second base layer 12b in the IGBT region 1. In the interlayer insulating film 21, contact holes 21b are formed to expose the contact region 18 and the stabilization layer 19 in the FWD region 2.

[0026] An upper electrode 22 is formed on the interlayer insulating film 21 in the IGBT region 1, electrically connected to the emitter region 17, the contact region 18, and the second base layer 12b through a contact hole 21a formed in the interlayer insulating film 21. An upper electrode 22 is formed on the interlayer insulating film 21 in the FWD region 2, electrically connected to the contact region 18 and the stabilization layer 19 through a contact hole 21b formed in the interlayer insulating film 21. In other words, the upper electrode 22 is formed on the interlayer insulating film 21, functioning as an emitter electrode in the IGBT region 1 and as an anode electrode in the FWD region 2.

[0027] In this embodiment, the upper electrode 22 forms an ohmic junction with the emitter region 17 and the contact region 18, and a Schottky junction with the second base layer 12b.

[0028] In this embodiment, a contact hole 21c that exposes the gate electrode 15 is formed in the interlayer insulating film 21 in the FWD region 2. The upper electrode 22 is also connected to the gate electrode 15 through this contact hole 21c. This allows the gate electrode 15 formed in the FWD region 2 to be maintained at the same potential as the upper electrode 22. In this embodiment, the upper electrode 22 corresponds to a first electrode.

[0029] An N-type field stop (hereinafter also simply referred to as an FS layer) 23 having a higher impurity concentration than the drift layer 11 is formed on the side of the drift layer 11 opposite to the base layer 12 side (i.e., on the side of the other surface 10b of the semiconductor substrate 10). This FS layer 23 is not necessarily required, but is provided to improve the breakdown voltage and steady-state loss performance by preventing the depletion layer from expanding, and to control the amount of holes injected from the other surface 10b side of the semiconductor substrate 10.

[0030] In the IGBT region 1, the P ＋ In the FWD region 2, a collector layer 24 of the N type is formed on the side opposite to the drift layer 11 with the FS layer 23 interposed therebetween. ＋A cathode layer 25 of the same type is formed on the other surface 10b of the semiconductor substrate 10. In other words, the IGBT region 1 and the FWD region 2 are separated depending on whether the layer formed on the other surface 10b of the semiconductor substrate 10 is the collector layer 24 or the cathode layer 25. The region on the collector layer 24 is the IGBT region 1, and the region on the cathode layer 25 is the FWD region 2.

[0031] A lower electrode 26 electrically connected to the collector layer 24 and the cathode layer 25 is formed on the opposite side of the drift layer 11 (i.e., the other surface 10b of the semiconductor substrate 10) across the collector layer 24 and the cathode layer 25. That is, the lower electrode 26 functions as a collector electrode in the IGBT region 1 and functions as a cathode electrode in the FWD region 2. In this embodiment, the lower electrode 26 is in ohmic contact with the collector layer 24 and the cathode layer 25. In this embodiment, the lower electrode 26 corresponds to a second electrode.

[0032] The semiconductor device of this embodiment is configured as described above, and in the IGBT region 1, an IGBT element is configured, with the base layer 12 and the contact region 18 as the base, the emitter region 17 as the emitter, and the collector layer 24 as the collector. In the FWD region 2, a PN-junction FWD element is configured, with the base layer 12 and the contact region 18 as the anode, and the drift layer 11, the FS layer 23, and the cathode layer 25 as the cathode.

[0033] The above is the configuration of the semiconductor device in this embodiment. ＋ Type, N － The type corresponds to the first conductivity type, and P type, P ＋ In the present embodiment, the semiconductor substrate 10 is configured as described above, and includes the collector layer 24, the cathode layer 25, the drift layer 11, the base layer 12, the barrier region 16, the emitter region 17, the contact region 18, the stabilization layer 19, and the like.

[0034] Next, the operation of the semiconductor device will be explained, and the detailed configuration of the semiconductor device will be explained.

[0035] In the semiconductor device described above, when a voltage higher than that of the upper electrode 22 is applied to the lower electrode 26, the PN junction formed between the base layer 12 and the drift layer 11 becomes reverse conductive, forming a depletion layer. When a low-level gate voltage (e.g., 0 V) ​​that is lower than the threshold voltage Vth of the insulated gate structure is applied to the gate electrode 15, no collector current flows between the upper electrode 22 and the lower electrode 26.

[0036] To turn the IGBT element on, a high-level gate voltage equal to or higher than the threshold voltage Vth of the insulated gate structure is applied to the gate electrode 15 of the IGBT region 1 while a voltage higher than that of the upper electrode 22 is applied to the lower electrode 26. As a result, an inversion layer is formed in the IGBT region 1 in the portion of the base layer 12 that contacts the trench 13. Then, in the IGBT element, electrons are supplied to the drift layer 11 from the emitter region 17 via the inversion layer, and holes are supplied to the drift layer 11 from the collector layer 24. As a result, the resistance value of the drift layer 11 in the IGBT element decreases due to conductivity modulation, and a collector current flows between the upper electrode 22 and the lower electrode 26.

[0037] At this time, in this embodiment, the barrier region 16 makes it difficult for holes supplied to the drift layer 11 to escape to the base layer 12 side, thereby reducing the on-voltage.

[0038] Furthermore, when the IGBT element is turned off and the FWD element is turned on (i.e., when the FWD element operates as a diode), the voltages applied to the upper electrode 22 and the lower electrode 26 are switched, and a forward bias is applied to the upper electrode 22 such that a voltage higher than that of the lower electrode 26 is applied. As a result, holes are supplied to the base layer 12 and electrons are supplied to the cathode layer 25, causing the FWD element to operate as a diode.

[0039] In this embodiment, in the FWD region 2, one surface 10a of the semiconductor substrate 10 is formed by the P-type contact region 18 and the N-type stabilization layer 19. That is, in the FWD region 2, the second base layer 12b, which is prone to variations in impurity concentration, is not exposed on the one surface 10a of the semiconductor substrate 10, and the upper electrode 22 is not in contact with the second base layer 12b. For this reason, the forward voltage Vf of the FWD element depends on the contact region 18. Therefore, variations in the forward voltage Vf of the FWD element can be suppressed.

[0040] Furthermore, in this embodiment, in the IGBT region 1, the second base layer 12b is exposed from the surface 10a of the semiconductor substrate 10, and the second base layer 12b is Schottky junctioned with the upper electrode 22. Therefore, compared to, for example, a semiconductor device in which this second base layer 12b is used as the contact region 18, fewer holes can be injected into the second base layer 12b of the IGBT region 1 when the FWD element is in the on state. Therefore, when the voltage between the upper electrode 22 and the lower electrode 26 is switched to a reverse bias, the injection of holes is suppressed, thereby reducing the recovery current and shortening the recovery time. As a result, switching loss can be reduced.

[0041] The inventors further studied the stabilization layer 19 and obtained the following results. As shown in FIG. 5 , it was confirmed that the forward voltage Vf of the FWD element increases as the surface concentration of the stabilization layer 19 increases. For this reason, it is preferable to adjust the surface concentration of the stabilization layer 19 appropriately depending on the application. Note that the surface concentration of the stabilization layer 19 here refers to the N-type impurity concentration of the stabilization layer 19 on the one surface 10 a of the semiconductor substrate 10.

[0042] According to the present embodiment described above, in the FWD region 2, the one surface 10a of the semiconductor substrate 10 connected to the upper electrode 22 includes the N-type stabilization layer 19. The upper electrode 22 is electrically connected to the contact region 18 and the stabilization layer 19. Therefore, compared to when the one surface 10a of the semiconductor substrate 10 in the FWD region 2 is configured by the contact region 18 and the second base layer 12b, the proportion of the second base layer 12b, which is prone to variations in impurity concentration, can be reduced on the one surface 10a of the semiconductor substrate 10, and variations in the forward voltage Vf of the FWD element can be suppressed.

[0043] (1) In this embodiment, the FWD region 2 is formed on one surface 10a of the semiconductor substrate 10 by the contact region 18 and the stabilization layer 19. This prevents the upper electrode 22 from coming into direct contact with the second base layer 12b, and further reduces variations in the forward voltage Vf of the FWD element.

[0044] Second Embodiment A second embodiment will be described. In this embodiment, in contrast to the first embodiment, a stabilization layer 19 is also formed in the IGBT region 1. As the rest of the configuration is the same as the first embodiment, a description thereof will be omitted here.

[0045] 6 , in the semiconductor device of this embodiment, a stabilization layer 19 is formed in the surface layer portion of the second base layer 12b, along with the emitter region 17 and the contact region 18. The surface 10a of the semiconductor substrate 10 in the IGBT region 1 is formed with the emitter region 17, the contact region 18, and the stabilization layer 19. Specifically, in the IGBT region 1, the contact region 18, the emitter region 17, the contact region 18, and the stabilization layer 19 are repeatedly formed in this order along the longitudinal direction between adjacent trenches 13. That is, in the IGBT region 1 of this embodiment, the stabilization layer 19 is formed in the surface 10a of the semiconductor substrate 10 in the portion where the second base layer 12b in the first embodiment was exposed. The stabilization layer 19 has a lower impurity concentration than the contact region 18.

[0046] The above is the configuration of the semiconductor device according to this embodiment. The stabilization layer 19 in this semiconductor device is formed as follows. Specifically, the stabilization layer 19 is formed by ion implanting N-type impurities after forming the emitter region 17 and the contact region 18 in the surface layer portion of the second base layer 12b. In this case, the impurity concentration of the stabilization layer 19 is lower than that of the contact region 18, so that even if the N-type impurities are ion implanted without a mask, the contact region 18 will not be converted to N-type. Therefore, in this embodiment, by forming the stabilization layer 19 also in the IGBT region 1, the stabilization layer 19 can be formed by ion implanting N-type impurities without a mask, thereby simplifying the manufacturing process.

[0047] Here, if the stabilization layer 19 is formed in the IGBT region 1, there is a concern that the latch-up resistance will decrease due to the increase in the N-type layer, since the stabilization layer 19 is N-type. However, according to the study by the present inventors, the results shown in FIG. 7 were obtained as a relationship between the collector-emitter voltage Vce and the collector current Ic and the surface concentration of the stabilization layer 19. Note that FIG. 7 shows the relationship when the surface concentration of the emitter region 17 is set to 2.0×10 ２０ / cm ３ This is the result when

[0048] 7, it has been confirmed that the latch-up current hardly changes when the surface concentration of the stabilization layer 19 is lower than the surface concentration of the emitter region 17. For this reason, it is preferable that the stabilization layer 19 has a lower impurity concentration than the emitter region 17 in order to prevent a decrease in the latch-up resistance.

[0049] Furthermore, when a stabilization layer 19 is formed in the IGBT region 1, the stabilization layer 19 may affect the threshold voltage Vth (i.e., the gate-emitter voltage Vge) of the IGBT element. According to the inventors' studies, the results shown in FIG. 8 were obtained, which show the relationship between the gate-emitter voltage Vge and the collector current Ic and the peak position of the stabilization layer 19. Note that FIG. 8 indicates the peak position of the stabilization layer 19 as the depth from the surface 10a of the semiconductor substrate 10 to the peak position where the impurity concentration of the stabilization layer 19 is maximum. Also, FIG. 8 shows the depth from the surface 10a of the semiconductor substrate 10 to the second peak position P2 of the second base layer 12b as 0.86 μm. The peak position of the stabilization layer 19 being 0 in FIG. 8 means that the stabilization layer 19 is not formed.

[0050] 8 , it has been confirmed that the threshold voltage Vth remains almost unchanged if the peak position where the impurity concentration of the stabilization layer 19 is maximum is 0.5 μm or less. That is, it has been confirmed that the threshold voltage Vth remains unchanged if the depth from the surface 10 a of the semiconductor substrate 10 to the peak position where the impurity concentration of the stabilization layer 19 is maximum is 58% or less of the depth from the surface 10 a of the semiconductor substrate 10 to the second peak position P2 of the second base layer 12 b. Therefore, it is preferable that the depth of the stabilization layer 19 to the peak position where the impurity concentration is maximum is 58% or less of the depth from the surface 10 a of the semiconductor substrate 10 to the second peak position P2 of the second base layer 12 b.

[0051] According to the present embodiment described above, the FWD region 2 is configured such that one surface 10 a of the semiconductor substrate 10 connected to the upper electrode 22 includes the N-type stabilization layer 19. Therefore, the same effects as those of the first embodiment can be obtained.

[0052] (1) In this embodiment, the stabilization layer 19 is also formed in the IGBT region 1, and the stabilization layer 19 has a lower impurity concentration than the contact region 18. Therefore, the stabilization layer 19 can be formed by ion implantation of N-type impurities without using a mask, which simplifies the manufacturing process.

[0053] (2) In this embodiment, the surface concentration of the stabilization layer 19 is set lower than the surface concentration of the emitter region 17, thereby preventing a decrease in latch-up resistance.

[0054] (3) In this embodiment, the stabilization layer 19 is formed so that the peak position of the stabilization layer 19 is 58% or less of the second peak position P2 of the second base layer 12b, thereby suppressing fluctuations in the threshold voltage Vth.

[0055] (Other Embodiments) While the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also encompasses various modifications and modifications within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure.

[0056] For example, in each of the above embodiments, the semiconductor device in which the first conductivity type is N type and the second conductivity type is P type has been described, but the semiconductor device in which the first conductivity type is P type and the second conductivity type is N type may also be used. Also, in each of the above embodiments, the trench gate structure does not have to be formed in the FWD region 2.

[0057] Furthermore, in the above-described embodiments, an example has been described in which the surface 10 a of the semiconductor substrate 10 in the FWD region 2 is formed of the contact region 18 and the stabilization layer 19. However, the stabilization layer 19 may be formed in a part of the surface layer of the second base layer 12 b, so that the second base layer 12 b is exposed from the surface 10 a of the semiconductor substrate 10. Even in such a semiconductor device, the proportion of the second base layer 12 b, which is prone to variations in impurity concentration, can be reduced on the surface 10 a of the semiconductor substrate 10, compared to when the surface 10 a of the semiconductor substrate 10 in the FWD region 2 is formed of the contact region 18 and the second base layer 12 b. Therefore, the same effects as those of the first embodiment can be obtained.

[0058] Similarly, in the second embodiment, an example has been described in which, in the IGBT region 1, the surface 10a of the semiconductor substrate 10 is formed by the emitter region 17, the contact region 18, and the stabilization layer 19. However, in the IGBT region 1, the stabilization layer 19 may be formed in a part of the surface layer portion of the second base layer 12b, so that the second base layer 12b is exposed from the surface 10a of the semiconductor substrate 10.

[0059] In the second embodiment, the surface concentration of the stabilization layer 19 may be higher than the surface concentration of the emitter region 17. The stabilization layer 19 may be formed at a depth at which the peak position of the stabilization layer 19 is greater than 58% of the second peak position P2 of the second base layer 12b. This semiconductor device also reduces the proportion of the second base layer 12b, which is prone to variations in impurity concentration, on the surface 10a of the semiconductor substrate 10, compared to when the surface 10a of the semiconductor substrate 10 in the FWD region 2 is composed of the contact region 18 and the second base layer 12b. Therefore, the same effects as those of the first embodiment can be obtained.

[0060] [Disclosure of the Present Invention] The above-described disclosure can be understood from the following viewpoints, for example: [First Aspect] A semiconductor device in which an IGBT region (1) having an IGBT element and an FWD region (2) having an FWD element are formed on a common semiconductor substrate (10), the semiconductor substrate having the IGBT region and the FWD region, and including: a drift layer (11) of a first conductivity type; a base layer (12) of a second conductivity type formed on the drift layer; a collector layer (24) of the second conductivity type formed on a side of the drift layer opposite to the base layer side in the IGBT region; and a cathode layer (25) of the first conductivity type formed on a side of the drift layer opposite to the base layer side in the FWD region, the semiconductor substrate having a surface on the base layer side as one surface (10a) and a surface on the collector layer and cathode layer side as another surface (10b); a first conductivity type barrier region (16) formed in the base layer and dividing the base layer into a first base layer (12a) on the drift layer side and a second base layer (12b) on one surface side of the semiconductor substrate; a gate insulating film (14) formed on a wall surface of a trench (13) that penetrates the base layer and the barrier region in the IGBT region to reach the drift layer, and a gate electrode (15) formed on the gate insulating film; an emitter region (17) of the first conductivity type formed in a surface layer portion of the second base layer in the IGBT region and in contact with the trench; a second conductivity type contact region (18) formed in a surface layer portion of the base layer in the FWD region and having a higher impurity concentration than the base layer; a first electrode (22) arranged on one surface side of the semiconductor substrate and electrically connected to the emitter region and the contact region; and a second electrode (26) arranged on the other surface side of the semiconductor substrate and electrically connected to the collector layer and the cathode layer, the base layer is an ion-implanted layer, the second base layer has a peak position (P2) where the impurity concentration is maximum, located between the emitter region and the barrier region, at a depth different from the boundary with the emitter region and the boundary with the barrier region, and a first conductivity type stabilization layer (19) is formed in a surface layer portion of the second base layer in the FWD region together with the contact region,The first electrode is electrically connected to the contact region and the stabilization layer in the FWD region.

[0061] Second Aspect The semiconductor device according to the first aspect, wherein the stabilization layer is formed in the FWD region over the entire region of a portion of one surface of the semiconductor substrate that is different from the contact region.

[0062] [Third Aspect] The semiconductor device according to the first or second aspect, wherein the stabilization layer is also formed on a surface layer portion of the second base layer in the IGBT region.

[0063] [Fourth Aspect] The semiconductor device according to the first or second aspect, wherein the contact region is also formed in a surface layer portion of the second base layer in the IGBT region, and the stabilization layer is formed in the FWD region over the entire region of a portion of one surface of the semiconductor substrate that is different from the contact region, and further formed in the IGBT region over the entire region of a portion of one surface of the semiconductor substrate that is different from the emitter region and the contact region, and has an impurity concentration lower than that of the contact region.

[0064] [Fifth Aspect] A semiconductor device according to the third or fourth aspect, wherein the stabilization layer in the IGBT region has a depth from one surface of the semiconductor substrate to a peak position where the impurity concentration in the stabilization layer is maximum that is 58% or less of the depth from one surface of the semiconductor substrate to a peak position where the impurity concentration in the second base layer is maximum.

Claims

1. A semiconductor device in which an IGBT region (1) having an IGBT element and an FWD region (2) having an FWD element are formed on a common semiconductor substrate (10), comprising: the semiconductor substrate having the IGBT region and the FWD region, and including a drift layer (11) of a first conductivity type, a base layer (12) of a second conductivity type formed on the drift layer, a collector layer (24) of a second conductivity type formed on the drift layer on the side opposite to the base layer side in the IGBT region, and a cathode layer (25) of a first conductivity type formed on the drift layer on the side opposite to the base layer side in the FWD region, the semiconductor substrate having a surface on the base layer side as one surface (10a) and a surface on the collector layer and cathode layer side as the other surface (10b); a first conductivity type barrier region (16) formed in the base layer and dividing the base layer into a first base layer (12a) on the drift layer side and a second base layer (12b) on one surface side of the semiconductor substrate; a gate insulating film (14) formed on a wall surface of a trench (13) that penetrates the base layer and the barrier region in the IGBT region to reach the drift layer, and a gate electrode (15) formed on the gate insulating film; an emitter region (17) of the first conductivity type formed in a surface layer portion of the second base layer in the IGBT region and in contact with the trench; a contact region (18) of a second conductivity type formed in a surface layer portion of the base layer in the FWD region and having a higher impurity concentration than the base layer; a first electrode (22) disposed on one surface side of the semiconductor substrate and electrically connected to the emitter region and the contact region; and a second electrode (26) disposed on the other surface side of the semiconductor substrate and electrically connected to the collector layer and the cathode layer, the base layer is an ion-implanted layer, the second base layer is between the emitter region and the barrier region and has a peak position (P2) where the impurity concentration is maximum at a depth different from the boundary with the emitter region and the boundary with the barrier region, a stabilization layer (19) of a first conductivity type is formed together with the contact region in a surface layer portion of the second base layer in the FWD region, and the first electrode is electrically connected to the contact region and the stabilization layer in the FWD region.

2. The semiconductor device according to claim 1, wherein said stabilization layer is formed in said FWD region over the entire area of ​​one surface of said semiconductor substrate that is different from said contact region.

3. The semiconductor device according to claim 1, wherein the stabilization layer is also formed on a surface layer portion of the second base layer in the IGBT region.

4. The semiconductor device described in claim 1, wherein the contact region is also formed in a surface portion of the second base layer in the IGBT region, and the stabilization layer is formed in the FWD region over the entire area of ​​a portion of one surface of the semiconductor substrate different from the contact region, and further formed in the IGBT region over the entire area of ​​a portion of one surface of the semiconductor substrate different from the emitter region and the contact region, and has a lower impurity concentration than the contact region.

5. A semiconductor device as described in claim 3 or 4, wherein the stabilization layer in the IGBT region has a depth from one surface of the semiconductor substrate to a peak position where the impurity concentration in the stabilization layer is at its maximum that is 58% or less of the depth from one surface of the semiconductor substrate to a peak position where the impurity concentration in the second base layer is at its maximum.

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