Multi-channel silicon carbide mosfet device and manufacturing method therefor

Abstract

A multi-channel silicon carbide MOSFET device and a manufacturing method therefor. The silicon carbide MOSFET device comprises first trenches (10), second trenches (11), a first conductive type substrate (2), a first conductive type epitaxial layer (3), a first conductive type source region (5), and a second conductive type well region (4). The first trenches (10) and the second trenches (11) are formed by etching in a direction perpendicular to the xz plane, and the first trenches (10) and the second trenches (11) pass through an active region of the device in the x direction. A gate dielectric layer (6) and a gate electrode (7) are formed in the first trenches (10) and the second trenches (11), and under a forward conduction working condition, the gate electrode (7), the gate dielectric layer (6) and the second conductive type well region (4) form five channels at different positions.

Description

Multi-channel silicon carbide MOSFET device and manufacturing method thereof

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on August 3, 2023, with application number 202310971536.7, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application belongs to the field of semiconductor device technology, and for example relates to a multi-channel silicon carbide MOSFET device and a manufacturing method thereof. Background Art

[0003] Power semiconductors are the core electronic components of power electronics systems. Silicon-based power devices dominate the power semiconductor market. However, due to the physical and chemical properties of silicon, their performance is gradually reaching a bottleneck.

[0004] Due to the advantages of silicon carbide (SiC) materials such as higher thermal conductivity, larger bandgap, higher electron saturation velocity and higher critical breakdown electric field strength, SiC materials have become one of the most important semiconductor materials for making high-power devices that can adapt to extreme environments.

[0005] Among SiC power devices, metal-oxide-semiconductor field-effect transistors (MOSFETs) are widely used due to their advantages such as simple gate drive and fast switching speed. However, planar-gate SiC MOSFETs suffer from low channel density and mobility, which severely limit their conduction capability.

[0006] Compared with planar-gate SiC MOSFETs, trench SiC MOSFET devices have advantages such as higher channel mobility and elimination of parasitic junction field-effect transistor effects, which can achieve higher conduction characteristics. However, the electric field concentration effect at the trench corners makes the gate dielectric prone to breakdown, reducing the reliability of the device.

[0007] Summary of the Invention

[0008] To address the shortcomings of the aforementioned planar and trench SiC MOSFET devices, this application provides a multi-channel silicon carbide MOSFET device and a method for manufacturing the same. While circumventing gate dielectric reliability issues, this application introduces a trench structure into a planar SiC MOSFET device to increase the channel width. By increasing the channel width, the channel resistance is reduced, thereby reducing the device's on-resistance and improving the current density.

[0009] The present application provides a multi-channel silicon carbide MOSFET device, comprising:

[0010] drain electrode;

[0011] a first conductive type substrate located on the drain electrode;

[0012] A first conductive type epitaxial layer is located on the first conductive type substrate;

[0013] A second conductive type well region is located in the first conductive type epitaxial layer;

[0014] A first conductive type source region is located in the second conductive type well region;

[0015] A first trench is located in the second conductive type well region and penetrates the first conductive type epitaxial layer and the first conductive type source region along the length direction of the device, that is, the x-axis direction;

[0016] A second trench is located above the first trench, in the first conductivity type epitaxial layer, in the second conductivity type well region, and in the first conductivity type source region;

[0017] a gate dielectric layer located on the bottom and sidewalls of the first trench, the bottom and sidewalls of the second trench, the first conductive type epitaxial layer, the second conductive type well region, and a portion of the first conductive type source region;

[0018] a gate electrode located in the first trench and wrapped by the gate dielectric layer, located in the second trench and wrapped by the gate dielectric layer, located on the first conductivity type epitaxial layer, on the second conductivity type well region, and on a portion of the first conductivity type source region and separated by the gate dielectric layer;

[0019] an isolation dielectric layer, located on both sides of and above the gate dielectric layer and the gate electrode;

[0020] The source metal is located on both sides and above the isolation dielectric layer.

[0021] The present application also provides a method for preparing a multi-channel silicon carbide MOSFET device, comprising:

[0022] forming a first conductive type epitaxial layer by epitaxial growth on a first conductive type substrate;

[0023] forming a second conductivity type well region in the first conductivity type epitaxial layer, and forming a first conductivity type source region in the second conductivity type well region;

[0024] etching the first conductive type epitaxial layer to form a second trench;

[0025] etching the bottom of the second trench to form a first trench;

[0026] forming a gate dielectric layer on top of the first conductive type epitaxial layer and inside the first trench and the second trench;

[0027] forming a patterned gate electrode material on the gate dielectric layer on top of the first conductive type epitaxial layer and within the gate dielectric layer in the first trench and the second trench to form a gate electrode;

[0028] forming a patterned isolation dielectric layer on the top and both sides of the gate electrode material;

[0029] Depositing source metal through the source electrode window to form a source ohmic contact, and depositing drain metal on the back side to form a drain ohmic contact;

[0030] A source electrode is formed on the surface of the source ohmic contact layer, and a drain electrode is formed on the surface of the drain ohmic contact layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] FIG1 is a schematic structural diagram of a multi-channel silicon carbide MOSFET device according to Example 1;

[0032] FIG2 is an xy plane cross-sectional view of the multi-channel silicon carbide MOSFET device of Example 1;

[0033] 3 is a cross-sectional view of the multi-channel silicon carbide MOSFET device of Example 1 taken along the yz plane where the AA' axis is located;

[0034] FIG4 is a schematic structural diagram of a multi-channel silicon carbide MOSFET device according to Example 2;

[0035] FIG5 is a schematic diagram of a preparation process of a multi-channel silicon carbide MOSFET device according to Example 1;

[0036] FIG6 is a schematic diagram of a preparation process of another multi-channel silicon carbide MOSFET device according to Example 1;

[0037] FIG7 is a schematic diagram of a preparation process of another multi-channel silicon carbide MOSFET device according to Example 1;

[0038] FIG8 is a schematic diagram of a preparation process of another multi-channel silicon carbide MOSFET device according to Example 1;

[0039] FIG9 is a schematic diagram of a preparation process of another multi-channel silicon carbide MOSFET device according to Example 1;

[0040] FIG10 is a schematic diagram of a preparation process of another multi-channel silicon carbide MOSFET device according to Example 1;

[0041] FIG11 is a schematic diagram of a preparation process of another multi-channel silicon carbide MOSFET device according to Example 1;

[0042] FIG12 is a schematic flow chart of a method for preparing a multi-channel silicon carbide MOSFET device according to Example 1.

[0043] Explanation of the accompanying symbols: 1. drain electrode; 2. first conductive type substrate; 3. first conductive type epitaxial layer; 4. second conductive type well region; 5. first conductive type source region; 6. gate dielectric layer; 7. gate electrode; 8. isolation dielectric layer; 9. source metal; 10. first trench; 11. second trench; 12. first conductive type current spreading layer. DETAILED DESCRIPTION

[0044] The present application is described below in conjunction with embodiments. The embodiments are only used to illustrate the present application and do not constitute a limitation on the scope of the claims. Other conceivable alternative means are all within the scope of the claims of the present application.

[0045] In addition, in the description of this application, the terms "central", "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings and are only for the convenience of describing this application and simplifying the description. They do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore should not be understood as limiting the application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only and should not be understood as indicating or implying relative importance.

[0046] Example 1

[0047] A multi-channel silicon carbide MOSFET device, as shown in FIG1 and an xy plane cross-sectional view as shown in FIG2, comprises: a drain electrode 1; a first conductive type substrate 2 located on the drain electrode 1, the first conductive type substrate 2 being a first conductive type SiC substrate; a first conductive type epitaxial layer 3 located on the first conductive type substrate 2, the first conductive type epitaxial layer 3 being a first conductive type SiC epitaxial layer; a second conductive type well region 4 located in the first conductive type epitaxial layer 3; a first conductive type source region 5 located in the second conductive type well region 4; a first trench 10 located in the second conductive type well region 4 and penetrating the first conductive type epitaxial layer 3 and the first conductive type source region 5 along the x-axis direction; a second trench 11 located above the first trench 10, in the first conductive type epitaxial layer 3, in the second conductive type well region 4, and in the first conductive type source region 5, the top of the second trench 11 being flush with the first conductive type epitaxial layer 3, the second conductive type well region 4, and the first conductive type source region 5; a second trench 11 located on the bottom and sidewalls of the first trench 10, the second conductive type well region 4, and the first conductive type source region 5 A gate dielectric layer 6 at the bottom and sidewalls of the trench 11, on the first conductive type epitaxial layer 3, on the second conductive type well region 4 and on a portion of the first conductive type source region 5; a gate electrode 7 located in the first trench 10 and wrapped by the gate dielectric layer 6, located in the second trench 11 and wrapped by the gate dielectric layer 6, located on the first conductive type epitaxial layer 3, on the second conductive type well region 4 and on a portion of the first conductive type source region 5 and separated by the gate dielectric layer 6; that is, the gate electrode 7 is located in the gate dielectric layer 6 in the first trench 10 and the second trench 11, and is located on the gate dielectric layer 6 at the top of the first conductive type epitaxial layer 3, and multiple parts of the gate electrode 7 are connected; an isolation dielectric layer 8 is located on both sides and above the gate dielectric layer 6 and the gate electrode 7; the isolation dielectric layer 8 covers a portion of the first conductive type source region 5; a source metal 9 is located on both sides and above the isolation dielectric layer 8, and the gate electrode 7 and the source metal 9 are separated by the isolation dielectric layer 8. In Figure 1 , the x-axis is the length of the device, the y-axis is the height of the device, and the z-axis is the width of the device. The depth mentioned in this application also refers to the height along the y-axis.

[0048] The depth of the second conductive type well region 4 is greater than the sum of the depths of the first trench 10 and the second trench 11 , and the difference between the sum of the depths is not less than 0.2 μm.

[0049] The semiconductor material used for the first conductive type substrate 2 and the first conductive type epitaxial layer 3 can be 3C-SiC, 4H-SiC or 6H-SiC. The doping concentration of the first conductive type epitaxial layer 3 is 1e15cm -3 ~1e17cm -3 The semiconductor material used in the device can be 3C-SiC, 4H-SiC or 6H-SiC.

[0050] The number of first trenches 10 and second trenches 11 is the same, and there are at least two of them. In this embodiment, the number of first trenches 10 and second trenches 11 is two. The number of first trenches 10 and second trenches 11 depends on the performance of the device. The more first trenches 10 and second trenches 11 there are, the larger the effective width of the channel and the better the device conduction performance; however, the process becomes more complex, and after the number of first trenches 10 and second trenches 11 increases to a certain level, the improvement in the device conduction capability will reach saturation. Therefore, in this application, the spacing between trenches in the z-axis direction is limited. The spacing between adjacent second trenches 11 along the z-axis direction is not less than 0.5μm and not more than 2.5μm; the spacing between adjacent first trenches 10 along the z-axis direction is not less than 0.2μm and not more than 2μm, and the distance between the first trench 10 and the device edge along the z-axis direction is not less than 0.5μm.

[0051] In the xy plane cross-sectional view, the device structure of the present application is a planar MOSFET structure; in the yz plane cross-sectional view, the trench structure of the device is reflected. A multi-channel silicon carbide MOSFET device in this embodiment, a local cross-sectional view of the yz plane where the AA' axis is located is shown in Figure 3, a gate dielectric layer 6 and a gate electrode 7 are provided in the first trench 10 and the second trench 11, and the gate dielectric layer 6 wraps the gate electrode 7. Under forward conduction working conditions, there are five channels in different positions, wherein the first channel (i.e., channel 1 in Figure 3) is located on the top surface of the second conductive type well region 4, the second channel (i.e., channel 2 in Figure 3) is located on the surface of the second conductive type well region 4 near the side wall of the second trench 11, the third channel (i.e., channel 3 in Figure 3) is located on the surface of the second conductive type well region 4 near the upper boundary of the first trench 10, the fourth channel (i.e., channel 4 in Figure 3) is located on the surface of the second conductive type well region 4 near the side wall of the first trench 10, and the fifth channel (i.e., channel 5 in Figure 3) is located on the surface of the second conductive type well region 4 near the bottom of the first trench 10. When the cell size remains constant, the length of the first channel is determined by the width of the second trench 11. The sum of the length of the first channel and 1 / 2 the width of the second trench 11 is 1 / 2 the cell size, where the cell size is the width of the device. Therefore, under a fixed cell size, the length of the first channel is determined by the width of the second trench 11; the length of the second channel is determined by the depth of the second trench 11, and the length of the third channel is determined by the width of the first trench 10, with the length of the third channel being half the difference between the widths of the first and second trenches 10, 11; the length of the fourth channel is determined by the depth of the first trench 10, and the length of the fifth channel is determined by the width of the first trench 10, with the length of the fifth channel being half the width of the first trench 10. The increase in the overall channel width of the device depends on the sum of the lengths of the first, second, third, fourth, and fifth channels. The first, third, and fifth channels are located on the Si plane parallel to the device surface, that is, parallel to the z-axis. The second and fourth channels are located on the A plane or M plane perpendicular to the device surface, and the second and fourth channels are parallel to the y-axis. The channel mobility of the A plane and M plane is generally significantly higher than that of the Si plane. Therefore, under forward conduction operating conditions, the mobility of channel 2 and channel 4 is significantly greater than that of channel 1, channel 3, and channel 5. According to solid-state physics theory, the basic unit of the microstructure of the 4H-SiC epitaxial layer is a hexagonal structure. The upper and lower bases of a regular hexahedron are regular hexagons, and the side surfaces are rectangular. The upper base of the regular hexahedron can be considered to be the Si plane, and the two different side surfaces are the A plane and the M plane.Figure 3 shows five different positions of channels under forward conduction working conditions when there is a first trench 10 and a second trench 11. When there are multiple first trenches 10 and multiple second trenches 11, the above conditions are the same. For example, when there is one first trench 10 and one second trench 11, the sum of the length of the first channel and the width of 1 / 2 of the second trench 11 is 1 / 2 of the cell size; when there are multiple first trenches 10 and multiple second trenches 11, the sum of the total length of all first channels and 1 / 2 of the total width of all second trenches 11 is 1 / 2 of the cell size; the total length of all third channels is half of the difference between the total width of all first trenches 10 and all second trenches 11; the length of all fifth channels is half of the sum of the widths of all first trenches 10.

[0052] The multi-channel silicon carbide MOSFET device of this embodiment, under forward conduction working conditions, with the help of the trench structure, the gate electrode 7, the gate dielectric layer 6 and the second conductive type well region 4 form five channels at different positions. By controlling the depth and width of the first trench 10 and the second trench 11, the lengths of the five channels can be adjusted, thereby controlling the increase in the overall channel width of the device. The trench structure of the present application effectively increases the channel width, greatly reduces the channel resistance of the device, and significantly improves the conduction characteristics of the device. In addition, the design in which most of the trench is completely wrapped in the second conductive type well region 4 effectively reduces the gate-drain capacitance, reduces the switching loss of the device, and thus improves the switching characteristics of the device.

[0053] The method for preparing the multi-channel silicon carbide MOSFET device, as shown in FIG5 to FIG11 , includes the following steps.

[0054] S1. As shown in FIG5 and FIG6 , a first conductive type epitaxial layer 3 is formed on a first conductive type substrate 2 by epitaxial growth. The doping concentration of the first conductive type epitaxial layer 3 is 1e15 cm -3 ~1e17cm -3 ; The first conductive type substrate 2 is a first conductive type SiC substrate; the first conductive type epitaxial layer 3 is a first conductive type SiC epitaxial layer.

[0055] S2. As shown in FIG7 , an ion implantation mask layer is grown on the surface of the first conductive type epitaxial layer 3 prepared in S1 by a chemical vapor deposition process, and then the ion implantation mask layer is patterned by a photolithography process, and then a second conductive type well region 4 is formed in the first conductive type epitaxial layer 3 by an ion implantation process; after removing the mask layer, a first conductive type source region 5 is formed in the second conductive type well region 4 in the same manner, and then the ion implantation mask layer is removed; the bottom of the second conductive type well region 4 is lower than the bottom of the first trench 10, and the second conductive type well region 4 is divided into two non-contacting parts, and is symmetrically arranged at the upper parts of both sides of the first conductive type epitaxial layer 3, and the first conductive type epitaxial layer 3 is between the two parts of the second conductive type well region 4; the first conductive type source region 5 is divided into two non-contacting parts, and is respectively arranged at the upper parts of both sides of the two parts of the second conductive type well region 4; the doping concentration of the second conductive type well region 4 is 5e16cm -3 ~5e17cm -3 .

[0056] S3. As shown in FIG8 , a patterned etch mask layer is formed on the surface of the device prepared in S2 by chemical vapor deposition and photolithography. The patterned etch mask layer is used to perform inductively coupled plasma (ICP) etching on the first conductive type epitaxial layer 3 to form a second trench 11. The etch mask layer is then removed. In this embodiment, the second trench 11 has a depth ranging from 0.5 μm to 2.5 μm and a width ranging from 0.5 μm to 1.5 μm, extending through the entire device. The spacing between adjacent second trenches 11 along the z-axis is not less than 0.5 μm and not greater than 2.5 μm. The top of the second trench 11 is flush with the first conductive type epitaxial layer 3, and the bottom is higher than the first conductive type source region 5. The second trench 11 is etched through the first conductive type epitaxial layer 3, two portions of the second conductive type well region 4, and two portions of the first conductive type source region 5 in the x-direction.

[0057] S4. As shown in FIG9 , a patterned etch mask layer is formed on the surface of the device prepared in S3 and on the sidewalls of the second trench 11 by chemical vapor deposition and photolithography. The patterned etch mask layer is used to perform isotropic dry etching on the bottom of the second trench 11. The etching gas used can be one or more of sulfur hexafluoride SF6, hydrogen bromide HBr, chlorine Cl2, oxygen O2, argon Ar, etc. A first trench 10 communicating with the second trench 11 is formed at the bottom of the second trench 11. The etch mask layer is then removed, and the first trench 10 and the second trench 11 are passivated. The width of the first trench 10 is greater than the width of the second trench 11, and the difference between the two is not less than 0.1 μm. In this embodiment, the first trench 10 has a depth ranging from 0.1 μm to 1.0 μm and a width ranging from 1.5 μm to 2.5 μm, extending through the entire device. The top of the first trench 10 is flush with the bottom of the second trench 11, and the bottom of the first trench 10 is higher than the bottom of the first conductivity type source region 5. The sum of the depths of the first trench 10 and the second trench 11 is less than the depth of the first conductivity type source region 5, and the difference between the sum of ...

[0058] S5. As shown in FIG10 , a gate dielectric layer 6 is formed on the surface of the device prepared in S4 and within the first trench 10 and the second trench 11 by chemical vapor deposition. Specifically, the gate dielectric layer 6 is located at the bottom and sidewalls of the first trench 10, the bottom and sidewalls of the second trench 11, the first conductivity type epitaxial layer 3, the second conductivity type well region 4, and a portion of the first conductivity type source region 5. Polycrystalline silicon is grown on the gate dielectric layer 6 by chemical vapor deposition, followed by polysilicon implantation. A patterned etch mask layer is formed by chemical vapor deposition and photolithography. The patterned etch mask layer is used to pattern the polycrystalline silicon material to form a gate electrode 7. Specifically, the gate electrode 7 is located within the first trench 10 and surrounded by the gate dielectric layer 6, within the second trench 11 and surrounded by the gate dielectric layer 6, and above the first conductivity type epitaxial layer 3, the second conductivity type well region 4, and a portion of the first conductivity type source region 5, separated by the gate dielectric layer 6. Multiple portions of the gate electrode 7 are interconnected. The gate dielectric layer 6 may be made of silicon oxide, silicon nitride, borophosphosilicate glass, aluminum oxide, sapphire or hafnium oxide. The gate electrode 7 may be made of metal or doped polysilicon.

[0059] S6. As shown in FIG11 , an isolation dielectric layer 8 is deposited on the surface of the device prepared in S5. The isolation dielectric layer 8 is located on both sides of and above the gate dielectric layer 6 and gate electrode 7, and the isolation dielectric layer 8 covers a portion of the first conductive type source region 5. The isolation dielectric layer 8 is etched to form a source electrode window. Ohmic metal, i.e., source metal 9, is deposited through this source electrode window and annealed to form a source ohmic contact. The interface between the source metal 9 and the first conductive type source region 5 is the source ohmic contact. The gate electrode 7 and the source metal 9 are separated by the isolation dielectric layer 8. A drain metal is deposited on the bottom layer of the first conductive type substrate 2 to form a drain ohmic contact. A source electrode is formed on the surface of the source ohmic contact layer, and a drain electrode is formed on the surface of the drain ohmic contact layer. The source metal 9 is located on the second trench 11, on a portion of the first conductive type source region 5, and on the isolation dielectric layer 8, and contacts the sidewalls of the gate dielectric layer 6.

[0060] The material of the isolation dielectric layer 8 can be silicon dioxide, nitride, or a composite of silicon dioxide and nitride.

[0061] The present embodiment provides a method for preparing a multi-channel silicon carbide MOSFET device, including the following steps, as shown in FIG12 .

[0062] S100 , forming a first conductivity type epitaxial layer 3 by epitaxial growth on a first conductivity type substrate 2 .

[0063] S200 , forming a second conductivity type well region 4 in the first conductivity type epitaxial layer 3 , and forming a first conductivity type source region 5 in the second conductivity type well region 4 .

[0064] S300 , etching the first conductive type epitaxial layer 3 to form a second trench 11 .

[0065] S400 , etching the bottom of the second trench 11 to form the first trench 10 .

[0066] S500 , forming a gate dielectric layer 6 on the top of the first conductivity type epitaxial layer 3 and inside the first trench 10 and the second trench 11 .

[0067] S600 , forming a patterned gate electrode material on the gate dielectric layer 6 on the top of the first conductive type epitaxial layer 3 and in the gate dielectric layer 6 in the first trench 10 and the second trench 11 to form a gate electrode 7 .

[0068] S700 , forming a patterned isolation dielectric layer 8 on the top and both sides of the gate electrode material.

[0069] S800: Deposit source metal through the source electrode window to form a source ohmic contact, and deposit drain metal on the back side to form a drain ohmic contact. The back side refers to the bottom surface of the drain electrode 1 in FIG1 (parallel to the xz plane).

[0070] S900 , forming a source electrode on the surface of the source ohmic contact layer, and forming a drain electrode 1 on the surface of the drain ohmic contact layer.

[0071] The multi-channel silicon carbide trench-gate MOSFET device provided in this embodiment introduces a trench structure based on the planar SiC MOSFET device. Protected by the second conductivity type well region 4, namely, the first trench 10 and the second trench 11 are disposed within the second conductivity type well region 4. The positive-negative (PN) junction formed by the second conductivity type well region 4 and the first conductivity type epitaxial layer 3 can effectively share the gate dielectric electric field strength, thereby avoiding the inherent gate dielectric breakdown problem of the trench structure. This effectively improves the device's conduction characteristics without compromising the breakdown characteristics.

[0072] Example 2

[0073] A multi-channel silicon carbide MOSFET device, as shown in FIG4, is basically the same as the first embodiment, except that it further includes a first conductive type current expansion layer 12, the first conductive type current expansion layer 12 is located in the first conductive type epitaxial layer 3, and the second conductive type well region 4 is located in the first conductive type current expansion layer 12; a first trench 10 is located in the second conductive type well region 4 and passes through the first conductive type current expansion layer 12 and the first conductive type source region 5 along the length direction of the device, that is, along the x-axis direction; a second trench 11 is located above the first trench 10 and the first conductive type current expansion layer 12 The gate dielectric layer 6 is located at the bottom and sidewalls of the first trench 10, the bottom and sidewalls of the second trench 11, the first conductive type current spreading layer 12, the second conductive type well region 4 and a portion of the first conductive type source region 5; the gate electrode 7 is located in the first trench 10 and is wrapped by the gate dielectric layer 6, is located in the second trench 11 and is wrapped by the gate dielectric layer 6, is located on the first conductive type current spreading layer 12, the second conductive type well region 4 and a portion of the first conductive type source region 5 and is separated by the gate dielectric layer 6. The first conductive type current spreading layer 12 can be formed by epitaxial growth or ion implantation, and its doping concentration is 1e16cm -3 ~1e17cm -3, which can reduce the on-resistance of the device. The first conductivity type current spreading layer 12 is formed by epitaxial growth or ion implantation before the second conductivity type well region 4 is formed in S2. Taking the ion implantation process as an example, an ion implantation mask layer is grown on the surface of the first conductivity type epitaxial layer 3 prepared in S1 by chemical vapor deposition. The ion implantation mask layer is then patterned by photolithography. Subsequently, the first conductivity type current spreading layer 12 is formed in the first conductivity type epitaxial layer 3 by ion implantation. The second conductivity type well region 4 and the first conductivity type source region 5 are then formed in the same manner. In this embodiment, the second conductivity type well region 4 and the first conductivity type source region 5 are the same as in the first embodiment and are still two non-contacting parts. However, the first conductivity type current spreading layer 12 is located between the two parts of the second conductivity type well region 4. S2 also includes forming the first conductivity type current spreading layer 12. This step includes: forming the first conductivity type current spreading layer 12 in the first conductivity type epitaxial layer 3, forming the second conductivity type well region 4 in the first conductivity type current spreading layer 12, and forming the first conductivity type source region 5 in the second conductivity type well region 4.

[0074] This application has the following effects:

[0075] (1) The multi-channel silicon carbide MOSFET device provided herein is formed by etching a first trench 10 and a second trench 11 in a direction perpendicular to the xz plane. The first trench 10 and the second trench 11 extend through the device active region in the x-direction. A gate dielectric layer 6 and a gate electrode 7 are formed in the first trench 10 and the second trench 11.

[0076] (2) The multi-channel silicon carbide MOSFET device provided in this application, under forward conduction operating conditions, utilizes a trench structure to form five channels at different locations between the gate electrode 7, the gate dielectric layer 6, and the second conductivity type well region 4. By controlling the depth and width of the first trench 10 and the second trench 11, the lengths of the five channels can be adjusted, thereby controlling the increase in the overall channel width of the device. This structure effectively increases the channel width, significantly reduces the channel resistance of the device, and significantly improves the device's conduction characteristics.

[0077] (3) The multi-channel silicon carbide MOSFET device provided in this application introduces a trench structure based on the planar SiC MOSFET device. Through the protection of the second conductive type well region 4, the inherent gate dielectric breakdown problem of the trench structure is avoided. Without compromising the breakdown characteristics, the conduction characteristics of the device are effectively improved. In addition, the design in which most of the trench is completely wrapped in the second conductive type well region 4 effectively reduces the gate-drain capacitance and the switching loss of the device, thereby improving the switching characteristics of the device.

Claims

1. A multi-channel silicon carbide MOSFET device, comprising: drain electrode; A first conductive type substrate, located on the drain electrode; A first conductive type epitaxial layer, located on the first conductive type substrate; A second conductivity type well region, located in the first conductivity type epitaxial layer; A first conductive type source region is located in the second conductive type well region; A first trench is located in the second conductivity type well region and runs through the first conductivity type epitaxial layer and the first conductivity type source region along the length direction of the device; A second trench is located above the first trench, in the first conductive type epitaxial layer, in the second conductive type well region, and in the first conductive type source region; a gate dielectric layer, located on the bottom and sidewalls of the first trench, the bottom and sidewalls of the second trench, the first conductive type epitaxial layer, the second conductive type well region, and a portion of the first conductive type source region; a gate electrode, located in the first trench and wrapped by the gate dielectric layer, located in the second trench and wrapped by the gate dielectric layer, located on the first conductive type epitaxial layer, on the second conductive type well region, and on a portion of the first conductive type source region and separated by the gate dielectric layer; An isolation dielectric layer, located on both sides and above the gate dielectric layer and the gate electrode; The source metal is located on both sides and on the isolation dielectric layer.

2. The multi-channel silicon carbide MOSFET device according to claim 1, wherein: The depth of the second conductive type well region is greater than the sum of the depths of the first trench and the second trench, and the difference between the depth of the second conductive type well region and the sum of the depths of the first trench and the second trench is not less than 0.2 μm.

3. A multi-channel silicon carbide MOSFET device according to claim 1, wherein: The width of the first groove is greater than the width of the second groove, and the difference between the width of the first groove and the width of the second groove is not less than 0.1 μm.

4. A multi-channel silicon carbide MOSFET device according to claim 1, wherein: The number of the first grooves is the same as that of the second grooves, which is at least two; the spacing between adjacent second grooves along the z-axis direction is not less than 0.5 μm and not more than 2.5 μm; The spacing between adjacent first grooves along the z-axis direction is not less than 0.2 μm and not more than 2 μm, and the distance between the first groove and the edge of the device along the z-axis direction is not less than 0.5 μm.

5. A multi-channel silicon carbide MOSFET device according to claim 1, wherein: The bottom of the second conductive type well region is lower than the bottom of the first trench, the second conductive type well region is divided into two non-contacting parts, and are symmetrically arranged at the upper parts of both sides of the first conductive type epitaxial layer, and the first conductive type epitaxial layer is between the two parts of the second conductive type well region; the first conductive type source region is divided into two non-contacting parts, and are respectively arranged at the upper parts of both sides of the two parts of the second conductive type well region.

6. A multi-channel silicon carbide MOSFET device according to claim 1, wherein: Under forward conduction working conditions, there are five channels in different positions, wherein the first channel is located at the top surface of the second conductive type well region, the second channel is located at the surface of the second conductive type well region near the side wall of the second trench, the third channel is located at the surface of the second conductive type well region near the upper boundary of the first trench, the fourth channel is located at the surface of the second conductive type well region near the side wall of the first trench, and the fifth channel is located at the surface of the second conductive type well region near the bottom of the first trench.

7. A multi-channel silicon carbide MOSFET device according to claim 6, wherein: Under a fixed cell size, the length of the first channel is determined by the width of the second groove, the length of the second channel is determined by the depth of the second groove, the length of the third channel is determined by the width of the first groove, the length of the fourth channel is determined by the depth of the first groove, and the length of the fifth channel is determined by the width of the first groove; the increase in the channel width of the entire device depends on the sum of the lengths of the first channel, the second channel, the third channel, the fourth channel and the fifth channel.

8. A multi-channel silicon carbide MOSFET device according to claim 6, wherein: The first channel, the third channel and the fifth channel are located on the Si plane parallel to the device surface, and the second channel and the fourth channel are located on the A plane or the M plane perpendicular to the device surface. Under forward conduction working conditions, the mobility of the second channel and the fourth channel is greater than the mobility of the first channel, the third channel and the fifth channel.

9. A multi-channel silicon carbide MOSFET device according to claim 1, further comprising a first conductive type current spreading layer, the first conductive type current spreading layer is located in the first conductive type epitaxial layer, and the second conductive type well region is located in the first conductive type current spreading layer; the first trench is located in the second conductive type well region and penetrates the first conductive type current spreading layer and the first conductive type source region along the length direction of the device; the second trench is located on the first trench, in the first conductive type current spreading layer, in the second conductive type well region, and in the first conductive type source region; the gate dielectric layer is located at the bottom and sidewalls of the first trench, the bottom and sidewalls of the second trench, on the first conductive type current spreading layer, on the second conductive type well region, and on a portion of the first conductive type source region; the gate electrode is located in the first trench and wrapped by the gate dielectric layer, in the second trench and wrapped by the gate dielectric layer, on the first conductive type current spreading layer, on the second conductive type well region, and on a portion of the first conductive type source region and separated by the gate dielectric layer.

10. A method for preparing a multi-channel silicon carbide MOSFET device according to any one of claims 1 to 9, comprising: epitaxially growing a first conductivity type epitaxial layer on a first conductivity type substrate; forming a second conductivity type well region in the first conductivity type epitaxial layer, and forming a first conductivity type source region in the second conductivity type well region; Etching the first conductive type epitaxial layer to form a second trench; Etching the bottom of the second trench to form a first trench; forming a gate dielectric layer on the top of the first conductive type epitaxial layer and inside the first trench and the second trench; Forming a patterned gate electrode material on the gate dielectric layer on the top of the first conductive type epitaxial layer and in the gate dielectric layer in the first trench and the second trench to form a gate electrode; forming a patterned isolation dielectric layer on the top and both sides of the gate electrode material; Depositing source metal through the source electrode window to form a source ohmic contact, and depositing drain metal on the back side to form a drain ohmic contact; A source electrode is formed on the surface of the source ohmic contact layer, and a drain electrode is formed on the surface of the drain ohmic contact layer.

11. The method for preparing a multi-channel silicon carbide MOSFET device according to claim 10, wherein: An isotropic dry etching process is adopted in etching the bottom of the second groove to form the first groove, and the etching gas adopted is at least one of sulfur hexafluoride SF6, hydrogen bromide HBr, chlorine Cl2, oxygen O2, or argon Ar gas.

12. The method for preparing a multi-channel silicon carbide MOSFET device according to claim 10, wherein: The forming of the second conductive type well region in the first conductive type epitaxial layer and the forming of the first conductive type source region in the second conductive type well region also includes forming a first conductive type current expansion layer, wherein the forming of the first conductive type current expansion layer includes: forming the first conductive type current expansion layer in the first conductive type epitaxial layer, forming the second conductive type well region in the first conductive type current expansion layer, and forming the first conductive type source region in the second conductive type well region.

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