Gate-all-around channel silicon carbide field-effect transistor and manufacturing method therefor

Abstract

A gate-all-around channel silicon carbide field-effect transistor and a manufacturing method therefor. The gate-all-around channel silicon carbide field-effect transistor comprises: second conductivity type channel layer etching windows (14) that are periodically distributed on a second conductivity type channel layer (4) in a y direction, pass through the second conductivity type channel layer (4) and are in contact with trenches (3); a first gate dielectric layer (8-1) located on the inner surfaces of the trenches (3), a second gate dielectric layer (8-2) located on the upper surface of the second conductivity type channel layer (4), and a third gate dielectric layer (8-3) located on the inner walls of the second conductivity type channel layer etching windows (14); and a first gate electrode (9-1) filling the trenches (3), a second gate electrode (9-2) covering part of the upper surface of the second gate dielectric layer (8-2), and a third gate electrode (9-3) filling the second conductivity type channel layer etching windows (14).

Description

Surround-gate channel silicon carbide field-effect transistor and manufacturing method thereof

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on August 3, 2023, with application number 202310971611.X. The entire contents of the above application are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of semiconductor technology, and for example, to a surround-gate channel silicon carbide field-effect transistor and a method for manufacturing the same. Background Art

[0003] The development of power electronics systems has placed higher demands on the performance of semiconductor devices, such as high temperature, high frequency, radiation resistance, and high voltage. While traditional silicon device manufacturing processes are mature, the inherent properties of the material limit its application in extreme operating environments. Compared to silicon (Si), silicon carbide (SiC) offers a wider bandgap, higher electron saturation drift velocity, stronger radiation resistance, higher breakdown electric field, and higher thermal conductivity. This gives it broad application prospects in power electronics, aerospace systems, high-speed rail traction equipment, and military electronic communications systems.

[0004] However, unlike Si materials, the oxidation process of SiC materials will produce the precipitation of free carbon (C). Although most C will be converted into gaseous carbon oxides in an oxygen atmosphere, a considerable portion of it will still exist as C clusters at the gate oxide layer interface. On the other hand, the epitaxial quality of SiC material itself is far inferior to that of Si material, and there are many crystal defects and dislocations. These combined factors lead to the interface state density in the channel region of conventional silicon carbide metal-oxide-semiconductor field-effect transistor (SiC MOSFET) devices being much higher than that of Si MOSFET, which directly affects the low channel mobility. Even with high-temperature annealing treatment with nitrogen oxide, the mobility can only be increased to 20cm 2 / V·s~30cm 2 / V·s. The channel resistance in SiC low-voltage MOSFET devices is particularly prominent. The vertical gate trench structure is a solution that can increase the channel mobility to 40cm 2 / V·s or above, but the trench gate structure needs to effectively shield the strong electric field at the bottom of the gate dielectric, which will directly affect the reliability of the device.

[0005] The channel mobility of conventional SiC MOSFETs is much lower than the bulk mobility, resulting in a significant proportion of channel on-resistance in low-voltage devices, affecting conduction performance. Although some literature reports that when the lateral spacing of SiC between trenches (i.e., between SiC trenches) is less than 100nm, especially when it approaches 50nm, the channel mobility of power devices can reach 200cm due to the double-sided gate effect, 2 / V·s, significantly improving channel mobility. However, because SiC is much more difficult to etch than Si, controlling the 50nm linewidth etching process for power devices is very challenging, making this structure unsuitable for mass production.

[0006] Summary of the Invention

[0007] The present application discloses a surround-gate channel silicon carbide field-effect transistor and a method for manufacturing the same. The surround-gate channel design is adopted, and upper and lower double-layer gate electrodes are used to realize gate-controlled conduction of the channel, thereby obtaining an ultra-high channel mobility and greatly reducing the on-resistance of the device.

[0008] The present application provides a gate-all-around channel silicon carbide field-effect transistor, comprising:

[0009] a first conductivity type SiC epitaxial layer;

[0010] a second conductivity type well region in the first conductivity type SiC epitaxial layer;

[0011] A trench in the first conductivity type SiC epitaxial layer adjacent to the second conductivity type well region; the first conductivity type SiC epitaxial layer between adjacent trenches in the x direction is defined as a device neck region;

[0012] A first conductivity type SiC epitaxial layer, a second conductivity type well region, and a second conductivity type channel layer on the trench;

[0013] a first conductivity type source region penetrating the second conductivity type channel layer and extending into the second conductivity type well region and adjacent to the trench;

[0014] Second conductivity type channel layer etching windows are periodically distributed along the y direction on the second conductivity type channel layer, penetrate the second conductivity type channel layer and contact the trench;

[0015] The gate dielectric layer includes a first gate dielectric layer located on the inner surface of the trench, a second gate dielectric layer located on the upper surface of the second conductive type channel layer, and a third gate dielectric layer located on the inner wall of the etching window of the second conductive type channel layer;

[0016] The gate electrode includes a first gate electrode filling the trench and wrapped by the first gate dielectric layer, a second gate electrode covering a portion of the upper surface of the second gate dielectric layer, and a third gate electrode filling the etched window of the second conductive type channel layer and wrapped by the third gate dielectric layer;

[0017] an isolation dielectric layer covering the second gate electrode, the second gate dielectric layer and a portion of the first conductive type source region;

[0018] a source ohmic resistor connected to a portion of the second conductive type channel layer and a portion of the first conductive type source region;

[0019] The x direction is the length direction of the transistor, and the y direction is the width direction of the transistor.

[0020] Optionally, the groove is continuous in the y direction or is a periodically distributed rectangle; the projection of the groove in the z direction completely covers the etching window of the second conductive type channel layer, the z direction is the height direction of the transistor, and x, y, and z are perpendicular to each other;

[0021] The depth of the trench along the z direction is greater than 0.5um, and the width of the trench along the x direction is greater than 0.3um and less than 1.5um; the depth of the trench is shallower than the depth of the second conductive type well region, the distance between the bottom of the trench and the bottom of the second conductive type well region is greater than 0.2um, and the spacing between the boundary of the second gate electrode and the boundary of the trench is greater than 0.2um.

[0022] Optionally, the second conductive type well region does not completely cover the trench, and a lateral boundary difference between the trench and an adjacent second conductive type well region in the x-direction on a side close to the device neck region is less than 0.8 um.

[0023] Optionally, the thickness of the second conductive type channel layer does not exceed 120 nm.

[0024] Optionally, the length of the second conductive type channel layer etching window in the x direction is not less than 1.0um, and the width in the y direction is not less than 0.8um; the spacing between adjacent second conductive type channel layer etching windows is in the range of 1.5um to 2.0um; the distance between the second conductive type channel layer etching window and the boundary of the groove is in the range of 0.1um to 1.0um.

[0025] Optionally, it also includes: a second conductive type heavily doped region that penetrates the second conductive type channel layer, extends into the second conductive type well region and is away from the trench; and a first conductive type current extension region that penetrates the second conductive type channel layer and extends into the first conductive type SiC epitaxial layer and is located in the middle of the device neck region.

[0026] The present application provides a method for manufacturing a gate-all-around channel silicon carbide field-effect transistor, comprising:

[0027] forming a first conductivity type SiC epitaxial layer on a first conductivity type SiC substrate;

[0028] Performing selective doping in the first conductivity type epitaxial layer to form a second conductivity type well region;

[0029] Etching the first conductive type SiC epitaxial layer to form a trench;

[0030] forming a sacrificial layer in the trench;

[0031] forming a second conductivity type channel layer on the first conductivity type SiC epitaxial layer, the second conductivity type well region, and the trench;

[0032] Performing selective doping to form a first conductivity type source region, wherein the first conductivity type source region penetrates the second conductivity type channel layer and extends into the second conductivity type well region and is adjacent to the trench;

[0033] Etching the second conductive type channel layer to form second conductive type channel layer etching windows, wherein the second conductive type channel layer etching windows are periodically distributed along the y direction on the second conductive type channel layer, and the second conductive type channel layer etching windows penetrate the second conductive type channel layer and stop on the sacrificial layer;

[0034] removing the sacrificial layer;

[0035] Growing a gate dielectric layer, including a first gate dielectric layer located on the inner surface of the trench, a second gate dielectric layer located on the upper surface of the second conductive type channel layer, and a third gate dielectric layer located on the inner wall of the etching window of the second conductive type channel layer;

[0036] Growing and etching a gate electrode material to form a gate electrode, including a first gate electrode filling the trench, a second gate electrode covering a portion of the upper surface of the second gate dielectric layer, and a third gate electrode filling the etched window of the second conductive type channel layer and wrapped by the third gate dielectric layer;

[0037] An isolation dielectric layer is grown to form a source ohmic layer, a drain ohmic layer, a source thickening metal layer, and a drain thickening metal layer.

[0038] Optionally, the sacrificial layer is made of a carbon film or a dielectric;

[0039] In the case where the sacrificial layer is a carbon film, the method of forming the sacrificial layer in the groove includes photoresist coating, carbonization and surface planarization processes, and removing the sacrificial layer includes removing the sacrificial layer by high-temperature thermal oxidation, with the oxidation temperature not exceeding 1150 degrees Celsius;

[0040] In the case where the sacrificial layer is a dielectric, removing the sacrificial layer includes removing the sacrificial layer by wet etching.

[0041] Optionally, the deposition thickness range of the second conductive type channel layer is 10nm to 250nm, wherein, when the gate dielectric layer is formed by thermal oxidation, the deposition thickness of the second conductive type channel layer is 80nm to 250nm; when the gate dielectric layer is formed by deposition, the deposition thickness of the second conductive type channel layer is 10nm to 120nm.

[0042] Optionally, the etching of the second conductive type channel layer to form a second conductive type channel layer etching window includes: defining the location of the groove as a groove etching area, and mapping the projection of the groove etching area onto the second conductive type channel layer to form at least one second conductive type channel layer etching window, each second conductive type channel layer etching window has a length in the x direction of not less than 1.0um, and a width in the y direction of not less than 0.8um; the spacing between adjacent second conductive type channel layer etching windows ranges from 1.5um to 2.0um; the distance between each second conductive type channel layer etching window and the boundary of the groove etching area ranges from 0.1um to 1.0um. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] FIG1 is a schematic cross-sectional view of a surround-gate channel silicon carbide field-effect transistor provided in Example 1, taken along a direction perpendicular to the gate strip;

[0044] FIG2 is a three-dimensional schematic diagram of a gate-around channel silicon carbide field-effect transistor provided in Example 1;

[0045] FIG3 is a schematic cross-sectional view of another gate-around channel silicon carbide field effect transistor provided in Example 1, taken along a direction perpendicular to the gate strip;

[0046] FIG4 is a schematic diagram of the cross-sectional structure at the position AA' in FIG2;

[0047] 5A is a schematic cross-sectional view taken along a direction perpendicular to the gate strips in step S2 of fabricating the gate-around channel silicon carbide field effect transistor of Example 1;

[0048] FIG5B is a schematic diagram of the cross-sectional structure at the position AA' in FIG5A corresponding to FIG2;

[0049] 6A is a schematic cross-sectional view taken along a direction perpendicular to the gate strips in step S3 of fabricating the gate-around channel silicon carbide field effect transistor of Example 1;

[0050] FIG6B is a schematic cross-sectional view of the structure at the position AA′ in FIG6A corresponding to FIG2 ;

[0051] 7A is a schematic cross-sectional view taken along a direction perpendicular to the gate strips in step S4 of fabricating the gate-around channel silicon carbide field effect transistor of Example 1;

[0052] FIG7B is a schematic diagram of the cross-sectional structure at the position AA' in FIG7A corresponding to FIG2;

[0053] 8A is a schematic cross-sectional view taken along a direction perpendicular to the gate strips in step S5 of fabricating the gate-around channel silicon carbide field effect transistor of Example 1;

[0054] FIG8B is a schematic diagram of the cross-sectional structure at the position AA' in FIG8A corresponding to FIG2;

[0055] 9A is a schematic cross-sectional view taken along a direction perpendicular to the gate strips in step S6 of fabricating the gate-around channel silicon carbide field effect transistor of Example 1;

[0056] FIG9B is a schematic cross-sectional view of the structure at the position AA' in FIG9A corresponding to FIG2;

[0057] 10A is a schematic cross-sectional view taken along a direction perpendicular to the gate strips in step S7 of fabricating the gate-around channel silicon carbide field effect transistor of Example 1;

[0058] FIG10B is a schematic cross-sectional view of the structure at the position AA' in FIG10A corresponding to FIG2;

[0059] 11A is a schematic cross-sectional view taken along a direction perpendicular to the gate strips during step S9 of fabricating the gate-around channel silicon carbide field effect transistor of Example 1;

[0060] FIG11B is a schematic cross-sectional view of the structure at the position AA' in FIG11A corresponding to FIG2;

[0061] 12A is a schematic cross-sectional view taken along a direction perpendicular to the gate strips during step S10 of fabricating the gate-around channel silicon carbide field-effect transistor of Example 1;

[0062] FIG12B is a schematic cross-sectional view of the structure at the position AA' in FIG12A corresponding to FIG2;

[0063] 13A is a schematic cross-sectional view taken along a direction perpendicular to the gate strips in step S11 of fabricating the gate-around channel silicon carbide field-effect transistor of Example 1;

[0064] FIG13B is a schematic cross-sectional view of the structure at the position AA' in FIG13A corresponding to FIG2;

[0065] 14 is a schematic diagram comparing etching patterns of the second conductivity type well region, the second conductivity type channel layer, and the gate electrode on the xy plane provided in Example 1;

[0066] FIG15 is a three-dimensional schematic diagram of an etched pattern of a second conductive type channel layer provided in Example 1;

[0067] 16 is a schematic diagram comparing etching patterns of the second conductivity type well region, the second conductivity type channel layer, and the gate electrode on the xy plane provided in Example 2;

[0068] FIG17 is a three-dimensional schematic diagram of an etched pattern of a second conductivity type channel layer provided in Example 2;

[0069] FIG18 is a schematic diagram of the cross-sectional structure at the position AA' of FIG15;

[0070] In the figure: 1. First conductivity type SiC epitaxial layer; 2. Second conductivity type well region; 3. Groove; 3-1. Sacrificial layer; 4. Second conductivity type channel layer; 5. First conductivity type source region; 6. Second conductivity type heavily doped region; 7. First conductivity type current extension region; 8. Gate dielectric layer; 8-1. First gate dielectric layer; 8-2. Second gate dielectric layer; 8-3. Third gate dielectric layer; 9. Gate electrode; 9-1. First gate electrode; 9-2. Second gate electrode; 9-3. Third gate electrode; 10. Isolation dielectric layer; 11. Source ohm; 12. Gate electrode etching region; 13. Trench etching region; 14. Second conductivity type channel layer etching window. DETAILED DESCRIPTION

[0071] The following describes a gate-all-around channel silicon carbide field-effect transistor and a manufacturing method thereof according to the present application with reference to the accompanying drawings.

[0072] Example 1

[0073] As shown in Figures 1-4, a surround-gate channel silicon carbide field-effect transistor includes: a first conductivity type SiC epitaxial layer 1; a second conductivity type well region 2 located in the first conductivity type SiC epitaxial layer 1; the second conductivity type well region 2 is doped with aluminum (Aluminum, Al) and has a junction depth of 1.5 μm from the upper surface of the epitaxial layer 1.

[0074] In the first conductivity type SiC epitaxial layer 1, a trench 3 is formed adjacent to the second conductivity type well region 2. As shown in Figure 2, the x-direction is defined as the length direction of the device, which is also the horizontal direction in Figure 1; the y-direction is defined as the width direction of the device, which is also the gate direction and the direction perpendicular to the paper in Figure 1; and the z-direction is defined as the height direction of the device, which is also the vertical direction in Figure 1. The first conductivity type SiC epitaxial layer 1 between adjacent trenches 3 in the x-direction is defined as the device neck region. As shown in Figure 2, the A-A' direction is the gate direction of the device, and the trench 3 is continuous along the gate direction.

[0075] The depth of the groove 3 is greater than 0.5um, and the width of the groove 3 along the x-direction is greater than 0.3um and less than 1.5um. Optionally, the width is greater than 0.5um and less than 1.2um. The depth of the groove 3 is shallower than the depth of the second conductive type well region 2. The difference in distance between the bottom of the groove 3 and the bottom of the second conductive type well region 2 should be greater than 0.2um, and optionally, greater than 0.5um. The second conductive type well region 2 does not completely cover the groove 3. The lateral boundary difference between the groove 3 and the adjacent second conductive type well region 2 on the side close to the neck region of the device should be less than 0.8um, and it is recommended to be less than 0.5um. Optionally, it should be less than 0.2um.

[0076] In some embodiments of the present application, the width of the trench 3 ranges from 1.2um to 1.5um, the depth of the trench 3 ranges from 0.8um to 1.0um, and the distance between the trench 3 and the boundary of the second conductivity type well region 2 near the device neck region in the x direction ranges from 0.3um to 0.5um.

[0077] A second conductive type channel layer 4 is located above the first conductive type SiC epitaxial layer 1, the second conductive type well region 2 and the trench 3; the thickness of the second conductive type channel layer 4 does not exceed 120nm, and the recommended thickness is less than 80nm, and optionally, less than 50nm.

[0078] In some embodiments of the present application, the thickness of the second conductive type channel layer 4 is in the range of 50 nm to 60 nm.

[0079] As shown in Figures 14 and 15, the second conductive type channel layer 4 has second conductive type channel layer etching windows 14 periodically distributed along the y direction. The second conductive type channel layer etching windows 14 penetrate the second conductive type channel layer 4 and contact the trench 3, facilitating the removal of the sacrificial layer 3-1 and connecting the gate electrode 9 during device fabrication. The distance L2 between the boundary of the second conductive type channel layer etching window 14 and the trench 3 ranges from 0.1um to 1.0um, and optionally, ranges from 0.1um to 0.5um. The width W of the second conductive type channel layer etching window 14 in the y direction is not less than 0.8um, and optionally, not less than 1.5um. The length L of the second conductive type channel layer etching window 14 in the x direction is not less than 1.0um, and optionally, not less than 1.5um. The spacing W1 between adjacent second conductive type channel layer etching windows 14 ranges from 1.5um to 2.0um.

[0080] In some embodiments of the present application, see Figure 14, the width W of the second conductive type channel layer etching window 14 ranges from 1.5um to 2.0um, the length L ranges from 1um to 1.2um, the spacing W1 between adjacent second conductive type channel layer etching windows 14 ranges from 1.5um to 2.0um, and the boundary distance L2 between the second conductive type channel layer etching window 14 and the groove 3 is approximately 0.15um.

[0081] A first conductivity type source region 5 penetrates the second conductivity type channel layer 4 , extends into the second conductivity type well region 2 , and is adjacent to the trench 3 .

[0082] Unlike the surround-gate channel silicon carbide field-effect transistor shown in FIG1 , as shown in FIG3 , the transistor in this embodiment further includes a second conductivity type heavily doped region 6 penetrating the second conductivity type channel layer 4, extending into the second conductivity type well region 2 and away from the trench 3; the second conductivity type heavily doped region 6 has a depth range of 0.6 μm to 1.0 μm, and a peak doping concentration greater than 1E19 cm -3 .

[0083] Unlike the surround-gate channel silicon carbide field-effect transistor shown in Figure 1, as shown in Figure 3, a first-conductivity-type current extension region 7 is located in the middle of the device neck region, penetrating the second-conductivity-type channel layer 4 and extending into the first-conductivity-type SiC epitaxial layer 1. The width of the first-conductivity-type current extension region 7 is greater than 0.5 μm. In some embodiments of the present application, the depth of the first-conductivity-type current extension region 7 ranges from 0.8 μm to 1.2 μm, and the width ranges from 0.6 μm to 1.0 μm.

[0084] The gate dielectric layer 8 includes a first gate dielectric layer 8-1 located on the inner surface of the trench 3, a second gate dielectric layer 8-2 located on the upper surface of the second conductive type channel layer 4, and a third gate dielectric layer 8-3 located on the inner wall of the second conductive type channel layer etching window 14. The gate dielectric layer 8 is made of silicon oxide and has a thickness ranging from 30nm to 100nm, optionally ranging from 50nm to 100nm, for example, ranging from 60nm to 80nm. In some other embodiments of the present application, the gate dielectric layer 8 can be made of materials such as aluminum oxide (Aluminum Oxide, Al2O3), hafnium oxide (HfO2), aluminum oxynitride (Aluminum Oxynitride, AlON), and the thickness range is adjusted according to the material.

[0085] The gate electrode 9 includes a first gate electrode 9-1 filling the trench 3 and surrounded by the first gate dielectric layer 8-1, a second gate electrode 9-2 covering a portion of the upper surface of the second gate dielectric layer 8-2, and a third gate electrode 9-3 filling the second conductivity type channel layer etch window 14 and surrounded by the third gate dielectric layer 8-3. The gate electrode 9 is made of doped polysilicon, and the thickness of the second gate electrode 9-2 ranges from 600nm to 800nm. The distance L1 between the boundary of the second gate electrode 9-2 and the boundary of the trench 3 is greater than 0.2μm, and optionally, L1 ranges from 0.3μm to 0.6μm. The second gate electrode 9-2 and the first gate electrode 9-1 are connected by the second conductivity type channel layer etch window 14 in the second conductivity type channel layer 4, that is, through the third gate electrode 9-3, as shown in Figure 4. The first gate electrode 9-1 completely fills the trench 3, and there are no voids in the trench 3. In some other embodiments of the present application, the gate electrode 9 may also be a metal electrode, and the material of the gate electrode 9 may be selected according to actual needs.

[0086] An isolation dielectric layer 10 covers the second gate electrode 9-2 and the second gate dielectric layer 8-2 and covers part of the first conductive type source region 5; the isolation dielectric layer 10 is made of silicon dioxide, silicon nitride, or a composite of silicon dioxide and silicon nitride, with a thickness ranging from 0.2um to 1.0um.

[0087] A source ohm 11 connected to a portion of the second conductivity type channel layer 4 , a portion of the first conductivity type source region 5 and the second conductivity type heavily doped region 6 .

[0088] In addition to the above parts, a surround-gate channel silicon carbide field-effect transistor of the present application should also have a first conductive type SiC substrate located on the lower surface of the first conductive type SiC epitaxial layer 1, a drain ohm and a drain thickening metal located on the lower surface of the first conductive type SiC substrate, and a source thickening metal covering the isolation dielectric layer 10 and the source ohm 11.

[0089] In some examples of the present application, the first conductivity type is N-type and the second conductivity type is P-type. P-type doping of SiC generally uses only Al, and N-type doping generally uses nitrogen.

[0090] This embodiment adopts a strip-shaped primitive cell design, that is, strip-shaped gate electrodes are periodically arranged to form a device structure.

[0091] The concentration and thickness of the first conductive type SiC epitaxial layer 1 are related to the device voltage rating. For example, a SiC MOSFET device with a voltage rating of 650V usually corresponds to a doping concentration of 1E16cm -3 ~2E16cm -3 , N-type SiC epitaxial material with a thickness of 5um to 6um.

[0092] A method for fabricating a surround-gate channel silicon carbide field-effect transistor of the present application is shown in FIG5A to FIG13B , wherein A and B are respectively a schematic cross-sectional view of the transistor perpendicular to the gate direction (i.e., the xz plane) and a schematic cross-sectional view of the transistor along the AA' direction in the same step. The steps are:

[0093] S1 . epitaxially grow a first conductivity type SiC epitaxial layer 1 on a first conductivity type SiC substrate.

[0094] S2. As shown in Figures 5A and 5B, a second conductivity type well region 2 is selectively implanted in the first conductivity type SiC epitaxial layer 1. The second conductivity type well region 2 is formed by a single implant or multiple epitaxial implants. Multiple epitaxial implants can be performed by first implanting the second conductivity type, then performing additional first conductivity type epitaxial implants, and finally performing the second conductivity type implant. The doping concentration of the first conductivity type epitaxial implant is substantially the same as that in S1, and the thickness of the first conductivity type epitaxial implant is within the implant depth penetration range, such as 1 μm. The second second conductivity type implant is implanted into the same region as the first second conductivity type implant, but the second second conductivity type implant penetrates a new 1 μm epitaxial layer. This method allows the final second conductivity type implant region to be deeper. In some embodiments of the present application, a multi-energy implant is used to form the second conductivity type well region 2, with a maximum implant energy of 600 keV to 640 keV. After S2, selective implantation of the first conductivity type can be performed to connect to the first conductivity type source region 5 in the subsequent S6, reducing the source region series circuit. That is, by implanting doping before and after the growth of the second conductive type channel layer 4, respectively, the first conductive type source region 5 is formed cumulatively, making the first conductive type source region 5 deeper, and forming a deeper first conductive type source region 5 by the first conductive type selective doping here, and the pattern for implanting the first conductive type selective doping and the pattern for implanting the first conductive type source region 5 in the subsequent S6 use the same mask pattern. After S2, the second conductive type selective doping can be performed to form a second conductive type heavily doped region 6 in the second conductive type well region 2 at a position away from the device neck region to improve the body diode characteristics. In other words, the second conductive type heavily doped region 6 is made deeper, and a deeper second conductive type heavily doped region 6 is formed by the second conductive type selective doping here.

[0095] S3. As shown in Figures 6A and 6B, a trench 3 is formed by photolithography and etching processes. Exemplarily, a trench etching region 13 is first provided at the junction of the first conductivity type SiC epitaxial layer 1 and the second conductivity type well region 2. A trench 3 is formed on the trench etching region 13. The length and width of the trench etching region 13 are the same as the length and width of the trench 3. The trench 3 is located at the junction of the first conductivity type SiC epitaxial layer 1 and the second conductivity type well region 2, and the bottom of the trench 3 is higher than the bottom of the second conductivity type well region 2, that is, the etching depth of the trench 3 is no greater than the depth of the second conductivity type well region 2. The trench 3 is continuous along the gate stripe direction. The depth of the trench 3 is greater than 0.5 μm, and the width of the trench 3 along the x-direction is greater than 0.3 μm and less than 1.5 μm. Optionally, the width is greater than 0.5 μm and less than 1.2 μm. The depth of the bottom of the trench 3 is shallower than the depth of the bottom of the second conductivity type well region 2. The difference between the depth of the bottom of the trench 3 should be greater than 0.2 μm, and optionally, greater than 0.5 μm.

[0096] S4. As shown in Figures 7A and 7B, a sacrificial layer 3-1 is filled in trench 3. Sacrificial layer 3-1 is configured to fill trench 3, flattening the device surface and facilitating subsequent deposition of the channel layer. Sacrificial layer 3-1 is formed of a carbon film, and the filling method includes photoresist coating, carbonization, and surface flattening. Sacrificial layer 3-1 can also be a dielectric. Sacrificial layer 3-1 completely fills trench 3. After deposition of sacrificial layer 3-1, an additional flattening process can be performed to remove sacrificial layer 3-1 from surfaces outside trench 3, maintaining an overall flat surface.

[0097] S5. As shown in Figures 8A and 8B, a second conductive type channel layer 4 is deposited; the second conductive type channel layer 4 is located above the first conductive type SiC epitaxial layer 1, the second conductive type well region 2 and the trench 3; the second conductive type channel layer 4 is grown by atomic layer deposition (ALD) to grow the second conductive type SiC, and the deposition temperature does not exceed 1000°C, optionally, does not exceed 800°C, and the deposition thickness of the second conductive type channel layer 4 ranges from 10nm to 250nm, optionally, the deposition thickness ranges from 50nm to 60nm, thereby achieving the growth of an ultra-thin second conductive type channel layer 4. When the gate dielectric layer 8 is formed by thermal oxidation, the recommended deposition thickness of the second conductivity type channel layer 4 is 80nm to 250nm. When the gate dielectric layer 8 is formed by deposition, the recommended deposition thickness of the second conductivity type channel layer 4 is 10nm to 120nm. Since the thickness of the second conductivity type channel layer 4 remains unchanged when the gate dielectric layer 8 is formed by deposition, but when the gate dielectric layer 8 is formed by thermal oxidation, the SiC in the second conductivity type channel layer 4 is consumed, making the second conductivity type channel layer 4 thinner, the recommended deposition thickness of the second conductivity type channel layer 4 needs to be increased. In this embodiment, the ALD process is used to achieve the production of an ultra-thin channel layer, which facilitates precise process control and has the ability to control the process for mass production.

[0098] S6. As shown in Figures 9A and 9B, a first conductive type source region 5 is selectively implanted on the surface of the device formed in step S5. The first conductive type source region 5 penetrates the second conductive type channel layer 4 and extends into the second conductive type well region 2, and is adjacent to the groove 3. In this embodiment, the first conductive type source region 5 is in contact with the groove 3 away from the neck region of the device; in other optional schemes of the present application, a second conductive type heavily doped region 6 and a first conductive type current extension region 7 can be selectively implanted on the surface of the device formed in step S5; wherein, the second conductive type heavily doped region 6 penetrates the second conductive type channel layer 4, extends into the second conductive type well region 2 and is away from the groove 3 and the neck region of the device; the first conductive type current extension region 7 penetrates the second conductive type channel layer 4 and extends into the first conductive type SiC epitaxial layer 1, and is located in the middle of the neck region of the device; the neck region of the device refers to the first conductive type SiC epitaxial layer 1 between adjacent trenches 3; the width of the first conductive type current extension region 7 is greater than 0.5um.

[0099] S7. As shown in Figures 10A and 10B, the second conductive type channel layer 4 is etched to form a second conductive type channel layer etching window 14. The second conductive type channel layer etching window 14 is periodically distributed along the y direction on the second conductive type channel layer 4. The second conductive type channel layer etching window 14 passes through the second conductive type channel layer 4 and stops on the sacrificial layer 3-1, which is convenient for the subsequent removal of the sacrificial layer 3-1 and the deposition of the gate dielectric layer 8. Before etching the second conductive type channel layer 4, an additional high-temperature activation annealing process is performed, and the annealing temperature range is 1500°C to 1700°C. As shown in Figures 14 and 15, the projection of the groove etching area 13 is mapped to the device surface formed by S6, that is, a plurality of second conductive type channel layer etching windows 14 are formed on the second conductive type channel layer 4. In this embodiment, all the second conductive type channel layer etching windows 14 have the same shape, that is, the length, width and depth are exactly the same; the spacing between the second conductive type channel layer etching windows 14 is W1; the distance between the second conductive type channel layer etching window 14 and the boundary of the groove etching area 13 is L2, and the range of L2 is 0.1um~1.0um, optionally, the range is 0 .1um~0.5um, the width W of the second conductive type channel layer etching window 14 is not less than 0.8um, optionally, not less than 1.5um; the length L of the second conductive type channel layer etching window 14 is not less than 1.0um, optionally, not less than 1.5um; in this embodiment, L2 is approximately 0.15um; the width W of the second conductive type channel layer etching window 14 ranges from 1.5um to 2.0um, the length L ranges from 1um to 1.2um, and the spacing W1 between adjacent second conductive type channel layer etching windows 14 ranges from 1.5um to 2.0um.

[0100] S8. Remove the sacrificial layer 3-1. When the sacrificial layer 3-1 is a carbon film, it is removed by high-temperature thermal oxidation. The oxidation temperature is recommended not to exceed 1150°C. Optionally, the oxidation temperature range is 900°C to 1000°C. When the sacrificial layer 3-1 is a dielectric, it is removed by wet etching. There should be a high-temperature activation annealing before S9, and the temperature should not be lower than 1400°C. When a dielectric is used as the sacrificial layer 3-1, the activation annealing should be performed after the sacrificial layer 3-1 is removed. In this embodiment, the sacrificial layer 3-1 adopts dielectrics such as silicon dioxide (SiO2) and silicon nitride (Si3N4). Different dielectrics have different corresponding wet etching solutions. For example, SiO2 is usually etched with buffered oxide etchant (BOE), and Si3N4 is usually etched with phosphoric acid.

[0101] S9. As shown in Figures 11A and 11B, a gate dielectric layer 8 is deposited, including a first gate dielectric layer 8-1 located on the inner surface of the groove 3, a second gate dielectric layer 8-2 located on the upper surface of the second conductive type channel layer 4, and a third gate dielectric layer 8-3 located on the inner wall of the second conductive type channel layer etching window 14; Figure 11A shows the first gate dielectric layer 8-1 located on the inner surface of the groove 3 and the second gate dielectric layer 8-2 located on the upper surface of the second conductive type channel layer 4, and Figure 11B shows the first gate dielectric layer 8-1 located on the inner surface of the groove 3, the second gate dielectric layer 8-2 located on the upper surface of the second conductive type channel layer 4, and the third gate dielectric layer 8-3 located on the inner wall of the second conductive type channel layer etching window 14; the gate dielectric layer 8 does not fill the groove 3 during the deposition process. The gate dielectric layer 8 may be grown by thermal oxidation or by low pressure chemical vapor deposition (LPCVD). After the gate dielectric layer 8 is grown, an additional high temperature annealing treatment is performed.

[0102] S10. As shown in FIG12A and FIG12B , a gate electrode material is deposited and etched to form a first gate electrode 9-1, a second gate electrode 9-2 and a third gate electrode 9-3; the second gate electrode 9-2 covers a portion of the upper surface of the second gate dielectric layer 8-2, the first gate electrode 9-1 fills the trench 3 and is wrapped by the first gate dielectric layer 8-1, the third gate electrode 9-3 fills the second conductive type channel layer etching window 14 and is wrapped by the third gate dielectric layer 8-3, and the third gate electrode 9-3 connects the first gate electrode 9-1 and the second gate electrode 9-2; the first gate electrode 9-1 and the second gate electrode 9-2 can be seen from FIG12A , and the first gate electrode 9-1, the second gate electrode 9-2 and the third gate electrode can be seen from FIG12B Electrode 9-3; second gate electrode 9-2 covers a portion of the upper surface of the second gate dielectric layer 8-2. In this step, gate electrode material is first deposited entirely on the second gate dielectric layer 8-2. Gate electrode etching regions 12 are provided on both sides of the device surface formed at this time. The gate electrode material within the gate electrode etching regions 12 is etched to expose the second gate dielectric layer 8-2 on both sides. As shown in Figure 14, the distance between the gate electrode etching region 12 and the trench etching region 13 is L1. The distance L1 is not less than 0.1um, and optionally not less than 0.3um. L1 is also the distance between the boundary of the second gate electrode 9-2 and the boundary of the trench 3. The gate electrode 9 is made of doped polysilicon with a deposition thickness of 600nm to 800nm. The gate electrode 9 needs to be grown using a partially isotropic growth method to ensure that the trench 3 is completely filled without voids.

[0103] S11. As shown in Figures 13A and 13B, an isolation dielectric layer 10 is deposited to form a source ohm electrode 11, a drain ohm electrode, a source thickening metal, and a drain thickening metal. The isolation dielectric layer 10 covers the second gate electrode 9-2 and the second gate dielectric layer 8-2, and also covers a portion of the first conductivity type source region 5. The source ohm electrode 11 contacts a portion of the second conductivity type channel layer 4, a portion of the first conductivity type source region 5, and the second conductivity type heavily doped region 6, and contacts a portion of the sidewall of the isolation dielectric layer 10. The drain ohm electrode and the drain thickening metal are located on the lower surface of the first conductivity type SiC substrate, and the source thickening metal covers the isolation dielectric layer 10 and the source ohm electrode 11.

[0104] The present application adopts the method of depositing a sacrificial layer in an etched trench and removing the sacrificial layer before forming the gate dielectric to realize the production of upper and lower double-layer gate electrodes. Compared with the conventional vertical silicon carbide fin field-effect transistor (SiC FinFET), the present application adopts ALD thin film to control the thickness of the channel layer, avoiding the use of high-precision (50nm to 100nm) level vertical line width control, providing a production method compatible with the process in the related art for the design structure of the present application, and having high practical value.

[0105] Example 2

[0106] The transistor structure of Example 2 is similar to that of Example 1, except that the groove 3 is discontinuous in the y direction and is a periodically distributed rectangle, as shown in Figures 16 and 17. Figure 18 is a schematic diagram of the cross-sectional structure of the surround gate channel silicon carbide field effect transistor provided in Example 2 along the A-A' direction. The manufacturing process of the transistor of Example 2 is basically the same as that of Example 1, except that the groove 3 etched in the groove etching area 13 in S3 is discontinuous in the y direction and is a periodically distributed rectangle, as shown in Figure 16. Each groove etching area 13 covers an integer number of second conductive type channel layer etching windows 14. In this embodiment, each groove etching area 13 covers two second conductive type channel layer etching windows 14. The value ranges of the length L of the second conductive type channel layer etching window 14, the width W of the second conductive type channel layer etching window 14, the spacing W1 between adjacent second conductive type channel layer etching windows 14, and the spacing L1 between the gate electrode etching area 12 and the trench etching area 13 are the same as those in Example 1.

[0107] This embodiment sacrifices part of the surround gate channel in exchange for a vertical channel in part of the non-surround gate area, and can be used as an alternative to the first embodiment.

[0108] As shown in the middle of Figure 18, the second conductive type channel layer 4 is a non-surrounding gate area, but in addition to being affected by the upper gate electrode 9-2, this area is also affected by the gate electrodes 9-3 on the left and right sides, forming a channel extending in the vertical area, which has no effect on the overall device function.

[0109] From the overall content of this application and the above two embodiments, it can be seen that this application adopts a surround gate channel design, and uses upper and lower double-layer gate electrodes to realize gate-controlled conduction of the channel, which can obtain ultra-high channel mobility and greatly reduce the on-resistance of the device. Reference (Enhanced Performance of 50nm Ultra-Narrow-Body Silicon Carbide MOSFETs based on FinFET effect, DOI: 10.1109 / ISPSD46842.2020.9170182), the document discloses a MOSFET structure based on traditional trenches. When the channel width is controlled to be below 100nm, an ultra-high channel mobility can be obtained, but the channel region current in the traditional SiC trench MOSFET structure is longitudinally conducted, and the goal of narrowing the channel layer is achieved by narrowing the size of adjacent trenches. However, this structural process is extremely difficult, and extremely narrow line width control is required to achieve this structure. On the one hand, the characteristic size of SiC power devices is usually 0.5um to 1um, which can be met by using 0.35um or 0.18um lithography equipment, but the reference structure requires 45nm-level lithography, and considering the overlay deviation, the requirements may be higher; on the other hand, SiC itself is much more difficult to etch than Si materials, and it is difficult to control such a large aspect ratio etching process, which is not conducive to high-consistency mass production. In this application, based on the above-mentioned principle of realizing ultra-high channel mobility and based on the conventional planar SiC MOSFET structure, a breakthrough is adopted to adopt the upper and lower layer surround gate design. The channel current is changed from the original up and down flow to planar flow, and the demand for ultra-narrow channel is transformed into the structure of ultra-thin channel layer, which can be achieved by atomic layer deposition ALD, and the process difficulty is greatly reduced. The ultra-thin channel layer (<150nm) generated by ALD is the first major feature of this application. To achieve a structure with a channel sandwiched between upper and lower electrodes, and given the need for ultra-high-temperature carrier activation in SiC, a layer-by-layer deposition method of gate electrode-channel layer-gate electrode is not feasible. Therefore, this patent innovatively employs a process approach that first forms a suspended channel layer structure and then fills it with a gate dielectric and polysilicon gate electrode. This structure, in turn, requires the construction and removal of a sacrificial layer. Therefore, the etching window on the channel layer and the sacrificial layer-related processes are the second major feature of this application. Through the structural and process flow design of this application, ultra-high channel mobility can be achieved while simplifying process capability and process control requirements. This makes it suitable for large-scale product production, combining innovation and practicality, and has enormous development potential and practical prospects.

[0110] The beneficial effects of this application are as follows: (1) The design of a surround gate channel is adopted, and the gate-controlled conduction of the channel is realized by using upper and lower double-layer gate electrodes, which can obtain ultra-high channel mobility and greatly reduce the on-resistance of the device. (2) The atomic layer deposition (ALD) process is used to realize the production of an ultra-thin channel layer, which facilitates precise process control and has the ability to control the process for mass production. (3) The sacrificial layer is deposited in the etched trench and removed before the gate dielectric is fabricated, realizing the production of upper and lower double-layer gate electrodes, which has high practical value.

Claims

1. A gate-all-around channel silicon carbide field effect transistor, comprising: A first conductivity type silicon carbide SiC epitaxial layer; A second conductivity type well region is formed in the first conductivity type SiC epitaxial layer; A trench is formed in the first conductive type SiC epitaxial layer, the trench is adjacent to the second conductive type well region, and the first conductive type SiC epitaxial layer between adjacent trenches in the x direction is a device neck region; A second conductive type channel layer, wherein the second conductive type channel layer is located on the first conductive type SiC epitaxial layer, the second conductive type well region and the trench; a first conductivity type source region, the first conductivity type source region penetrating the second conductivity type channel layer and extending into the second conductivity type well region, and adjacent to the trench; A second conductive type channel layer etching window, wherein the second conductive type channel layer etching window penetrates the second conductive type channel layer and contacts the groove, and the second conductive type channel layer etching window is periodically distributed along the y direction on the second conductive type channel layer; A gate dielectric layer, comprising a first gate dielectric layer, a second gate dielectric layer and a third gate dielectric layer, wherein the first gate dielectric layer is located on the inner surface of the groove, the second gate dielectric layer is located on the upper surface of the second conductive type channel layer, and the third gate dielectric layer is located on the inner wall of the etching window of the second conductive type channel layer; A gate electrode, comprising a first gate electrode, a second gate electrode and a third gate electrode, wherein the first gate electrode fills the groove and is wrapped by the first gate dielectric layer, the second gate electrode covers a portion of the upper surface of the second gate dielectric layer, and the third gate electrode fills the etching window of the second conductive type channel layer and is wrapped by the third gate dielectric layer; an isolation dielectric layer, wherein the isolation dielectric layer covers the second gate electrode, the second gate dielectric layer and a portion of the first conductive type source region; A source ohm, the source ohm is connected to a portion of the second conductivity type channel layer and a portion of the first conductivity type source region; The x direction is the length direction of the transistor, and the y direction is the width direction of the transistor.

2. The transistor according to claim 1, wherein The grooves are continuous along the y direction, or are periodically distributed rectangles; The projection of the groove in the z direction completely covers the etching window of the second conductive type channel layer, the z direction is the height direction of the transistor, and the x, y, and z directions are perpendicular to each other; The depth of the groove along the z direction is greater than 0.5 um, and the width of the groove along the x direction is greater than 0.3um and less than 1.5um; the depth of the groove is shallower than the depth of the second conductive type well region, the distance between the bottom of the groove and the bottom of the second conductive type well region is greater than 0.2um, and the spacing between the boundary of the second gate electrode and the boundary of the groove is greater than 0.2um.

3. The transistor according to claim 1, wherein The second conductive type well region does not completely cover the trench, and a lateral boundary difference between the trench and an adjacent second conductive type well region in the x direction at a side close to the device neck region is less than 0.8 um.

4. The transistor according to claim 1, wherein: The thickness of the second conductive type channel layer does not exceed 120 nm.

5. The transistor according to claim 1, wherein The length of the second conductive type channel layer etching window in the x direction is not less than 1.0um, and the width in the y direction is not less than 0.8um; the spacing between adjacent second conductive type channel layer etching windows ranges from 1.5um to 2.0um; the distance between the second conductive type channel layer etching window and the boundary of the groove ranges from 0.1um to 1.0um.

6. The transistor according to claim 1, further comprising: The second conductivity type heavily doped region and the first conductivity type current extension region: The second conductivity type heavily doped region penetrates the second conductivity type channel layer, extends into the second conductivity type well region and is away from the trench; The first conductive type current extension region penetrates the second conductive type channel layer and extends into the first conductive type SiC epitaxial layer, and is located in the middle of the device neck region.

7. A method for manufacturing a surround-gate channel silicon carbide field effect transistor, comprising: forming a first conductivity type SiC epitaxial layer on a first conductivity type silicon carbide SiC substrate; Performing selective doping in the first conductive type SiC epitaxial layer to form a second conductive type well region; Etching the first conductive type SiC epitaxial layer to form a trench; forming a sacrificial layer in the trench; forming a second conductivity type channel layer on the first conductivity type SiC epitaxial layer, the second conductivity type well region and the trench; Performing selective doping to form a first conductivity type source region, wherein the first conductivity type source region penetrates the second conductivity type channel layer and extends into the second conductivity type well region and is adjacent to the trench; Etching the second conductive type channel layer to form second conductive type channel layer etching windows, wherein the second conductive type channel layer etching windows are periodically distributed along the y direction on the second conductive type channel layer, and the second conductive type channel layer etching windows penetrate the second conductive type channel layer and stop on the sacrificial layer; removing the sacrificial layer; Growing a gate dielectric layer, including a first gate dielectric layer located on the inner surface of the groove, a second gate dielectric layer located on the upper surface of the second conductive type channel layer, and a third gate dielectric layer located on the inner wall of the etching window of the second conductive type channel layer; Growing and etching a gate electrode material to form a gate electrode, including a first gate electrode filling the trench, a second gate electrode covering a portion of the upper surface of the second gate dielectric layer, and a third gate electrode filling the etching window of the second conductive type channel layer and wrapped by the third gate dielectric layer; An isolation dielectric layer is grown to form a source ohmic layer, a drain ohmic layer, a source thickened metal layer and a drain thickened metal layer.

8. The method according to claim 7, wherein: The sacrificial layer is made of carbon film or dielectric; In the case where the sacrificial layer is a carbon film, the method for forming the sacrificial layer in the groove includes photoresist coating, carbonization and surface planarization processes, and the removal of the sacrificial layer includes removing the sacrificial layer by high-temperature thermal oxidation, and the oxidation temperature does not exceed 1150 degrees Celsius; In the case that the sacrificial layer is made of a dielectric, removing the sacrificial layer includes removing the sacrificial layer by wet etching.

9. The method according to claim 7, wherein: The deposition thickness of the second conductive type channel layer is in the range of 10 nm to 250 nm.

10. The method according to claim 9, wherein: When the gate dielectric layer is formed by thermal oxidation, the deposition thickness of the second conductive type channel layer is 80 nm to 250 nm; When the gate dielectric layer is formed by deposition, the deposition thickness of the second conductive type channel layer is 10 nm to 120 nm.

11. The method according to claim 7, wherein: The etching of the second conductive type channel layer to form a second conductive type channel layer etching window comprises: The location of the groove is defined as a groove etching area, and the projection of the groove etching area is mapped onto the second conductive type channel layer to form at least one second conductive type channel layer etching window, and the length of each second conductive type channel layer etching window in the x direction is not less than 1.0um, and the width in the y direction is not less than 0.8um; the spacing between adjacent second conductive type channel layer etching windows ranges from 1.5um to 2.0um; the distance between each second conductive type channel layer etching window and the boundary of the groove etching area ranges from 0.1um to 1.0um.

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