Chip packaging structure and chip packaging method, chip, and mask assembly

Abstract

A chip packaging structure and a chip packaging method, a chip, and a mask assembly. The packaging method comprises: configuring a bonding layer (20) on one side of a substrate (10); placing dies (30) on the side of the bonding layer (20) away from the substrate (10) according to preset positions; preparing a packaging positioning layer (40), wherein the packaging positioning layer (40) is filled in gaps between the dies (30); and coating a plastic packaging material on the side of the packaging positioning layer (40) away from the substrate (10), and curing same to obtain a packaging layer (60). The packaging layer (60) is located on the side of the packaging positioning layer (40) away from the bonding layer (20); and a redistribution layer (70) and pins (80) are formed on the side of the dies (30) away from the packaging layer (60). The packaging method fixes the dies (30) by means of stacking the packaging positioning layer (40) on the bonding layer (20). The packaging positioning layer (40) has a certain strength and also has a supporting and fixing function, and can effectively eliminate stress generated by EMC in subsequent processes and ameliorate the defects of the shifting of the dies (30).

Description

Chip packaging structure and chip packaging method, chip, and mask assembly

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 202310953086.9, filed on July 31, 2023, entitled “A mask plate assembly, packaging structure and packaging method”, the entire contents of which are incorporated herein by reference.

[0003] This application claims priority to Chinese patent application 202311765649.8, filed on December 20, 2023, entitled “A chip packaging structure and chip packaging method, chip, and mask assembly,” and the entire contents of that application are incorporated herein by reference. Technical Field

[0004] The present disclosure relates to the field of packaging technology, and in particular to a chip packaging structure and a chip packaging method, a chip, and a mask assembly. Background Art

[0005] Dies are semiconductor electronic components with small size, high brightness, and low energy consumption, making them widely used in lighting and other fields. However, in existing die manufacturing processes, die position shifts during packaging, increasing the difficulty of subsequent process steps.

[0006] Summary of the Invention

[0007] In view of this, the purpose of the present disclosure is to provide a chip packaging structure and chip packaging method, a chip, and a mask assembly. The packaging structure can reduce the phenomenon of die offset in the chip.

[0008] Based on the above objectives, the present disclosure discloses a chip packaging structure, which includes:

[0009] Multiple grains;

[0010] A packaging positioning layer is at least partially formed between adjacent dies and has a hollow portion formed corresponding to the dies, wherein the dies are sleeved in the hollow portion;

[0011] An encapsulation layer is provided on the encapsulation positioning layer, wherein the rigidity of the encapsulation layer is smaller than that of the encapsulation positioning layer;

[0012] a redistribution layer, located on a side of the package positioning layer away from the package layer, wherein a signal line is provided in the redistribution layer, and the die is electrically connected to the signal line;

[0013] A plurality of pins are arranged on a side of the redistribution layer away from the die and are electrically connected to the signal lines in the redistribution layer.

[0014] Through such a structural design, the package positioning layer can effectively fix the position of the die, eliminating the influence of stress release on the die position in the EMC process; it can also serve as a dense connection layer between the die and the package layer; the package positioning layer has a mesh structure, which surrounds the die and provides support for it.

[0015] In one embodiment, the packaging positioning layer includes at least one organic film layer and at least one inorganic film layer stacked together, and the thickness of the packaging positioning layer is greater than or equal to 3 μm;

[0016] Preferably, the encapsulation positioning layer includes an organic film layer and an inorganic film layer, the organic film layer is located between the encapsulation layer and the inorganic film layer, and the thickness of the organic film layer is greater than or equal to 10% of the height of the grain thickness and less than or equal to 50% of the height of the grain;

[0017] Preferably, the thickness of the organic film layer is greater than or equal to 12 μm;

[0018] Further preferably, the density of the organic film layer on the side away from the encapsulation layer is less than 0.5 g / cm3;

[0019] Alternatively, the packaging positioning layer includes two inorganic film layers and one organic film layer, and the packaging positioning layer is composed of inorganic film layers on both sides of the chip thickness direction, and the lower surface of the inorganic film layer close to the packaging layer among the two or more inorganic film layers is less than or equal to 50% of the height of the grain.

[0020] The stacked organic and inorganic film layers can fix the position of the grains while increasing the connection density between the organic film layer and the packaging layer. It can also prevent water and oxygen from entering the chip packaging structure through the organic film layer, thereby extending the service life of the device.

[0021] In one embodiment, the thickness of the package positioning layer is greater than or equal to 2 μm and less than the height of the die. Preferably, the thickness of the package positioning layer is greater than or equal to 2.5 μm and less than 50% of the height of the die. Preferably, the thickness of the package positioning layer is greater than or equal to 3 μm and less than 30% of the height of the die. This design ensures that the package positioning layer has a certain degree of rigidity while reliably connecting to the EMC material. If the thickness is too small, the rigidity is weak and the fixing effect is limited.

[0022] In one embodiment, the thermal expansion coefficient of the package positioning layer is less than that of the packaging layer. The material of the package positioning layer includes one or more of inorganic materials, organic materials, and composite materials. Preferably, the inorganic material includes one or more of metal materials, ceramic materials, carbon-based materials, and oxide materials, and the organic material includes a polymer material. Further preferably, the inorganic material is an amorphous material. Using a material with a lower thermal expansion coefficient for the package positioning layer can reduce the risk of film deformation and shrinkage stress at different temperatures, thereby firmly securing the grains.

[0023] In one embodiment, the metal material includes one or more of gold nanoparticles (AuNPs), silver nanoparticles (AgNPs), and copper nanoparticles (CuNPs). The oxide material includes at least one of aluminum oxide (Al2O3), zinc oxide (ZnO), titanium dioxide (TiO2), hafnium dioxide (HfO2), zirconium dioxide (ZrO2), and tantalum pentoxide (Ta2O5). The amorphous material includes at least one of amorphous silicon (a-Si), silicon oxide (SiOx), silicon nitride (SiNx), indium tin oxide (ITO), and indium gallium zinc oxide (IGZO). The carbon-based material includes one or more of carbon nanotubes (CNTs), graphene, and carbon black (CB). The polymer material includes one or more of polyvinyl alcohol (PVA), polydimethylsiloxane (PDMS), polyacrylonitrile (PAN), polyethylene terephthalate (PET), PMMA, and polyimide (PI). The composite material includes one or more of AgNWs / PEO, styrene-ethylene-butylene-styrene (SEBS) / TiO2 and poly(melamine-co-formaldehyde) (PMF) / PVA.

[0024] Based on the same concept, the present disclosure provides a mask assembly for chip packaging, which includes:

[0025] A mask plate, wherein the mask plate includes a plurality of shielding members and a plurality of connecting members, wherein the connecting members connect the shielding members, and the plurality of shielding members and the plurality of connecting members enclose a plurality of hollow areas;

[0026] The plurality of connecting members form a mesh, and one edge of each shielding member corresponds to two or more connecting members.

[0027] Based on the same inventive concept, the present disclosure provides a chip packaging method, comprising the following steps:

[0028] S10, configuring a bonding layer on one side of the substrate;

[0029] S20, placing the die at a preset position on the bonding layer away from the substrate;

[0030] S30, preparing a packaging positioning layer, wherein the packaging positioning layer fills the gaps (also called grooves) between the grains to fix the grains;

[0031] S40, coating a plastic encapsulation material on the side of the encapsulation positioning layer away from the substrate, and curing the material to obtain an encapsulation layer.

[0032] S50, removing the substrate and the bonding layer;

[0033] S60 , forming a redistribution layer on the packaging positioning layer and the side of the die away from the packaging layer through a redistribution process; and arranging pins on the redistribution layer.

[0034] This packaging method incorporates a positioning layer between the die. This layer provides a certain degree of rigidity, providing both support and fixation. This layer effectively eliminates stress caused by EMC during subsequent processes, such as after substrate separation, and mitigates die offset defects.

[0035] In one embodiment, the step S30 includes using an inkjet printing device to fill the gaps between the grains with a filling material to obtain the packaging positioning layer; or

[0036] The step S30 also includes: setting a mask on the grain, the shielding parts of the mask correspond to the grains, the hollow parts of the mask correspond to the gaps between the grains, and filling the filling material from the hollow parts into the gaps between the grains to obtain the packaging positioning layer.

[0037] In one embodiment, before step S30 or before step S20, the method includes: forming an inhibition layer on top of the grains, filling a filling material into the gaps between the grains from a side of the grains away from the substrate to form the packaging positioning layer, and removing the inhibition layer after forming the packaging positioning layer;

[0038] Preferably, the inhibition layer is formed before cutting the mother board to form the die;

[0039] Preferably, the inhibition layer comprises an organic polymer, and the organic polymer includes at least one of polymethyl methacrylate (PMMA) and polyvinyl pyrrolidone (PVP).

[0040] In one embodiment, the filling material includes one or more of an inorganic material, an organic material, and a composite material;

[0041] Preferably, the step S30 includes: filling the gap with the organic material, filling the gap with the inorganic material after the organic material is solidified, and obtaining a packaging positioning layer formed by stacking the organic film layer and the inorganic film layer after the inorganic material is solidified;

[0042] Further preferably, the organic material includes a polymer material, and the polymer material includes a cross-linking agent; the step S30 includes: modifying the polymer material by adjusting the atomic ratio between the functional groups in the cross-linking agent or adding a cross-linking agent containing a carbonyl functional group or a hydroxyl functional group to the polymer material, and filling the modified polymer material into the gap.

[0043] In one embodiment, step S40 includes: coating a packaging material on the packaging positioning layer, the packaging material covering the die and a side of the packaging positioning layer away from the bonding layer, and curing the packaging material to form the packaging layer;

[0044] Preferably, the packaging material comprises epoxy film plastic.

[0045] Preferably, the step S30 includes preparing the package positioning layer by multiple coating processes. Further preferably, the step S30 includes preparing the package positioning layer by forward and reverse coating processes;

[0046] Step S50 includes: separating the substrate and the bonding layer from the package positioning layer and the die through a stripping process; preferably, step S50 includes removing the substrate and the bonding layer through laser stripping or wet stripping.

[0047] The present disclosure discloses a chip formed by dividing the above chip packaging structure; or, formed by dividing the chip packaging structure obtained by the above method.

[0048] Compared to the prior art, the chip packaging method provided by the present disclosure stacks a packaging positioning layer with a certain degree of rigidity on the bonding layer. The packaging positioning layer fills the gaps between the grains to fix the grains. Preferably, the thickness of the packaging positioning layer is less than the height of the grains. The packaging positioning layer provides rigid support for the grains and fixes the positions of the corresponding grains. After removing the substrate, the packaging positioning layer eliminates the stress caused by EMC and improves the grain offset defect. The thickness of the packaging positioning layer is less than the height of the grains. After stacking the packaging layers, the packaging layer covers the gaps and grooves between the multiple grains, achieving a reliable connection. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the present disclosure or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are only embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0050] FIG1 is a schematic cross-sectional view of a conventional chip packaging structure.

[0051] FIG2 is a schematic flow chart of a chip packaging method according to an embodiment of the present disclosure.

[0052] FIG3 is a cross-sectional schematic diagram of a bonding layer structure stacked on one side of a substrate provided by an embodiment of the present disclosure.

[0053] FIG4 is a cross-sectional schematic diagram of placing a die on a bonding layer structure provided by an embodiment of the present disclosure.

[0054] FIG5 is a cross-sectional schematic diagram of a packaging positioning layer structure for preparing a mesh structure provided by an embodiment of the present disclosure.

[0055] FIG6 is a cross-sectional schematic diagram of a structure for preparing an inhibition layer provided by an embodiment of the present disclosure.

[0056] FIG7 is a cross-sectional schematic diagram of a packaging positioning layer structure prepared by using an inhibition layer according to an embodiment of the present disclosure.

[0057] FIG8 is a cross-sectional schematic diagram of a package positioning layer stacked on a package layer according to an embodiment of the present disclosure.

[0058] FIG9 is a cross-sectional schematic diagram of a structure in which a substrate and a bonding layer are removed, provided in one embodiment of the present disclosure.

[0059] FIG10 is a schematic cross-sectional view of a chip packaging structure provided by an embodiment of the present disclosure.

[0060] FIG11 is a schematic cross-sectional view of a packaging positioning layer having a double-layer structure provided by an embodiment of the present disclosure.

[0061] FIG12 is a schematic cross-sectional view of a package positioning layer having a multi-layer structure provided by an embodiment of the present disclosure.

[0062] FIG13 is a schematic structural diagram of a mask provided in an embodiment of the present disclosure.

[0063] FIG14 is a schematic diagram showing the force applied to a chip according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0064] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0065] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the usual meanings understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative position relationships. When the absolute position of the described object changes, the relative position relationship may also change accordingly.

[0066] In existing chip packaging processes, there is a stress mismatch between the packaging material and the die (Die: refers to the bare chip / bare die / die. The die is cut from the wafer and includes a complete single die and the portion of the scribe groove area adjacent to the die in the horizontal and vertical directions). This causes the die to shift in position and leads to abnormal connections between the die pad and internal circuits. Referring to Figure 1, packaging material 1 and die 2 are cured and separated from the substrate after the packaging process. After the substrate is separated, stress shrinkage causes the placed die array to shift in position, causing die 2 to shift in position. This will cause abnormal connections between the die 2 pad and the internal circuits in subsequent processes, and will also increase the process difficulty (such as pattern deviation) of the subsequent redistribution layer (RDL) process.

[0067] To this end, the applicant has improved the existing packaging solution and proposed a chip packaging structure, which can improve die packaging and reduce the phenomenon of deviation after substrate separation.

[0068] Next, the chip packaging structure and chip packaging method proposed in the present disclosure will be described with reference to the accompanying drawings.

[0069] FIG8 and FIG10 are cross-sectional schematic diagrams of the chip packaging structure proposed in the present disclosure.

[0070] The chip packaging structure includes:

[0071] Multiple dies 30. Dies are made of silicon-based materials and are tiny structures on a wafer. They are the basic units of semiconductor chips. Wafers are silicon chips, and semiconductor chips (i.e., integrated circuits) are manufactured by creating many circuits on wafers. Therefore, wafers are the foundation of semiconductors, and dies are the foundation of wafers.

[0072] The packaging positioning layer 40 has a hollow portion corresponding to the die 30. The die 30 is sleeved in the hollow portion and fixed by the hollow portion.

[0073] The encapsulation layer 60 is stacked on the encapsulation positioning layer 40 and covers the plurality of dies 30 and the gaps between the dies 30. Specifically, the chip encapsulation structure uses epoxy molding compound (EMC) to cover and mold all the dies 30 over a large area, thereby forming an encapsulation layer 60 that protects the dies 30. The rigidity of the encapsulation layer 60 is less than that of the encapsulation positioning layer 40.

[0074] A redistribution layer 70 is disposed on the side of the package positioning layer 40 facing away from the package layer 60, and the die 30 is electrically connected to this redistribution layer 70. Specifically, the redistribution layer 70 includes signal lines 71 and an insulating film 72. The signal lines 71 are disposed within the insulating film 72. The die 30 is disposed on a surface of the insulating film 72 facing the package positioning layer 40 and is connected to the signal lines 71 exposed on this surface. Specifically, the redistribution layer 70 is used to re-route the original circuit wiring, thereby optimizing circuit routing and signal transmission to improve circuit performance and meet requirements.

[0075] A plurality of pins 80 are disposed on a surface of the redistribution layer 70 facing away from the die 30 and electrically connected to the signal lines 71 in the redistribution layer 70. Pins 80 may be solder balls, typically made of tin with varying proportions of silver and / or copper. Pins 80 serve as pin terminals of the resulting chip package structure and can be soldered to other components, such as a printed circuit board (PCB), thereby interconnecting the die 30, which is electrically connected to the redistribution layer 70, with the outside world via the pins 80.

[0076] In this embodiment, the encapsulation positioning layer 40 has a mesh structure, and its hollow portion is arranged around the die 30 to achieve rigid support for the die 30 and fix the position of each die 30. During implementation, the encapsulation positioning layer 40 fills the gap between two adjacent die 30 to provide effective rigid support for the die 30. It should be noted that the substrate 10 and the bonding layer 20 must be removed before the rewiring process, and there is no substrate 10 and bonding layer 20 in the finished product structure (see Figure 10). Such a large-area EMC will have shrinkage stress after the substrate 10 is peeled off. The encapsulation positioning layer 40 provides rigid support for the die (Die) to eliminate the shrinkage stress caused by the encapsulation layer 60 (EMC) after the substrate 10 is separated, thereby improving the defect of positional displacement of the die 30. In addition, the encapsulation positioning layer 40 can also serve as a dense connection layer between the die 30 and the encapsulation layer 60 after the EMC is cured, thereby improving the reliability of the connection between the die 30 and the encapsulation layer 60. In one embodiment of the present embodiment, the chip packaging structure can be operated using a panel level package (PLP) process. The substrate 10 (also called a carrier plate) can be made of glass, metal and high molecular polymer materials. In addition to achieving the effect of wafer level package (WLP), its efficiency is greatly improved compared to the existing wafer level package, which can effectively reduce the packaging cost. The package positioning layer 40 can be prepared by deposition (such as thin film deposition, ALD deposition) or printing (such as inkjet printing / electronic inkjet printing). The package positioning layer 40 plays the role of connecting, supporting and fixing the grains 30. In other embodiments, the material of the package positioning layer 40 includes one or more of an inorganic material, an organic material and a composite material. Furthermore, the inorganic material can be one or more of a metal material, a ceramic material, a carbon-based material and an oxide material, and the organic material can be a polymer material. Optionally, the inorganic material is an amorphous material, and the amorphous material includes at least one of amorphous silicon (a-Si), silicon oxide (SiOx), silicon nitride (SiNx), indium tin oxide (ITO), and indium gallium zinc oxide (IGZO). Preferably, the packaging positioning layer 40 is made of amorphous silicon, silicon oxide, silicon nitride, or a combination thereof. Such materials have a higher degree of match with the crystal grains 30 (the crystal grains themselves are silicon-based materials) and a better fixing effect. The packaging positioning layer can be a single film layer, or it can be composed of multiple layers of films of different materials stacked together (for example, a stack of organic film layers and inorganic film layers).

[0077] The thickness of the packaging positioning layer 40 is greater than or equal to 2μm and is less than the height of the grain. Optionally, the thickness of the packaging positioning layer 40 is less than the height of the grain 30 (in this case, when the subsequent packaging layer 60 is encapsulated, part of the epoxy molding compound fills the gap between the grains 30, that is, it acts as a dense connection between the grain 30 and the EMC-cured packaging layer 60, thereby improving the reliability of the bonding). Preferably, the thickness of the packaging positioning layer 40 is greater than or equal to 12μm. In this embodiment, the height of the grain 30 is generally greater than 70μm (for example, the height of the grain 30 is selected to be about 100μm).

[0078] In other embodiments, the thickness of the package positioning layer 40 may also be greater than the height of the die. In this case, the die 30 is equivalent to being embedded in the package positioning layer 40 .

[0079] In this embodiment, the encapsulation layer 60 is obtained by encapsulating and curing epoxy molding compound (EMC).

[0080] Based on the same inventive concept, the present disclosure also provides a packaging method for the above chip packaging structure.

[0081] As shown in FIG2 , the packaging method includes the following steps:

[0082] S10, laminating a bonding layer on one side of the substrate.

[0083] In this step, the substrate 10 is used as a carrier plate to apply the bonding layer 20 (see Figure 3). The substrate can be selected from glass, metal or high molecular polymer materials. The size of the substrate can be 320*400 (mm), 370*470 (mm), 550*650 (mm), 680*880 (mm), 730*920 (mm) or 1100*1300 (mm) of a conventional panel generation line, or it can be any size obtained by cutting the panel generation line. The bonding layer 20 is also called a temporary bonding layer, through which the grains 30 are temporarily bonded to a rigid carrier to obtain support. The bonding layer 20 can be applied to the substrate 10 by spin coating using a spin coater, and can be removed later by laser, cleaning, etc.

[0084] S20, placing a plurality of dies 30 at a predetermined position of the bonding layer 20 away from the substrate 10.

[0085] In this step, a plurality of crystal grains 30 are attached to one side of the bonding layer 20 away from the substrate 10 (see FIG4 for a cross-sectional view). The crystal grains 30 are placed on the bonding layer 20 in an array or other preset positions. During placement, the crystal grains 30 can be regularly placed on the bonding layer 20 through a pick-up assembly process. Alternatively, laser transfer technology (also known as mass transfer technology) can be used to transfer the crystal grains 30 one by one to predetermined positions on the bonding layer 20 using a specially shaped light spot (such as a square) in combination with high-speed galvanometer scanning. In this way, the crystal grains 30 are temporarily fixed on the bonding layer 20 and supported by the substrate 10.

[0086] S30 , preparing a package positioning layer 40 , wherein the package positioning layer 40 fills the gaps between the dies 30 to fix the dies 30 .

[0087] The thickness of the packaging positioning layer 40 may be less than the height of the grain 30. The packaging positioning layer 40 is used to fix each corresponding grain 30 to improve the stress strain resistance (contraction stress) of the grain 30 and reduce the phenomenon of grain offset (Die Shift). In this step, a dense packaging positioning layer 40 with a certain thickness is formed between the grains 30. The thickness of the packaging positioning layer 40 is greater than or equal to 2μm and is less than the height of the grain (if the thickness of the packaging positioning layer 40 is too small, its rigidity is small and its fixing effect is limited). Optionally, the thickness of the packaging positioning layer 40 is greater than or equal to 2.5μm and is less than half the height of the grain 30; in some embodiments, the thickness of the packaging positioning layer 40 is greater than or equal to 3μm and less than one-third the height of the grain 30. Preferably, the thickness of the packaging positioning layer 40 is greater than or equal to 12μm.

[0088] In one embodiment, the encapsulation positioning layer 40 is obtained by printing, such as using an inkjet printer (e.g., an electronic inkjet printer) to inkjet print a filler material (e.g., an organic material) into the gaps between the dies 30. After curing, the encapsulation positioning layer 40 is obtained. The thickness of the encapsulation positioning layer 40 is greater than or equal to 12 μm. In this embodiment, no mask is required. The filler material is directly sprayed using the electronic inkjet printer (during spraying, the material may fall on the top of the dies. Because the filler material is fluid before curing, the filler material that falls on the top of the dies will flow into the gaps between the dies 30). The fluidity of the filler material is used to fill the gaps between the dies 30. After curing, the filler material surrounds the dies 30 and effectively fixes them in place, eliminating the effect of stress release from the encapsulation layer 60 on the position of the dies 30 during subsequent processing. When selecting the filler material, a material that matches the stress of the dies 30 is selected to precisely fill the gaps between the dies 30. Preferably, the thermal expansion coefficient of the filling material selected for the packaging positioning layer 40 is greater than or equal to 0 and is less than the thermal expansion coefficient of the packaging layer 60 (i.e., the thermal expansion coefficient of the EMC). Optionally, the thermal expansion coefficient of the filling material is equal to 0, that is, the packaging positioning layer 40 prepared by the filling material will not deform under temperature changes, and will not generate shrinkage stress, and can firmly fix the grains 30. Furthermore, the filling material includes one or more of metal materials, ceramic materials, carbon-based materials, polymer materials and composite materials. After filling, the solvent in the filling material is evaporated through a curing process, and the solute in the filling material is precipitated in the gaps between the grains to form the packaging positioning layer 40.

[0089] Furthermore, the metal material includes one or more of gold nanoparticles (AuNPs), silver nanoparticles (AgNPs) and copper nanoparticles (CuNPs).

[0090] The ceramic material includes nano-scale ultrafine inorganic materials, and the ultrafine inorganic materials can be prepared by nano-scale processes such as deposition process, hydrothermal process or solvent-gel process.

[0091] The carbon-based material includes one or more of carbon nanotubes (CNTs), graphene, and carbon black (CB).

[0092] The polymer material includes one or more of polyvinyl alcohol (PVA), polydimethylsiloxane (PDMS), polyacrylonitrile (PAN), polyethylene terephthalate (PET), PMMA, and polyimide materials.

[0093] The composite material comprises one or more of AgNWs / PEO, styrene-ethylene-butylene-styrene (SEBS) / TiO2 and poly(melamine-co-formaldehyde) (PMF) / PVA.

[0094] In one embodiment, the packaging positioning layer 40 may include an organic film layer made of an organic material obtained by the above-mentioned printing method, and a layer of inorganic material is deposited on the organic film layer by deposition to form an inorganic film layer. In this case, the packaging positioning layer 40 includes a stacked organic film layer 41 and an inorganic film layer 42 (refer to the chip packaging structure shown in Figure 11). The organic film layer 41 is used to fix the position of the die 30 and prevent the die 30 from shifting during subsequent processes. The inorganic film layer 42 is located between the organic film layer 41 and the encapsulation layer 60. The inorganic film layer 42 serves as a connecting layer connecting the organic film layer 41 and the encapsulation layer 60, thereby improving the connection reliability between the packaging positioning layer 40 and the encapsulation layer 60. The thickness of the organic film layer 41 is greater than or equal to 10% of the height of the die 30 and less than or equal to 50% of the height of the die 30. Optionally, the thickness of the organic film layer 41 is greater than or equal to 12μm. The desired thickness of the organic film layer 41 can be achieved by spraying and stacking the organic material multiple times. In some embodiments, the density of the organic film layer 41 at a side away from the encapsulation layer 60 is less than 0.5 g / cm 3 .

[0095] As an extension of the above embodiment, in other embodiments of the present invention, the packaging positioning layer 40 may further include two inorganic film layers 42 and one organic film layer 41 (referring to the chip packaging structure shown in FIG12 ). The packaging positioning layer 40 is provided with inorganic film layers 43 on both sides of the chip thickness direction, and the organic film layer 41 is provided between two adjacent inorganic film layers 42. The lower surface of the inorganic film layer 42 closer to the packaging layer 60 (i.e., the surface of the inorganic film layer 42 closer to the packaging layer 60 away from the packaging layer 60) is less than or equal to 50% of the height of the grain 30 from the lower surface of the grain 30 (i.e., the surface of the grain 30 away from the packaging layer 60). Because the organic film layer 41 is loose and porous and lacks any ability to block water and oxygen, external water and oxygen can easily penetrate through the organic film layer 41 into the interior of the grain packaging structure. Therefore, an inorganic film layer 42 is also provided on a layer of the organic film layer 41 away from the encapsulation layer to prevent external water and oxygen from continuing to invade the interior of the grain encapsulation structure after passing through the organic film layer 41, thereby enhancing the water and oxygen barrier performance and improving the service life of the grain encapsulation structure.

[0096] In one embodiment, in step S30, the packaging positioning layer 40 is obtained by deposition. Specifically, a mask is first set on the 30 grains, the shielding parts of the mask correspond to the grains 30, and the hollow parts of the mask correspond to the gaps between the grains 30. The gaps between the grains 30 are filled with a filling material through a deposition process to obtain the packaging positioning layer. In some embodiments, the deposition process adopts one of plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD) or physical vapor deposition (PVD). Furthermore, inorganic films containing materials such as amorphous silicon, silicon oxide, and silicon nitride can be prepared by plasma chemical vapor deposition; or inorganic films containing oxide materials can be prepared by atomic layer deposition (ALD), wherein the oxide material is selected from at least one of aluminum oxide (Al2O3), zinc oxide (ZnO), titanium dioxide (TiO2), hafnium dioxide (HfO2), zirconium dioxide (ZrO2), and tantalum pentoxide (Ta2O5); or metal films and amorphous films (such as ITO and IGZO) can be prepared by physical vapor deposition (PVD). In this embodiment, the height of the grain 30 can be understood as the height of the grain 30 perpendicular to the substrate (sometimes also referred to as thickness). Preferably, the packaging positioning layer 40 is obtained by deposition, and the thickness of the packaging positioning layer 40 is greater than or equal to 3μm and less than the height of the grain. A mask 100 is matched during deposition (see Figure 5). The mask can be a metal mask. To this end, the present disclosure also discloses a mask assembly, see FIG13 , which includes a mask 100, wherein the mask 100 includes a plurality of shielding members 110 and a plurality of connecting members 140, wherein the connecting members 140 connect the shielding members 110, and the plurality of shielding members 110 and the plurality of connecting members 140 enclose a plurality of hollow areas 120, wherein the shielding members 110 and the hollow areas 120 are arranged according to a preset pattern. Among them, each shielding member 110 has two or more connecting members 140 corresponding to one edge. While ensuring the overall strength of the mask 100, the more connecting members there are, the smaller their width can be, and the smaller the impact on the package positioning layer when forming the package positioning layer. The mask is matched with a frame 130, and the frame 130 is used to support the mask.

[0097] When depositing the packaging positioning layer 40, the shielding members 110 of the mask 100 correspond to the dies 30 (to cover the dies 30), and the hollow regions 120 correspond to the gaps between the dies 30. That is, based on the array pattern of the dies 30 on the substrate, a metal mask having a certain hollow shape is formed, and filler material can be deposited only within the orthographic projection area of ​​the hollow regions 120 on the substrate 10, thereby forming a mesh-like packaging positioning layer 40. The hollow regions 120 can be a fully hollow structure or a patterned hollow structure, such as the hollow regions 120 including an array of holes, the holes being circular, elliptical, geometrically polygonal, or a combination thereof. The mask 100 can be pattern-customized based on the array pattern of the dies 30 on the substrate 10, forming hollow regions 120 for depositing filler material in the gaps between the dies 30 and shielding members 110 for covering the dies 30, thereby achieving customization of the packaging positioning layer 40 to accommodate different dies structures in the packaging process.

[0098] In one embodiment, as a variation of step S30, the package positioning layer can be formed by atomic layer deposition. This embodiment does not require a metal mask or a metal frame, resulting in a denser connection between the package layers and lowering costs.

[0099] As a variation of the above embodiment, before preparing the packaging positioning layer 40 or before transferring the die 30 to the bonding layer 20, an inhibition layer 200 can be pre-set / coated on the top of the die 30, see Figures 6 and 7. For example, the inhibition layer 200 is formed on the top of the die 30 by an electronic inkjet printing process, and the inhibition layer is removed after the packaging positioning layer 40 is prepared by an atomic layer deposition process. The inhibition layer 200 contains an organic polymer, which can be polymethyl methacrylate (PMMA) and polyvinyl pyrrolidone (PVP). Its function is to lack the surface functional groups required for atomic layer deposition nucleation and growth on the polymer surface, and oxide materials such as aluminum oxide, zinc oxide, titanium dioxide, hafnium dioxide, zirconium dioxide and tantalum pentoxide cannot form a film on its surface. In this embodiment, there is no need for a mask, no metal frame blocking, and the packaging layer 60 is more densely connected, which is also conducive to reducing costs. Optionally, the inhibition layer 200 can be prepared on the grain 30 before cutting the grain motherboard to form the grain 30, and cut together with the cutting process of the grain 30, which can prevent the inhibition layer material from falling into the gap between the grains 30. At the same time, it can further reduce a mask (the mask used to pattern the inhibition layer), thereby further reducing production costs.

[0100] In step 30, the encapsulation positioning layer 40 can be prepared by applying the filler material in a single coating or multiple coatings and then curing the filler material to form the encapsulation positioning layer 40. When multiple coatings are used, coating in a forward direction (e.g., from left to right) and in a reverse direction (e.g., from right to left) can be performed alternately. Multiple coatings and alternating forward and reverse coatings can achieve balanced stress within the encapsulation positioning layer 40.

[0101] S40, coating the packaging material on the packaging positioning layer 40, and curing to obtain the packaging layer 60.

[0102] In this step, a layer of encapsulation material is applied to the encapsulation positioning layer 40 by a single coating, multiple coatings, or both forward and reverse coatings. This encapsulation material covers the die 30 and the side of the encapsulation positioning layer 40 away from the bonding layer 20 (see FIG8 ). The encapsulation material is then cured to form an encapsulation layer 60 . Preferably, the encapsulation material includes EMC. The thickness of the encapsulation layer 60 in this step is between 200 and 500 μm.

[0103] S50, removing the substrate 10 and the bonding layer 20.

[0104] Referring to FIG9 , in this step, the substrate 10 and bonding layer 20 can be directly removed by laser stripping or wet stripping, or the substrate 10 can be laser stripped and then the bonding layer 20 can be removed by cleaning. The specific implementation is not limited, as long as it satisfies the need to remove the substrate 10 and bonding layer 20.

[0105] S60 , forming a redistribution layer 70 and pins 80 through a redistribution process.

[0106] A redistribution layer (RDL) 70 is formed on the side of the die 30 and the package positioning layer 40 away from the package layer 60 through a redistribution process. Pre-ground pins 80 are fixed to the surface of the redistribution layer 70 away from the die 30 through a hot pressing or welding process, thereby forming the chip package structure shown in Figure 10. The redistribution layer 70 includes signal lines 71 and an insulating film 72. The signal lines 71 are used to re-arrange the connection relationship between the original circuits, the insulating film 72 is used to insulate and protect the signal lines 71, and the pins 80 are used to interconnect with external circuits.

[0107] The packaging method disclosed herein eliminates the stress caused by the EMC material properties in the packaging layer 60 after separation from the substrate 10 through the prepared packaging positioning layer 40. The coefficient of thermal expansion (CTE) of EMC is greater than that of silicon, and during cooling, the EMC shrinks more than the silicon grains 30. Referring to Figure 14 , the CTE of EMC is 10-70×10-6 / K, while the CTE of silicon is 2.4×10-6 / K. The shrinkage stress F1 of the EMC is 1. Rigid materials such as metals and ceramics can effectively offset the shrinkage stress F1 from the EMC, thereby eliminating the die shift phenomenon caused by the shrinkage of the packaging layer 60. For elastic polymer materials, their thermal expansion coefficient can be reduced by cross-linking agent modification. For example, by adjusting the atomic ratio between the functional groups in the original cross-linking agent in the polymer material or adding a cross-linking agent containing carbonyl or hydroxyl functional groups to the polymer material to increase the carbonyl or hydroxyl content in the polymer material, the thermal expansion coefficient can reach 10-6 / K or even 10-7 / K. The use of such low CTE (coefficient of thermal expansion) materials can also effectively offset the effects of stress F1 during cooling and improve the grain shift defect. The packaging positioning layer 40 can also serve as a dense connection layer between the grain 30 and the packaging layer 60.

[0108] The packaging method disclosed herein employs a packaging positioning layer 40 disposed between die 30. This layer 40 possesses a certain degree of rigidity, providing both support and fixation. This layer 40 effectively eliminates stress introduced by the packaging layer 60 during subsequent steps, such as after substrate 10 separation, thereby improving die 30 offset defects. This packaging method can be used in panel-level packaging.

[0109] As shown in FIG14 , a chip disclosed in the present disclosure can be formed by dividing the above-mentioned chip packaging structure; or, it can be formed by dividing the chip packaging structure obtained by the above-mentioned method.

[0110] The embodiments of the present disclosure are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present disclosure should be included in the scope of protection of the present disclosure.

[0111] It should be noted that the above description is limited to some embodiments of the present disclosure. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in an order different from that described in the above embodiments and still achieve the desired results. Furthermore, the processes depicted in the accompanying drawings do not necessarily require the specific order or sequential order shown to achieve the desired results. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0112] The embodiments of the present disclosure are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present disclosure should be included in the scope of protection of the present disclosure.

Claims

1. A chip packaging structure, comprising: Multiple grains; A packaging positioning layer is at least partially formed between adjacent crystal grains, and a hollow portion is formed corresponding to the crystal grains, and the crystal grains are sleeved in the hollow portion; A packaging layer, disposed on the packaging positioning layer, the packaging layer covers the plurality of crystal grains and the gaps between the plurality of crystal grains, and the rigidity of the packaging layer is smaller than that of the packaging positioning layer; A redistribution layer is located at a side of the package positioning layer away from the package layer, a signal line is provided in the redistribution layer, and the die is electrically connected to the signal line; A plurality of pins are arranged on a side of the redistribution layer away from the die and are electrically connected to the signal lines in the redistribution layer.

2. The chip packaging structure according to claim 1, wherein: The packaging positioning layer includes at least one organic film layer and at least one inorganic film layer which are stacked.

3. The chip packaging structure according to claim 2, wherein: The packaging positioning layer includes an organic film layer and an inorganic film layer, the organic film layer is located between the packaging layer and the inorganic film layer, and the thickness of the organic film layer is greater than or equal to 10% and less than or equal to 50% of the grain height.

4. The chip packaging structure according to claim 3, wherein: The thickness of the organic film layer is greater than or equal to 12 μm.

5. The chip packaging structure according to claim 3, wherein: The density of the organic film layer on the side of the organic film layer far away from the encapsulation layer is less than 0.5 g / cm3; Alternatively, the packaging positioning layer includes two inorganic film layers and one organic film layer, and the packaging positioning layer is composed of inorganic film layers on both sides of the chip thickness direction, and the lower surface of the inorganic film layer close to the packaging layer among more than two inorganic film layers is less than or equal to 50% of the height of the grain.

6. The chip packaging structure according to claim 1, wherein: The thickness of the packaging positioning layer is greater than or equal to 2 μm and less than the height of the grain.

7. The chip packaging structure according to claim 6, wherein: The thickness of the packaging positioning layer is greater than or equal to 2.5 μm and less than 50% of the height of the grain.

8. The chip packaging structure according to claim 6, wherein: The thickness of the packaging positioning layer is greater than or equal to 3 μm and less than 30% of the height of the grain.

9. The chip packaging structure according to claim 1, wherein: The thermal expansion coefficient of the packaging positioning layer is smaller than the thermal expansion coefficient of the packaging layer.

10. The chip packaging structure according to claim 9, wherein: The material of the packaging positioning layer includes one or more of inorganic materials, organic materials and composite materials.

11. The chip packaging structure according to claim 10, wherein: The inorganic material includes one or more of a metal material, a ceramic material, a carbon-based material and an oxide material, and the organic material includes a polymer material.

12. The chip packaging structure according to claim 11, wherein: The inorganic material is an amorphous material.

13. The chip packaging structure as claimed in claim 12, wherein: The metal material includes one or more of gold nanoparticles (AuNPs), silver nanoparticles (AgNPs) and copper nanoparticles (CuNPs); or, The oxide material is selected from at least one of aluminum oxide (Al2O3), zinc oxide (ZnO), titanium dioxide (TiO2), hafnium dioxide (HfO2), zirconium dioxide (ZrO2) and tantalum pentoxide (Ta2O5); or, The amorphous material includes at least one of amorphous silicon (a-Si), silicon oxide (SiOx), silicon nitride (SiNx), indium tin oxide (ITO) and indium gallium zinc oxide (IGZO); or, The carbon-based material includes one or more of carbon nanotubes (CNTs), graphene and carbon black (CB); or, The polymer material includes one or more of polyvinyl alcohol (PVA), polydimethylsiloxane (PDMS), polyacrylonitrile (PAN), polyethylene terephthalate (PET), PMMA and polyimide (PI); or, The composite material includes one or more of AgNWs / PEO, styrene-ethylene-butylene-styrene (SEBS) / TiO2 and poly(melamine-co-formaldehyde) (PMF) / PVA.

14. A mask assembly for chip packaging, comprising: The mask plate includes a plurality of shielding members and a plurality of connecting members, wherein the connecting members are connected The shielding member, a plurality of the shielding members and a plurality of the connecting members enclose a plurality of hollow areas; the plurality of the connecting members form a mesh, One edge of each shielding member corresponds to two or more of the connecting members.

15. A chip packaging method, comprising the following steps: S10, configuring a bonding layer on one side of the substrate; S20, placing a plurality of crystal grains at preset positions on a side of the bonding layer away from the substrate; S30, preparing a packaging positioning layer, wherein the packaging positioning layer is filled in the gaps between the grains; S40, coating a packaging material on the side of the packaging positioning layer away from the substrate, and curing to obtain a packaging layer; S50, removing the substrate and the bonding layer; S60, forming a redistribution layer on the packaging positioning layer and on a side of the die away from the packaging layer through a redistribution process; And, pins are arranged on the redistribution layer.

16. The chip packaging method according to claim 15, wherein: The step S30 includes: using an inkjet printing device to fill the gaps between the grains with a filling material to obtain the packaging positioning layer; or The step S30 includes: setting a mask on the grain, the shielding member of the mask corresponds to the grain, the hollow part of the mask corresponds to the gap between the grains, and filling the filling material from the hollow part into the gap between the grains to obtain the packaging positioning layer.

17. The chip packaging method according to claim 15, wherein: Before step S30 or before step S20, the method includes: forming an inhibition layer on the top of the grains, filling the gaps between the grains with filling material from the side of the grains away from the substrate to obtain the packaging positioning layer, and removing the inhibition layer after forming the packaging positioning layer.

18. The chip packaging method according to claim 17, wherein: The inhibiting layer is formed before cutting a mother substrate to form the die.

19. The chip packaging method according to claim 17, wherein: The inhibition layer includes an organic polymer, and the organic polymer includes at least one of polymethyl methacrylate (PMMA) and polyvinyl pyrrolidone (PVP).

20. The chip packaging method according to any one of claims 16 to 19, wherein: The filling material includes one or more of inorganic materials, organic materials and composite materials.

21. The chip packaging method according to claim 20, wherein: The step S30 includes: filling the gap with the organic material, filling the gap with the inorganic material after the organic material is solidified, and obtaining a packaging positioning layer formed by stacking an organic film layer and an inorganic film layer after the inorganic material is solidified.

22. The chip packaging method according to claim 21, wherein: The organic material includes a polymer material, and the polymer material includes a cross-linking agent; the step S30 includes: modifying the polymer material by adjusting the atomic ratio between the functional groups in the cross-linking agent or adding a cross-linking agent containing a carbonyl functional group or a hydroxyl functional group to the polymer material, and filling the modified polymer material into the gap.

23. The chip packaging method according to claim 15, wherein: Step S40 includes: coating a packaging material on the packaging positioning layer, the packaging material covering the die and a side of the packaging positioning layer away from the bonding layer, and curing the packaging material to form the packaging layer.

24. The chip packaging method according to claim 23, wherein: The packaging material includes epoxy film plastic.

25. The chip packaging method according to claim 24, wherein: The step S30 includes preparing the packaging positioning layer by multiple coating processes.

26. The chip packaging method according to claim 25, wherein: The step S30 includes preparing the packaging positioning layer by forward and reverse coating; The step S50 includes: separating the substrate and the bonding layer from the packaging positioning layer and the die through a peeling process.

27. The chip packaging method according to claim 26, wherein: The step S50 includes removing the substrate and the bonding layer by laser stripping or wet stripping.

28. A chip formed by dividing the chip packaging structure described in any one of claims 1 to 13; or, formed by dividing the chip packaging structure obtained by the method described in any one of claims 15 to 27.

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