Pixel circuit and driving method therefor, and display panel

Abstract

A pixel circuit (10), a driving method, and a display panel (100). The pixel circuit (10) comprises a driving module (101), a threshold compensation module (102), a coupling module (104), a data writing module (105), and a first light-emitting control module (106). The threshold compensation module (102) has a control end electrically connected to a first scanning signal line (S1), a first end electrically connected to a control end of the driving module (101), and a second end electrically connected to a second end of the driving module (101). A first end of the coupling module (104) is electrically connected to the second end of the driving module (101). The data writing module (105) has a control end electrically connected to a second scanning signal line (S2), a first end electrically connected to a second end of the coupling module (104), and a second end electrically connected to a data voltage signal end (Data). Before a data writing stage (T3), the node potential of the second end of the coupling module (104) is kept stable, and a threshold compensation stage (T2) does not overlap with the data writing stage (T3). The brightness uniformity of the pixel circuit (10) can be achieved, thereby improving the display effect of the display panel (100).

Description

Pixel circuit and driving method thereof, and display panel

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 202310960805X, filed on August 1, 2023, entitled “A pixel circuit and its driving method,” and the entire contents of that application are incorporated herein by reference. Technical Field

[0003] The present application belongs to the technical field of display panels, and in particular relates to a pixel circuit and a driving method thereof, as well as a display panel.

[0004] Background of the Invention

[0005] With the rapid development of display technology, people's demand for display panels is increasing day by day. Based on this, how to fully ensure the display effect of display panels has become one of the hot issues that continue to be concerned about in this field.

[0006] Summary of the Invention

[0007] The embodiments of the present application provide a pixel circuit and a driving method thereof, as well as a display panel, which can better achieve brightness uniformity, thereby effectively improving the display effect of the display panel.

[0008] In a first aspect, an embodiment of the present application provides a pixel circuit, the pixel circuit comprising:

[0009] A driving module, used for driving the light-emitting element to emit light;

[0010] a threshold compensation module, wherein a control end of the threshold compensation module is electrically connected to the first scan signal line, a first end of the threshold compensation module is electrically connected to the control end of the driving module, and a second end of the threshold compensation module is electrically connected to the second end of the driving module;

[0011] a coupling module, wherein a first end of the coupling module is electrically connected to a second end of the driving module;

[0012] a data writing module, wherein a control end of the data writing module is electrically connected to the second scanning signal line, a first end of the data writing module is electrically connected to the second end of the coupling module, and a second end of the data writing module is electrically connected to the data voltage signal end;

[0013] a first light control module, wherein a control terminal of the first light control module is electrically connected to the first light control signal line, a first terminal of the first light control module is electrically connected to the first power supply voltage signal terminal, and a second terminal of the first light control module is electrically connected to the first terminal of the driving module;

[0014] Before the data writing phase, the node potential of the second end of the coupling module is kept stable; and the threshold compensation phase does not overlap with the data writing phase.

[0015] Based on the same inventive concept, in a second aspect, an embodiment of the present application provides a driving method, which is applied to the pixel circuit provided by any of the aforementioned embodiments of the first aspect of the present application. The driving method includes:

[0016] Before the data writing phase, the node potential of the second end of the coupling module is controlled to be stable; and the threshold compensation phase is controlled not to overlap with the data writing phase.

[0017] Based on the same inventive concept, in a third aspect, an embodiment of the present application provides a display panel, which includes a pixel circuit provided in any of the aforementioned embodiments of the first aspect of the present application.

[0018] Based on the same inventive concept, in a fourth aspect, an embodiment of the present application provides a display device, which includes a display panel provided in the implementation of the third aspect of the present application.

[0019] As can be seen from the above description, an embodiment of the present application provides a pixel circuit and a driving method thereof, wherein the pixel circuit includes a driving module, a threshold compensation module, a coupling module, a data writing module, and a first light-emitting control module. During the threshold compensation phase, the first light-emitting control module, the driving module, and the threshold compensation module are turned on, and the threshold compensation of the driving module is performed using the first power supply voltage signal provided by the first power supply voltage signal terminal; during the data writing phase, the threshold compensation module and the data writing module are turned on, and the data signal provided by the data voltage signal terminal is coupled to the control terminal of the driving module via the coupling module; wherein, before the data writing phase, the node potential of the second terminal of the control coupling module is maintained stable so that the data signal can be quickly written through coupling during the data writing phase, and the threshold compensation phase and the data writing phase do not overlap.

[0020] A pixel circuit and driving method according to an embodiment of the present application separates the threshold compensation phase from the data writing phase, thereby freeing the pixel circuit's threshold compensation time from being limited by the row scanning time. This allows for better brightness uniformity, effectively improving the display quality of the display panel. Furthermore, the present application employs a first power supply voltage signal terminal to perform threshold compensation on the driver module, thereby simultaneously compensating for the voltage drop caused by the first power supply voltage signal terminal, further improving the brightness uniformity of the display panel.

[0021] BRIEF DESCRIPTION OF THE DRAWINGS

[0022] FIG1 is a schematic structural diagram of a pixel circuit provided in an embodiment of the present application;

[0023] FIG2 is a timing diagram of a pixel circuit provided in an embodiment of the present application;

[0024] FIG3 is a schematic structural diagram of another pixel circuit provided in an embodiment of the present application;

[0025] FIG4 is a schematic structural diagram of another pixel circuit provided in an embodiment of the present application;

[0026] FIG5 is a timing diagram of another pixel circuit provided in an embodiment of the present application;

[0027] FIG6 is a schematic structural diagram of another pixel circuit provided in an embodiment of the present application;

[0028] FIG7 is a timing diagram of another pixel circuit provided in an embodiment of the present application;

[0029] FIG8 is a schematic structural diagram of another pixel circuit provided in an embodiment of the present application;

[0030] FIG9 is a timing diagram of another pixel circuit provided in an embodiment of the present application;

[0031] FIG10 is a timing diagram of another pixel circuit provided in an embodiment of the present application;

[0032] FIG11 is a schematic structural diagram of another pixel circuit provided in an embodiment of the present application;

[0033] FIG12 is a timing diagram of another pixel circuit provided in an embodiment of the present application;

[0034] FIG13 is a timing diagram of another pixel circuit provided in an embodiment of the present application;

[0035] FIG14 is a schematic structural diagram of another pixel circuit provided in an embodiment of the present application;

[0036] FIG15 is a schematic structural diagram of another pixel circuit provided in an embodiment of the present application;

[0037] FIG16 is a timing diagram of another pixel circuit provided in an embodiment of the present application;

[0038] FIG17 is a timing diagram of another pixel circuit provided in an embodiment of the present application;

[0039] FIG18 is a schematic flow chart of a driving method provided in an embodiment of the present application;

[0040] FIG19 is a schematic flow chart of another driving method provided in an embodiment of the present application;

[0041] FIG20 is a schematic structural diagram of a display panel provided in an embodiment of the present application;

[0042] FIG21 is a schematic structural diagram of a display device provided in an embodiment of the present application.

[0043] Modes for Carrying Out the Invention

[0044] The transistors in the embodiments of the present application can be either N-type transistors or P-type transistors. For N-type transistors, the on-level is a high level, and the off-level is a low level. That is, when the gate of the N-type transistor is at a high level, the first terminal and the second terminal are conductive, and when the gate of the N-type transistor is at a low level, the first terminal and the second terminal are disconnected. For P-type transistors, the on-level is a low level, and the off-level is a high level. That is, when the control terminal of the P-type transistor is at a low level, the first terminal and the second terminal are conductive, and when the control terminal of the P-type transistor is at a high level, the first terminal and the second terminal are disconnected. In a specific implementation, the gate of each of the above-mentioned transistors serves as its control terminal, and depending on the signal of the gate of each transistor and its type, the first terminal can serve as the source and the second terminal as the drain, or the first terminal can serve as the drain and the second terminal as the source, without distinction being made here. In addition, the on-level and off-level in the embodiments of the present application are both general terms. The on-level refers to any level that can turn the transistor on, and the off-level refers to any level that can turn the transistor off / on.

[0045] In the embodiments of the present application, the term “electrically connected” may refer to a direct electrical connection between two components, or may refer to an electrical connection between two components via one or more other components.

[0046] In the embodiment of the present application, the first node, the second node and the third node are only defined for the convenience of describing the circuit structure. The first node, the second node and the third node are not actual circuit units.

[0047] It will be apparent to those skilled in the art that various modifications and variations can be made in this application without departing from the spirit or scope of this application. Therefore, this application is intended to cover modifications and variations of this application that fall within the scope of the corresponding claims (technical solutions claimed for protection) and their equivalents. The embodiments provided in the examples of this application may be combined with each other unless there is any contradiction.

[0048] Before describing the technical solutions provided by the embodiments of the present application, in order to facilitate understanding of the embodiments of the present application, the present application first specifically describes the problems existing in the related art:

[0049] As previously mentioned, the inventors of this application have discovered that thin-film transistor (TFT) device characteristics directly affect the grayscale brightness variations of a display panel. When the TFT device characteristics vary significantly between different pixel circuits, uneven image quality can easily result. Currently, in the field of display panel technology, internal compensation is typically performed on the threshold voltage of the driver transistor in the pixel circuit to reduce the grayscale brightness variations caused by the TFT device characteristics, thereby improving the brightness uniformity of the entire display image.

[0050] Further research by the inventors of this application has revealed that for conventional pixel circuits in existing display panels, such as 7T1C, as refresh rates continue to increase, the data writing time for each row of pixel circuits in the display panel is continuously compressed. Consequently, the time required to perform threshold compensation for the driver transistors in the pixel circuits is also compressed, resulting in insufficient threshold voltage compensation. As a result, the display panel is still susceptible to mura brightness unevenness, which in turn seriously affects the uniformity of the display panel's light emission and the display quality.

[0051] In response to the above technical problems, the embodiments of the present application provide a pixel circuit, a driving method, a display panel and a display device, which can solve the problem existing in the related technology: as the refresh rate continues to increase, the compensation time of the pixel circuit in the display panel is insufficient, resulting in insufficient threshold voltage compensation, thereby affecting the uniformity and display effect of the display panel.

[0052] The embodiments provided in this application are not intended to limit the scope of the disclosure of this application.

[0053] The technical concept of the embodiments of the present application is: in view of the fact that the threshold compensation time in the existing pixel circuit (such as 7T1C) is limited by the data writing time / row scanning time, resulting in insufficient threshold voltage compensation time in the pixel circuit when the refresh rate is increased, that is, when the row scanning time is compressed, resulting in poor display uniformity of the display panel, the present application considers proposing a new type of pixel circuit. Specifically, during the operation of the pixel circuit, by separating the threshold voltage compensation process from the data writing process, the threshold voltage compensation time is not limited by the row scanning time, which is conducive to fully ensuring the threshold voltage compensation effect, thereby improving the brightness uniformity of the display panel. In addition, in a new type of pixel circuit provided by the present application, it is considered to use the power supply voltage signal terminal (VDD) to charge the gate of the driving module during the compensation process to compensate for the power supply voltage signal terminal voltage drop (VDD IR Drop), which is conducive to further improving display uniformity.

[0054] The following first introduces the pixel circuit provided in the embodiment of the present application.

[0055] FIG1 is a schematic diagram showing the structure of a pixel circuit according to an embodiment of the present application. As shown in FIG1 , a pixel circuit 10 according to an embodiment of the present application may include a driving module 101, a threshold compensation module 102, a first storage module 103, a coupling module 104, a data writing module 105, and a first light emission control module 106.

[0056] 1 , the driving module 101 can be used to drive the light emitting element to emit light. For example, the driving module 101 can be a transistor, and the second end of the driving module 101 can be a drain (or source) of the transistor.

[0057] The control end of the threshold compensation module 102 is electrically connected to the first scan signal line S1 , the first end of the threshold compensation module 102 is electrically connected to the control end of the driving module 101 , and the second end of the threshold compensation module 102 is electrically connected to the second end of the driving module 101 .

[0058] A first end of the coupling module 104 is electrically connected to a second end of the driving module 101 .

[0059] The control end of the data writing module 105 is electrically connected to the second scan signal line S2 , the first end of the data writing module 105 is electrically connected to the second end of the coupling module 104 , and the second end of the data writing module 105 is electrically connected to the data voltage signal end Data.

[0060] The control end of the first light control module 106 is electrically connected to the first light control signal line EM1 , the first end of the first light control module 106 is electrically connected to the first power supply voltage signal end VDD, and the second end of the first light control module 106 is electrically connected to the first end of the driving module 101 .

[0061] Furthermore, the second electrode of the light-emitting element is electrically connected to VSS, which is a second power supply voltage signal terminal. The first power supply voltage signal terminal VDD provides a first power supply voltage signal, which can be a positive voltage signal. The second power supply voltage signal terminal VSS provides a second power supply voltage, which can be a negative voltage signal. The light-emitting element can be an LED (Light-Emitting Diode), an OLED (Organic Electroluminescence Display), or other.

[0062] In conjunction with Figure 1, please refer to Figure 2 below, which is a timing diagram of a pixel circuit provided by an embodiment of the present application. In this embodiment, the on-level is a low level and the off-level is a high level.

[0063] Specifically, during the operation of the pixel circuit 10, as shown in FIG2 , during the threshold compensation phase, the first emission control signal line EM1 provides an on-level voltage, and the first emission control module 106 is turned on under the control of the first emission control signal line EM1. The first scanning signal line S1 provides an on-level voltage, and the threshold compensation module 102 is turned on under the control of the first scanning signal line S1. During this phase, the driver module 101 is turned on, and the first power supply voltage signal provided by the first power supply voltage signal terminal VDD is written to the control terminal of the driver module 101 via the turned-on first emission control module 106, the driver module 101, and the threshold compensation module 102, thereby achieving threshold compensation for the driver module 101.

[0064] In a specific implementation, in the data writing stage, the first scanning signal line S1 provides a conduction level, and the threshold compensation module 102 is turned on under the control of the first scanning signal line S1. The second scanning signal line S2 provides a conduction level, and the data writing module 105 is turned on under the control of the first scanning signal line S1. The first light-emitting control signal line EM provides a cut-off level, and the first light-emitting control module 106 is turned off under the control of the first light-emitting control signal line EM. The data signal provided by the above-mentioned data voltage signal terminal Data is coupled to the second end of the driving module 101 through the coupling module 104, and is transmitted to the control end of the driving module 101 through the turned-on threshold compensation module 102 to realize the writing of the data signal. Among them, the above-mentioned threshold compensation stage does not overlap with the above-mentioned data writing stage. It should be supplemented that, in order to better realize data writing in this embodiment, the above-mentioned threshold compensation stage can precede the data writing stage, and this application does not impose specific restrictions on this.

[0065] Furthermore, in this embodiment, before the pixel circuit 10 enters the data writing phase, the node potential at the second end of the coupling module 104 is maintained stable. This allows the coupling function of the coupling module 104 to quickly write the data signal provided by the data voltage signal terminal Data during the data writing phase.

[0066] Specifically, when maintaining the node potential at the second end of coupling module 104 stable, the second end of coupling module 104 can, for example, be electrically connected to a voltage signal line. This voltage signal line can be controlled by a driver chip in the display panel. The driver chip can use this voltage signal line to provide a stable voltage to the second end of coupling module 104 before the data writing phase, and stop transmitting this stable voltage during the data writing phase to facilitate data signal writing. The above is merely an example, and other feasible implementations for maintaining the potential stability of the second end of coupling module 104 are also intended to be within the scope of protection of this application.

[0067] It should also be noted that during the threshold compensation phase, the driver module 101 must remain in an on state so that the first power supply voltage signal provided by the first power supply voltage signal terminal VDD can be written to the control terminal of the driver module 101 through the first light-emitting control module 106, the driver module 101, and the threshold compensation module 102, thereby achieving threshold compensation for the driver module 101. Based on this, the first storage module 103 can be specifically used to keep the driver module 101 on during the threshold compensation phase of the pixel circuit 10. In a specific implementation, the first storage module 103 can be initialized before the threshold compensation phase. Thus, after the first light-emitting control module 106 is turned on, the node voltage difference between the first terminal and the control terminal of the driver module 101 meets the on condition, causing the driver module 101 to turn on during the threshold compensation phase.

[0068] Of course, it is worth noting that in some other feasible implementations, other signal lines can also be directly electrically connected to the control end of this driving module 101. In this way, by controlling the voltage transmitted by the signal line, it is ensured that the driving module 101 can remain in the on state during the threshold compensation stage. This application does not make specific restrictions here.

[0069] As can be seen from the above description, this embodiment provides a pixel circuit 10, which includes a driver module 101, a threshold compensation module 102, a coupling module 104, a data writing module 105, and a first light-emitting control module 106. During the threshold compensation phase, the first light-emitting control module 106, the driver module 101, and the threshold compensation module 102 are turned on, and the first power supply voltage signal provided by the first power supply voltage signal terminal VDD is used to perform threshold compensation on the driver module 101. During the data writing phase, the threshold compensation module 102 and the data writing module 105 are turned on, and the data signal provided by the data voltage signal terminal Data is coupled to the control terminal of the driver module 101 via the coupling module 104. The threshold compensation phase and the data writing phase do not overlap.

[0070] A pixel circuit 10 according to an embodiment of the present application separates the threshold compensation phase from the data writing phase, thereby freeing the pixel circuit 10's threshold compensation time from being limited by the row scan time. This reduces the severity of mura, improves brightness uniformity, and effectively enhances the display quality of the display panel. Furthermore, the present application utilizes a first power supply voltage signal terminal VDD to perform threshold compensation on the driver module, thereby simultaneously compensating for the voltage drop (IR drop) caused by the first power supply voltage signal terminal, further improving the brightness uniformity of the display panel.

[0071] In addition, compared with the data writing method of the traditional 7T1C pixel circuit, the present application uses the coupling effect of the coupling module 104 to write the data signal, which can achieve faster and smoother data voltage writing to the control end of the driving module 101, thereby helping to further improve the refresh rate of the display panel.

[0072] According to some embodiments of the present application, as shown in FIG3 , which is a schematic diagram of the structure of another pixel circuit provided in an embodiment of the present application, in order to fully ensure that the display panel has good display performance and display effects at different refresh rates, the pixel circuit 10 may further include a first switch module 107 and a second storage module 108.

[0073] Specifically, as shown in Figure 3, the control end of the above-mentioned first switch module 107 is electrically connected to the first scan signal line S1, the first end of the first switch module 107 is electrically connected to the control end of the driving module 101, and the second end of the first switch module 107 is electrically connected to the first end of the threshold compensation module 102.

[0074] A first terminal of the second storage module 108 is electrically connected to the first power supply voltage signal terminal VDD, and a second terminal of the second storage module 108 is electrically connected to a first terminal of the threshold compensation module 102 .

[0075] In this embodiment, the first end of the second storage module 108 provides a first power supply voltage signal end VDD with a constant voltage signal, and the second end of the second storage module 108 is electrically connected through the first end of the threshold compensation module 102, which is beneficial to maintaining the potential stability of the control end of the driving module 101, and is beneficial to slowing down the leakage phenomenon during the operation of the pixel circuit 10, thereby avoiding the leakage current from adversely affecting the circuit stability and the display effect of the display panel at different refresh rates.

[0076] In particular, specifically, considering that in existing conventional pixel circuits, when the display panel is refreshed at a low frequency, the control terminal potential holding time of the pixel circuit driving module 101 is often increased exponentially compared to the high-frequency state, if the threshold compensation module 102 has a large leakage current, the threshold compensation module 102 will continue to leak current during the potential holding process, resulting in more data signals being leaked through the threshold compensation module 102 during low-frequency display, thereby more seriously affecting the display effect, and the display panel will have a poor display effect during low-frequency display.

[0077] Based on this, the second storage module 108 and the first switch module 107 are added in this embodiment. The gates of the first switch module 107 and the threshold compensation module 102 are both electrically connected to the first scan signal line S1, and the second end of the first switch module 107 is connected to the first end of the threshold compensation module 102. The first switch module 107 and the threshold compensation module 102 may include transistors of the same channel type. The first switch module 107 and the threshold compensation module 102 can be regarded as a "dual-gate transistor". This "dual-gate transistor" can effectively reduce leakage current, which is conducive to maintaining the voltage stability of the control terminal of the driving module 101 at various refresh frequencies, especially at low frequencies.

[0078] Furthermore, considering that when this "dual-gate transistor" is turned off, that is, when the first switch module 107 and the threshold compensation module 102 are both turned off, the middle node (the first end of the above-mentioned threshold compensation module 102) is floating, the potential of the middle node will be easily affected by other signals in the display panel, causing the node potential of the middle node of this "dual-gate transistor" to be unstable, and the leakage current may still be large, resulting in the display effect of the display panel still not being fully improved.

[0079] For the above considerations, this embodiment further introduces the aforementioned second storage module 108, which can specifically implement its module function using a storage capacitor. The first end of the second storage module 108 is electrically connected to the first power supply voltage signal terminal VDD that provides a constant voltage. This allows the potential of the middle node of the "dual-gate transistor" to remain constant when it is turned off, thereby reducing leakage current and making the potential of the control terminal of the driver module 101 more stable. This helps avoid problems such as display panel brightness changes caused by data signal leakage losses from the gate of the driver module 101 and the first storage module 103, thereby improving the display effect of the display panel, especially helping to ensure the display effect of the display panel during low-frequency refresh, and also facilitating lower-frequency display of the display panel.

[0080] In addition, in this embodiment, the first end of the second storage module 108 is electrically connected to the first power supply voltage signal terminal VDD, which can make the node potential of the middle node of this "dual-gate transistor" close to the potential of the control terminal of the driving module 101, which is equivalent to reducing the voltage difference between the first end of the first switch module 107 and the second end of the first switch module 107. This can further achieve the effect of suppressing the leakage current between the first switch module 107 and the control terminal of the driving module 101, and help maintain the stability of the potential of the control terminal of the driving module 101. Therefore, when the display panel refreshes the display at different refresh frequencies, especially low frequencies, the driving module 101 in the pixel circuit 10 can drive the light-emitting element to emit light with a stable driving current during the light-emitting stage, thereby effectively improving the display effect and competitiveness of the display panel.

[0081] During the actual operation of the pixel circuit 10, in the threshold compensation stage, the first scanning signal line S1 provides a conduction level, and the first switch module 107 is turned on under the control of the first scanning signal line S1. The first power supply voltage signal provided by the first power supply voltage signal terminal VDD is written to the control terminal of the driver module 101 through the turned-on first light-emitting control module 106, the driver module 101, the threshold compensation module 102, and the first switch module 107, thereby achieving threshold compensation for the driver module 101.

[0082] During the data writing phase, the first scanning signal line S1 provides a conduction voltage, and the first switch module 107 is turned on under the control of the first scanning signal line S1. The data signal provided by the data voltage signal terminal Data is coupled to the second terminal of the driving module 101 via the coupling module 104, and is transmitted to the control terminal of the driving module 101 via the turned-on threshold compensation module 102 and the turned-on first switch module 107, thereby achieving rapid writing of the data signal.

[0083] Please refer to Figure 4 below, which is a schematic diagram of the structure of another pixel circuit provided in an embodiment of the present application. Considering that during the threshold compensation stage, if the second end of the coupling module 104 is left floating, it may have an adverse effect on the threshold voltage compensation of the driving module 101. Based on this, in order to ensure the normal operation of the pixel circuit during the threshold compensation stage, as shown in Figure 4, the pixel circuit 10 may further include a second switch module 109.

[0084] Specifically, the control end of the second switch module 109 is electrically connected to the third scan signal line S3, the first end of the second switch module 109 is electrically connected to the second end of the coupling module 104, and the second end of the second switch module 109 is electrically connected to the initial voltage signal end Vini.

[0085] Please refer to Figure 5 below, which is a timing diagram of another pixel circuit provided in an embodiment of the present application. As shown in Figure 5, during the threshold compensation phase, the third scan signal line S3 provides a conduction level, and the second switch module 109 is turned on under the control of the third scan signal line S3, writing the initial voltage signal provided by the initial voltage signal terminal Vini to the second terminal of the coupling module 104 to provide a constant voltage to the second terminal of the coupling module 104.

[0086] According to some embodiments of the present application, further, in order to more reasonably realize the initialization of the aforementioned coupling module 104, so as to avoid adverse effects on subsequent threshold compensation, data writing and light-emitting stages due to leakage or residual charge, in the first initialization stage before the threshold compensation stage, the third scanning signal line S3 provides a conduction level, the second switch module 109 is turned on, and the initial voltage signal provided by the initial voltage signal terminal Vini is written to the second end of the coupling module 104 to initialize the second end of the coupling module 104.

[0087] According to some embodiments of the present application, optionally, before the data writing phase, the second switch module 109 is continuously turned on under the control of the third scan signal line S3 to continuously transmit the initial voltage signal provided by the initial voltage signal terminal Vini to the second terminal of the coupling module 104, thereby maintaining the node potential of the second terminal of the coupling module 104 stable before the data writing phase. In this way, during the data writing phase, due to the difference between the data signal during the data writing phase and the initial voltage signal, the voltage at the second terminal of the coupling module 104 will jump, thereby ultimately achieving rapid writing of the data signal provided by the data voltage signal terminal Data through the coupling effect of the coupling module 104.

[0088] According to some embodiments of the present application, optionally, please refer to Figure 6, which is a structural diagram of another pixel circuit provided in an embodiment of the present application. In a specific implementation, in order to improve the bias state of the driving module 101 at different refresh frequencies, thereby improving the display unevenness mura that occurs when different refresh frequencies are switched, as shown in Figure 6, the pixel circuit 10 may further include a reset module 110. In the pixel circuit 10, the control end of the reset module 110 is electrically connected to the fourth scan signal line S4, the first end of the reset module 110 is electrically connected to the first end of the driving module 101, and the second end of the reset module 110 is electrically connected to the reset reference voltage signal terminal VEH.

[0089] Please refer to Figure 7 below, which is a timing diagram of another pixel circuit provided in an embodiment of the present application. As shown in Figure 7, in the second initialization phase, the fourth scan signal line S4 provides a low level, and the reset module 110 is turned on under the control of the fourth scan signal line S4, transmitting the reset reference voltage signal provided by the reset reference voltage signal terminal VEH to the first terminal of the driver module 101 to reset the first terminal and the second terminal of the driver module 101. This ensures that the bias state of the driver module 101 at the same refresh rate can achieve a better adjustment effect, thereby improving the display uniformity of the display panel and significantly improving the display quality of the display panel.

[0090] According to some embodiments of the present application, more specifically, please refer to FIG8 . FIG8 is a schematic diagram of the structure of another pixel circuit provided in an embodiment of the present application. As shown in FIG8 , the pixel circuit 10 may further include a first storage module 103, a first initialization module 111, a second initialization module 112, and a second light-emitting control module 113. Specifically, a first terminal of the first storage module 103 is electrically connected to the first power supply voltage signal terminal VDD, and a second terminal of the first storage module 103 is electrically connected to the control terminal of the driving module 101. Regarding the first initialization module 111, the control terminal of the first initialization module 111 is electrically connected to the fifth scan signal line S5, the first terminal of the first initialization module 111 is electrically connected to the first terminal of the threshold compensation module 102, and the second terminal of the first initialization module 111 is electrically connected to the first reference voltage signal terminal Vref1. The control terminal of the second initialization module 112 is electrically connected to the fourth scan signal line S4, the first terminal of the second initialization module 112 is electrically connected to the first electrode of the light-emitting element, and the second terminal of the second initialization module 112 is electrically connected to the second reference voltage signal terminal Vref2. The control terminal of the second light-emitting control module 113 is electrically connected to the second light-emitting control signal line EM2. The first terminal of the second light-emitting control module 113 is electrically connected to the second terminal of the driver module 101. The second terminal of the second light-emitting control module 113 is electrically connected to the first electrode of the light-emitting element. It should be noted that in this embodiment, the first storage module 103 may be initialized before the threshold compensation stage. In this way, after the first light-emitting control module 106 is turned on, the node voltage difference between the first terminal and the control terminal of the driver module 101 meets the turn-on condition, causing the driver module 101 to turn on during the threshold compensation stage.

[0091] Please refer to FIG9 , which is a timing diagram of another pixel circuit provided in an embodiment of the present application. As shown in FIG9 , in a first initialization phase, the fifth scan signal line S5 provides a conduction level, and the first initialization module 111 is turned on under the control of the fifth scan signal line S5, and transmits the first reference level voltage provided by the first reference voltage signal terminal Vref1 to the second electrode of the first storage module 103 to initialize the second electrode of the first storage module 103. Furthermore, in the first initialization phase, if the pixel circuit 10 further includes the aforementioned second storage module 108, the fourth scan signal line S4 provides a conduction level, and the first initialization module 111 is turned on under the control of the fourth scan signal line S4, and transmits the first reference level voltage provided by the first reference voltage signal terminal Vref1 to the second electrode of the second storage module 108 to initialize the second electrode of the second storage module 108.

[0092] In the second initialization stage, the fourth scan signal line S4 provides a conduction level, and the second initialization module 112 is turned on under the control of the fourth scan signal line S4, and the second reference level voltage provided by the second reference voltage signal terminal Vref2 is transmitted to the first electrode of the light-emitting element to reset the first electrode of the light-emitting element.

[0093] In conjunction with Figure 9, please refer to Figure 10 below. Figure 10 is a timing diagram of another pixel circuit provided in an embodiment of the present application. According to some embodiments of the present application, the display frame can optionally be divided into a data write frame and a hold frame. Figure 9 may correspond to the case where the display frame is a data write frame, and Figure 10 may correspond to the case where the display frame is a hold frame.

[0094] As shown in FIG9 , when the display frame is a data writing frame, the operating phases of the pixel circuit 10 may include a first initialization phase, a threshold compensation phase, a data writing phase, a second initialization phase, and a light-emitting phase. During the light-emitting phase, the first light-emitting control signal line EM1 provides a conduction voltage level. Under the control of the first light-emitting control signal line EM1, the first light-emitting control module 106 is turned on and transmits the first power supply voltage signal provided by the first power supply voltage signal terminal VDD to the first terminal of the driver module 101. The second light-emitting control signal line EM2 provides a conduction voltage level. Under the control of the second light-emitting control signal line EM2, the second light-emitting control module 113 is turned on and writes the voltage at the second terminal of the driver module 101 to the first electrode of the light-emitting element.

[0095] As shown in FIG10 , when the display frame is a hold frame, the operating phase of the pixel circuit 10 may include the aforementioned second initialization phase and the aforementioned light-emitting phase, which are not further described in this embodiment. Furthermore, when the display frame is a hold frame, the operating phase of the pixel circuit 10 may also include a reset phase. During the reset phase, the first light-emitting control signal line EM1 provides a conduction level, and the first light-emitting control module 106 is turned on under the control of the first light-emitting control signal line EM1, transmitting the first power supply voltage signal provided by the first power supply voltage signal terminal VDD to the first terminal of the driver module 101, thereby resetting the first and second terminals of the driver module 101.

[0096] To facilitate understanding of the pixel circuit provided in this application, some specific application embodiments are described below.

[0097] Please refer to Figure 11 below, which is a schematic diagram of the structure of another pixel circuit provided in an embodiment of the present application. According to some embodiments of the present application, optionally, as shown in Figure 11, the driving module 101 may include a first transistor M1, the threshold compensation module 102 may include a second transistor M2, the data writing module 105 may include a third transistor M3, the first light emitting control module 106 may include a fourth transistor M4, and the coupling module 104 may include a second capacitor C2.

[0098] Specifically, the control terminal of the second transistor M2 is electrically connected to the first scan signal line S1, the first terminal of the second transistor M2 is electrically connected to the control terminal of the first transistor M1, and the second terminal of the second transistor M2 is electrically connected to the second terminal of the first transistor M1. The first electrode of the second capacitor C2 is electrically connected to the second terminal of the first transistor M1. The control terminal of the third transistor M3 is electrically connected to the second scan signal line S2, the first terminal of the third transistor M3 is electrically connected to the second electrode of the second capacitor C2, and the second terminal of the third transistor M3 is electrically connected to the data voltage signal terminal Data. The control terminal of the fourth transistor M4 is electrically connected to the first light emission control signal line EM1, the first terminal of the fourth transistor M4 is electrically connected to the first power supply voltage signal terminal VDD, and the second terminal of the fourth transistor M4 is electrically connected to the first terminal of the first transistor M1.

[0099] Please continue to refer to Figure 11. According to some embodiments of the present application, the pixel circuit 10 may optionally further include a first storage module 103, a first switch module 107, a second storage module 108, a second switch module 109, a reset module 110, a first initialization module 111, a second initialization module 112, and a second light-emitting control module 113. The first storage module 103 may include a first capacitor C1, the first switch module 107 may include a fifth transistor M5, the second storage module 108 may include a third capacitor C3, the second switch module 109 may include a sixth transistor M6, the reset module 110 may include a seventh transistor M7, the first initialization module 111 may include an eighth transistor M8, the second initialization module 112 may include a ninth transistor M9, and the second light-emitting control module 113 may include a tenth transistor M10. Specifically, the first electrode of the first capacitor C1 is electrically connected to the first power supply voltage signal terminal VDD, and the second electrode of the first capacitor C1 is electrically connected to the control terminal of the first transistor M1. A control terminal of the fifth transistor M5 is electrically connected to the first scan signal line S1, a first terminal of the fifth transistor M5 is electrically connected to the control terminal of the first transistor M1, and a second terminal of the fifth transistor M5 is electrically connected to the first terminal of the second transistor M2. A first terminal of the third capacitor C3 is electrically connected to the first power supply voltage signal terminal VDD, and a second terminal of the third capacitor C3 is electrically connected to the first terminal of the second transistor M2. A control terminal of the sixth transistor M6 is electrically connected to the third scan signal line S3, a first terminal of the sixth transistor M6 is electrically connected to the first terminal of the second capacitor C2, and a second terminal of the sixth transistor M6 is electrically connected to the initial voltage signal terminal Vini. A control terminal of the seventh transistor M7 is electrically connected to the fourth scan signal line S4, a first terminal of the seventh transistor M7 is electrically connected to the first terminal of the first transistor M1, and a second terminal of the seventh transistor M7 is electrically connected to the reset reference voltage signal terminal VEH. A control terminal of the eighth transistor M8 is electrically connected to the fifth scan signal line S5, a first terminal of the eighth transistor M8 is electrically connected to the first terminal of the second transistor M2, and a second terminal of the eighth transistor M8 is electrically connected to the first reference voltage signal terminal Vref1. The control terminal of the ninth transistor M9 is electrically connected to the fourth scan signal line S4, the first terminal of the ninth transistor M9 is electrically connected to the first electrode of the light-emitting element, and the second terminal of the ninth transistor M9 is electrically connected to the second reference voltage signal terminal Vref2. The control terminal of the tenth transistor M10 is electrically connected to the second light-emitting control signal line EM2, the first terminal of the tenth transistor M10 is electrically connected to the second terminal of the driving module 101, and the second terminal of the tenth transistor M10 is electrically connected to the first electrode of the light-emitting element. It should be understood that, considering that dual-gate transistors have lower leakage characteristics than single-gate transistors, in order to reduce leakage current and further ensure the display effect of the display panel, the eighth transistor M8 can be a dual-gate thin-film transistor.

[0100] Corresponding to the pixel circuit structure shown in Figure 11, please refer to Figures 12 and 13, which are timing diagrams of another pixel circuit provided in an embodiment of the present application. Figure 12 corresponds to the case where the display frame is a data write frame, and Figure 13 corresponds to the case where the display frame is a hold frame. The pixel circuit shown in Figure 11 is described below in conjunction with the timing diagrams shown in Figures 12 and 13. In this embodiment, the on-level is a low level, and the off-level is a high level.

[0101] As shown in FIG12 , when the display frame is a data writing frame, the operation process of the pixel circuit 10 in FIG11 includes a first initialization stage T1 , a threshold compensation stage T2 , a data writing stage T3 , a second initialization stage T4 and a light emitting stage T5 .

[0102] In the first initialization phase T1, the third scan signal line S3 provides a conduction level, the sixth transistor M6 is turned on, and the initial voltage signal provided by the initial voltage signal terminal Vini is written to the second terminal of the second capacitor C2 to initialize the second terminal of the second capacitor C2. The fifth scan signal line S5 provides a conduction level, and the eighth transistor M8 is turned on under the control of the fifth scan signal line S5, transmitting the first reference level voltage provided by the first reference voltage signal terminal Vref1 to the second terminal of the first capacitor C1 to initialize the second terminal of the first capacitor C1. The fourth scan signal line S4 provides a conduction level, and the eighth transistor M8 is turned on under the control of the fourth scan signal line S4, transmitting the first reference level voltage provided by the first reference voltage signal terminal Vref1 to the second terminal of the third capacitor C3 to initialize the second terminal of the third capacitor C3. It should be understood that the duration of the above-mentioned first initialization phase can be flexibly adjusted according to the actual initialization requirements of the storage capacitor, etc., and this application does not impose specific limitations on this.

[0103] During the threshold compensation phase T2, the first light-emitting control signal line EM1 provides a conduction voltage level, and the fourth transistor M4 is turned on under the control of the first light-emitting control signal line EM1. The first scan signal line S1 provides a conduction voltage level, and the fifth transistor M5 and the second transistor M2 are turned on under the control of the first scan signal line S1. During this phase, the first transistor M1 is turned on, and the first power supply voltage signal provided by the first power supply voltage signal terminal VDD is written to the control terminal of the first transistor M1 through the turned-on fourth transistor M4, the first transistor M1, the second transistor M2, and the fifth transistor M5, until the potential at the control terminal of the first transistor M1 reaches the sum of its threshold voltage and the first power supply voltage signal, thereby achieving threshold compensation for the first transistor M1. The compensation time is adjustable.

[0104] Furthermore, in this threshold compensation phase T2, the third scan signal line S3 provides a conduction level, and the sixth transistor M6 is turned on under the control of the third scan signal line S3, and the initial voltage signal provided by the initial voltage signal terminal Vini is written into the second electrode of the second capacitor C2, so as to provide a constant voltage for the second electrode of the second capacitor C2, thereby preventing the second electrode of the second capacitor C2 from being in a floating state, and at the same time ensuring that the second electrode of the second capacitor C2 is maintained at a stable potential before the data writing phase T3, so that the data signal can be coupled to the second end of the first transistor M1 through the coupling effect of the second capacitor C2 during the data writing phase T3.

[0105] During the data writing phase T3, the first scanning signal line S1 provides a conduction level, and the second transistor M2 is turned on under the control of the first scanning signal line S1. The second scanning signal line S2 provides a conduction level, and the third transistor M3 is turned on under the control of the first scanning signal line S1. The first light-emitting control signal line EM provides a cutoff level, and the fourth transistor M4 is turned off under the control of the first light-emitting control signal line EM. The data signal provided by the above-mentioned data voltage signal terminal Data is coupled to the second terminal of the first transistor M1 through the second capacitor C2, and is transmitted to the control terminal of the first transistor M1 through the turned-on second transistor M2 to realize the writing of the data signal. In this phase, the voltage written to the control terminal of the first transistor M1 is finally: VG = Vdd + Vth + k*(data-Vint), k = c2 / (c1+c2+c3). Wherein, VG is the node potential of the control terminal of the first transistor M1; Vdd is the first power supply voltage signal provided by the first power supply voltage signal terminal VDD; Vth is the threshold voltage of the first transistor M1; data is the data signal provided by the data voltage signal terminal Data during the data writing phase; Vint is the initial voltage signal provided by the aforementioned initial voltage signal terminal Vini; c1 is the capacitance value of the first capacitor C1; c2 is the capacitance value of the second capacitor C2; and c3 is the capacitance value of the third capacitor C3. Furthermore, it should be noted that after the data signal is written, the scan signal provided by the aforementioned first scan signal line S1 can first jump to a high voltage, and the scan signal provided by the second scan signal line S2 can then jump to a high voltage, to effectively ensure the validity and accuracy of the data signal written to the gate of the first transistor M1.

[0106] During the second initialization phase T4, the fourth scan signal line S4 provides a low voltage level, and the seventh transistor M7 is turned on under the control of the fourth scan signal line S4. The reset reference voltage signal provided by the reset reference voltage signal terminal VEH is transmitted to the first terminal of the first transistor M1, thereby resetting the first and second terminals of the first transistor M1. The fourth scan signal line S4 provides an on voltage level, and the ninth transistor M9 is turned on under the control of the fourth scan signal line S4. The reset reference voltage signal provided by the second reference voltage signal terminal Vref2 is transmitted to the first terminal of the light-emitting element, thereby resetting the first terminal of the light-emitting element. It should be understood that, given the varying bias adjustment requirements of different display panels in different states, the reset reference voltage signal provided by the reset reference voltage signal terminal VEH is adjustable, and this embodiment does not impose any specific limitations on this.

[0107] In the light-emitting stage T5, the first light-emitting control signal line EM1 provides a conduction level, and the fourth transistor M4 is turned on under the control of the first light-emitting control signal line EM1, transmitting the first power supply voltage signal Vdd provided by the first power supply voltage signal terminal VDD to the first terminal of the first transistor M1. The second light-emitting control signal line EM2 provides a conduction level, and the tenth transistor M10 is turned on under the control of the second light-emitting control signal line EM2. The first transistor M1 provides a driving current according to the data signal written in the previous data writing stage T3 to drive the light-emitting element to emit light. The driving current is: I = , where W is the channel width of the first transistor M1, L is the channel length of the first transistor M1, μ is the mobility, and is the capacitance constant. As can be seen from this formula, the driving current is independent of the threshold voltage and the first power supply voltage signal Vdd. In the pixel circuit 10 provided in the embodiment of the present application, by time-sharing data writing and threshold compensation, and using VDD to perform threshold compensation on the driving transistor, it is possible to achieve full threshold voltage compensation and rapid data signal writing while compensating for the IR drop (IR drop) of the first power supply voltage signal Vdd.

[0108] As shown in FIG13 , when the display frame is a hold frame, the operation process of the pixel circuit 10 in FIG11 includes a reset phase T1 , a second initialization phase T2 and a light emitting phase T3 .

[0109] In the reset stage T1, the first light-emitting control signal line EM1 provides a conduction level, and the fourth transistor M4 is turned on under the control of the first light-emitting control signal line EM1, and the first power supply voltage signal provided by the first power supply voltage signal terminal VDD is transmitted to the first end of the first transistor M1, so as to reset the first end and the second end of the first transistor M1.

[0110] In the second initialization phase T2, the fourth scan signal line S4 provides a low level, and the seventh transistor M7 is turned on under the control of the fourth scan signal line S4, transmitting the reset reference voltage signal provided by the reset reference voltage signal terminal VEH to the first terminal of the first transistor M1, thereby resetting the first terminal and the second terminal of the first transistor M1. The fourth scan signal line S4 provides a conduction level, and the ninth transistor M9 is turned on under the control of the fourth scan signal line S4, transmitting the second reference level voltage provided by the second reference voltage signal terminal Vref2 to the first electrode of the light-emitting element, thereby resetting the first electrode of the light-emitting element.

[0111] During light-emitting phase T3, the first light-emitting control signal line EM1 provides a conduction level, and the fourth transistor M4 is turned on under the control of the first light-emitting control signal line EM1, transmitting the first power supply voltage signal provided by the first power supply voltage signal terminal VDD to the first terminal of the first transistor M1. The second light-emitting control signal line EM2 provides a conduction level, and the tenth transistor M10 is turned on under the control of the second light-emitting control signal line EM2. The first transistor M1 provides a driving current based on the data signal written in the previous data writing frame to drive the light-emitting element to emit light.

[0112] The present embodiment provides a pixel circuit 10, in which, during the threshold compensation stage, the first transistor M1, the second transistor M2, and the fourth transistor M4 are turned on, and the threshold compensation of the driving transistor M1 is performed by the first power supply voltage signal provided by the first power supply voltage signal terminal VDD. During the data writing stage, the second transistor M2 and the third transistor M3 are turned on, and the data signal provided by the data voltage signal terminal Data is coupled to the control terminal of the first transistor M1 through the second capacitor C2. The threshold compensation stage does not overlap with the data writing stage. The present embodiment separates the threshold compensation stage from the data writing stage, so that the threshold compensation time of the pixel circuit 10 is not limited by the row scanning time, and can better achieve brightness uniformity, thereby effectively improving the display effect of the display panel. In addition, the first power supply voltage signal terminal VDD is also used in the present application to charge the gate of the driving transistor M1, which can simultaneously compensate for the voltage drop (IR Drop) caused by the first power supply voltage signal terminal, thereby further achieving the purpose of improving the brightness uniformity of the display panel.

[0113] In addition, the present application utilizes the coupling effect of coupling module 104 to write data signals, enabling more stable data voltage writing to the control terminal of driver module 101. Furthermore, the third transistor M3, which controls data signal writing, actually operates in a linear region, with a high operating current and a short data signal writing time. This results in lower power consumption during the data writing phase compared to conventional 7T1C pixel circuits. Furthermore, a seventh transistor M7 is added in this embodiment to reset the source and drain of the first transistor M1. This can improve stress differences in the first transistor M1 at different refresh rates, thereby reducing mura during refresh rate switching and enhancing the uniformity of the display panel's brightness and the panel's competitiveness.

[0114] It should be noted that the above-mentioned driving timing given in the embodiment of the present application is only a possible example. In some other embodiments, the working timing of the pixel driving circuit can also be flexibly adjusted according to actual conditions and needs, and the present application does not impose any specific restrictions on it.

[0115] Please refer to Figure 14 below, which is a schematic diagram of the structure of another pixel circuit provided in an embodiment of the present application. Figure 14 is substantially identical to Figure 11 , with the following differences: In Figure 14 , to fully reduce the impact of leakage during pixel circuit operation, the second transistor M2 is a dual-gate thin-film transistor, comprising a first sub-transistor and a second sub-transistor. Furthermore, the threshold compensation module 102 may further include a fourth capacitor C4.

[0116] Specifically, as shown in Figure 14, the control terminal of the first sub-transistor is electrically connected to the first scan signal line S1, the first terminal of the first sub-transistor is electrically connected to the control terminal of the driving module 101, and the second terminal of the first sub-transistor is electrically connected to the second electrode of the fourth capacitor C4. The control terminal of the second sub-transistor is electrically connected to the first scan signal line S1, the first terminal of the second sub-transistor is electrically connected to the second electrode of the fourth capacitor C4, and the second terminal of the second sub-transistor is electrically connected to the second terminal of the driving module 101. The first electrode of the fourth capacitor C4 is electrically connected to the first power supply voltage signal terminal VDD.

[0117] In this embodiment, considering that if the threshold compensation tube (second transistor M2) has a large leakage current, the leakage phenomenon of the driving transistor M1 will be more serious, resulting in a large attenuation of the display brightness within a frame, which is not conducive to maintaining the brightness uniformity of the display panel, the above-mentioned second transistor M2 is set to a dual-gate thin film transistor to reduce the leakage current.

[0118] Furthermore, after the second transistor M2 is set as a dual-gate thin-film transistor, considering that when the dual-gate transistor is turned off, if the middle node of the dual-gate transistor (the second end of the above-mentioned first sub-transistor) floats, the potential of the middle node will be easily affected by other signals in the display panel, causing the node potential of the middle node of the dual-gate transistor to be unstable, and the leakage current may still be large, resulting in the display effect of the display panel still not being fully improved.

[0119] For the above considerations, the fourth capacitor C4 is further introduced in this embodiment. The first electrode of the fourth capacitor C4 is electrically connected to the first power supply voltage signal terminal VDD providing a constant voltage. This allows the potential of the middle node of the dual-gate second transistor M2 to remain constant when it is turned off, thereby helping to reduce the leakage current of the second transistor M2, making the gate potential of the first transistor M1 more stable, and helping to avoid problems such as changes in the brightness of the display panel caused by leakage losses of the data signal from the gate of the first transistor M1 and the first capacitor C1. This can improve the display effect of the display panel, especially help to ensure the display effect of the display panel during low-frequency refresh, and is also beneficial to lower-frequency display of the display panel.

[0120] In addition, in this embodiment, the first electrode of the fourth capacitor C4 is electrically connected to the first power supply voltage signal terminal VDD, which can make the node potential of the above-mentioned intermediate node close to the gate potential of the first transistor M1, which is equivalent to reducing the voltage difference between the first terminal and the second terminal of the first sub-transistor. This can further achieve the effect of suppressing the leakage current between the first sub-transistor and the gate of the first transistor M1, and help maintain the stability of the gate potential of the first transistor M1. Therefore, the first transistor M1 can drive the light-emitting element to emit light with a stable driving current during the light-emitting stage, thereby effectively improving the display effect and competitiveness of the display panel.

[0121] It should be understood that the working process and related timing settings of the pixel circuit 10 shown in Figure 14 are basically consistent with the above. Specifically, it can be combined with the timing diagrams shown in Figures 12 and 13 and the corresponding description parts in the above text. This embodiment will not go into details about this.

[0122] Please refer to FIG15 below, which is a schematic diagram of the structure of another pixel circuit provided in an embodiment of the present application. FIG15 is substantially identical to FIG11 in structure. The difference is that in FIG15 , considering the low off-state leakage current of oxide transistors, and to further enhance the display quality of the display panel, the second transistor M2 and the eighth transistor M8 are both indium gallium zinc oxide thin-film transistors. This helps maintain the stability of the gate potential of the drive transistor (first transistor M1), thereby ensuring the stability of the drive current during the light-emitting phase, thereby avoiding problems such as image sticking and low-frequency brightness decay during display operation, thereby improving the display quality of the display panel. Furthermore, to reduce the number of components in the pixel circuit and thereby minimize the cost of the display panel, the pixel circuit 10 shown in FIG15 may not include the fifth transistor M5 and the third capacitor C3, considering that the use of indium gallium zinc oxide thin-film transistors as the threshold compensation transistor (second transistor M2) and the initialization transistor (eighth transistor M8) can effectively suppress leakage in the pixel circuit 10.

[0123] Corresponding to the pixel circuit structure shown in Figure 15, please refer to Figures 16 and 17, which are timing diagrams of another pixel circuit provided in an embodiment of the present application. Figure 16 corresponds to the case where the display frame is a data write frame, and Figure 17 corresponds to the case where the display frame is a hold frame. The timing shown in Figures 16 and 17 corresponds to the pixel circuit shown in Figure 15. In the timing shown in Figures 16 and 17, the conduction level provided by the first scan signal line S1 and the fifth scan signal line S5 is a high level, and the conduction level provided by the remaining signal lines is a low level.

[0124] It should be understood that the working principle and actual working process of the pixel circuit 10 shown in FIG13 are basically similar to those described above. Therefore, for the sake of brevity, the working timing of the pixel circuits shown in FIG16 and FIG17 is not described in detail in this embodiment.

[0125] In addition to the transistors listed above, the pixel circuit 10 of the present application may also include other transistors. These transistors together constitute various types of pixel circuits, and the present application does not impose any specific restrictions on this.

[0126] Based on the pixel circuit provided in the above embodiment, the embodiment of the present application also provides a driving method. The driving method of the embodiment of the present application can be applied to the pixel circuit provided in any of the above embodiments.

[0127] FIG18 is a flow chart of a driving method provided by an embodiment of the present application. As shown in FIG18 , a driving method according to an embodiment of the present application may include the following steps:

[0128] S1801 , before the data writing phase, controlling the node potential of the second end of the coupling module to remain stable; and controlling the threshold compensation phase and the data writing phase to not overlap.

[0129] According to the implementation of the second aspect of the present application, FIG19 is a flow chart of another driving method provided in an embodiment of the present application. As shown in FIG19 , a driving method in an embodiment of the present application may further include:

[0130] S1802: In a threshold compensation stage, the first light-emitting control signal line is controlled to provide an on-level so that the first light-emitting control module is turned on in response to the on-level provided by the first light-emitting control signal line, and the first scanning signal line is controlled to provide an on-level so that the threshold compensation module is turned on in response to the on-level provided by the first scanning signal line, so as to perform threshold compensation on the driving module using the first power supply voltage signal provided by the first power supply voltage signal terminal.

[0131] S1803. In the data writing phase, the first scanning signal line is controlled to provide a conduction level so that the threshold compensation module is turned on in response to the conduction level provided by the first scanning signal line, and the second scanning signal line is controlled to provide a conduction level so that the data writing module is turned on in response to the conduction level provided by the second scanning signal line, so as to couple the data signal provided by the data voltage signal end to the control end of the driving module through the second storage module; wherein the threshold compensation phase and the data writing phase do not overlap.

[0132] In this embodiment, before the pixel circuit enters the data writing phase, the node potential at the second end of the coupling module is controlled to maintain stability. This allows the data signal provided by the data voltage signal terminal to be quickly written during the data writing phase through the coupling effect of the coupling module. Specifically, when maintaining the node potential at the second end of the coupling module stable, the second end of the coupling module can, for example, be electrically connected to a voltage signal line. This voltage signal line can be controlled by a driver chip in the display panel. The driver chip can provide a stable voltage to the second end of the coupling module through this voltage signal line before the data writing phase, and stop transmitting this stable voltage during the data writing phase to facilitate data signal writing. The above is merely an example, and other feasible implementations for controlling and maintaining the stable potential of the second end of the coupling module should also be included within the scope of protection of this application.

[0133] A driving method according to an embodiment of the present application controls the first light-emitting control signal line and the first scanning signal line to provide an on-level voltage during a threshold compensation phase, thereby turning on the first light-emitting control module, the driving module, and the threshold compensation module. This allows threshold compensation for the driving module to be performed using the first power supply voltage signal provided by the first power supply voltage signal terminal. Furthermore, during a data writing phase, which does not overlap with the threshold compensation phase, the first scanning signal line and the second scanning signal line are controlled to provide an on-level voltage to turn on the threshold compensation module and the data writing module. Furthermore, prior to the data writing phase, the node potential at the second terminal of the coupling module is controlled to remain stable, enabling rapid data signal writing via coupling during the data writing phase.

[0134] A driving method according to an embodiment of the present application controls the output levels of each signal line, thereby separating the threshold compensation phase from the data writing phase. This allows the threshold compensation time of the pixel circuit to be unconstrained by the row scanning time, thereby better achieving brightness uniformity and effectively improving the display quality of the display panel. Furthermore, the present application also utilizes a first power supply voltage signal terminal to perform threshold compensation on the driving module, thereby simultaneously compensating for the voltage drop caused by the first power supply voltage signal terminal, thereby further improving the brightness uniformity of the display panel.

[0135] Based on the pixel circuit provided in any of the above embodiments, the present application also provides a display panel, including the pixel circuit provided in any of the above embodiments of the present application. Please refer to Figure 20, which is a structural schematic diagram of a display panel provided in an embodiment of the present application. As shown in Figure 20, the display panel 100 provided in an embodiment of the present application may include the pixel circuit 10 described in any of the above embodiments. The display panel shown in Figure 20 may be an organic light-emitting diode (OLED) display panel.

[0136] Those skilled in the art should understand that in other implementations of the present application, the display panel may also be a micro light emitting diode (Micro LED) display panel, a quantum dot display panel, etc.

[0137] The display panel provided in the embodiment of the present application has the beneficial effects of the pixel circuit 10 provided in the embodiment of the present application. For details, please refer to the specific description of the pixel circuit 10 in the above embodiments, and this embodiment will not be repeated here.

[0138] Based on the display panel provided in the above embodiments, the present application also provides a display device, including the display panel provided in the present application. Please refer to Figure 21, which is a structural schematic diagram of the display device provided in the embodiment of the present application. The display device 1000 provided in Figure 21 includes the display panel 100 provided in any of the above embodiments of the present application. The embodiment of Figure 21 takes a mobile phone as an example to illustrate the display device 1000. It can be understood that the display device provided in the embodiment of the present application can be a wearable product, a computer, a television, a car display device, or other display device with a display function, and the present application does not impose specific restrictions on this. The display device provided in the embodiment of the present application has the beneficial effects of the display panel 100 provided in the embodiment of the present application. For details, please refer to the specific description of the display panel 100 in the above embodiments, and this embodiment will not be repeated here.

[0139] It should be understood that the specific circuit structures and cross-sectional structures of the display panels provided in the drawings of the embodiments of the present application are merely examples and are not intended to limit the present application. In addition, the above embodiments provided in the present application may be combined with each other unless there is any contradiction.

Claims

1. A pixel circuit, comprising: A driving module, used for driving the light-emitting element to emit light; A threshold compensation module, wherein a control end of the threshold compensation module is electrically connected to the first scan signal line, a first end of the threshold compensation module is electrically connected to the control end of the driving module, and a second end of the threshold compensation module is electrically connected to the second end of the driving module; A coupling module, a first end of the coupling module is electrically connected to a second end of the driving module; a data writing module, wherein a control end of the data writing module is electrically connected to the second scanning signal line, a first end of the data writing module is electrically connected to the second end of the coupling module, and a second end of the data writing module is electrically connected to the data voltage signal end; a first light-emitting control module, wherein a control end of the first light-emitting control module is electrically connected to a first light-emitting control signal line, a first end of the first light-emitting control module is electrically connected to a first power supply voltage signal end, and a second end of the first light-emitting control module is electrically connected to a first end of the driving module; Before the data writing stage, the node potential of the second end of the coupling module is kept stable; And, the threshold compensation phase does not overlap with the data writing phase.

2. The pixel circuit according to claim 1, further comprising: a first switch module, wherein a control end of the first switch module is electrically connected to the first scan signal line, a first end of the first switch module is electrically connected to the control end of the driving module, and a second end of the first switch module is electrically connected to the first end of the threshold compensation module; a second storage module, wherein a first end of the second storage module is electrically connected to the first power supply voltage signal end, and a second end of the second storage module is electrically connected to the first end of the threshold compensation module; In the threshold compensation phase and the data writing phase, the first switch module is turned on under the control of the first scanning signal line.

3. The pixel circuit according to claim 2, wherein: The first switch module and the threshold compensation module include transistors of the same channel type.

4. The pixel circuit according to any one of claims 1 to 3, wherein: The pixel circuit further includes: a second switch module, wherein a control end of the second switch module is electrically connected to the third scan signal line, a first end of the second switch module is electrically connected to the second end of the coupling module, and a second end of the second switch module is electrically connected to the initial voltage signal end; In the threshold compensation stage, the second switch module is turned on under the control of the third scan signal line, and the initial voltage signal provided by the initial voltage signal terminal is written into the second terminal of the coupling module to provide a constant voltage for the second terminal of the coupling module.

5. The pixel circuit according to claim 4, wherein: In the first initialization phase before the threshold compensation phase, the second switch module is turned on to write the initial voltage signal provided by the initial voltage signal terminal into the second terminal of the coupling module to initialize the second terminal of the coupling module.

6. The pixel circuit according to claim 4 or 5, wherein: Before the data writing phase, the second switch module is turned on under the control of the third scanning signal line, so that the node potential of the second end of the coupling module remains stable before the data writing phase.

7. The pixel circuit according to any one of claims 4 or 5, wherein: The pixel circuit further includes: A reset module, wherein a control end of the reset module is electrically connected to the fourth scan signal line, a first end of the reset module is electrically connected to the first end of the driving module, and a second end of the reset module is electrically connected to a reset reference voltage signal end; In the second initialization stage, the reset module is turned on to transmit the reset reference voltage signal provided by the reset reference voltage signal terminal to the first terminal of the driving module to reset the first terminal and the second terminal of the driving module.

8. The pixel circuit according to claim 7, wherein: The pixel circuit further includes: a first storage module, wherein a first end of the first storage module is electrically connected to the first power supply voltage signal end, and a second end of the first storage module is electrically connected to the control end of the driving module; A first initialization module, wherein a control end of the first initialization module is electrically connected to the fifth scanning signal line, and the first initialization module The first end of the block is electrically connected to the first end of the threshold compensation module, and the second end of the first initialization module is electrically connected to the first reference voltage signal end; a second initialization module, wherein a control end of the second initialization module is electrically connected to the fourth scanning signal line, a first end of the second initialization module is electrically connected to the first electrode of the light-emitting element, and a second end of the second initialization module is electrically connected to a second reference voltage signal end; A second light-emitting control module, wherein the control end of the second light-emitting control module is electrically connected to the second light-emitting control signal line, the first end of the second light-emitting control module is electrically connected to the second end of the driving module, and the second end of the second light-emitting control module is electrically connected to the first pole of the light-emitting element.

9. The pixel circuit according to claim 8, wherein: In the first initialization stage, the first initialization module is turned on to transmit the first reference level voltage provided by the first reference voltage signal terminal to the second electrode of the first storage module to initialize the second electrode of the first storage module; In the second initialization stage, the second initialization module is turned on to transmit the second reference level voltage provided by the second reference voltage signal terminal to the first electrode of the light emitting element to reset the first electrode of the light emitting element.

10. The pixel circuit according to claim 8 or 9, wherein: The pixel circuit further includes the second storage module; In the first initialization stage, the first initialization module is turned on to transmit the first reference level voltage provided by the first reference voltage signal terminal to the second electrode of the second storage module to initialize the second electrode of the second storage module.

11. The pixel circuit according to any one of claims 8 to 10, wherein: Display frames are divided into data writing frames and holding frames; When the display frame is the data writing frame, the working phases of the pixel circuit include the first initialization phase, the threshold compensation phase, the data writing phase, the second initialization phase and the light emitting phase; In the light-emitting stage, the first light-emitting control module is turned on to transmit the first power supply voltage signal provided by the first power supply voltage signal terminal to the first terminal of the driving module; the second light-emitting control module is turned on to write the voltage of the second terminal of the driving module into the first electrode of the light-emitting element; When the display frame is the holding frame, the working phase of the pixel circuit includes the second initialization phase and the light emitting phase.

12. The pixel circuit according to claim 11, wherein: When the display frame is the holding frame, the working phase of the pixel circuit further includes a reset phase; In the reset stage, the first light-emitting control module is turned on to transmit the first power supply voltage signal provided by the first power supply voltage signal terminal to the first terminal of the driving module to reset the first terminal and the second terminal of the driving module.

13. The pixel circuit according to claim 1, wherein: The driving module includes a first transistor, the threshold compensation module includes a second transistor, the data writing module includes a third transistor, the first light emitting control module includes a fourth transistor, and the coupling module includes a second capacitor; The control end of the second transistor is electrically connected to the first scan signal line, the first end of the second transistor is electrically connected to the control end of the first transistor, the second end of the second transistor is electrically connected to the second end of the first transistor; the first electrode of the second capacitor is electrically connected to the second end of the first transistor; The control end of the third transistor is electrically connected to the second scan signal line, the first end of the third transistor is electrically connected to the second electrode of the second capacitor, and the second end of the third transistor is electrically connected to the data voltage signal end; The control end of the fourth transistor is electrically connected to the first light emitting control signal line, the first end of the fourth transistor is electrically connected to the first power supply voltage signal end, and the second end of the fourth transistor is electrically connected to the first end of the first transistor.

14. The pixel circuit according to claim 13, wherein: The second transistor is a dual-gate thin film transistor, and the second transistor includes a first sub-transistor and a second sub-transistor; the threshold compensation module also includes a fourth capacitor; The control end of the first sub-transistor is electrically connected to the first scanning signal line, the first end of the first sub-transistor is electrically connected to the control end of the first transistor, and the second end of the first sub-transistor is electrically connected to the second electrode of the fourth capacitor; The control end of the second sub-transistor is electrically connected to the first scanning signal line, the first end of the second sub-transistor is electrically connected to the second electrode of the fourth capacitor, and the second end of the second sub-transistor is electrically connected to the second end of the first transistor; A first electrode of the fourth capacitor is electrically connected to the first power supply voltage signal terminal.

15. The pixel circuit according to claim 13 or 14, wherein: The pixel circuit further includes a first storage module, a first switch module, a second storage module, a second switch module, a reset module, a first initialization module, a second initialization module, and a second light-emitting control module; the first storage module includes a first capacitor, the first switch module includes a fifth transistor, the second storage module includes a third capacitor, the second switch module includes a sixth transistor, the reset module includes a seventh transistor, the first initialization module includes an eighth transistor, the second initialization module includes a ninth transistor, and the second light-emitting control module includes a tenth transistor; A first electrode of the first capacitor is electrically connected to the first power supply voltage signal terminal, and a second electrode of the first capacitor is electrically connected to the control terminal of the first transistor; The control end of the fifth transistor is electrically connected to the first scan signal line, the first end of the fifth transistor is electrically connected to the control end of the first transistor, and the second end of the fifth transistor is electrically connected to the first end of the second transistor; A first electrode of the third capacitor is electrically connected to the first power supply voltage signal terminal, and a second electrode of the third capacitor is electrically connected to the first terminal of the second transistor; The control end of the sixth transistor is electrically connected to the third scan signal line, the first end of the sixth transistor is electrically connected to the first electrode of the second capacitor, and the second end of the sixth transistor is electrically connected to the initial voltage signal end; The control end of the seventh transistor is electrically connected to the fourth scan signal line, the first end of the seventh transistor is electrically connected to the first end of the first transistor, and the second end of the seventh transistor is electrically connected to the reset reference voltage signal end; The control end of the eighth transistor is electrically connected to the fifth scan signal line, the first end of the eighth transistor is electrically connected to the first end of the second transistor, and the second end of the eighth transistor is electrically connected to the first reference voltage signal end; The control end of the ninth transistor is electrically connected to the fourth scan signal line, the first end of the ninth transistor is electrically connected to the first electrode of the light emitting element, and the second end of the ninth transistor is electrically connected to the second reference voltage signal end; The control end of the tenth transistor is electrically connected to the second light emitting control signal line, the first end of the tenth transistor is electrically connected to the second end of the driving module, and the second end of the tenth transistor is electrically connected to the first electrode of the light emitting element.

16. The pixel circuit according to claim 15, wherein: The eighth transistor is a dual-gate thin film transistor.

17. The pixel circuit according to claim 15, wherein: The second transistor and the eighth transistor are both indium gallium zinc oxide thin film transistors.

18. A method for driving a pixel circuit, applied to the pixel circuit according to any one of claims 1 to 17; the method comprising: Before the data writing phase, the node potential of the second end of the coupling module is controlled to be stable; Furthermore, the threshold compensation phase is controlled not to overlap with the data writing phase.

19. The method according to claim 18, wherein: The method further comprises: In the threshold compensation stage, the first light-emitting control signal line is controlled to provide a conduction level, so that the first light-emitting control module is turned on in response to the conduction level provided by the first light-emitting control signal line, and the first scanning signal line is controlled to provide a conduction level, so that the threshold compensation module is turned on in response to the conduction level provided by the first scanning signal line, so as to perform threshold compensation on the driving module through the first power supply voltage signal provided by the first power supply voltage signal terminal; In the data writing stage, the first scanning signal line is controlled to provide a conduction level so that the threshold compensation module is turned on in response to the conduction level provided by the first scanning signal line, and the second scanning signal line is controlled to provide a conduction level so that the data writing module is turned on in response to the conduction level provided by the second scanning signal line, so as to couple the data signal provided by the data voltage signal end to the control end of the driving module through the second storage module; the threshold compensation stage does not overlap with the data writing stage.

20. A display panel comprising the pixel circuit according to any one of claims 1 to 17.

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