Semiconductor device and method for manufacturing semiconductor device

Abstract

The objective of the present invention is to provide a technology that can suppress cracking of an insulating substrate even when a product warps after transfer molding. Provided is a semiconductor device comprising: an insulating substrate having an insulating layer, a front surface pattern, and a back surface pattern; a semiconductor element mounted on the front surface pattern; and a mold resin that seals the insulating substrate and the semiconductor element in a state in which the surface of the back surface pattern on the opposite side of the surface thereof that opposes the insulating layer is exposed. The back surface pattern is joined to a heatsink through use of solder, the surface of the back surface pattern that is joined to the heat sink is located at the same height as the surface of the mold resin that opposes the heatsink, the front surface pattern is provided with a first slit for dividing the front surface pattern into a plurality of regions, the back surface pattern is provided with a second slit for dividing the back surface pattern into a plurality of regions. The first slit and the second slit do not overlap or only partially overlap as viewed from the thickness direction of the insulating substrate.

Description

Semiconductor device and method for manufacturing the same

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] For example, Patent Document 1 discloses a semiconductor device including a plurality of wiring layers (corresponding to front surface patterns), an insulating substrate (corresponding to insulating layer) to which first back surfaces of the plurality of wiring layers are bonded, a plurality of heat dissipation layers (corresponding to back surface patterns) having second main surfaces bonded to the insulating substrate, a semiconductor element bonded to any of the first main surfaces of the plurality of wiring layers, and a sealing resin covering the insulating substrate, the plurality of wiring layers, and the semiconductor element. By arranging the plurality of wiring layers bonded to the front surface of the insulating substrate and the plurality of heat dissipation layers bonded to the back surface of the insulating substrate so as to overlap when viewed in the thickness direction of the insulating substrate, the difference in the amount of expansion and contraction between the front side and the back side of the insulating substrate due to temperature changes is reduced, thereby suppressing warping of the insulating substrate.

[0003] International Publication No. 2020 / 149225

[0004] However, the technology described in Patent Document 1 does not take into consideration warpage of the product that occurs after transfer molding. In particular, because the slits that divide the insulating substrate into multiple wiring layers on the front side and the slits that divide the insulating substrate into multiple heat dissipation layers on the back side are located in the same position when viewed from the thickness direction of the insulating substrate, there is a problem that the entire substrate including the multiple wiring layers and multiple heat dissipation layers is prone to bending and cracking.

[0005] Therefore, an object of the present disclosure is to provide a technique that can prevent cracking of an insulating substrate even when warpage occurs in a product after transfer molding.

[0006] The semiconductor device according to the present disclosure comprises an insulating substrate having an insulating layer, a surface pattern formed on the surface of the insulating layer, and a back surface pattern formed on the back surface of the insulating layer, a semiconductor element mounted on the surface pattern, and a sealing resin that seals the insulating substrate and the semiconductor element while exposing a surface of the back surface pattern opposite to a surface facing the insulating layer, wherein the back surface pattern is soldered to a heat sink, the surface of the back surface pattern that is joined to the heat sink is located at the same height as a surface of the sealing resin that faces the heat sink, the front surface pattern has a first slit for dividing the front surface pattern into a plurality of regions, and the back surface pattern has a second slit for dividing the back surface pattern into a plurality of regions, and when viewed from the thickness direction of the insulating substrate, the first slit and the second slit do not overlap or only partially overlap.

[0007] According to the present disclosure, when viewed from the thickness direction of the insulating substrate, the overlapping area between the first slit on the front side of the insulating substrate and the second slit on the back side is reduced, thereby preventing the insulating substrate from cracking even if warping occurs in the product after transfer molding.

[0008] The objects, features, aspects, and advantages of the present disclosure will become more apparent from the following detailed description and the accompanying drawings.

[0009] FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment. FIG. 2 is a flowchart showing a manufacturing method of a semiconductor device according to an embodiment. FIG. 3 is a cross-sectional view showing a die bonding process in an embodiment. FIG. 4 is a cross-sectional view showing a lead bonding process in an embodiment. FIG. 5 is a cross-sectional view showing a wire bonding process in an embodiment. FIG. 6 is a cross-sectional view showing a molding process in an embodiment. FIG. 7 is a cross-sectional view showing a solder mounting process in an embodiment. FIG. 8 is a cross-sectional view of a semiconductor device for explaining the occurrence of solder voids in an embodiment. FIG. 9 is a bottom view showing an example of an insulating substrate provided in a semiconductor device according to an embodiment. FIG. 10 is a bottom view showing another example of an insulating substrate provided in a semiconductor device according to an embodiment. FIG. 11 is an enlarged cross-sectional view of the periphery of a second slit provided in a back surface pattern provided in a semiconductor device according to an embodiment. FIG. 12 is an enlarged cross-sectional view of the periphery of a second slit provided in a back surface pattern provided in a semiconductor device according to a modified embodiment. FIG. 13 is a cross-sectional view of a semiconductor device for explaining the occurrence of solder voids in a related art.

[0010] <Embodiments> <Configuration of Semiconductor Device> An embodiment will be described below with reference to the drawings. Fig. 1 is a cross-sectional view of a semiconductor device according to an embodiment.

[0011] As shown in FIG. 1, the semiconductor device includes an insulating substrate 1, a plurality of semiconductor elements 2, a plurality of lead frames 3, and a molding resin 5 as a sealing resin.

[0012] The insulating substrate 1 includes an insulating layer 1a, a front surface pattern 1b, and a back surface pattern 1c. The insulating layer 1a is made of ceramics. The front surface pattern 1b is made of a metal such as copper or aluminum and is formed on the front surface of the insulating layer 1a. The front surface pattern 1b is provided with first slits 6 for dividing the front surface pattern 1b into multiple regions. The back surface pattern 1c is made of a metal such as copper or aluminum and is formed on the back surface of the insulating layer 1a. The back surface pattern 1c is provided with second slits 7 for dividing the back surface pattern 1c into multiple regions. The second slits 7 are provided in a lattice pattern when viewed from the thickness direction of the insulating substrate 1. The second slits 7 are also provided so as to surround the periphery of the semiconductor element 2 when viewed from the thickness direction of the insulating substrate 1.

[0013] The semiconductor elements 2 are mounted on the surface pattern 1b via solder 4. The semiconductor elements 2 are elements that function as, for example, switching elements or rectifying elements. The switching elements are, for example, insulated gate bipolar transistors (IGBTs) or metal-oxide-semiconductor field-effect transistors (MOSFETs). The rectifying elements are diode elements.

[0014] The material constituting the plurality of semiconductor elements 2 is, for example, silicon (Si). Note that the material constituting the plurality of semiconductor elements 2 is not limited to silicon, and may be, for example, a wide bandgap semiconductor material such as silicon carbide (SiC), gallium nitride (GaN), or diamond (C). A wide bandgap semiconductor material is a material having a bandgap wider than that of Si. The plurality of semiconductor elements 2 made of a wide bandgap semiconductor material can operate using a large current and in a high-temperature environment. For this reason, it is preferable that the material constituting the plurality of semiconductor elements 2 be a wide bandgap semiconductor material.

[0015] The lead frames 3 are made of, for example, copper. The lead frames 3 are bonded to the surface electrodes of the semiconductor element 2 with solder 4, bonded to the surface pattern 1 b with solder 4, and connected to the wire pads of the semiconductor element 2 via aluminum wires 8.

[0016] The molding resin 5 is, for example, an epoxy-based thermosetting resin, and seals the insulating substrate 1 and the semiconductor element 2 while leaving the surface of the back surface pattern 1 c opposite to the surface facing the insulating layer 1 a exposed.

[0017] Here, the semiconductor device is bonded to a heat sink 10 (see Figure 7), but the surface of the back surface pattern 1c that is bonded to the heat sink 10 is located at the same height as the surface of the molded resin 5 that faces the heat sink 10, so no step is created between the back surface pattern 1c and the molded resin 5.

[0018] <Method of Manufacturing a Semiconductor Device> Next, a method of manufacturing a semiconductor device will be described with reference to FIGS. 2 to 7. FIG. 2 is a flowchart showing a method of manufacturing a semiconductor device according to an embodiment. FIG. 3 is a cross-sectional view showing a die bonding process in the embodiment. FIG. 4 is a cross-sectional view showing a lead bonding process in the embodiment. FIG. 5 is a cross-sectional view showing a wire bonding process in the embodiment. FIG. 6 is a cross-sectional view showing a molding process in the embodiment. FIG. 7 is a cross-sectional view showing a solder mounting process in the embodiment. Note that FIG. 2 simply illustrates the main steps of the method of manufacturing a semiconductor device.

[0019] 2 and 3, in step S1, solder 4 is placed on the surface pattern 1b of the insulating substrate 1, the semiconductor element 2 is mounted thereon, and the solder 4 is melted by reflow or the like to bond the semiconductor element 2 to the insulating substrate 1. Note that although the embodiment uses solder 4 as an example for bonding, this is not limiting and sintering using silver or copper may also be used.

[0020] Next, as shown in Figures 2 and 4, in step S2, solder 4 is placed on the surface electrodes of the semiconductor element 2 and the surface pattern 1b, and the lead frame 3 is placed on top of them and the solder 4 is melted by reflow or the like, thereby joining the surface electrodes of the semiconductor element 2 to the lead frame 3 and also joining the surface pattern 1b to the lead frame 3.

[0021] Next, as shown in FIGS. 2 and 5, in step S3, the wire pads of the semiconductor element 2 and the signal terminals of the lead frame 3 are ultrasonically bonded with aluminum wires 8 having a wire diameter of about 100 to 400 μm.

[0022] 2 and 6, in step S4, the wire-bonded product and a tablet-shaped resin that will be the material for molding resin 5 are placed in the lower mold of a metal mold (not shown), the upper mold is closed, and the resin is gelled at a high temperature of about 180°C, and then pressure is applied to force the resin through the runner and gate into the space (cavity) within the metal mold. The gelled resin hardens again at high temperature to become molding resin 5 that has the same shape as the cavity. This is then removed from the metal mold.

[0023] Next, as shown in Figures 2 and 7, in step S5, solder 11 and the semiconductor device, which is a molded product, are placed on heat sink 10, which is a heat dissipation member, and solder 11 is melted by reflow or the like to join the semiconductor device and heat sink 10.

[0024] Among the above steps, the insulating substrate 1 is exposed to high temperatures during the die bonding step (step S1), lead bonding step (step S2), molding step (step S4), and solder mounting step (step S5). Because the ceramics constituting the insulating layer 1a of the insulating substrate 1 is a brittle material, it has low bending resistance, and it is important to minimize warping during each step.

[0025] However, since the insulating substrate 1 requires electrical conductivity and heat dissipation for its functionality, a front surface pattern 1b and a back surface pattern 1c are bonded and patterned on the front and back surfaces, respectively. Copper is generally used for the front surface pattern 1b and the back surface pattern 1c because of its superior performance. Copper is a highly rigid material and has a different linear expansion coefficient from ceramics. Therefore, if the front and back surfaces of the insulating layer 1a are not balanced, warping occurs with temperature changes. The front surface pattern 1b is generally divided into multiple regions by first slits 6 to allow electrical conductivity, resulting in lower rigidity than the undivided front surface pattern 1b. To balance out the lowered rigidity of the front surface pattern 1b, second slits 7 are provided in the back surface pattern 1c, thereby reducing its rigidity.

[0026] Furthermore, because the back surface pattern 1c serves as a heat dissipation path for transmitting heat generated from the semiconductor element 2 to the heat sink 10, the second slits 7 are not provided directly below the semiconductor element 2 but are provided around the area directly below the semiconductor element 2. In other words, the second slits 7 are provided so as to surround the area of ​​the front surface pattern 1b corresponding to the location where the semiconductor element 2 is mounted.

[0027] Next, we will explain solder voids 12 that occur in solder 11. Figure 13 is a cross-sectional view of a semiconductor device to explain the occurrence of solder voids 12 in the related art. Figure 8 is a cross-sectional view of a semiconductor device to explain the occurrence of solder voids 12 in the embodiment.

[0028] If air is entrained during soldering to the heat sink 10 and remains in the solder 11, it becomes a solder void 12 that inhibits heat dissipation, as shown in Figure 13. The smaller the area of ​​the joining member joined to the heat sink 10, the easier it is for the solder void 12 to escape, but it is difficult for it to escape from a joining member with a large area, such as the insulating substrate 1. However, even within the large area of ​​the insulating substrate 1, the area directly below the semiconductor element 2 primarily contributes to heat dissipation. Therefore, if the solder void 12 can be evacuated to the second slit 7 provided in the back surface pattern 1c, as shown in Figure 8, the impact on heat dissipation is reduced, resulting in a semiconductor device with excellent heat dissipation. Because the location where the solder void 12 occurs is not specific, creating a reduced-pressure atmosphere or rocking the device further enhances the evacuating effect of the solder void 12 from directly below the semiconductor element 2.

[0029] As described above, in order to discharge the solder voids 12 into the second slit 7, it is necessary to prevent the second slit 7 from being filled with the molding resin 5. When setting the wire-bonded product in the lower mold of the mold, it is necessary to position it using the lead frame 3. This is because the mold is machined so that there is no gap between the lead frame 3 and the mold to prevent resin leakage when the upper and lower molds are closed and the resin is injected into the cavity. However, slight misalignment occurs depending on the precision and clearance of the jig used to join the lead frame 3 and the insulating substrate 1 with the solder 4. Therefore, although it is possible to bring the insulating substrate 1 into contact only with the surface of the lower mold, it is difficult to fit the periphery of the back surface pattern 1c into the lower mold without any gaps.

[0030] Therefore, by connecting only the outermost periphery of the back surface pattern 1c without completely dividing it like the front surface pattern 1b, it is possible to prevent the molding resin 5 from flowing into the second slit 7. The width of the connected portion of the outermost periphery of the back surface pattern 1c depends on the pressure when the resin is injected and the flatness of the insulating substrate 1, but it is preferable that it be about 1 mm.

[0031] 9 is a bottom view showing an example of an insulating substrate 1 included in a semiconductor device according to an embodiment. FIG. 10 is a bottom view showing another example of an insulating substrate 1 included in a semiconductor device according to an embodiment. As shown in FIG. 9 , if the outermost periphery of the back surface pattern 1c is not connected, it is necessary to suppress the inflow of resin from the outermost periphery of the back surface pattern 1c by pressing a cushioning sheet or the like against the back surface pattern 1c during transfer molding. However, this becomes more difficult as the thickness of the back surface pattern 1c increases. As shown in FIG. 10 , because the back surface pattern 1c is connected at the outermost periphery, a cushioning sheet or the like is not required, and therefore it is possible to suppress the inflow of resin without any restriction on the thickness of the back surface pattern 1c.

[0032] As explained above, suppressing warpage of the insulating substrate 1 alone is important, but even if warpage occurs in the product after transfer molding, it is also important to suppress cracking of the insulating substrate 1. Warpage of the product after transfer molding is caused by differences in expansion and contraction between the mold resin 5 and the insulating substrate 1. Therefore, it is important to make the linear expansion coefficients of the mold resin 5 and the insulating substrate 1 similar.

[0033] The main components that determine the mechanical properties such as the linear expansion coefficient of mold resin 5 are resin and filler, and the linear expansion coefficient can be reduced by increasing the filler ratio. However, if the filler ratio is too high, the fluidity of the resin deteriorates during transfer molding, so in reality, the filler ratio is adjusted so that the linear expansion coefficient is in the range of 10 ppm / °C to 20 ppm / °C.

[0034] On the other hand, if the insulating substrate 1 is a composite of ceramics (insulating layer 1a) and front and back copper patterns (front pattern 1b and back pattern 1c), the linear expansion coefficient can be adjusted by changing the thickness. For example, silicon nitride is often used as the ceramic, and its linear expansion coefficient is 3.5 ppm / °C, while the copper pattern has a linear expansion coefficient of 16.7 ppm / °C. The linear expansion coefficient of these composites will be a value between these, and which value it approaches is determined by the ratio of their respective rigidities. The rigidity ratio can be approximated by the ratio of the product of the respective volumes and elastic moduli.

[0035] The linear expansion coefficient of mold resin 5, 10 ppm / °C, is intermediate between the linear expansion coefficients of silicon nitride and copper, and it is sufficient if the rigidity of each is equivalent. The elastic modulus of silicon nitride is 300 GPa, the elastic modulus of copper is 117 GPa, the thickness of silicon nitride is t1, the thickness of copper is t2, and the area ratio of copper varies depending on the design specifications but is assumed to be approximately 90%, so 300 × t1 × 1 = 117 × t2 × 0.9, or t2 = 300 / (117 × 0.9) × t1 ≈ 2.85 × t1.

[0036] In other words, if the total thickness of the copper patterns on the front and back is 2.8 times the thickness of the ceramic, or 1.4 times the thickness of the copper patterns on the front and back if they are the same thickness, the linear expansion coefficient will be about 10 ppm / °C. By further increasing the thickness of the copper pattern, it can be made greater than 10 ppm / °C, and by making it copper-rich, the linear expansion coefficient can theoretically be made as close as possible to that of copper. However, considering the manufacturing constraints of the insulating substrate 1 and the size constraints of the semiconductor device, the thickness of the copper patterns on the front and back is thought to be approximately 3 to 3.5 times the thickness of the ceramic.

[0037] Warping of the insulating substrate 1 itself and warping of the product after transfer molding cannot be eliminated, so it is important to make the insulating layer 1a made of ceramic, which is a brittle material, less likely to crack.

[0038] When no slits are provided in the front and back patterns 1b and 1c, the front and back patterns 1b and 1c protect the insulating layer 1a and are resistant to bending. On the other hand, when slits are provided, the difference in rigidity between the portion with the front pattern 1b (or back pattern 1c) and the portion with the first slit 6 (or second slit 7) is large, so bending occurs in the portion with the first slit 6 (or second slit 7), making it more likely to crack. When the first slit 6 and the second slit 7 overlap when viewed from the thickness direction of the insulating substrate 1, it is even more likely to crack.

[0039] To solve this problem, in the embodiment, the first slits 6 and the second slits 7 do not overlap or only partially overlap when viewed from the thickness direction of the insulating substrate 1. Hereinafter, a case where the first slits 6 and the second slits 7 only partially overlap will be described. The first slits 6 and the second slits 7 each have at least one straight line portion. When the first slits 6 and the second slits 7 partially overlap when viewed from the thickness direction of the insulating substrate 1, the length of the overlapping portion between the predetermined straight line portion of the first slits 6 and the predetermined straight line portion of the second slits 7 when viewed from the thickness direction of the insulating substrate 1 is 50% or less of the sum of the lengths of the predetermined straight line portions of the first slits 6 and the second slits 7. In FIGS. 9 and 10 , the second slits 7 are formed in a lattice pattern and have a plurality of straight line portions.

[0040] In this way, by reducing the overlapping portion between the first slit 6 and the second slit 7, a structure can be achieved in which the insulating substrate 1 is less likely to crack even if warping occurs in the product after transfer molding.

[0041] <Effects> As described above, the semiconductor device according to the embodiment includes an insulating substrate 1 having an insulating layer 1 a, a front pattern 1 b formed on the front surface of the insulating layer 1 a, and a back pattern 1 c formed on the back surface of the insulating layer 1 a, a semiconductor element 2 mounted on the front pattern 1 b, and a molded resin 5 that seals the insulating substrate 1 and the semiconductor element 2 while exposing a surface of the back pattern 1 c opposite to a surface facing the insulating layer 1 a. The back pattern 1 c is joined to a heat sink 10 with solder 11, the surface of the back pattern 1 c joined to the heat sink 10 is located at the same height as the surface of the molded resin 5 facing the heat sink 10, the front pattern 1 b is provided with first slits 6 for dividing the front pattern 1 b into a plurality of regions, and the back pattern 1 c is provided with second slits 7 for dividing the back pattern 1 c into a plurality of regions, and the first slits 6 and the second slits 7 do not overlap or only partially overlap when viewed from the thickness direction of the insulating substrate 1.

[0042] Specifically, both the first slit 6 and the second slit 7 have at least one straight line portion, and when viewed from the thickness direction of the insulating substrate 1, the length of the overlapping portion between a predetermined straight line portion of at least one straight line portion of the first slit 6 and a predetermined straight line portion of at least one straight line portion of the second slit 7 is 50% or less of the sum of the length of the predetermined straight line portion of the first slit 6 and the length of the predetermined straight line portion of the second slit 7.

[0043] Therefore, when viewed from the thickness direction of the insulating substrate 1, the overlapping portion between the first slits 6 on the front side of the insulating substrate 1 and the second slits 7 on the back side is small, so that even if the product warps after transfer molding, cracking of the insulating substrate 1 can be suppressed. As a result, the semiconductor device can be used for a long period of time.

[0044] Furthermore, since the second slits 7 are not filled with the molding resin 5, solder voids 12 remaining in the solder 4 at the time of soldering can be discharged to the second slits 7. This allows the heat generated from the semiconductor element 2 to be dissipated efficiently.

[0045] Furthermore, since the rear surface pattern 1c is connected at the outermost periphery thereof, it is possible to prevent the molding resin 5 from flowing into the second slits 7 during transfer molding.

[0046] Furthermore, since the second slits 7 surround the periphery of the position on the surface pattern 1b corresponding to the location where the semiconductor element 2 is mounted, solder voids 12 are less likely to occur directly below the semiconductor element 2. This improves the heat dissipation performance of the semiconductor device.

[0047] Furthermore, the thickness of both the front surface pattern 1b and the back surface pattern 1c is 1.4 times or more the thickness of the insulating layer 1a, which increases the effect of suppressing warpage of the insulating substrate 1 and, in turn, increases the effect of suppressing warpage of the product after transfer molding.

[0048] Furthermore, since the semiconductor element 2 is a wide bandgap semiconductor element, it can operate at higher temperatures than a Si semiconductor element, but since the heat dissipation effect of the semiconductor device can be improved as described above, it is possible to suppress the temperature rise of the semiconductor element 2. This makes it possible to suppress loss in the semiconductor element 2.

[0049] Furthermore, although SiC MOSFETs can operate at high temperatures, their loss deteriorates significantly at high temperatures, so it is desirable to use them at temperatures as low as possible. The configuration of the semiconductor device according to the embodiment is particularly suitable for SiC MOSFETs, as it can efficiently transfer heat generated from the semiconductor element 2 to the heat sink 10 and suppress a temperature rise of the semiconductor element 2.

[0050] <Modification of the embodiment> Next, a modification of the embodiment will be described. Fig. 11 is an enlarged cross-sectional view of the periphery of a second slit 7 provided in a back surface pattern 1c of a semiconductor device according to the embodiment. Fig. 12 is an enlarged cross-sectional view of the periphery of a second slit 7 provided in a back surface pattern 1c of a semiconductor device according to the modification of the embodiment.

[0051] In a semiconductor device, a high voltage may be applied to the front and back sides of the insulating substrate 1. For example, in an electric vehicle, the voltage may be about 400 V to 1000 V. As shown in Figure 11, if the second slit 7 is formed through the back pattern 1c to the back surface of the insulating layer 1a, and if a solder void 12 (see Figure 8) exists in the second slit 7, the solder void 12 may come into contact with the insulating layer 1a, causing a partial discharge 13 to occur from the insulating layer 1a.

[0052] To avoid this problem, in the modified example of the embodiment, the second slits 7 do not penetrate the rear surface pattern 1c and do not reach the rear surface of the insulating layer 1a, as shown in Fig. 12. In other words, the rear surface pattern 1c is in close contact with the rear surface of the insulating layer 1a even in the area where the second slits 7 are provided.

[0053] Next, a description will be given of a manufacturing method of the insulating substrate 1. There are two methods: one is to attach a rear surface pattern 1c on which the second slits 7 have been formed by punching using a press or the like to the insulating layer 1a, and the other is to attach a rear surface pattern 1c on which the second slits 7 have not been formed, and then to form the second slits 7 by melting copper by etching and patterning it, and the latter manufacturing method is generally adopted.

[0054] In the rear surface pattern 1c, portions where the second slits 7 are not to be formed are masked, and an etching solution is sprayed and dissolved only in the portions where the second slits 7 are to be formed, thereby forming a pattern. Normally, the insulating layer 1a is exposed in the etched portions, but in this modified embodiment, the second slits 7 are formed by half-etching, which stops etching partway through the thickness of the insulating substrate 1 when etching the rear surface pattern 1c. Therefore, the insulating layer 1a is not exposed in the etched portions. As a result, the solder voids 12 do not come into contact with the insulating layer 1a, thereby suppressing the occurrence of partial discharges 13.

[0055] Although this disclosure has been described in detail, the above description is illustrative in all respects and is not restrictive. It is understood that countless variations not illustrated can be envisioned.

[0056] It should be noted that the embodiments can be freely combined, and each embodiment can be modified or omitted as appropriate.

[0057] REFERENCE SIGNS LIST 1 insulating substrate, 1a insulating layer, 1b front surface pattern, 1c rear surface pattern, 2 semiconductor element, 5 molding resin, 6 first slit, 7 second slit, 10 heat sink, 11 solder

Claims

1. A semiconductor device comprising: an insulating substrate having an insulating layer, a surface pattern formed on a surface of the insulating layer, and a back pattern formed on a back surface of the insulating layer; a semiconductor element mounted on the surface pattern; and a sealing resin that seals the insulating substrate and the semiconductor element with a surface of the back pattern opposite to a surface facing the insulating layer being exposed, wherein the back pattern is joined to a heat sink with solder, a surface of the back pattern that is joined to the heat sink is located at the same height as a surface of the sealing resin that faces the heat sink, the front pattern is provided with a first slit for dividing the front pattern into a plurality of regions, and the back pattern is provided with a second slit for dividing the back pattern into a plurality of regions, and when viewed from the thickness direction of the insulating substrate, the first slit and the second slit do not overlap or only partially overlap.

2. The semiconductor device according to claim 1, wherein the second slit is not filled with the sealing resin.

3. The semiconductor device according to claim 1 or 2, wherein the rear surface pattern is connected at the outermost periphery of the rear surface pattern.

4. The semiconductor device according to any one of claims 1 to 3, wherein the second slit surrounds a position on the surface pattern that corresponds to the location where the semiconductor element is mounted.

5. A semiconductor device as described in any one of claims 1 to 4, wherein both the first slit and the second slit have at least one straight portion, and when viewed in the thickness direction of the insulating substrate, the length of an overlapping portion between a predetermined one of the at least one straight portion of the first slit and a predetermined one of the at least one straight portion of the second slit is 50% or less of the sum of the length of the predetermined straight portion of the first slit and the length of the predetermined straight portion of the second slit.

6. The semiconductor device according to claim 1, wherein the thickness of each of the front and rear patterns is at least 1.4 times the thickness of the insulating layer.

7. The semiconductor device according to claim 1, wherein the second slit is not formed to reach the rear surface of the insulating layer without penetrating the rear surface pattern.

8. The semiconductor device according to any one of claims 1 to 7, wherein the semiconductor element is a wide band gap semiconductor element.

9. A method for manufacturing a semiconductor device as described in claim 7, wherein the second slit is formed by half-etching, which stops etching midway through the thickness direction of the insulating substrate when etching the rear surface pattern.

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