Semiconductor device manufacturing method and semiconductor substrate

Abstract

[Problem] To provide a semiconductor device manufacturing method and a semiconductor substrate in which a mark of the semiconductor substrate can be identified with certainty. [Solution] A semiconductor device manufacturing method according to the present embodiment involves forming a first mark (10) that is recessed in a first direction approximately orthogonal to a first surface of an SiC substrate, is surrounded on the first surface by first and third sides, extending in a second direction orthogonal to the first direction, and second and fourth sides, extending in a third direction orthogonal to the first and second directions, and has, in the first side, at least one recessed pattern recessed in the third direction from the first side toward the third side opposite the first side. An SiC layer is epitaxially grown on the first mark (10) of the SiC substrate.

Description

Semiconductor device manufacturing method and semiconductor substrate

[0001] The present embodiment relates to a method for manufacturing a semiconductor device and a semiconductor substrate.

[0002] Silicon carbide (SiC) has a larger band gap than silicon, resulting in high breakdown field strength and low on-resistance, and therefore SiC semiconductors are being developed as materials for power semiconductor devices.

[0003] When forming semiconductor elements on a SiC substrate, marks such as alignment marks are required. After forming the marks on the SiC substrate, a SiC epitaxial layer may be grown on the surface of the SiC substrate. In this process, specific crystal planes called facets appear in the SiC epitaxial layer, causing the marks on the SiC substrate to appear blurred and distorted in images. This can make it difficult to identify the marks in images in each process, potentially making pattern alignment and other tasks difficult.

[0004] Japanese Patent No. 6705670 Japanese Patent No. 6696248 JP 2015-207595 A Japanese Patent No. 6041292 JP 2000-252189 A

[0005] A method for manufacturing a semiconductor device and a semiconductor substrate that allow marks on the semiconductor substrate to be reliably identified are provided.

[0006] The method for manufacturing a semiconductor device according to the present embodiment includes forming a first mark having at least one recessed pattern recessed in a first direction substantially perpendicular to a first surface of a SiC substrate, the first mark being surrounded on the first surface by first and third sides extending in a second direction orthogonal to the first direction and second and fourth sides extending in the third direction orthogonal to the first and second directions, and the first side being recessed in the third direction from the first side toward the third side opposite the first side. A SiC layer is epitaxially grown on the first mark of the SiC substrate.

[0007] 2 is a plan view showing a configuration example of a silicon carbide (SiC) substrate according to the first embodiment; FIG. 3 is a plan view showing an example of a mark according to the first embodiment; FIG. 4 is a plan view showing a configuration example of one mark; FIG. 5 is a cross-sectional view taken along line 4-4 of FIG. 2; FIG. 6 is a cross-sectional view of a SiC substrate according to a comparative example; FIG. 7 is a diagram showing an image of a mark with a facet; FIG. 8 is a diagram showing an image of a mark without a facet;

[0008] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The present invention is not limited to the embodiment. The drawings are schematic or conceptual. In the specification and drawings, the same elements are designated by the same reference numerals.

[0009] First Embodiment FIG. 1 is a plan view showing an example of the configuration of a silicon carbide (SiC) substrate according to a first embodiment. The SiC substrate 1 is an example of a semiconductor substrate. The SiC substrate 1 is, for example, an n-type silicon carbide single crystal substrate made of four-layer hexagonal silicon carbide (4H—SiC). The SiC substrate 1 can be used as a semiconductor substrate for power semiconductor devices such as a Schottky barrier diode, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a PN diode, an IGBT (Insulated Gate Bipolar Transistor), and a GTO (Gate Turn-Off thyristor).

[0010] The SiC substrate 1 has a first surface F1. Dicing lines 3 are provided on the first surface F1 of the SiC substrate 1 to separate the semiconductor chips C. The dicing lines 3 are positions along which cutting is planned in a dicing process. The semiconductor chips C are separated by cutting the SiC substrate 1 along the dicing lines 3. The dicing lines 3 include, for example, a dicing line 3a extending in an X direction parallel to the orientation flat 4 and a dicing line 3b extending in a Y direction perpendicular to the X direction.

[0011] The semiconductor chip C may be provided with a semiconductor element (not shown) or with a pattern during the manufacturing process.

[0012] 2 is a plan view showing an example of a mark according to the first embodiment. Mark 10 is a mark provided on dicing line 3 a on first surface F1 of SiC substrate 1. Mark 10 may be, for example, an alignment mark used for aligning processing of SiC substrate 1 in a semiconductor manufacturing process. A semiconductor manufacturing device such as an exposure device in a lithography process automatically recognizes mark 10 to align SiC substrate 1. If mark 10 cannot be clearly recognized, the semiconductor manufacturing device cannot automatically align using an image of mark 10, which may result in failure to manufacture a semiconductor device or may cause defects.

[0013] The marks 10 are arranged at predetermined second intervals in the X direction. Each mark 10 extends in the Y direction. The marks 10 are formed in an uneven shape in the Z direction (first direction) that is substantially perpendicular to the first surface F1. For example, the marks 10 are formed into recessed grooves by etching the first surface F1 of the SiC substrate 1 from the Z direction.

[0014] FIG. 3 is a plan view showing an example of the configuration of one mark. Mark 10 is an elongated mark having a first side 11, a second side 12, a third side 13, and a fourth side 14. Mark 10 is surrounded by first to fourth sides 11 to 14 in a plan view seen from the Z direction. First side 11 and third side 13 are long sides extending in the Y direction (second direction) perpendicular to the Z direction. Third side 13 is the opposite side to first side 11. Second side 12 and fourth side 14 are short sides extending in the X direction (third direction) perpendicular to the Z direction and the Y direction. Fourth side 14 is the opposite side to second side 12. First and third sides 11 and 13 are longer than second and fourth sides 12 and 14.

[0015] The first and third sides 11, 13 have a plurality of concave patterns P1 recessed in the X direction in a plan view seen from the Z direction. The concave pattern P1 on the first side 11 is a pattern recessed in a direction from the first side 11 to the third side 13 in a plan view seen from the Z direction, and the concave pattern P1 on the third side 13 is a pattern recessed in a direction from the third side 13 to the first side 11 in a plan view seen from the Z direction. The concave patterns P1 are recessed (constricted) in the X direction from the length of the second and fourth sides 12, 14 (the maximum width of the mark 10 in the X direction) and appear periodically and repeatedly in the Y direction on the first and third sides 11, 13.

[0016] For example, the length (width) W10 of the second and fourth sides 12, 14 is, for example, approximately 6 μm, and the length L10 of the first and third sides 11, 13 (the length of the mark 10 in the Y direction) is, for example, approximately 50 μm. In this case, the recessed patterns P1 periodically appear repeatedly in the Y direction on the first and third sides 11, 13 with a length Lp1. The length Lp1 is, for example, 1 μm to 2 μm. Each recessed pattern P1 is composed of two inclined sides inclined with respect to the Y direction or the X direction. Therefore, the first and third sides 11, 13 are not composed of sides parallel to the Y direction but are composed of inclined sides. As a result, in a plan view seen from the Z direction, the first and third sides 11, 13 are composed of sides inclined with respect to the Y direction and are processed in a zigzag shape.

[0017] The recess width Wp1 of the recessed pattern P1 in the X direction is less than half the length of the second and fourth sides 12, 14. For example, if the length of the second and fourth sides 12, 14 is approximately 6 μm, the recess width Wp1 of the recessed pattern P1 is less than 3 μm. As a result, the mark 10 is not divided in the Y direction and is continuously connected.

[0018] Each of the marks 10 shown in FIG. 2 has the configuration shown in FIG.

[0019] 4 is a cross-sectional view taken along line 4-4 in FIG. 2. The mark 10 is a groove machined in the Z direction on the first face F1 of the SiC substrate 1. The mark 10 makes the first face F1 uneven. A SiC epitaxial layer 20 is provided on the mark 10 provided on the SiC substrate 1. The SiC epitaxial layer 20 covers the side and bottom faces of the mark 10 and also covers the first face F1.

[0020] Here, in a cross section perpendicular to the Y direction, the first plane F1 is inclined at an angle θ in the <11-20> direction from the (0001) crystal plane of the SiC substrate 1. However, the inclination of the first plane F1 is not limited to this direction, and inclination in other directions is also possible. The angle θ is called the off-angle of the SiC substrate 1. The off-angle θ is, for example, 8 degrees or less, specifically, 4 degrees. A SiC substrate having an off-angle is also called an off-angle substrate. The downward direction (+X direction) of the inclination of the off-angle θ as the third direction is also called the upstream side of the off-direction. The upward direction (-X direction) of the inclination of the off-angle θ as the opposite direction to the third direction is also called the downstream side of the off-direction.

[0021] According to this embodiment, the first and third sides 11, 13 of the mark 10 have a concave pattern P1 in a plan view seen from the Z direction. As a result, even if the SiC substrate 1 has an off-angle θ, the SiC epitaxial layer 20 can be formed with a substantially uniform film thickness on the mark 10 and the first face F1.

[0022] If the first and third sides 11, 13 of the mark 10 do not have the recessed pattern P1 in a plan view seen from the Z direction and are linearly parallel to the Y direction, a crystal plane called a facet will be formed in the SiC epitaxial layer 20. For example, FIG. 5 is a cross-sectional view of a SiC substrate according to a comparative example. In this comparative example, the first and third sides 11, 13 of the mark 10 are formed linearly parallel to the Y direction in a plan view seen from the Z direction. In this case, a facet FC will be generated at the upper end of the groove in the mark 10 depending on the off-angle θ of the SiC substrate 1.

[0023] 6 is a diagram showing an image of a mark with a facet. A facet FC has occurred on the first side 11 of the mark 10. In this case, as shown in FIG. 6, the image of the first side 11 is blurred and unclear. Therefore, there is a risk that the semiconductor manufacturing equipment will not be able to automatically recognize the mark 10.

[0024] In contrast, FIG. 7 is a diagram showing an image of a mark without facets. In this embodiment, the first and third sides 11 and 13 of the mark 10 have a concave pattern P1 in a plan view seen from the Z direction. Because the SiC substrate 1 is an off-angle substrate, some facets occur in the SiC epitaxial layer 20. However, the facets are small and barely noticeable. In this case, as shown in FIG. 7, the images of the first and third sides 11 and 13 are clear and not blurred. This allows the semiconductor manufacturing equipment to automatically recognize the mark 10. As a result, pattern alignment and other processes are facilitated.

[0025] Next, a method for manufacturing the semiconductor device according to the first embodiment will be described.

[0026] 8A to 8C are cross-sectional views showing an example of a method for manufacturing the semiconductor device according to the first embodiment.

[0027] The first face F1 of the SiC substrate 1, which has an off-angle θ, is processed using lithography and etching techniques such as RIE (Reactive Ion Etching). The off-angle θ is, for example, 4 degrees. As a result, grooves for the marks 10 are formed on the first face F1 of the SiC substrate 1. In a plan view seen from the Z direction, the configuration of the marks 10 is as described with reference to FIGS. 2 and 3 .

[0028] Next, an SiC epitaxial layer 20 is formed on the first face F1 of the SiC substrate 1 using an epitaxial growth method. At this time, as shown in FIGS. 2 and 3 , the mark 10 has a concave pattern P1 in a plan view seen from the Z direction. As a result, the SiC epitaxial layer 20 is formed with a substantially uniform film thickness on the mark 10 and the first face F1, and facets are suppressed. As a result, the SiC epitaxial layer 20 shown in FIG. 4 is obtained.

[0029] 1, a semiconductor element is formed on the SiC substrate 1 or the SiC epitaxial layer 20. The semiconductor element is a power semiconductor element such as a Schottky barrier diode, a MOSFET, a PN diode, an IGBT, or a GTO.

[0030] After semiconductor elements are formed on the SiC substrate 1 or the SiC epitaxial layer 20, the SiC substrate 1 is singulated into semiconductor chips C in a dicing process. The marks 10 are used as alignment marks or the like for aligning the processing of the SiC substrate 1 in each semiconductor manufacturing process, and are formed on the dicing lines 3. Therefore, in the dicing process, the marks 10 are cut along with the dicing lines 3.

[0031] The individual semiconductor chips C are mounted on other substrates or the like and packaged, thereby completing the semiconductor device according to this embodiment.

[0032] In this embodiment, mark 10 has a concave pattern P1 in a plan view seen from the Z direction. This suppresses the facets of SiC epitaxial layer 20 and makes them less noticeable, even if SiC substrate 1 is an off-angle substrate. In this case, images of first and third sides 11 and 13 are clear, allowing semiconductor manufacturing equipment to automatically recognize mark 10. As a result, pattern alignment and other processes are facilitated in each process.

[0033] Second Embodiment Fig. 9 is a plan view showing an example of the configuration of one mark according to the second embodiment. The mark 10 according to the second embodiment is composed of a plurality of partial marks 10a of a first length L10a arranged at a first interval D10a in the Y direction. The first interval D10a is, for example, 4 µm. The first length L10a is, for example, 4 µm. The width W10 is, for example, 4 µm. Note that the first interval D10a, first length L10a, and width W10 are not limited to these.

[0034] Each partial mark 10a has a first side 11, a second side 12, a third side 13, and a fourth side 14. In a plan view seen from the Z direction, each partial mark 10a is surrounded by the first to fourth sides 11 to 14. The first side 11 and the third side 13 are sides that extend in the Y direction. The third side 13 is the opposite side to the first side 11. The second side 12 and the fourth side 14 are sides that extend in the X direction. The fourth side 14 is the opposite side to the second side 12.

[0035] In a plan view seen from the Z direction, the first and third sides 11 and 13 have a plurality of recessed patterns P1 recessed in the X direction. The recessed patterns P1 are recessed (constricted) in the X direction from the length of the second and fourth sides 12 and 14 (the maximum width of the mark 10 in the X direction), and appear periodically and repeatedly in the Y direction on the first and third sides 11 and 13.

[0036] For example, the recessed pattern P1 appears periodically and repeatedly with a length of 1 μm to 2 μm in the Y direction on the first and third sides 11, 13. As a result, in a plan view seen from the Z direction, the first and third sides 11, 13 are processed in a zigzag shape with respect to the Y direction.

[0037] As in the first embodiment, each recessed pattern P1 is formed by two inclined sides inclined with respect to the Y direction or the X direction, so that the first and third sides 11 and 13 are not parallel to the Y direction but are inclined.

[0038] Furthermore, the recess width Wp1 of the concave pattern P1 in the X direction is less than half the length of the second and fourth sides 12, 14. For example, if the length of the second and fourth sides 12, 14 is approximately 4 μm, the recess width Wp1 of the concave pattern P1 is less than 2 μm. As a result, the partial mark 10 a itself is continuously connected in the Y direction.

[0039] Fig. 10 is a plan view showing a plurality of marks. In the second embodiment, the plurality of marks 10 each have the configuration shown in Fig. 9. As a result, as shown in Fig. 10, a plurality of partial marks 10a are two-dimensionally arranged on the first surface F1. That is, in a plan view seen from the Z direction, the plurality of partial marks 10a are two-dimensionally arranged in the form of dots.

[0040] Even with this configuration, when the SiC substrate 1 is an off-angle substrate, the facets of the SiC epitaxial layer 20 are suppressed and inconspicuous. Therefore, the images of the first and third sides 11, 13 of the mark 10 according to the second embodiment are clear, and the semiconductor manufacturing equipment can automatically recognize the mark 10. Therefore, the second embodiment can achieve the same effects as the first embodiment. Furthermore, the mark 10 of the second embodiment can be manufactured in the same manner as the first embodiment by changing the mask pattern in lithography.

[0041] Third Embodiment FIG. 11 is a plan view showing a configuration example of a mark according to a third embodiment. In a mark 10 according to the third embodiment, a concave pattern P1 is provided on a first side 11 but not on a third side 13. The first side 11 is one of the two sides 11, 13 of the mark 10, depending on the tilt direction of the (0001) crystal plane of the SiC substrate 1 shown in FIG. 8. That is, when the first surface F1 of the SiC substrate 1 in FIG. 8 is horizontal, the concave pattern P1 is formed on the side 11 in a direction that climbs up the (0001) crystal plane of the SiC substrate 1 (the dashed line in FIG. 8). Note that the first surface F1 of the SiC substrate 1 is inclined by 4 degrees from the (0001) crystal plane of the SiC substrate 1 in the <11-20> direction of the SiC substrate 1.

[0042] 8 , when the off-angle θ is an acute angle, and the first face F1 is horizontal, the mark 10 has repeated irregularities as it moves up the slope (approximately the −X direction: downstream of the off-direction) of the (0001) crystal plane of the SiC substrate 1. In the direction (approximately the −X direction) of the slope of the (0001) crystal plane of the SiC substrate 1, the facets of the SiC epitaxial layer 20 are easily noticeable along the first side 11, which rises from the bottom surface of the groove of the mark 10 to the first face F1, among the first and third sides 11 and 13.

[0043] 8, the off-angle θ is assumed to be an acute angle, and the concave pattern P1 is formed on the first side 11 from which the mark 10 rises, in the direction (approximately the −X direction) ascending the slope of the (0001) crystal plane of the SiC substrate 1. This effectively suppresses the facets of the SiC epitaxial layer 20, making them less noticeable.

[0044] Even if the third side 13 rising from the bottom surface of the groove of the mark 10 to the first surface F1 is linear in the direction down the slope of the (0001) crystal plane of the SiC substrate 1 (approximately the +X direction: upstream side of the off-direction), the facets of the SiC epitaxial layer 20 are not noticeable. Therefore, the concave pattern P1 does not need to be formed on the third side 13.

[0045] Even with this configuration, the images of the first and third sides 11, 13 of the mark 10 are clear, and the semiconductor manufacturing equipment can automatically recognize the mark 10. Therefore, the third embodiment can achieve the same effects as the first embodiment. Furthermore, the mark 10 of the third embodiment can be manufactured in the same manner as the first embodiment by changing the mask pattern in lithography.

[0046] 12 is a plan view showing an example of the configuration of a mark according to a fourth embodiment. The fourth embodiment is a combination of the second and third embodiments. Therefore, in the fourth embodiment, a plurality of partial marks 10a are arranged two-dimensionally in a dot pattern in a plan view seen from the Z direction. The arrangement of the plurality of partial marks 10a may be the same as that of the second embodiment.

[0047] Like the mark 10 of the third embodiment, each partial mark 10a has a concave pattern P1 on a first side 11, but does not have a concave pattern P1 on a third side 13. The first side 11 is formed on one of the two sides 11, 13 of the partial mark 10a, which depends on the tilt direction of the (0001) crystal plane of the SiC substrate 1.

[0048] 8, the recessed pattern P1 is formed on the first side 11 from which the mark 10 rises, in the direction (approximately the −X direction) ascending the slope of the (0001) crystal plane of the SiC substrate 1. This effectively suppresses the facets of the SiC epitaxial layer 20, making them less noticeable.

[0049] In the direction (approximately the +X direction) down the slope of the (0001) crystal plane of the SiC substrate 1, even if the third side 13 along which the mark 10 rises is linear, the facets of the SiC epitaxial layer 20 are not noticeable. Therefore, the concave pattern P1 does not need to be formed on the third side 13.

[0050] Even with this configuration, the images of the first and third sides 11, 13 of the mark 10 are clear, and the semiconductor manufacturing equipment can automatically recognize the mark 10. Therefore, the fourth embodiment can achieve the same effects as the first embodiment. Furthermore, the mark 10 of the fourth embodiment can be manufactured in the same way as the first embodiment by changing the mask pattern in lithography.

[0051] Fifth Embodiment Fig. 13 is a plan view showing an example of the configuration of a mark according to the fifth embodiment. In each mark 10 according to the fifth embodiment, one concave pattern P1 is provided on the first side 11 in plan view from the Z direction. In plan view from the Z direction, the concave pattern P1 is composed of two straight lines inclined with respect to the Y direction. The two straight lines constituting the concave pattern P1 are inclined so as to recess from the center of the mark 10 in the Y direction toward the center of the mark 10 in the X direction. In this way, the number of concave patterns P1 provided on the first side 11 is not limited.

[0052] The recess width Wp1 in the X direction of the concave pattern P1 may be set to be approximately equal to the width in the X direction of the facets generated in the SiC epitaxial layer 20. This makes it possible to cancel out image blurring caused by the facets.

[0053] In this way, even in the fifth embodiment, the facet of the SiC epitaxial layer 20 on the first side 11 can be relaxed and made less noticeable.

[0054] Sixth Embodiment Fig. 14 is a plan view showing an example of the configuration of a mark according to the sixth embodiment. In each mark 10 according to the sixth embodiment, one concave pattern P1 is provided on the first side 11 in a plan view seen from the Z direction. In a plan view seen from the Z direction, the concave pattern P1 is configured in a substantially arc shape. The arc of the concave pattern P1 is formed so as to be recessed from the center of the mark 10 in the Y direction toward the center of the mark 10 in the X direction. In this way, the shape of the concave pattern P1 provided on the first side 11 may be configured as a curve.

[0055] The recess width Wp1 in the X direction of the concave pattern P1 may be set to be approximately equal to the width in the X direction of the facets generated in the SiC epitaxial layer 20. This makes it possible to cancel out image blurring caused by the facets.

[0056] In this way, even in the sixth embodiment, the facet of the SiC epitaxial layer 20 on the first side 11 can be reduced and made less noticeable.

[0057] The fifth and sixth embodiments may be applied to the second or fourth embodiment. That is, the first side 11 of each partial mark 10a may have one concave pattern P1.

[0058] (Note) (1) A method for manufacturing a semiconductor device, comprising: forming a first mark recessed in a first direction substantially perpendicular to a first surface of a SiC substrate, the first mark being surrounded by first and third sides extending in a second direction perpendicular to the first direction on the first surface and second and fourth sides extending in a third direction perpendicular to the first and second directions, the first mark having at least one recessed pattern recessed in the third direction from the first side toward the third side opposite the first side; and epitaxially growing a SiC layer on the first mark of the SiC substrate.

[0059] (2) The method according to (1), wherein the first surface is inclined from a (0001) crystal plane of the SiC substrate in a direction opposite to the third direction.

[0060] (3) The method according to (1) or (2), wherein a plurality of the recessed patterns are formed on the first side.

[0061] (4) The method according to (1) or (2), wherein the recess width of the recessed pattern in the third direction is less than half the length of the second side.

[0062] (5) The method according to any one of (1) to (4), wherein the first and third sides are longitudinal sides of the first mark, and the second and fourth sides are shorter than the first and third sides.

[0063] (6) The method according to any one of (1) to (4), wherein the plurality of first marks are arranged at first intervals in the second direction.

[0064] (7) The method according to any one of (1) to (6), wherein the recessed pattern is configured with straight lines inclined with respect to the second direction in a plan view seen from the first direction.

[0065] (8) The method according to any one of (1) to (6), wherein the recessed pattern has a substantially arc-shaped shape in a plan view seen from the first direction.

[0066] (9) The method according to any one of (1) to (8), wherein a plurality of the first marks are arranged in the second direction or the third direction in a plan view seen from the first direction.

[0067] (10) The method according to (1), wherein the first plane is inclined in the <11-20> direction from the (0001) plane.

[0068] (11) A semiconductor substrate comprising: a SiC substrate having a first surface, the SiC substrate having a first mark recessed in a first direction substantially perpendicular to the first surface; and a SiC epitaxial layer provided on the first mark, wherein the first mark is surrounded by first and third sides extending in a second direction perpendicular to the first direction on the first surface, and second and fourth sides extending in a third direction perpendicular to the first and second directions, and has at least one recessed pattern on the first side recessed in the third direction from the first side toward the third side opposite the first side.

[0069] (12) The semiconductor substrate according to (11), wherein the first surface is inclined from a (0001) crystal plane of the SiC substrate in a direction opposite to the third direction.

[0070] (13) The semiconductor substrate according to (11) or (12), wherein a plurality of the recessed patterns are formed on the first side.

[0071] (14) The semiconductor substrate according to any one of (11) to (13), wherein the recess width of the recessed pattern in the third direction is less than half the length of the second side.

[0072] (15) The semiconductor substrate according to any one of (11) to (14), wherein the first and third sides are sides in the longitudinal direction of the first mark, and the second and fourth sides are shorter than the first and third sides.

[0073] (16) The semiconductor substrate according to any one of (11) to (15), wherein the plurality of first marks are arranged at first intervals in the second direction.

[0074] (17) The semiconductor substrate according to any one of (11) to (16), wherein, in a plan view seen from the first direction, the recessed pattern is configured with straight lines inclined with respect to the second direction.

[0075] (18) The semiconductor substrate according to any one of (11) to (16), wherein the recessed pattern has a substantially arc-shaped shape in a plan view seen from the first direction.

[0076] (19) The semiconductor substrate according to any one of (11) to (18), wherein a plurality of the first marks are arranged in the second direction or the third direction in a plan view seen from the first direction.

[0077] (20) The semiconductor substrate according to (11), wherein the first surface is inclined in the <11-20> direction from the (0001) plane.

[0078] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents.

[0079] 1 SiC substrate 10 Mark 20 SiC epitaxial layer F1 First surface C Semiconductor chip 3 Dicing lines 11 to 14 First to fourth sides

Claims

1. A method for manufacturing a semiconductor device, comprising: forming a first mark, the first mark being recessed in a first direction approximately perpendicular to a first surface of a SiC substrate, the first mark being surrounded by first and third sides extending in a second direction perpendicular to the first direction on the first surface and second and fourth sides extending in a third direction perpendicular to the first and second directions, the first mark having at least one recessed pattern recessed in the third direction from the first side toward the third side which is the opposite side to the first side; and epitaxially growing a SiC layer on the first mark of the SiC substrate.

2. The method of claim 1, wherein the first surface is tilted from a (0001) crystal plane of the SiC substrate in a direction opposite to the third direction.

3. The method according to claim 1, wherein a plurality of said recessed patterns are formed on said first side.

4. The method according to claim 1, wherein the recess width of the recessed pattern in the third direction is less than half the length of the second side.

5. A method according to any one of claims 1 to 4, wherein the first and third sides are longitudinal sides of the first mark, and the second and fourth sides are shorter than the first and third sides.

6. A method according to any one of claims 1 to 4, wherein the first marks are arranged at first intervals in the second direction.

7. A method according to any one of claims 1 to 4, wherein, in a plan view from the first direction, the recessed pattern is composed of straight lines inclined with respect to the second direction.

8. A method according to any one of claims 1 to 4, wherein the recessed pattern has an approximately arc-shaped shape when viewed in a plan view from the first direction.

9. A method according to any one of claims 1 to 4, wherein a plurality of the first marks are arranged in the second direction or the third direction in a plan view seen from the first direction.

10. The method according to any one of claims 1 to 4, wherein the first surface is inclined in the <11-20> direction from the (0001) surface.

11. A semiconductor substrate comprising: a SiC substrate having a first surface, the SiC substrate having a first mark recessed in a first direction approximately perpendicular to the first surface; and a SiC epitaxial layer provided on the first mark, the first mark being surrounded by first and third sides extending in a second direction perpendicular to the first direction on the first surface, and second and fourth sides extending in a third direction perpendicular to the first and second directions, the first mark having at least one recessed pattern on the first side recessed in the third direction from the first side toward the third side which is the opposite side to the first side.

Images