Semiconductor device

Abstract

[Problem] To provide a semiconductor device in which the structure is simplified and the performance is improved. [Solution] A semiconductor device according to the present embodiment comprises a first insulating substrate having a first surface and a second surface that is on the opposite side from the first surface. First and second conductive layers are provided on the first surface side. A plurality of semiconductor chips include a third surface that faces the first surface, a fourth surface that is on the opposite side from the third surface, a first electrode that is on the third surface, and a second electrode that is on the fourth surface. The first electrode is electrically connected to the first conductive layer. A common electrode plate has a fifth surface that faces the fourth surface, is electrically connected to the second electrodes of the plurality of semiconductor chips, and is electrically connected to the second conductive layer. A second insulating substrate is provided on the second surface side of the first insulating substrate.

Description

Semiconductor Devices

[0001] The present embodiment relates to a semiconductor device.

[0002] Power semiconductor devices used in automotive main inverters and the like are sometimes housed in cases. However, as the structures of power semiconductor devices become more complex, more and more devices are being sealed with molded resin.

[0003] JP 2022-053400 A JP 2022-165445 A JP 2023-041490 A

[0004] A semiconductor device with a simplified structure and improved performance is provided.

[0005] The semiconductor device according to this embodiment includes a first insulating substrate having a first surface and a second surface opposite the first surface. First and second conductive layers are provided on the first surface side. The plurality of semiconductor chips have a third surface opposite the first surface, a fourth surface opposite the third surface, a first electrode on the third surface, and a second electrode on the fourth surface. The first electrode is electrically connected to the first conductive layer. A common electrode plate has a fifth surface opposite the fourth surface, is electrically connected in common to the second electrodes of the plurality of semiconductor chips, and is also electrically connected to the second conductive layer. A second insulating substrate is provided on the second surface side of the first insulating substrate.

[0006] 10A and 10B are cross-sectional views showing an example of the configuration of a semiconductor device; a schematic plan view showing an example of the configuration of a semiconductor module; a schematic plan view showing an example of the configuration of a semiconductor module; a schematic cross-sectional view showing the configuration of a semiconductor module; a cross-sectional view showing an example of the configuration of a connection portion between a semiconductor chip and a common electrode plate; a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to a first embodiment; a plan view showing an example of a method for manufacturing a semiconductor device according to a first embodiment; a cross-sectional view showing an example of a method for manufacturing a semiconductor device following FIG. 6A; a plan view showing an example of a method for manufacturing a semiconductor device following FIG. 6B; a cross-sectional view showing an example of a method for manufacturing a semiconductor device following FIG. 7A; a plan view showing an example of a method for manufacturing a semiconductor device following FIG. 7B; a cross-sectional view showing an example of a method for manufacturing a semiconductor device following FIG. 8A; a cross-sectional view showing an example of a method for manufacturing a semiconductor device following FIG. 9; a cross-sectional view showing an example of a method for manufacturing a semiconductor device following FIG. 10; a cross-sectional view showing an example of a configuration of a connection portion between a semiconductor chip and a common electrode plate according to a second embodiment; a cross-sectional view showing an example of a configuration of a connection portion between a semiconductor chip and a common electrode plate according to a third embodiment; a cross-sectional view showing an example of a configuration of a connection portion between a common electrode plate and wiring on a substrate according to a fourth embodiment; a cross-sectional view showing an example of a configuration of a semiconductor module according to a fifth embodiment; a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to a fifth embodiment. Fig. 16B is a plan view showing an example of a method for manufacturing a semiconductor device according to a fifth embodiment; Fig. 16A is a cross-sectional view showing an example of a method for manufacturing a semiconductor device following Fig. 16B; Fig. 17A is a cross-sectional view showing an example of a method for manufacturing a semiconductor device following Fig. 17B; Fig. 17B is a cross-sectional view showing an example of a method for manufacturing a semiconductor device 1 according to a sixth embodiment; Fig. 17A is a cross-sectional view showing an example of a method for manufacturing a semiconductor device 1 according to a sixth embodiment; Fig. 17B is a plan view showing an example of a configuration of a semiconductor module according to a seventh embodiment;

[0007] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The present invention is not limited to the embodiment. The drawings are schematic or conceptual. In the specification and drawings, the same elements are designated by the same reference numerals.

[0008] 1 is a cross-sectional view showing an example of the configuration of a semiconductor device 1. The semiconductor device 1 includes a semiconductor module 10, a base 20, a sintered material 30, a housing 40, a fastener 50, a sealing material 60, a lid 70, wiring 80, and heat dissipation fins 90.

[0009] The semiconductor device 1 may be a power semiconductor device that switches a relatively large current with low on-resistance and is used, for example, in an in-vehicle main inverter, etc. The stacking direction of the semiconductor module 10 relative to the base 20 is defined as the Z direction, one direction substantially perpendicular to the Z direction is defined as the X direction, and a direction substantially perpendicular to the X direction and the Z direction is defined as the Y direction.

[0010] The semiconductor module 10 includes a semiconductor chip 11 and is disposed on a base 20. The semiconductor module 10 may be, for example, an insulated gate bipolar transistor (IGBT), a high electron mobility transistor (HEMT), a metal oxide semiconductor field effect transistor (MOSFET), or a power semiconductor element such as a diode. The semiconductor module 10 may be, for example, a SiC-MOSFET module, which is a high-voltage power semiconductor element with a withstand voltage of 800 V or more and a rated current exceeding 400 A. The detailed configuration of the semiconductor module 10 will be described later.

[0011] The base 20 has the semiconductor module 10 mounted on its front surface, and its rear surface is bonded to the heat dissipation fins 90 via an adhesive 30. The base 20 is made of a material with high thermal conductivity, such as AlSiC, which is a SiC substrate coated with aluminum. The adhesive 30 is made of a material with high thermal conductivity, such as solder.

[0012] The heat dissipation fins 90 have the base 20 mounted on their front surface, and the rear surface is formed into a fin shape to improve heat dissipation performance. The heat dissipation fins 90 are made of a highly thermally conductive material such as ceramic or metal.

[0013] The housing 40 is provided on the base 20 so as to surround the periphery of the semiconductor module 10. The housing 40 accommodates the base 20 and the plurality of semiconductor modules 10 in a space surrounded by the base 20 and the housing 40. The housing 40 is made of an insulating material such as resin, for example.

[0014] The fasteners 50 pass through openings in the housing 40 and the base 20 and fit into the heat dissipation fins 90, fixing the housing 40 to the base 20 and further fixing the housing 40 and the base 20 to the heat dissipation fins 90.

[0015] The sealing material 60 seals the semiconductor module 10 in the space surrounded by the housing 40, the base 20, and the lid 70. The sealing material 60 may be a gel-like material that seals the plurality of substrates 100, the plurality of semiconductor chips 11, the plurality of common electrode plates 120, etc. in the space. The sealing material 60 is made of an insulating material such as silicone resin, mold resin, etc.

[0016] The lid 70 closes the opening of the housing 40 and protects the sealing material 60 that seals the semiconductor module 10. Like the housing 40, the lid 70 is made of an insulating material such as resin.

[0017] The wiring 80 is electrically connected to a portion of the wiring of the semiconductor module 10, and passes through the sealing material 60 and the housing 40 to be led out of the housing 40. The wiring 80 is made of a conductive metal such as copper, for example.

[0018] 2 and 3 are schematic plan views showing examples of the configuration of a semiconductor module. Fig. 4 is a schematic cross-sectional view showing the configuration of a semiconductor module. Note that the common electrode plates 120g, 120s, 120p, and 120n shown in Fig. 3 are omitted from Fig. 2. In Fig. 2, the electrical connection relationships between the electrodes of the semiconductor chip 11 and the wiring of the substrate 100 are indicated by dashed lines.

[0019] 4, the substrate 100 as a first insulating substrate has a first surface F1 and a second surface F2 opposite to the first surface F1. The substrate 100 is made of an insulating material such as ceramic and a material with high thermal conductivity.

[0020] Wiring 110 is provided on the first surface F1 of the substrate 100. The wiring 110 as first and second conductive layers is formed in an arbitrary planar pattern on the first surface F1. The wiring 110 is made of a material with high electrical conductivity and thermal conductivity, such as copper. A base 20 as a second insulating substrate is provided on the second surface F2 side of the substrate 100. The substrate 100 is bonded to wiring 22 of the base 20 by a bonding material 21. In other words, the bonding material 21 is provided between the substrate 100 and the base 20 and bonds them to each other. The bonding material 21 is made of a conductive bonding material, such as solder. The wiring 22 is made of the same material as the wiring 110, such as a material with high electrical conductivity and thermal conductivity, such as copper. However, the bonding material 21 and the wiring 22 are used for thermal conduction and do not necessarily need to be used for electrical connection. Furthermore, by providing the bonding material 21 and the wiring 22 on the second surface F2 side, the linear expansion coefficients of the first surface F1 and the second surface F2 of the substrate 100 can be balanced, and warping of the substrate 100 can be suppressed.

[0021] 2, the wiring 110 on the first surface F1 of the substrate 100 includes an anode input terminal wiring WP, a cathode input terminal wiring WN, a source wiring WS, a gate wiring WG, and an output terminal wiring WAC. A high-voltage waveform is formed between the anode input terminal wiring WP and the output terminal wiring WAC. A low-voltage waveform is formed between the output terminal WAC and the cathode input terminal wiring WN.

[0022] 4, the semiconductor chip 11 is disposed on the anode input terminal wiring WP or the output terminal wiring WAC. A drain (or collector) is provided as a first electrode on the bottom surface F3 of the semiconductor chip 11. The bottom surface F3 of the semiconductor chip 11 faces the first surface F1 of the substrate 100, and the drain (or collector) is electrically connected to the anode input terminal wiring WP or the output terminal wiring WAC. The semiconductor chip 11 is bonded to the substrate 100 with a conductive sintered material such as a laminated film of Ti, Ni, and Au, an Ag film, or a laminated film of Au and Ag.

[0023] A gate electrode G, a source electrode S (or an emitter electrode), and an electrode M are provided on a surface F4 of the semiconductor chip 11 opposite to the bottom surface F3.

[0024] 3, common electrode plates 120g, 120s, 120p, and 120n are provided on a surface F4 of the semiconductor chip 11. The common electrode plates 120g, 120s, 120p, and 120n connect the gate electrode G and source electrode S of the semiconductor chip 11 to the gate wiring WG, source wiring WS, anode input terminal wiring WP, cathode input terminal wiring WN, or output terminal wiring AC.

[0025] For example, as shown in FIG. 3 , a common electrode plate 120g is commonly connected between the gate electrodes G and gate wiring WG of multiple semiconductor chips 11. A common electrode plate 120s is commonly connected between the source electrodes S and source wiring WS of multiple semiconductor chips 11. A common electrode plate 120p is commonly connected between the electrode M and output terminal wiring WAC of the three upper semiconductor chips 11 in FIG. 3 . A common electrode plate 120n is commonly connected to the electrode M and cathode input terminal wiring WN of the three lower semiconductor chips 11 in FIG. 3 . Each electrode M is connected to the source electrode S of the semiconductor chip 11. In this way, the electrodes G, S, and M on the surface F4 of each semiconductor chip 11 are electrically connected to the wiring WG, WS, WAC, and WN of the substrate 100 by the common electrode plates 120g, 120s, 120p, and 120n. Hereinafter, the common electrode plates 120g, 120s, 120p, and 120n will also be collectively referred to as the common electrode plate 120. The wirings WG, WS, WAC, and WN will hereinafter be collectively referred to as wirings 110. The electrodes G, S, and M will hereinafter be collectively referred to as electrodes G and the like.

[0026] The common electrode plate 120 is made of a material that has both electrical conductivity and thermal conductivity, such as copper, aluminum, molybdenum, or tungsten. The thickness of the common electrode plate 120 is, for example, 400 μm to 1000 μm. As shown in FIG. 3 , the common electrode plate 120 is a plate-shaped connector when viewed from the Z direction, and has an arbitrary planar shape. Also, as shown in FIG. 4 , in cross section, the common electrode plate 120 extends in the X-Y plane from the electrodes 120 on the surface F4 of the semiconductor chip 11 and bends in the −Z direction toward the wiring 110 on the substrate 100. This allows the common electrode plate 120 to electrically connect any of the electrodes 120 on the surface F4 of the semiconductor chip 11 to any of the wiring 110 on the substrate 100.

[0027] 5 is a cross-sectional view showing an example of the configuration of a connection portion between a semiconductor chip and a common electrode plate. The common electrode plate 120 has a fifth surface F5 facing the surface F4 of the semiconductor chip 11. One end of the common electrode plate 120 is electrically connected to one of the electrodes G of the semiconductor chip 11 via a sintered material 140 and a metal plating 130 provided between the fifth surface F5 and the surface F4 of the semiconductor chip 11. Although not shown, the other end of the common electrode plate 120 is electrically connected to one of the wirings 110 of the substrate 100 via a sintered material and a metal plating (not shown) provided between the fifth surface F5 and the wirings 110 of the substrate 100.

[0028] The metal plating 130 as the first metal plating is provided on the electrodes G of the semiconductor chip 11. The metal plating 130 is made of, for example, copper, nickel, silver, gold, or palladium (Pd), and more specifically, is made of a material with high electrical and thermal conductivity, such as NiAu or Cu. The thickness of the metal plating 130 is, for example, 1 μm to 15 μm. Other metal platings may also be made of the same material as the metal plating 130.

[0029] The sintered material 140, which serves as a first sintered material, is provided on the metal plating 130. The sintered material 140 is made of, for example, copper, silver, lead, a tin-copper compound, a tin-silver compound, or a tin-nickel compound. The thickness of the sintered material 140 is, for example, 10 μm to 300 μm. The sintered material 140 is a paste-like or sheet-like material when initially supplied, and is sintered between the metal plating 130 and the common electrode plate 120 by heat treatment. Other sintered materials may also be made of the same material as the sintered material 140.

[0030] In this way, the common electrode plate 120 is electrically connected to the electrodes G of the semiconductor chip 11 through the metal plating 130 by being bonded to the sintered material 140 .

[0031] The side surfaces of the semiconductor chip 11 and the metal plating 130 are covered with an insulating layer 150. The insulating layer 150 is made of an insulating material such as polyimide. The thickness of the insulating layer 150 is, for example, 5 μm to 10 μm. In the Z direction in which the semiconductor chip 11 and the common electrode plate 120 are stacked on the substrate 100, the height of the surface (eighth surface) F8 of the insulating layer 150 is higher than the surface F1 of the semiconductor chip 11 and lower than the surface (seventh surface) F7 of the metal plating 130. This allows the insulating layer 150 to protect the side surfaces of the semiconductor chip 11 and the metal plating 130 while maintaining the heat dissipation performance from the sintered material 140 and the common electrode plate 120.

[0032] The semiconductor device 1 according to this embodiment includes a common electrode plate 120 electrically connected in common to the electrodes G, etc. of the multiple semiconductor chips 11 and electrically connected to the wiring 110 of the substrate 100. This eliminates the need for wire bonding, and the common electrode plate 120 can connect the electrodes G, etc. of the semiconductor chips 11 and the wiring 110 of the substrate 100 with low resistance. By using the common electrode plate 120, a sintered material 140 and the common electrode plate 120 can be stacked on the semiconductor chips 11, and the sintered material 140 and the common electrode plate 120 can be sintered by pressing. This allows the common electrode plate 120 to connect the electrodes G, etc. of the semiconductor chips 11 and the wiring 110 of the substrate 100 with low resistance, thereby providing the semiconductor device 1 with high heat dissipation performance. Furthermore, the semiconductor device 1 can be made into a structure with a substantially uniform thickness.

[0033] Furthermore, by using the common electrode plate 120 instead of wire bonding, the electrodes G of a plurality of semiconductor chips 11 can be simultaneously connected to the common wiring 110. Therefore, the number of parts constituting the semiconductor device 1 can be reduced.

[0034] Next, a method for manufacturing the semiconductor device 1 according to this embodiment will be described.

[0035] 6A to 11 are cross-sectional views or plan views showing an example of a method for manufacturing the semiconductor device according to the first embodiment.

[0036] 6A and 6B, a sintering material 160 is applied onto the wiring 110 of the substrate 100. The sintering material 160 is applied to the position where the semiconductor chip 11 is to be disposed. The sintering material 160 is made of, for example, copper, silver, lead, a tin-copper compound, a tin-silver compound, or a tin-nickel compound.

[0037] 7A and 7B, the semiconductor chip 11 is placed on the sintered material 160. The semiconductor chip 11 is placed at the position of the sintered material 160 applied onto the wiring 110 of the substrate 100.

[0038] Next, as shown in Fig. 7A, the semiconductor chip 11 is pressed from the Z direction by a pressurizer P. At this time, a buffer material S is sandwiched between the pressurizer P and the semiconductor chip 11 to prevent the pressurizer P from damaging the semiconductor chip 11. While the pressurizer P presses the semiconductor chip 1, the sintering material 160 is heated and sintered. As a result, the semiconductor chip 1 is sintered to the wiring 110 by the sintering material 160, and is electrically connected to the wiring 110 with low resistance.

[0039] 8A and 8B, a sintered material 140 is applied onto the electrodes G of the semiconductor chip 11 and onto the wiring 110 of the substrate 100. The sintered material 140 is applied to the position where the common electrode plate 120 will be disposed. The sintered material 140 is made of, for example, copper, silver, lead, a tin-copper compound, a tin-silver compound, or a tin-nickel compound.

[0040] Next, as shown in FIGS. 9 and 3 , the common electrode plate 120 is placed on the sintered material 140. The common electrode plate 120 is placed on the electrodes G of the semiconductor chip 11 and on the sintered material 140 applied to the wiring 110 of the substrate 100. For example, as shown in FIG. 3 , the common electrode plate 120g is placed on the sintered material 140 applied to the electrodes G of the semiconductor chip 11 and the wiring WG of the substrate 100. The common electrode plate 120s is placed on the sintered material 140 applied to the electrodes S of the semiconductor chip 11 and the wiring WS of the substrate 100. The common electrode plate 120p is placed on the sintered material 140 applied to the electrodes M of the upper three semiconductor chips 11 and the wiring WAC of the substrate 100 in FIG. 3 . The common electrode plate 120n is placed on the sintered material 140 applied to the electrodes M of the lower three semiconductor chips 11 and the wiring WN of the substrate 100 in FIG. 3 .

[0041] Next, as shown in FIG. 9 , a pressure device P presses the common electrode plate 120 in the Z direction. At this time, a buffer material S is sandwiched between the pressure device P and the semiconductor chip 11 to prevent the pressure device P from damaging the common electrode plate 120 and the semiconductor chip 11. While the pressure device P presses the common electrode plate 120, the sintering material 140 is heated and sintered. As a result, the common electrode plate 120 is sintered to the electrodes G, etc. of the semiconductor chip 11 and the wiring 110 of the substrate 100 by the sintering material 140, and is electrically connected to the electrodes G, etc. of the semiconductor chip 11 and the wiring 110 of the substrate 100 with low resistance. In this way, the semiconductor module 10 is formed.

[0042] 10 , a plurality of semiconductor modules 10 are joined onto a base 20 with solder 21. The base 20 is made of a material with high thermal conductivity, such as AlSiC, which is a SiC substrate coated with aluminum. Therefore, heat generated in the semiconductor modules 10 is transferred to the base 20 via the wiring 22 and solder 21, and can be easily transferred from the base 20 to the heat dissipation fins 90 shown in FIG.

[0043] Next, the housing 40 is arranged around the semiconductor module 10 on the base 20. The housing 40 is fixed to the base 20 with fasteners 50. At this time, the heat dissipation fins 90 shown in FIG. 1 may also be fixed to the base 20 together with the housing 40 with the fasteners 50.

[0044] 11 , an ultrasonic bonding tool B is used to ultrasonically bond the wiring 80 to the wiring 110 of the substrate 100. The wiring 80 penetrates through the housing 40 and is led out to the outside. This allows the user to supply signals or power from the outside to the semiconductor module 10 via the wiring 80.

[0045] Thereafter, a gel-like sealing material 60 is poured onto the semiconductor module 10 inside the housing 40, and a lid 70 is fitted onto the housing 40. In this way, the semiconductor device 1 shown in FIG.

[0046] According to this embodiment, the sintered material 140 and the common electrode plate 120 are stacked on the semiconductor chip 11, and then the sintered material 140 and the common electrode plate 120 are pressed and sintered. As a result, the common electrode plate 120 connects the electrodes G of the semiconductor chip 11 and the wiring 110 of the substrate 100 with low resistance, and can provide high heat dissipation performance to the semiconductor device 1. In addition, the semiconductor device 1 can be made into a structure with a substantially uniform thickness.

[0047] Furthermore, by using the common electrode plate 120 instead of wire bonding, the electrodes G of a plurality of semiconductor chips 11 can be simultaneously connected to the wiring 110. Therefore, the number of parts constituting the semiconductor device 1 can be reduced.

[0048] Second Embodiment FIG. 12 is a cross-sectional view showing an example of the configuration of a connection portion between a semiconductor chip and a common electrode plate according to a second embodiment. In the second embodiment, an intermediate electrode plate 122 is provided between the semiconductor chip 11 and the common electrode plate 120. Sintered materials 141 and 142 are provided on both sides of the intermediate electrode plate 122 in the Z direction. The sintered material 141, which serves as a second sintered material, is provided on the metal plating 130. The sintered material 142, which serves as a third sintered material, is provided between the intermediate electrode plate 122 and the common electrode plate 120. The sintered materials 141 and 142 are made of, for example, copper, silver, lead, a tin-copper compound, a tin-silver compound, or a tin-nickel compound. The thickness of the sintered materials 141 and 142 is 10 μm to 100 μm.

[0049] The intermediate electrode plate 122 may be made of the same material as the common electrode plate 120. In a plan view seen from the Z direction, the intermediate electrode plate 122 is configured to have a size that allows it to fit inside the electrodes G of the semiconductor chip 11. The thickness of the intermediate electrode plate 122 is 100 μm to 300 μm.

[0050] Furthermore, the surface F8 of the insulating layer 150 may be located higher in the Z direction than the surface F7 of the metal plating 130 provided on the electrodes G of the semiconductor chip 11. Since the intermediate electrode plate 122 is interposed between the common electrode plate 120 and the semiconductor chip 11, the surface F7 of the metal plating 130 may be located lower than the surface F8 of the insulating layer 150.

[0051] A method for manufacturing the semiconductor device 1 according to the second embodiment will now be described.

[0052] After going through the steps described with reference to Figures 6A to 7B, in Figures 8A and 8B, sintered material 141 is applied to the electrodes G of the semiconductor chip 11 and the wiring 110 of the substrate 100, an intermediate electrode plate 122 is placed on the sintered material 141, and the sintered material 142 is applied to the intermediate electrode plate 122.

[0053] Next, through the steps described with reference to FIGS. 9 and 3 , the common electrode plate 120 is placed at the position of the sintered material 142. The common electrode plate 120 is pressed in the Z direction using a pressurizer P. As a result, the intermediate electrode plate 122 is sintered to the electrodes G of the semiconductor chip 11 and the like by the sintered material 141, and the common electrode plate 120 is sintered to the intermediate electrode plate 122 and the wiring 110 of the substrate 100 by the sintered material 142. This completes the formation of the semiconductor module 10 according to the second embodiment. The remaining configuration and manufacturing process of the second embodiment may be the same as those of the first embodiment. Therefore, the second embodiment can achieve the same effects as those of the first embodiment.

[0054] Third Embodiment FIG. 13 is a cross-sectional view showing an example of the configuration of a connection between a semiconductor chip and a common electrode plate according to a third embodiment. The third embodiment further includes metal platings 131 and 132. The metal plating 131 is provided on the fifth surface F5 of the common electrode plate 120. The metal plating 132 is provided on the sixth surface F6 of the common electrode plate 120, opposite the fifth surface F5. The metal platings 131 and 132 are made of, for example, copper, nickel, silver, gold, or palladium (Pd), specifically, highly conductive and thermally conductive materials such as NiAu and Cu. By providing the metal platings 131 and 132 on the front and back surfaces of the common electrode plate 120, surface oxidation of the common electrode plate 120 (e.g., copper) is suppressed. Therefore, the common electrode plate 120 can be firmly bonded by the sintered material 140.

[0055] Other configurations and manufacturing processes of the third embodiment may be the same as those of the first embodiment, and therefore the third embodiment can achieve the same effects as the first embodiment.

[0056] Fourth Embodiment FIG. 14 is a cross-sectional view showing an example of the configuration of a connection portion between a common electrode plate and wiring on a substrate according to a fourth embodiment. The common electrode plate 120 is bonded to wiring 110 on a substrate 100 via a sintered material 140. Metal plating (not shown) may be used instead of the sintered material 140. The metal plating may be made of, for example, copper, nickel, silver, gold, or palladium (Pd), specifically, a material with high electrical and thermal conductivity such as NiAu or Cu. The common electrode plate 120 can be firmly bonded to the wiring 110 by the sintered material 140 or metal plating. The metal plating may be formed by a wet process, vapor deposition, ion plating, sputtering, or the like.

[0057] The other configurations and manufacturing processes of the fourth embodiment may be the same as those of the first embodiment, and therefore the fourth embodiment can achieve the same effects as those of the first embodiment.

[0058] 15 is a cross-sectional view showing an example of the configuration of a semiconductor module according to a fifth embodiment. The semiconductor module 10 according to the fifth embodiment includes a substrate 100 provided on the bottom surface F3 side of the semiconductor chip 11 (the fifth surface F5 side of the common electrode plate 120) and a substrate 200 provided on the front surface F4 side of the semiconductor chip 11 (the sixth surface F6 side of the common electrode plate 120). That is, the substrates 100 and 200 are provided on both the bottom surface F3 and the front surface F4 of the semiconductor chip 11. Like the substrate 100, the substrate 200 is also made of an insulating material with high thermal conductivity, such as ceramic.

[0059] Furthermore, a terminal 250 is provided between the substrate 100 and the substrate 200. When pressure is applied by the pressure device P, the terminal 250 is electrically connected to a portion of the wiring 110 and functions as a terminal that is drawn out to the outside of the semiconductor module 10. For example, the terminal 250 may be electrically connected to the wiring 80 in FIG. 1 and drawn out to the outside of the housing 40. The terminal 250 also functions as a spacer between the substrate 100 and the substrate 200 when pressure is applied by the pressure device P. Therefore, the terminal 250 maintains the distance between the substrate 100 and the substrate 200 so that the substrates 100 and 200 are not bent or damaged.

[0060] The substrate 200 is joined to the common electrode plate 120 by a sintered material 240 provided on a sixth surface F6 of the common electrode plate 120. The sintered material 240 is made of, for example, copper, nickel, silver, gold, or palladium (Pd), and more specifically, is made of a material with high electrical conductivity and thermal conductivity, such as NiAu or Cu.

[0061] The seventh surface F7 of the substrate 200 faces the sixth surface F6 of the common electrode plate 120 and the surface F1 of the substrate 100. The eighth surface F8 of the substrate 200 is the surface opposite the seventh surface F7. The wiring 22 is provided on the eighth surface F8 of the substrate 200. The wiring 22 is made of a material with high electrical conductivity and thermal conductivity, such as copper. This allows heat from the semiconductor chip 11 to be dissipated not only through the substrate 100 but also through the substrate 200. In other words, the semiconductor chip 11 is a so-called DSC (double-side cooling) type semiconductor device that dissipates heat from both the bottom surface F3 and the surface F4 of the semiconductor chip 11.

[0062] The semiconductor device 1 according to the fifth embodiment can improve the heat dissipation performance of the semiconductor chip 11. The other configurations of the fifth embodiment may be the same as those of the first embodiment. As a result, the fifth embodiment can obtain the same effects as those of the first embodiment. The fifth embodiment may be combined with any of the second to fourth embodiments. As a result, the fifth embodiment can obtain the effects of any of the second to fourth embodiments.

[0063] A method for manufacturing the semiconductor device 1 according to the fifth embodiment will be described.

[0064] 16A to 18B are cross-sectional views or plan views showing an example of a method for manufacturing a semiconductor device according to the fifth embodiment.

[0065] After the steps described with reference to FIGS. 6A to 8B, a sintering material 140 is applied onto the semiconductor chip 11 and the wiring 110.

[0066] 16A and 16B, the common electrode plate 120 is placed on the sintered material 140 of the semiconductor chip 11, and the terminals 250 are placed on the sintered material 140 of the wiring 110. As shown in Fig. 16B, the terminals 250 are placed on the wiring WG, WS, WP, WN, and WAC, and are drawn out to the outside of the substrate 100.

[0067] Next, as shown in FIG. 16A , a pressure device P presses the common electrode plate 120 and the terminals 250 in the Z direction. At this time, a buffer material S is sandwiched between the pressure device P and the semiconductor chip 11 to prevent the pressure device P from damaging the common electrode plate 120 and the semiconductor chip 11. The terminals 250 function as spacers to prevent excessive pressure from being applied locally to the common electrode plate 120, the semiconductor chip 11, and the substrate 100. While the pressure device P presses the common electrode plate 120 and the terminals 250, the sintering material 140 is heated and sintered. As a result, the common electrode plate 120 is sintered to the electrodes G, etc. of the semiconductor chip 11 and the wiring 110 of the substrate 100 by the sintering material 140, and is electrically connected to the electrodes G, etc. of the semiconductor chip 11 and the wiring 110 of the substrate 100 with low resistance. The terminal 250 is sintered to the wiring 110 by the sintering material 140 , and the wiring 110 of the substrate 100 can be drawn out to the outside of the semiconductor device 1 .

[0068] Next, as shown in FIGS. 17A and 17B, a sintering material 240 is applied onto the common electrode plate 120.

[0069] 18A and 18B , the substrate 200 is placed on the sintered material 240 of the common electrode plate 120. The seventh surface F7 of the substrate 200 faces the common electrode plate 120 via the sintered material 240. The substrate 200 is also provided on the terminal 250, and the terminal 250 is sandwiched between the substrate 200 and the substrate 100.

[0070] Next, the wiring 222 is formed on the eighth face F8 of the substrate 200 opposite to the seventh face F7.

[0071] Next, as shown in FIG. 18A , the substrate 200 is pressed from the Z direction by a pressurizer P. At this time, a buffer material S is sandwiched between the pressurizer P and the semiconductor chip 11 to prevent the pressurizer P from damaging the substrate 200 and other components. The terminals 250 function as spacers to prevent excessive pressure from being applied locally to the substrate 200. While the pressurizer P presses the substrate 200, the sintering material 240 is heated and sintered. As a result, the substrate 200 is sintered to the common electrode plate 120 by the sintering material 240. The terminals 250 are sandwiched between the substrates 100 and 200 and are pulled out to the outside of the semiconductor device 1, but can be reliably connected to the wiring 110.

[0072] 15, the peripheries of the substrates 100, 200 and the semiconductor chip 11 are sealed with an insulating layer 150. At this time, a portion of the terminal 250 protrudes from the insulating layer 150. This allows electrical connection to the semiconductor chip 11 from outside the semiconductor device 1. The wiring 22, 222 is exposed from the insulating layer 150. This makes it easier to dissipate heat from the substrates 100, 200.

[0073] Other manufacturing steps of the fifth embodiment may be the same as those of the first embodiment, and therefore the fifth embodiment can achieve the same effects as the first embodiment.

[0074] 19 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device 1 according to a sixth embodiment. The configuration of the sixth embodiment may be the same as that of the fifth embodiment.

[0075] A manufacturing method according to the sixth embodiment will be described.

[0076] After the steps described with reference to FIGS. 6A to 8B, a sintering material 140 is applied onto the semiconductor chip 11 and the wiring 110.

[0077] 19 , some of the common electrode plates 120 are arranged in a state where they are connected by a frame 120F. A plurality of terminals 250 are arranged in a state where they are connected by a frame 250F. The frame 120F connects the plurality of common electrode plates 120, and the frame 250F connects the plurality of terminals 250.

[0078] Next, as described with reference to Fig. 16A, the common electrode plate 120, frame 120F, terminals 250, and frame 250F are pressed together in the Z direction by a pressurizer P. While the pressurizer P presses together the common electrode plate 120, frame 120F, terminals 250, and frame 250F, the sintering material 140 is heated and sintered. As a result, the multiple common electrode plates 120, together with the frame 120F, are sintered into the electrodes and wiring 110 of the semiconductor chip 11 by the sintering material 140. The multiple terminals 250, together with the frame 250F, are sintered into the wiring 110 by the sintering material 140.

[0079] Next, the frames 120F and 250F are cut away, leaving the common electrode plate 120 and the terminals 250 on the semiconductor chip 11 and the wiring 110. This results in a configuration similar to that shown in FIG.

[0080] Other manufacturing processes of the sixth embodiment may be the same as those of the fifth embodiment. Therefore, the sixth embodiment can achieve the same effects as those of the fifth embodiment. Furthermore, the frame 120F connects multiple common electrode plates 120, and the frame 250F connects multiple terminals 250. This allows the number of parts to be handled in the manufacturing process of the semiconductor device 1 to be reduced.

[0081] In the sixth embodiment, the substrate 200 and the wiring 222 may be provided in the same manner as in the fifth embodiment, but the substrate 200 and the wiring 222 may be omitted.

[0082] Seventh Embodiment Fig. 20 is a plan view showing an example of the configuration of a semiconductor module according to a seventh embodiment. The common electrode plate 120 of the seventh embodiment has an opening OP that exposes the gate electrode G. The semiconductor chip 11 has the gate electrode G on its surface, and the opening OP is provided in the area of ​​the gate electrode G. This allows the gate electrode G to be electrically isolated from the common electrode plate 120 and to be electrically connected to wiring WG, etc., via a metal wire WR or another metal plate. The connection portion CN is the connection portion between the common electrode plate 120 and the wiring 110, and is the location where the sintered material 140 is provided.

[0083] The use of the metal wire WR for the gate electrode G increases the degree of freedom in wiring. On the other hand, a common electrode plate 120 is used to connect the other electrodes and wiring. The other configurations of the seventh embodiment may be the same as those of the first embodiment. Therefore, the seventh embodiment can also obtain the effects of the first embodiment.

[0084] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents.

[0085] REFERENCE SIGNS LIST 1 semiconductor device 10 semiconductor module 20 substrate 30 sintered material 40 housing 50 fastener 60 sealing material 70 lid 80 wiring 90 heat dissipation fin 100 substrate 110 wiring 120 common electrode plate 130 metal plating 140 sintered material 150 insulating layer 21 bonding material 22 wiring G, S, M electrodes

Claims

1. A semiconductor device comprising: a first insulating substrate having a first surface and a second surface opposite to the first surface; first and second conductive layers provided on the first surface side; a plurality of semiconductor chips having a third surface opposing the first surface, a fourth surface opposite to the third surface, a first electrode on the third surface, and a second electrode on the fourth surface, the first electrodes being electrically connected to the first conductive layer; a common electrode plate having a fifth surface opposing the fourth surface, electrically connected in common to the second electrodes of the plurality of semiconductor chips and electrically connected to the second conductive layer; and a second insulating substrate provided on the second surface side of the first insulating substrate.

2. The semiconductor device described in claim 1, further comprising: a first metal plating provided on the second electrodes of the plurality of semiconductor chips; and a first sintered material provided on the first metal plating, wherein the common electrode plate is electrically connected to the second electrodes of the plurality of semiconductor chips by being bonded to the first sintered material.

3. The semiconductor device according to claim 1 or 2, further comprising a bonding material provided between said first insulating substrate and said second insulating substrate.

4. The semiconductor device described in claim 2, further comprising an insulating layer provided on side surfaces of the plurality of semiconductor chips and on side surfaces of the first metal plating, wherein the height of the insulating layer in a first direction in which the semiconductor chips and the common electrode plate are stacked on the first insulating substrate is higher than that of the semiconductor chips and lower than that of the first metal plating.

5. The semiconductor device according to claim 1, comprising: a plurality of intermediate electrode plates respectively provided between the plurality of semiconductor chips and the common electrode plate; a first metal plating provided on the second electrodes of the plurality of semiconductor chips; a second sintered material provided on the first metal plating; and a third sintered material provided between the plurality of intermediate electrode plates and the common electrode plate.

6. The semiconductor device described in claim 5, further comprising an insulating layer provided on side surfaces of the plurality of semiconductor chips and on side surfaces of the first metal plating, the insulating layer having a height in a first direction in which the semiconductor chips and the common electrode plate are stacked on the first insulating substrate that is greater than that of the first metal plating.

7. The semiconductor device according to claim 2, further comprising: a second metal plating provided on a fifth surface of said common electrode plate; and a third metal plating provided on a sixth surface of said common electrode plate opposite said fifth surface.

8. The semiconductor device according to claim 1 or 2, wherein said common electrode plate and said second conductive layer are joined by solder.

9. The semiconductor device according to claim 1 or 2, further comprising a third insulating substrate provided above a sixth surface of said common electrode plate on the opposite side to said fifth surface.

10. The semiconductor device according to claim 9, further comprising a conductive terminal sandwiched between said second insulating substrate and said third insulating substrate and electrically connected to said first conductive layer or said second conductive layer.

11. The semiconductor device according to claim 10, further comprising a fourth sintered material provided between said common electrode plate and said third insulating substrate.

12. The semiconductor device according to claim 7, wherein the first to third metal plating layers are made of any one of copper, nickel, silver, gold, and palladium.

13. The semiconductor device according to claim 2, wherein the first sintered material is made of any one of copper, silver, lead, a tin-copper compound, a tin-silver compound, and a tin-nickel compound.

14. The semiconductor device according to claim 1, wherein said common electrode plate has openings in the areas of third electrodes provided on said fourth surfaces of said plurality of semiconductor chips, and is electrically isolated from said third electrodes.

15. The semiconductor device described in claim 1, further comprising: a housing fixed to the second insulating substrate, the housing accommodating the first insulating substrate, the plurality of semiconductor chips, and the common electrode plate within a space surrounded by the second insulating substrate and the housing; and a gel sealing the first insulating substrate, the plurality of semiconductor chips, and the common electrode plate within the space.

16. The semiconductor device according to claim 1, further comprising a molding resin that seals said first insulating substrate, said plurality of semiconductor chips and said common electrode plate on said second insulating substrate.

17. The semiconductor device according to claim 1, wherein each of said plurality of semiconductor chips includes a high-voltage power semiconductor element having a withstand voltage of 800 volts or more.

18. The semiconductor device according to claim 1, wherein each of the semiconductor chips includes an IGBT (Insulated Gate Bipolar Transistor), a HEMT (High Electron Mobility Transistor), a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), or a diode using a SiC substrate.

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