Semiconductor device, circuit board, and method for producing circuit board

Abstract

A semiconductor device according to an embodiment is one having a first surface, which faces a first side, and a second surface, which faces a second side that is opposite from the first side. The semiconductor device according to an embodiment comprises: a semiconductor device main body; a lead frame to which the semiconductor device main body is electrically connected; electroconductive bumps electrically connected to the semiconductor device main body or the lead frame; and a resin part which covers and holds at least a part of the semiconductor device main body and at least a part of the lead frame. At least some of the electroconductive bumps are exposed to the outside of the resin part.

Description

Semiconductor device, circuit board, and method for manufacturing circuit board

[0001]

[0001] This application claims priority to Japanese Patent Application No. 2023-124558, filed on July 31, 2023, the contents of which are incorporated herein by reference.

[0002] There is a demand for thinner semiconductor devices. However, thinner semiconductor devices are less easy to handle. This can lead to a decrease in the yield of products in which semiconductor devices are mounted, and limitations on the mounting method for mounting semiconductor devices, resulting in a decrease in the productivity of products using semiconductor devices.

[0003] Japanese Patent Application Laid-Open No. 2016-25143

[0004] An object of the present invention is to provide a semiconductor device that can be easily handled, a circuit board including such a semiconductor device, and a method for manufacturing such a circuit board.

[0005] The semiconductor device of the embodiment has a first surface facing a first side and a second surface facing a second side opposite to the first side. The semiconductor device of the embodiment has a semiconductor device body, a lead frame to which the semiconductor device body is electrically connected, conductive bump portions electrically connected to the semiconductor device body or the lead frame, and a resin portion that covers and holds at least a portion of the semiconductor device body and at least a portion of the lead frame. At least a portion of the conductive bump portions is exposed to the outside of the resin portion.

[0006] 1 is a cross-sectional view showing a portion of a circuit board according to the first embodiment; a cross-sectional view showing a semiconductor device according to the first embodiment; a plan view showing a semiconductor device according to the first embodiment; a cross-sectional view showing stud bumps for forming conductive bump portions according to the first embodiment; a flowchart showing a method for manufacturing a semiconductor device according to the first embodiment; a cross-sectional view showing a first accommodating portion forming step according to the first embodiment; a cross-sectional view showing a chip fixing step according to the first embodiment; a cross-sectional view showing a stud bump forming step according to the first embodiment; a cross-sectional view showing a state after the stud bump forming step according to the first embodiment has been performed; a cross-sectional view showing a state after the molding step according to the first embodiment has been performed; a cross-sectional view showing a state after the grinding step according to the first embodiment; a plan view showing a base material of a lead frame according to the first embodiment; a flowchart showing a method for manufacturing a circuit board according to the first embodiment; a cross-sectional view showing a semiconductor device accommodating step according to the first embodiment; a cross-sectional view showing a state after the sealing step according to the first embodiment has been performed; a cross-sectional view showing a laser processing step according to the first embodiment; a cross-sectional view showing a state after the laser processing step according to the first embodiment; a cross-sectional view showing a semiconductor device according to a second embodiment; a plan view showing a semiconductor device according to a second embodiment; a cross-sectional view showing a semiconductor device according to a third embodiment; a plan view showing a semiconductor device according to a third embodiment. 10 is a cross-sectional view showing a semiconductor device according to a fourth embodiment; FIG. 11 is a flowchart showing a method for manufacturing a semiconductor device according to a fourth embodiment; FIG. 12 is a cross-sectional view showing a chip fixing step according to a fourth embodiment; FIG. 13 is a cross-sectional view showing a stud bump forming step and a vertical wire forming step according to a fourth embodiment; FIG. 14 is a cross-sectional view showing a state after the stud bump forming step and the vertical wire forming step according to a fourth embodiment have been performed; FIG. 15 is a cross-sectional view showing a state after the molding step according to a fourth embodiment has been performed; FIG. 16 is a cross-sectional view showing a state after the grinding step according to a fourth embodiment has been performed; FIG. 17 is a cross-sectional view showing a part of a circuit board according to a fifth embodiment; FIG. 18 is a cross-sectional view showing a part of a circuit board according to a sixth embodiment.

[0007] Hereinafter, a semiconductor device, a circuit board, and a method for manufacturing a circuit board according to embodiments will be described with reference to the drawings.

[0008] In the drawings, the thickness direction of the circuit board of the embodiment is indicated as the Z-axis direction, a direction perpendicular to the thickness direction of the circuit board is indicated as the X-axis direction, and a direction perpendicular to both the Z-axis direction and the X-axis direction is indicated as the Y-axis direction. In the following description, the X-axis direction is referred to as the "first direction X," the Y-axis direction is referred to as the "second direction Y," and the Z-axis direction is referred to as the "thickness direction Z." Furthermore, the side of the thickness direction Z toward which the Z-axis arrow points (+Z side) is referred to as the "upper side," and the side of the thickness direction Z opposite to the side toward which the Z-axis arrow points (-Z side) is referred to as the "lower side." In the following embodiments, the upper side corresponds to the "first side," and the lower side corresponds to the "second side" opposite to the first side.

[0009] First Embodiment FIG. 1 is a cross-sectional view showing a portion of a circuit board 100 according to a first embodiment. As shown in FIG. 1, in the first embodiment, the circuit board 100 is a circuit board having a semiconductor device 20 built in. The circuit board 100 includes a substrate main body 10, a semiconductor device 20, and a wiring portion 40. The substrate main body 10 is plate-shaped with its plate surface facing the thickness direction Z. The semiconductor device 20 is mounted on the substrate main body 10. The substrate main body 10 includes a plate-shaped substrate portion 11, a resin layer 12 laminated on an upper surface of the substrate portion 11, a resin layer 13 laminated on a lower surface of the substrate portion 11, and a sealing resin portion 30.

[0010] The base member 11 is formed with a second housing portion 14 that houses the semiconductor device 20 therein. In the first embodiment, the second housing portion 14 is a hole that penetrates the base member 11 in the thickness direction Z. The upper opening of the second housing portion 14 is closed with a resin layer 12. The lower opening of the second housing portion 14 is closed with a resin layer 13. The interior of the second housing portion 14 is filled with a sealing resin portion 30 except for the portion where the semiconductor device 20 is located.

[0011] FIG. 2 is a cross-sectional view showing a semiconductor device 20 according to the first embodiment. FIG. 3 is a plan view showing the semiconductor device 20 according to the first embodiment. In the first embodiment, the semiconductor device 20 is, for example, a vertical field effect transistor (FET). The semiconductor device 20 is, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET). As shown in FIGS. 2 and 3 , the semiconductor device 20 has a thin plate shape in the thickness direction Z. As shown in FIG. 3 , the semiconductor device 20 has a substantially square shape with sides extending along the first direction X and the second direction Y when viewed in the thickness direction Z. As shown in FIG. 2 , the semiconductor device 20 includes a semiconductor device body 50, a lead frame 60, conductive bump portions 80, and a resin portion 70.

[0012] In the first embodiment, the semiconductor device body 50 is a semiconductor chip on which electrodes of a field-effect transistor are formed. The semiconductor device body 50 is accommodated inside a first accommodation portion 63 (described later) of a lead frame 60. The semiconductor device body 50 includes a substrate portion 51, a first metal film 52a, a second metal film 52b, and a third metal film 52c. As shown in FIGS. 2 and 3 , the substrate portion 51 is plate-shaped with its surface facing the thickness direction Z. The substrate portion 51 has a rectangular shape when viewed in the thickness direction Z. The material constituting the substrate portion 51 is a semiconductor material. Examples of the material constituting the substrate portion 51 include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN).

[0013] The first metal film 52a and the second metal film 52b are formed on the upper surface of the substrate portion 51. The third metal film 52c is formed on the lower surface of the substrate portion 51. As shown in FIG. 3, the first metal film 52a is formed at one corner of the upper surface of the substrate portion 51. The first metal film 52a is substantially square-shaped when viewed in the thickness direction Z. The second metal film 52b is formed across the remaining three corners of the upper surface of the substrate portion 51. The second metal film 52b is substantially L-shaped when viewed in the thickness direction Z. The second metal film 52b has a portion adjacent to the first metal film 52a in the first direction X and a portion adjacent to the first metal film 52a in the second direction Y. As shown in FIG. 2, the third metal film 52c is formed over the entire lower surface of the substrate portion 51.

[0014] The first metal film 52a, the second metal film 52b, and the third metal film 52c are formed by, for example, sputtering. The materials constituting the first metal film 52a and the second metal film 52b are, for example, the same. The materials constituting the first metal film 52a and the second metal film 52b are not particularly limited as long as they are conductive, but are, for example, aluminum. The material constituting the third metal film 52c is not particularly limited as long as it is conductive, but is, for example, a material containing one or more materials such as titanium (Ti), nickel (Ni), gold (Au), silver (Ag), and copper (Cu). The third metal film 52c is, for example, a Ti / Ni / Au laminated film or a Ti / Ni / Ag laminated film.

[0015] In the first embodiment, the first metal film 52a is a gate electrode. The second metal film 52b is a source electrode. The third metal film 52c is a drain electrode. Each metal film may be any electrode. Furthermore, the third metal film 52c does not have to be an electrode. In this case, three metal films may be formed on the upper surface of the substrate portion 51, and the three metal films may correspond to the gate electrode, source electrode, and drain electrode, respectively.

[0016] The semiconductor device body 50 is electrically connected to the lead frame 60. The lead frame 60 is a conductive member made of metal. The material constituting the lead frame 60 is not particularly limited as long as it is conductive, but may be, for example, copper (Cu). Although not shown, a silver (Ag) coating is formed on the surface of the lead frame 60 to prevent oxidation. However, this coating does not have to be formed. The lead frame 60 has a support portion 61 that supports the semiconductor device body 50 from below, a frame portion 62 that protrudes upward from the support portion 61, and a protrusion 64 that protrudes from the support portion 61 in a direction perpendicular to the thickness direction Z.

[0017] The semiconductor device body 50 is joined to the upper surface of the support portion 61 via a joint portion 53. The joint portion 53 is conductive. The joint portion 53 is, for example, solder, a metal paste, or the like. In the first embodiment, the joint portion 53 electrically connects the upper surface of the support portion 61 and the third metal film 52c.

[0018] 3, in the first embodiment, the frame portion 62 has a rectangular frame shape. The frame portion 62 surrounds the semiconductor device body 50. As shown in FIG. 2, the upper surface of the frame portion 62 is located at the same position as the upper surface of the semiconductor device body 50 in the thickness direction Z. The upper surface of the frame portion 62 may be located higher than the upper surface of the semiconductor device body 50, or may be located lower than the upper surface of the semiconductor device body 50.

[0019] The support portion 61 and the frame portion 62 form a first accommodation portion 63 that opens upward. In the first embodiment, the upper surface of the frame portion 62 is the periphery of the opening of the first accommodation portion 63 on the upper surface of the lead frame 60. The protrusion portion 64 is connected to the support portion 61. A plurality of protrusion portions 64 are provided. The plurality of protrusion portions 64 includes a protrusion portion 64 that protrudes from the support portion 61 in the first direction X and a protrusion portion 64 that protrudes from the support portion 61 in the second direction Y.

[0020] The conductive bump portion 80 is a bump having conductivity. In this specification, the term "conductive bump portion" refers to, for example, a portion formed as a mass of a conductive material having a certain thickness. "A certain thickness" refers to, for example, a thickness greater than the thickness of a film generally formed by sputtering and the thickness of a film generally formed by plating. In the first embodiment, the dimension of the conductive bump portion 80 in the thickness direction Z is greater than 4 μm. As an example, the dimension of the conductive bump portion 80 in the thickness direction Z is approximately 10 μm or more and 50 μm or less. The dimension of the conductive bump portion 80 in the thickness direction Z is not particularly limited.

[0021] In the first embodiment, the conductive bump portion 80 is formed by a stud bump. The stud bump is formed by performing ball bonding using a bonding wire and then cutting the bonding wire. FIG. 4 is a cross-sectional view showing a stud bump 180 for forming the conductive bump portion 80. The stud bump 180 has a generally conical shape whose outer diameter decreases toward the top. The stud bump 180 has a base portion 181 bonded to an object to which the stud bump 180 is connected, and a reduced diameter portion 182 protruding from the base portion 181. The outer diameter of the reduced diameter portion 182 decreases with increasing distance from the base portion 181.

[0022] The outer diameter D1 shown in FIG. 4 is the outer diameter of the bonding wire. For example, the outer diameter of a portion of the upper part of the reduced diameter portion 182 is equal to the outer diameter D1 of the bonding wire. The outer diameter D1 of the bonding wire is not particularly limited, but is, for example, approximately 20 μm or more and 100 μm or less. The outer diameter D2 of the base portion 181 is, for example, approximately two times or more and three times the outer diameter D1 of the bonding wire. The height H2 of the base portion 181 is, for example, approximately one-fifth the outer diameter D2 of the base portion 181. The height H1 of the stud bump 180 can be arbitrarily increased by overlapping ball bonding. The conductive bump portion 80 of the first embodiment is formed by cutting a portion of the reduced diameter portion 182 of the stud bump 180. Specifically, for example, the conductive bump portion 80 is formed by cutting a portion of the reduced diameter portion 182 of the stud bump 180 along the imaginary line CL shown in FIG. 4. 4, the imaginary line CL is located at a portion of the reduced diameter portion 182 whose outer diameter is larger than the outer diameter D1 of the bonding wire. Therefore, the outer diameter D3 at the upper end of the conductive bump portion 80 is smaller than the outer diameter D2 of the base portion 181 and larger than the outer diameter D1 of the bonding wire.

[0023] Because the conductive bump portion 80 is formed by cutting a portion of the upper portion of the stud bump 180, the conductive bump portion 80 has a generally truncated cone shape with an outer diameter that decreases toward the top. The upper end face of the conductive bump portion 80 is a flat surface perpendicular to the thickness direction Z. The material constituting the conductive bump portion 80 is not particularly limited as long as it is conductive, and examples thereof include gold (Au), silver (Ag), and copper (Cu). From the perspective of ease of manufacturing the stud bump 180, it is preferable to select gold (Au) as the material constituting the conductive bump portion 80. From the perspective of reducing manufacturing costs, it is preferable to select copper (Cu) as the material constituting the conductive bump portion 80.

[0024] As shown in FIG. 2 , the conductive bump 80 includes a first conductive bump 81 and a second conductive bump 82. The first conductive bump 81 is electrically connected to the semiconductor device body 50. More specifically, the first conductive bump 81 is connected to the upper surface of the semiconductor device body 50. A plurality of first conductive bumps 81 are provided. The plurality of first conductive bumps 81 include a first conductive bump 81 electrically connected to the first metal film 52 a and a first conductive bump 81 electrically connected to the second metal film 52 b. As shown in FIG. 3 , for example, only one first conductive bump 81 is provided electrically connected to the first metal film 52 a. Note that two or more first conductive bumps 81 electrically connected to the first metal film 52 a may be provided. A plurality of first conductive bumps 81 electrically connected to the second metal film 52 b are provided. A plurality of first conductive bump portions 81 electrically connected to the second metal film 52b are arranged side by side in the first direction X and the second direction Y, so as to be spread out on the approximately L-shaped second metal film 52b.

[0025] As shown in FIG. 2 , the second conductive bump 82 is electrically connected to the lead frame 60. In the first embodiment, the second conductive bump 82 is electrically connected to the upper surface of the frame 62. In other words, the second conductive bump 82 is connected to the periphery of the opening of the first accommodation portion 63 on the upper surface of the lead frame 60. The second conductive bump 82 is electrically connected to the third metal film 52c via the lead frame 60 and the bonding portion 53. A plurality of second conductive bumps 82 are provided. As shown in FIG. 3 , in the first embodiment, the plurality of second conductive bumps 82 are arranged in a rectangular frame shape along the frame 62. When viewed from above, the plurality of second conductive bumps 82 are arranged to surround the first conductive bump 81.

[0026] In the first embodiment, the material constituting the first conductive bump portion 81 is the same as the material constituting the second conductive bump portion 82. In addition, in the first embodiment, the material constituting the first conductive bump portion 81 and the material constituting the second conductive bump portion 82 is different from the material constituting the lead frame 60.

[0027] 2 , the resin portion 70 covers and holds at least a portion of the semiconductor device body 50 and at least a portion of the lead frame 60. In the first embodiment, the resin portion 70 covers the entire semiconductor device body 50, the entire lead frame 60 except for the tip surfaces of the protrusions 64, and the entire conductive bump portions 80 except for the upper end surfaces. In the first embodiment, the semiconductor device body 50, the lead frame 60, and the conductive bump portions 80 are embedded and held in the resin portion 70. In the first embodiment, the resin portion 70 is formed by resin molding using a mold.

[0028] The upper surface of the resin portion 70 constitutes a part of the first surface 20a of the semiconductor device 20 facing upward. The resin portion 70 covers the entire lower surface of the lead frame 60. The lower surface of the resin portion 70 constitutes the second surface 20b of the semiconductor device 20 facing downward. At least a part of the conductive bump portion 80 is exposed to the outside of the resin portion 70. In the first embodiment, the upper end faces of the plurality of conductive bump portions 80 are exposed to the outside of the resin portion 70. More specifically, the upper end faces of the plurality of conductive bump portions 80 are exposed on the first surface 20a of the semiconductor device 20. In the first embodiment, the first surface 20a is formed by the upper surface of the resin portion 70 and the upper end faces of the plurality of conductive bump portions 80. The material constituting the resin portion 70 is not particularly limited as long as it is a resin having insulating properties. The material constituting the resin portion 70 may be a mold resin or an interlayer insulating material.

[0029] In the first embodiment, the upper end face of the first conductive bump portion 81 and the upper end face of the second conductive bump portion 82 are exposed on the first surface 20a. That is, the end faces of the first conductive bump portion 81 and the second conductive bump portion 82 are exposed on the same surface of the semiconductor device 20. As shown in FIG. 3 , in the first embodiment, the upper end faces of the first conductive bump portion 81 and the second conductive bump portion 82 are circular. The first conductive bump portion 81 connected to the first metal film 52a has its upper end face exposed to the outside of the resin portion 70, thereby functioning as a gate electrode of the semiconductor device 20. The first conductive bump portion 81 connected to the second metal film 52b has its upper end face exposed to the outside of the resin portion 70, thereby functioning as a source electrode of the semiconductor device 20. The second conductive bump portion 82, which is electrically connected to the third metal film 52c via the lead frame 60 and the joint portion 53, functions as a drain electrode of the semiconductor device 20 by having its upper end surface exposed to the outside of the resin portion 70.

[0030] 1 , the semiconductor device 20 is accommodated in the second accommodation portion 14 of the substrate main body 10 and is built into the substrate main body 10. The second surface 20b of the semiconductor device 20 is in contact with the upper surface of the resin layer 13. The first surface 20a of the semiconductor device 20 is disposed downward and spaced apart from the lower surface of the resin layer 12. A portion of the sealing resin portion 30 is interposed between the first surface 20a and the resin layer 12 in the thickness direction Z.

[0031] The wiring portion 40 forms at least a portion of the circuit pattern formed on the circuit board 100. The wiring portion 40 includes a first wiring pattern 41 formed on the upper surface of the substrate main body 10 and a second wiring pattern 42 formed on the lower surface of the substrate main body 10. The wiring portion 40 is electrically connected to a portion of the conductive bump portion 80 exposed outside the resin portion 70 via a hole portion 15 formed in the substrate main body 10. The hole portion 15 extends from the outer surface of the substrate main body 10 to the portion of the conductive bump portion 80 exposed outside the resin portion 70. In the first embodiment, the hole portion 15 is a hole recessed downward from the upper surface of the substrate main body 10. The hole portion 15 penetrates the resin layer 12 and a portion of the sealing resin portion 30 located above the semiconductor device 20 in the thickness direction Z. The inner diameter of the hole portion 15, for example, decreases toward the bottom. The hole portion 15 is formed by drilling using laser light. A plurality of holes 15 are formed. The plurality of holes 15 are respectively positioned above the plurality of conductive bumps 80. At the lower end of each hole 15, the upper end face of each conductive bump 80 is exposed.

[0032] The wiring portion 40 has a connection wiring portion 43 formed inside the hole 15. The connection wiring portion 43 is provided for each of the plurality of holes 15. The connection wiring portion 43 is electrically connected to the conductive bump portion 80. More specifically, the lower end of each connection wiring portion 43 is electrically connected to the upper end surface of each conductive bump portion 80 exposed in each hole 15. The upper end of each connection wiring portion 43 is connected to the first wiring pattern 41. In the first embodiment, the connection wiring portion 43 fills the hole 15. Note that the connection wiring portion 43 may be a conductive film formed on the inner circumferential surface of the hole 15.

[0033] The wiring portion 40 has a connection wiring portion 44 that connects the first wiring pattern 41 and the second wiring pattern 42. The connection wiring portion 44 is formed in a through hole 16 that penetrates the substrate main body 10 in the thickness direction Z. In the first embodiment, the connection wiring portion 44 fills the through hole 16. Note that the connection wiring portion 44 may be a conductive film formed on the inner circumferential surface of the through hole 16.

[0034] FIG. 5 is a flowchart showing a manufacturing method of the semiconductor device 20 of the first embodiment. As shown in FIG. 5, the manufacturing method of the semiconductor device 20 includes a first housing portion forming step S11, a chip fixing step S12, a stud bump forming step S13, a molding step S14, a grinding step S15, and a singulation step S16. FIG. 6A is a cross-sectional view showing the first housing portion forming step S11. FIG. 6B is a cross-sectional view showing the chip fixing step S12. FIG. 6C is a cross-sectional view showing the stud bump forming step S13. FIG. 6D is a cross-sectional view showing the state after the stud bump forming step S13 has been performed. FIG. 6E is a cross-sectional view showing the state after the molding step S14 has been performed. FIG. 6F is a cross-sectional view showing the state after the grinding step S15 has been performed.

[0035] As shown in FIG. 6A , the first housing portion forming step S11 is a step of forming a first housing portion 63 in a base material 160 for forming a lead frame 60. FIG. 7 is a plan view showing the base material 160. The base material 160 has a plurality of frame main body portions 161. The plurality of frame main body portions 161 are arranged in a matrix. Adjacent frame main body portions 161 are connected to each other by two connecting portions 162. As shown in FIG. 6A , the dimension of the connecting portion 162 in the thickness direction Z is smaller than the dimension of the frame main body portion 161 in the thickness direction Z. The connecting portion 162 is connected to the lower end of the frame main body portion 161. In the first housing portion forming step S11 of the first embodiment, a first housing portion 63 recessed downward is formed in each frame main body portion 161 by etching. As shown in FIG. 6B , the formation of the first housing portion 63 results in the formation of a support portion 61 and a frame portion 62 in each frame main body portion 161.

[0036] The chip fixing process S12 is a process of fixing the semiconductor device body 50 in the first housing portion 63. As shown in Figures 6B and 6C, in the chip fixing process S12, the semiconductor device body 50 is housed in the first housing portion 63 from above and fixed to the support portion 61 by the joint portion 53. In the chip fixing process S12, one semiconductor device body 50 is fixed in each of the first housing portions 63 formed in each frame main body portion 161 of the base material 160.

[0037] 6C and 6D , the stud bump formation step S13 is a step of forming a plurality of stud bumps 180 on the upper surface of the semiconductor device body 50 and the upper surface of the frame portion 62. As described above, the stud bumps 180 are formed by performing ball bonding using a bonding wire and then cutting the bonding wire. The stud bumps 180 formed on the upper surface of the semiconductor device body 50 are stud bumps 180 that form the first conductive bump portion 81. The stud bumps 180 formed on the upper surface of the frame portion 62 are stud bumps 180 that form the second conductive bump portion 82.

[0038] The molding step S14 is a step of performing insert molding using the base material 160, to which the semiconductor device body 50 is fixed and on which the stud bumps 180 are formed, as an insert member. As shown in Fig. 6E, the molding step S14 forms the base material 160, the semiconductor device body 50, and the resin part 170 in which the stud bumps 180 are embedded.

[0039] The grinding step S15 is a step of grinding the resin part 170 from above to reduce the dimension of the resin part 170 in the thickness direction Z. In the grinding step S15, the resin part 170 is ground until the dimension of the resin part 170 in the thickness direction Z matches the dimension of the semiconductor device 20 in the thickness direction Z. As shown in FIG. 6F , the grinding step S15 grinds the resin part 170 from above, exposing the stud bumps 180 on the upper surface of the resin part 170. In the grinding step S15, the upper portions of the stud bumps 180 are also ground together with the resin part 170. By grinding and removing the upper portions of the stud bumps 180 in the grinding step S15, each stud bump 180 becomes each conductive bump part 80.

[0040] The singulation process S16 is a process in which the resin portion 170 and the base material 160 are diced to separate each frame main body portion 161. In the singulation process S16, each connection portion 162 is cut to separate the base material 160. In this way, a plurality of semiconductor devices 20 are manufactured.

[0041] FIG. 8 is a flowchart showing a manufacturing method of the circuit board 100 of the first embodiment. As shown in FIG. 8, the manufacturing method of the circuit board 100 includes a support substrate fixing step S21, a semiconductor device accommodating step S22, a sealing step S23, a support substrate removing step S24, a resin layer forming step S25, a laser processing step S26, and a wiring portion forming step S27. FIG. 9A is a cross-sectional view showing the semiconductor device accommodating step S22. FIG. 9B is a cross-sectional view showing the state after the sealing step S23 has been performed. FIG. 9C is a cross-sectional view showing the laser processing step S26. FIG. 9D is a cross-sectional view showing the state after the laser processing step S26 has been performed.

[0042] The support substrate fixing step S21 is a step of fixing a support substrate 90 to the base member 11 in which the second accommodation section 14 is formed. The support substrate 90 is plate-shaped with its plate surface facing the thickness direction Z. The support substrate 90 is made of, for example, stainless steel. The material constituting the support substrate 90 is not particularly limited. Although not shown in the drawings, an adhesive layer is formed on the upper surface of the support substrate 90. In the support substrate fixing step S21, the support substrate 90 is fixed to the lower surface of the base member 11 via the adhesive layer. As a result, the lower opening of the second accommodation section 14 is blocked by the support substrate 90, as shown in FIG. 9A .

[0043] The semiconductor device accommodating step S22 is a step of accommodating the semiconductor device 20 in the second accommodating section 14. As shown in Fig. 9A , in the semiconductor device accommodating step S22, the semiconductor device 20 is inserted into the second accommodating section 14 through an upper opening of the second accommodating section 14. As shown in Fig. 9B , the semiconductor device 20 inserted into the second accommodating section 14 is placed on the upper surface of a support substrate 90 and fixed to the support substrate 90 via an adhesive layer formed on the support substrate 90.

[0044] The sealing step S23 is a step of sealing the second housing portion 14 with resin. In the sealing step S23, resin is poured into the second housing portion 14 with the semiconductor device 20 housed therein, to form a sealing resin portion 30. By forming the sealing resin portion 30, the semiconductor device 20 is embedded in the sealing resin portion 30 and is fixed to the base portion 11 via the sealing resin portion 30. The support substrate removal step S24 is a step of removing the support substrate 90 from the base portion 11. There are no particular limitations on the method of removing the support substrate 90 in the support substrate removal step S24.

[0045] The resin layer forming step S25 is a step of forming a pair of resin layers 12, 13. In the resin layer forming step S25, the pair of resin layers 12, 13 are formed simultaneously, for example. Note that in the resin layer forming step S25, the pair of resin layers 12, 13 may be formed sequentially. By the resin layer forming step S25, as shown in FIG. 9C , the resin layer 12 is formed on the upper surface of the substrate 11, and the resin layer 13 is formed on the lower surface of the substrate 11.

[0046] The laser processing step S26 is a step of forming the hole 15 and the through-hole 16 by irradiating the resin layer 12 with laser light LB. As shown in FIG. 9C , in the laser processing step S26, the resin layer 12 is irradiated with laser light LB from above downward. The laser light LB that forms the hole 15 is irradiated toward the conductive bump 80. The laser light LB irradiated from above the resin layer 12 toward the conductive bump 80 penetrates the resin layer 12 and the portion of the sealing resin part 30 located above the conductive bump 80, and is irradiated onto the conductive bump 80. The laser light LB is blocked by the conductive bump 80. In the first embodiment, the conductive bump 80 functions as an absorption layer for the laser light LB. This forms the hole 15 that extends from the upper surface of the resin layer 12 to the conductive bump 80. The laser light LB that forms the through-hole 16 is irradiated at a position that does not overlap with the second housing part 14 in the thickness direction Z. The laser beam LB that forms the through holes 16 penetrates the resin layer 12, the substrate 11, and the resin layer 13 in the thickness direction Z to form the through holes 16. By the laser processing step S26, a plurality of holes 15 and a plurality of through holes 16 are formed, as shown in FIG. 9D . Note that the through holes 16 may be formed using a drill instead of the laser beam LB. In this case, the shape of the through holes 16 will be a straight shape with a substantially uniform inner diameter.

[0047] The wiring portion forming process S27 is a process for forming the wiring portion 40. In the wiring portion forming process S27, a metal layer is formed by, for example, plating on the upper surface of the resin layer 12, the lower surface of the resin layer 13, the inside of the hole 15, and the inside of the through hole 16, thereby forming the wiring portion 40. Through the above processes, the circuit board 100 of the first embodiment shown in FIG. 1 is manufactured.

[0048] According to the first embodiment, the semiconductor device 20 has a first surface 20a facing upward and a second surface 20b facing downward, and includes a semiconductor device body 50, a lead frame 60 to which the semiconductor device body 50 is electrically connected, conductive bump portions 80 electrically connected to the semiconductor device body 50 or the lead frame 60, and a resin portion 70 that covers and holds at least a portion of the semiconductor device body 50 and at least a portion of the lead frame 60. At least a portion of the conductive bump portions 80 is exposed to the outside of the resin portion 70. Therefore, even if the semiconductor device body 50 is covered with the resin portion 70, the semiconductor device body 50 can be electrically connected to other components via the conductive bump portions 80 exposed to the outside of the resin portion 70. This allows the semiconductor device 20 to be a packaged semiconductor device in which the semiconductor device body 50, fixed to the lead frame 60, is covered with the resin portion 70. By being able to package the semiconductor device 20 including not only the semiconductor device main body 50 but also the lead frame 60 and the resin portion 70, the semiconductor device 20 can be made easier to handle even when the semiconductor device main body 50 is made thinner. This improves the handleability of the semiconductor device 20. This improves the yield of products on which the semiconductor device 20 is mounted, and improves the productivity of products on which the semiconductor device 20 is mounted. In the first embodiment, the yield when manufacturing the circuit board 100 by mounting the semiconductor device 20 on the board main body 10 can be improved, and the productivity of the circuit board 100 can be improved.

[0049] Furthermore, by electrically connecting the lead frame 60 to the electrodes of the semiconductor device body 50, the positions of the electrodes to which external terminals are connected in the semiconductor device 20 can be freely designed. Specifically, for example, in the first embodiment, the lead frame 60 is connected to the third metal film 52c serving as a drain electrode provided on the lower surface of the semiconductor device body 50, and the second conductive bump portion 82 connected to the lead frame 60 is exposed on the upper first surface 20a, thereby enabling the drain electrode of the semiconductor device 20 to be located on the upper surface of the semiconductor device 20. This allows the gate electrode, source electrode, and drain electrode to be provided on the upper surface of the semiconductor device 20. Therefore, while the semiconductor device body 50 is a vertical-structure field-effect transistor, the semiconductor device 20 as a whole can be treated as a horizontal-structure field-effect transistor. In this way, the degree of freedom in the arrangement of the electrodes to which external terminals are connected in the semiconductor device 20 can be easily adopted, depending on the product to which the semiconductor device 20 is mounted, and the productivity of the product to which the semiconductor device 20 is mounted can be further improved. In the first embodiment, the productivity of the circuit board 100 incorporating the semiconductor device 20 can be further improved.

[0050] Furthermore, heat from the semiconductor device body 50 can be easily released to the outside via the lead frame 60. This improves the heat dissipation of the semiconductor device 20. Furthermore, the conductive bump portion 80 has a larger dimension in the thickness direction Z and a larger heat capacity than, for example, a conductive film formed by plating. Therefore, by connecting the conductive bump portion 80 to the semiconductor device body 50, heat can be more easily transferred from the semiconductor device body 50 to the conductive bump portion 80 than, for example, when a conductive film formed by plating is provided on the semiconductor device body 50 instead of the conductive bump portion 80. This makes it easier to release heat from the semiconductor device body 50 to the outside, further improving the heat dissipation of the semiconductor device 20.

[0051] Furthermore, when forming a conductive film by plating on the lower surface of the thin semiconductor device body 50, using plating not only makes the process complicated but is also technically difficult. In contrast, in the first embodiment, since the lead frame 60 can be fixed to the lower surface of the semiconductor device body 50, there is no need to form a conductive film by plating on the lower surface of the semiconductor device body 50.

[0052] Furthermore, according to the first embodiment, the conductive bump portion 80 includes a first conductive bump portion 81 electrically connected to the semiconductor device body 50 and a second conductive bump portion 82 electrically connected to the lead frame 60. This makes it easy to electrically connect other members to the semiconductor device body 50 and the lead frame 60 from outside the semiconductor device 20 via the first conductive bump portion 81 and the second conductive bump portion 82.

[0053] Furthermore, according to the first embodiment, the end faces of the first conductive bump portion 81 and the second conductive bump portion 82 are exposed on the same surface of the semiconductor device 20. Therefore, compared to when the first conductive bump portion 81 and the second conductive bump portion 82 are exposed on different surfaces of the semiconductor device 20, the work of electrically connecting other members to the first conductive bump portion 81 and the second conductive bump portion 82 can be facilitated. This further improves the productivity of products on which the semiconductor device 20 is mounted. Furthermore, because the work of forming the first conductive bump portion 81 and the second conductive bump portion 82 can be performed from the same side, the number of steps required to manufacture the semiconductor device 20 can be reduced. This improves the productivity of the semiconductor device 20.

[0054] Furthermore, according to the first embodiment, the first conductive bump 81 is connected to the upper surface of the semiconductor device body 50. The lead frame 60 has a first housing portion 63 that opens upward. The semiconductor device body 50 is housed within the first housing portion 63. The second conductive bump 82 is connected to the periphery of the opening of the first housing portion 63 on the upper surface of the lead frame 60. The upper end surfaces of the first conductive bump 81 and the second conductive bump 82 are exposed on the first surface 20a. This makes it easy to align the positions of the upper surface of the semiconductor device body 50 and the periphery of the opening of the first housing portion 63 on the upper surface of the lead frame 60 in the thickness direction Z, making it easy to form the first conductive bump 81 and the second conductive bump 82 by a similar method. Specifically, in the first embodiment, the first conductive bump 81 and the second conductive bump 82 can be formed by forming similar stud bumps 180. This makes it easier to form the first conductive bump portion 81 and the second conductive bump portion 82 .

[0055] Furthermore, according to the first embodiment, the conductive bump portion 80 is formed by a stud bump. In other words, the first conductive bump portion 81 and the second conductive bump portion 82 are formed by a stud bump. Therefore, the first conductive bump portion 81 and the second conductive bump portion 82 can be easily formed by ball bonding using a bonding wire. This reduces the number of steps required to form a conductive portion electrically connected to the semiconductor device body 50 or the lead frame 60 compared to forming a conductive film by plating instead of the conductive bump portion 80. Therefore, the manufacturing cost of the semiconductor device 20 can be reduced.

[0056] Furthermore, according to the first embodiment, a plurality of second conductive bump portions 82 are provided, and the plurality of second conductive bump portions 82 are arranged surrounding the first conductive bump portion 81 when viewed from above. This makes it easy to connect an external terminal or the like to the second conductive bump portion 82. This also allows heat from the third metal film 52c serving as the drain electrode to be dissipated efficiently over a large area to the side (upper side) where the semiconductor device 20 is mounted.

[0057] Furthermore, according to the first embodiment, the material constituting the first conductive bump portion 81 and the material constituting the second conductive bump portion 82 are the same as each other but different from the material constituting the lead frame 60. For example, a configuration is also conceivable in which the conductive bump portion 80 is not connected to the lead frame 60, and the lead frame 60 itself is exposed outside the resin portion 70 to serve as a terminal portion of the semiconductor device 20. In this case, in the grinding step S15 described above, when the resin portion 170 is ground, a portion of the conductive bump portion 80 and a portion of the lead frame 60 are ground together with the resin portion 170, so that a portion of the conductive bump portion 80 and a portion of the lead frame 60 are exposed outside the resin portion 70. In this case, if the material constituting the conductive bump portion 80 and the material constituting the lead frame 60 are different from each other, it becomes necessary to grind three different materials, including the resin portion 170, which may make the grinding process difficult. In contrast, in the first embodiment, by providing second conductive bump portion 82 connected to lead frame 60 and forming second conductive bump portion 82 from the same material as first conductive bump portion 81, it is possible to reduce the amount of other material to be ground when grinding resin portion 170 in grinding step S15 to one type. This makes it easier to perform the grinding process in grinding step S15. Furthermore, by using the same material for first conductive bump portion 81 and second conductive bump portion 82, it is easier to form multiple conductive bump portions 80.

[0058] Furthermore, according to the first embodiment, the semiconductor device 20 is embedded in the substrate main body 10. Therefore, the length of the wiring connecting the electrodes of the semiconductor device 20 to the wiring pattern formed on the substrate main body 10 can be shortened, compared to when the semiconductor device 20 is attached to the surface of the substrate main body 10 and the electrodes of the semiconductor device 20 are connected to the wiring pattern formed on the substrate main body 10 by wire bonding or the like. This makes it easier to reduce the resistance between the electrodes of the semiconductor device 20 and the wiring pattern formed on the substrate main body 10, and facilitates the flow of current between the electrodes of the semiconductor device 20 and the wiring pattern formed on the substrate main body 10. Therefore, the circuit board 100 can be easily adapted to high-speed communications in which high-frequency electrical signals flow. Furthermore, the circuit board 100 can be more compact than when the semiconductor device 20 is attached to the surface of the substrate main body 10 and the electrodes of the semiconductor device 20 are connected to the wiring pattern formed on the substrate main body 10 by wire bonding or the like. Furthermore, it is possible to form other layers in the thickness direction Z and mount other devices in the portion of the substrate main body 10 in which the semiconductor device 20 is embedded. This allows for greater freedom in designing the circuit board 100 .

[0059] Furthermore, according to the first embodiment, the substrate main body 10 has a second housing portion 14 that houses the semiconductor device 20 therein. The substrate main body 10 has a hole 15 formed therein, extending from the outer surface of the substrate main body 10 to the portion of the conductive bump 80 that is exposed outside the resin portion 70. A connection wiring portion 43 electrically connected to the conductive bump 80 is formed inside the hole 15. To form such a hole 15, the substrate main body 10 is processed using, for example, the laser processing described above to form the hole 15. In this process, to prevent the laser light LB from damaging the semiconductor device main body 50 and other components, an absorption layer that receives the laser light LB must be provided on the upper surface of the semiconductor device main body 50 and other components. If this absorption layer is a thin film formed by, for example, sputtering, the laser light LB may penetrate the thin film and damage the semiconductor device main body 50 and other components. In contrast, in the first embodiment, the conductive bump 80, which can be increased in size in the thickness direction Z to a certain extent, can serve as an absorption layer for the laser light LB. Therefore, when forming the hole 15 by laser processing, the laser light LB can be appropriately received by the conductive bump portion 80, and damage to the semiconductor device body 50 and the like can be suppressed.

[0060] Alternatively, for example, a conductive film having a relatively large dimension in the thickness direction Z can be formed on the semiconductor device body 50 by plating or the like, and the conductive film can be used as an absorption layer for the laser light LB when the hole 15 is formed. However, the process of forming a conductive film by plating tends to require many steps, which increases the manufacturing cost of the semiconductor device 20. Furthermore, the conductive film formed by plating may not be thick enough to function as an absorption layer. In contrast, in the first embodiment, instead of the conductive film formed by plating, a conductive bump portion 80 is formed, which is easily formed thicker than the conductive film. The number of steps required to form the conductive bump portion 80 tends to be fewer than the number of steps required to form a conductive film by plating. This prevents an increase in the manufacturing cost of the semiconductor device 20. Furthermore, the conductive bump portion 80 easily provides a sufficient thickness to function as an absorption layer.

[0061] Furthermore, according to the first embodiment, the manufacturing method for manufacturing the circuit board 100 includes forming the hole 15 by irradiating the conductive bump 80 with laser light LB. Therefore, as described above, the conductive bump 80 can be used as an absorption layer, and the laser light LB can be suitably prevented from penetrating the conductive bump 80. This makes it possible to suitably prevent the semiconductor device body 50 and the like from being damaged by the laser light LB.

[0062] Second Embodiment The second embodiment differs from the first embodiment in the number of second conductive bump portions 82. In the following description, the same components as those in the above-described embodiments may be denoted by the same reference numerals as appropriate, and the description thereof may be omitted.

[0063] FIG. 10 is a cross-sectional view showing a semiconductor device 220 of the second embodiment. FIG. 11 is a plan view showing the semiconductor device 220 of the second embodiment. As shown in FIGS. 10 and 11 , the semiconductor device 220 has a smaller number of second conductive bump portions 82 than the semiconductor device 20 of the first embodiment. Specifically, as shown in FIG. 11 , the second conductive bump portions 82 are arranged in an L-shape along two sides of the rectangular frame portion 62. In other words, the second conductive bump portions 82 are not provided on the other two sides of the rectangular frame portion 62. In this way, by not arranging the second conductive bump portions 82 in a frame shape and not providing the second conductive bump portions 82 on one or more of the four sides of the frame portion 62, the second conductive bump portions 82 can be prevented from interfering with the routing of wiring on a circuit board on which the semiconductor device 220 is mounted. This improves the degree of freedom in routing wiring on a circuit board on which the semiconductor device 220 is mounted. The other configurations of the semiconductor device 220 are similar to the other configurations of the semiconductor device 20 of the first embodiment.

[0064] (Third Embodiment) The third embodiment differs from the first embodiment in that it does not include the second conductive bump portion 82. In the following description, the same components as those in the above-described embodiments may be denoted by the same reference numerals as appropriate, and the description thereof may be omitted.

[0065] FIG. 12 is a cross-sectional view showing a semiconductor device 320 of the third embodiment. FIG. 13 is a plan view showing the semiconductor device 320 of the third embodiment. As shown in FIGS. 12 and 13 , unlike the semiconductor device 20 of the first embodiment, the semiconductor device 320 does not have a second conductive bump portion 82 connected to the lead frame 360. As shown in FIG. 12 , the upper end surface of the frame portion 362 of the lead frame 360 ​​is located above the upper surface of the semiconductor device body 50. The upper end surface of the frame portion 362 is exposed on a first upper surface 320a of the semiconductor device 320. In the third embodiment, the first surface 320a is composed of the upper surface of the resin portion 70, the upper end surfaces of the first conductive bump portions 81, and the upper end surface of the frame portion 362. In the third embodiment, the upper end surface of the frame portion 362 can be used as an absorption layer when performing the laser processing step S26.

[0066] In the third embodiment, the material constituting the lead frame 360 ​​and the material constituting the first conductive bump portion 81 are the same. Therefore, when performing the grinding step S15, only one type of material other than the resin portion 70 needs to be ground, making the grinding process easier. When the material constituting the lead frame 360 ​​and the material constituting the first conductive bump portion 81 are the same, for example, from the perspective of manufacturing cost, it is preferable that the material be copper (Cu). Note that in the third embodiment, the material constituting the lead frame 360 ​​and the material constituting the first conductive bump portion 81 may be different from each other. The other configurations of the semiconductor device 320 are the same as the other configurations of the semiconductor device 20 of the first embodiment.

[0067] (Fourth embodiment) The fourth embodiment differs from the first embodiment in the shape of the second conductive bump portion 482. In the following description, the same components as those in the above-described embodiments may be denoted by the same reference numerals as appropriate, and the description thereof may be omitted.

[0068] 14 is a cross-sectional view showing a semiconductor device 420 according to the fourth embodiment. As shown in Fig. 14, the first accommodation portion 63 is not formed in the lead frame 460 of the semiconductor device 420. The lead frame 460 is a flat plate whose plate surface faces in the thickness direction Z.

[0069] In the fourth embodiment, the second conductive bump portion 482 is formed by a vertical wire 480 a. The vertical wire 480 a is formed by performing ball bonding using a bonding wire, extending the bonding wire vertically from the stud bump formed by ball bonding, and cutting the bonding wire at a certain length. The second conductive bump portion 482 is connected to the upper surface of the lead frame 460.

[0070] The second conductive bump portion 482 has a stud bump portion 482a connected to the lead frame 460 and a wire portion 482b extending upward from the stud bump portion 482a. The stud bump portion 482a is a portion formed by a stud bump. The stud bump portion 482a has a shape similar to that of the stud bump 180 described in the first embodiment. The stud bump portion 482a is connected to the upper surface of the lead frame 460. In the fourth embodiment, the stud bump portion 482a and the semiconductor device body 50 are fixed to the same surface of the lead frame 460. In other words, the second conductive bump portion 482 and the semiconductor device body 50 are fixed to the same surface of the lead frame 460. The wire portion 482b is a portion formed by a bonding wire. The upper end surface of the wire portion 482b is exposed on the first surface 420a. The other configurations of the semiconductor device 420 are similar to those of the semiconductor device 20 of the first embodiment.

[0071] FIG. 15 is a flowchart showing a manufacturing method of the semiconductor device 420 of the fourth embodiment. As shown in FIG. 15, the manufacturing method of the semiconductor device 420 includes a chip fixing step S31, a stud bump forming step S32, a vertical wire forming step S33, a molding step S34, a grinding step S35, and a singulation step S36. FIG. 16A is a cross-sectional view showing the chip fixing step S31. FIG. 16B is a cross-sectional view showing the stud bump forming step S32 and the vertical wire forming step S33. FIG. 16C is a cross-sectional view showing the state after the stud bump forming step S32 and the vertical wire forming step S33 have been performed. FIG. 16D is a cross-sectional view showing the state after the molding step S34 has been performed. FIG. 16E is a cross-sectional view showing the state after the grinding step S35 has been performed.

[0072] 16A , the chip fixing step S31 is a step of fixing the semiconductor device body 50 to a base material 460a of a lead frame 460. The base material 460a is similar to the base material 160 of the first embodiment, except that, for example, the dimension in the thickness direction Z is constant throughout. Note that the base material 460a may be the same base material as the base material 160 of the first embodiment. In the chip fixing step S31, the semiconductor device body 50 is fixed to the upper surface of the base material 460a by bonding portions 53. In the chip fixing step S31, one semiconductor device body 50 is fixed to each of a plurality of frame body portions formed on the base material 460a.

[0073] The stud bump formation step S32 is similar to the stud bump formation step S13 in the first embodiment, except that only the first conductive bump portion 81 is formed. As shown in Figures 16B and 16C, the vertical wire formation step S33 is a step of forming a vertical wire 480a on a base material 460a of a lead frame 460. As described above, the vertical wire 480a is formed by performing ball bonding using a bonding wire, extending the bonding wire in a vertical direction from the stud bump formed by ball bonding, and cutting the bonding wire at a certain length.

[0074] 16B shows the stud bump forming step S32 and the vertical wire forming step S33 as being performed simultaneously, but this is not a limitation. The vertical wire forming step S33 may be performed after the stud bump forming step S32 is completed, or the stud bump forming step S32 may be performed after the vertical wire forming step S33 is completed, or the stud bump forming step S32 and the vertical wire forming step S33 may be performed simultaneously.

[0075] The molding step S34 is a step of performing insert molding using the base material 460a, to which the semiconductor device body 50 is fixed and on which the stud bumps 180 and vertical wires 480a are formed, as an insert member. As shown in Fig. 16D, the molding step S34 forms the resin part 170 in which the base material 460a, the semiconductor device body 50, the stud bumps 180, and the vertical wires 480a are embedded.

[0076] The grinding process S35 is a process of grinding the resin portion 170 from above to reduce the dimension of the resin portion 170 in the thickness direction Z. In the grinding process S35, the resin portion 170 is ground until the dimension of the resin portion 170 in the thickness direction Z matches the dimension of the semiconductor device 420 in the thickness direction Z. As shown in FIG. 16E , the grinding process S35 grinds the resin portion 170 from above, exposing the stud bumps 180 and the vertical wires 480a on the upper surface of the resin portion 170. In the grinding process S35, the upper portions of the stud bumps 180 and the upper portions of the wire portions of the vertical wires 480a are also ground along with the resin portion 170. In the grinding process S35, the upper portions of the stud bumps 180 are ground and removed, so that each stud bump 180 becomes a first conductive bump portion 81. In the grinding step S35, the upper portions of the wire portions of the vertical wires 480a are ground and removed, so that each vertical wire 480a becomes each second conductive bump portion 482.

[0077] The singulation step S36 is the same as the singulation step S16 of the first embodiment. The singulation step S36 forms a plurality of semiconductor devices 420. The other methods in the manufacturing method of the semiconductor device 420 are the same as the other methods in the manufacturing method of the semiconductor device 20 of the first embodiment.

[0078] According to the fourth embodiment, the second conductive bump 482 includes a stud bump 482a connected to the lead frame 460 and a wire 482b extending upward from the stud bump 482a. The upper end surface of the wire 482b is exposed on the first surface 420a. By configuring the second conductive bump 482 to be formed by the vertical wire 480a in this manner, the upper end of the second conductive bump 482 connected to the lead frame 460 can be positioned at the same position as the upper end of the first conductive bump 81, without forming the first accommodation portion 63 in the lead frame 460. This reduces the number of steps required to process the lead frame 460.

[0079] Fifth Embodiment The fifth embodiment differs from the first embodiment in the shape of the wiring portion 540. In the following description, the same components as those in the above-described embodiments may be denoted by the same reference numerals as appropriate, and the description thereof may be omitted.

[0080] 17 is a cross-sectional view showing a portion of a circuit board 500 of the fifth embodiment. As shown in FIG. 17, a board main body 510 of the circuit board 500 does not have a through hole 16 formed therein. A wiring portion 540 of the circuit board 500 does not have a second wiring pattern 42 or a connection wiring portion 44 formed in the through hole 16. The other configurations of the wiring portion 540 are the same as the other configurations of the wiring portion 40 of the first embodiment. The other configurations of the circuit board 500 are the same as the other configurations of the circuit board 100 of the first embodiment.

[0081] Sixth Embodiment The sixth embodiment differs from the first embodiment in that the circuit board 600 does not incorporate the semiconductor device 20. In the following description, the same components as those in the above-described embodiments may be denoted by the same reference numerals as appropriate, and the description thereof may be omitted.

[0082] 18 is a cross-sectional view showing a portion of a circuit board 600 according to the sixth embodiment. As shown in FIG. 18 , in the sixth embodiment, a semiconductor device 20 is attached to one surface of a substrate main body 610. The semiconductor device 20 is mounted on the substrate main body 610 by flip-chip mounting. The first conductive bump portion 81 and the second conductive bump portion 82 of the semiconductor device 20 are electrically connected to a wiring pattern (not shown) on the substrate main body 610 via bumps 691 formed by solder or the like. An adhesive layer 692 is formed between the semiconductor device 20 and the substrate main body 610 to bond the semiconductor device 20 to the substrate main body 610. The bumps 691 are embedded in the adhesive layer 692.

[0083] According to the sixth embodiment, the semiconductor device 20 is attached to one surface of the substrate main body 610. Therefore, the structure of the substrate main body 610 can be simplified compared to when the semiconductor device 20 is built into the substrate main body 610.

[0084] Furthermore, because the handleability of the semiconductor device body 50 is reduced when the semiconductor device body 50 is thinned, conventionally, it has been difficult to mount the semiconductor device body 50 on the substrate body 610 by flip-chip mounting. Furthermore, flip-chip mounting also poses structural constraints, such as the need for the semiconductor device body 50 to be a horizontal field-effect transistor. In response to this, the semiconductor device body 50 and the lead frame 60 are covered and packaged with a resin portion 70, improving the handleability of the semiconductor device 20, thereby facilitating the mounting of the semiconductor device 20 on the substrate body 610 by flip-chip mounting. Even when the semiconductor device body 50 is a vertical field-effect transistor, the gate electrode, source electrode, and drain electrode of the semiconductor device 20 can be provided on the same surface via the lead frame 60. This allows flip-chip mounting to be employed as a mounting method for the semiconductor device 20 regardless of the structure of the semiconductor device body 50.

[0085] According to at least one embodiment described above, the semiconductor device has a first surface facing a first side and a second surface facing a second side opposite the first side. The semiconductor device has a semiconductor device body, a lead frame to which the semiconductor device body is electrically connected, conductive bump portions electrically connected to the semiconductor device body or the lead frame, and a resin portion that covers and holds at least a portion of the semiconductor device body and at least a portion of the lead frame. At least a portion of the conductive bump portions is exposed to the outside of the resin portion. This improves the handleability of the semiconductor device.

[0086] The conductive bump portion is not limited to the conductive bump portion formed by the stud bump and the conductive bump portion formed by the vertical wire. The method of forming the conductive bump portion is not particularly limited. The conductive bump portion may be formed by a metal bump formed by screen printing or by an inkjet method. The entire conductive bump portion may be exposed to the outside of the resin portion.

[0087] The conductive bump may include only a first conductive bump or only a second conductive bump. The number of conductive bumps is not particularly limited as long as it is one or more. The surface of the semiconductor device on which the first conductive bump is exposed and the surface of the semiconductor device on which the second conductive bump is exposed may be different surfaces. When a plurality of first conductive bumps are provided, the plurality of first conductive bumps may include two or more first conductive bumps exposed on different surfaces of the semiconductor device. When a plurality of second conductive bumps are provided, the plurality of second conductive bumps may include two or more second conductive bumps exposed on different surfaces of the semiconductor device. The materials constituting the first conductive bump and the second conductive bump may be different from each other.

[0088] The configuration of the circuit board on which the semiconductor device is mounted is not particularly limited. The circuit board may be a multilayer board. The number of semiconductor devices mounted on the circuit board is not particularly limited, as long as it is one or more. The holes formed in the circuit board may be formed by a method other than laser processing. Even in this case, by forming conductive bump portions having a certain thickness, damage to the semiconductor device body, etc. can be suppressed.

[0089] The semiconductor device, circuit board, and circuit board manufacturing method of the embodiments include the following supplementary aspects: (Supplementary Note 1) A semiconductor device having a first surface facing a first side and a second surface facing a second side opposite to the first side, comprising: a semiconductor device body; a lead frame to which the semiconductor device body is electrically connected; conductive bump portions electrically connected to the semiconductor device body or the lead frame; and a resin portion covering and holding at least a portion of the semiconductor device body and at least a portion of the lead frame, wherein at least a portion of the conductive bump portions is exposed to the outside of the resin portion. (Supplementary Note 2) The semiconductor device according to Supplementary Note 1, wherein the conductive bump portions include a first conductive bump portion electrically connected to the semiconductor device body, and a second conductive bump portion electrically connected to the lead frame. (Appendix 3) The semiconductor device according to Appendix 2, wherein an end face of the first conductive bump portion and an end face of the second conductive bump portion are exposed on the same surface of the semiconductor device. (Appendix 4) The semiconductor device according to Appendix 3, wherein the first conductive bump portion is connected to the first side surface of the semiconductor device body, the lead frame has a first housing portion that opens to the first side, the semiconductor device body is housed inside the first housing portion, the second conductive bump portion is connected to a peripheral portion of the opening of the first housing portion on the first side surface of the lead frame, and the first side end face of the first conductive bump portion and the first side end face of the second conductive bump portion are exposed on the first surface. (Appendix 5) The semiconductor device according to Appendix 4, wherein the first conductive bump portion and the second conductive bump portion are formed by stud bumps.(Supplementary Note 6) The semiconductor device according to Supplementary Note 3, wherein the first conductive bump portion is connected to the first side surface of the semiconductor device body, the second conductive bump portion is connected to the first side surface of the lead frame, the first conductive bump portion is formed by a stud bump, and the second conductive bump portion has: a stud bump portion connected to the lead frame and a wire portion extending from the stud bump portion to the first side, and the first side end surface of the first conductive bump portion and the first side end surface of the wire portion are exposed on the first surface. (Supplementary Note 7) The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 3, wherein the conductive bump portion is formed by a stud bump. (Supplementary Note 8) The semiconductor device according to any one of Supplementary Note 4 to Supplementary Note 6, wherein a plurality of the second conductive bump portions are provided, and the plurality of second conductive bump portions are arranged surrounding the first conductive bump portion when viewed from the first side. (Supplementary Note 9) The semiconductor device according to any one of Supplementary Notes 2 to 6, wherein the first conductive bump portion and the second conductive bump portion are made of the same material but different from the material of the lead frame. (Supplementary Note 10) A circuit board comprising: the semiconductor device according to any one of Supplementary Notes 1 to 9; and a substrate main body portion on which the semiconductor device is mounted. (Supplementary Note 11) The circuit board according to Supplementary Note 10, wherein the semiconductor device is built into the substrate main body portion. (Supplementary Note 12) The circuit board according to Supplementary Note 11, wherein the substrate main body portion has a second housing portion that houses the semiconductor device therein, and wherein the substrate main body portion has a hole portion formed in it that extends from the outer surface of the substrate main body portion to a portion of the conductive bump portion that is exposed outside the resin portion, and wherein a connection wiring portion electrically connected to the conductive bump portion is formed inside the hole portion. (Supplementary Note 13) The circuit board according to Supplementary Note 10, wherein the semiconductor device is attached to one plate surface of the substrate main body portion. (Supplementary Note 14) A method for manufacturing the circuit board according to Supplementary Note 12, comprising forming the hole by irradiating the conductive bump with laser light.

[0090] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents.

[0091] DESCRIPTION OF SYMBOLS 10, 510, 610...substrate main body portion, 14...second accommodating portion, 15...hole portion, 20, 220, 320, 420...semiconductor device, 20a, 320a, 420a...first surface, 20b...second surface, 40, 540...wiring portion, 43...connecting wiring portion, 50...semiconductor device main body, 60, 360, 460...lead frame, 63...first accommodating portion, 70...resin portion, 80...conductive bump portion, 81...first conductive bump portion, 82, 482...second conductive bump portion, 100, 500, 600...circuit board, 180...stud bump, 482a...stud bump portion, 482b...wire portion, LB...laser light

Claims

1. A semiconductor device having a first surface facing a first side and a second surface facing a second side opposite to the first side, comprising: a semiconductor device body; a lead frame to which the semiconductor device body is electrically connected; a conductive bump portion electrically connected to the semiconductor device body or the lead frame; and a resin portion covering and holding at least a portion of the semiconductor device body and at least a portion of the lead frame, wherein at least a portion of the conductive bump portion is exposed to the outside of the resin portion.

2. The semiconductor device according to claim 1, wherein the conductive bump portion includes: a first conductive bump portion electrically connected to the semiconductor device body; and a second conductive bump portion electrically connected to the lead frame.

3. The semiconductor device according to claim 2, wherein an end face of said first conductive bump portion and an end face of said second conductive bump portion are exposed on the same surface of said semiconductor device.

4. The semiconductor device described in claim 3, wherein the first conductive bump portion is connected to the first side surface of the semiconductor device body, the lead frame has a first accommodating portion opening to the first side, the semiconductor device body is accommodated inside the first accommodating portion, the second conductive bump portion is connected to the peripheral opening portion of the first accommodating portion on the first side surface of the lead frame, and the first side end face of the first conductive bump portion and the first side end face of the second conductive bump portion are exposed to the first surface.

5. The semiconductor device according to claim 4, wherein the first conductive bump portion and the second conductive bump portion are formed by stud bumps.

6. The semiconductor device described in claim 3, wherein the first conductive bump portion is connected to the first side surface of the semiconductor device body, the second conductive bump portion is connected to the first side surface of the lead frame, the first conductive bump portion is formed by a stud bump, and the second conductive bump portion has a stud bump portion connected to the lead frame and a wire portion extending from the stud bump portion to the first side, and the first side end face of the first conductive bump portion and the first side end face of the wire portion are exposed to the first surface.

7. The semiconductor device according to claim 1, wherein the conductive bump portion is formed by a stud bump.

8. The semiconductor device according to claim 4, wherein a plurality of the second conductive bump portions are provided, and the plurality of second conductive bump portions are arranged surrounding the first conductive bump portion when viewed from the first side.

9. The semiconductor device according to claim 2, wherein the material constituting the first conductive bump portion and the material constituting the second conductive bump portion are the same as each other and different from the material constituting the lead frame.

10. A circuit board comprising: a semiconductor device according to any one of claims 1 to 9; and a board main body on which the semiconductor device is mounted.

11. The circuit board according to claim 10, wherein the semiconductor device is built into the board body.

12. The circuit board described in claim 11, wherein the substrate main body has a second accommodating portion for accommodating the semiconductor device therein, the substrate main body has a hole portion formed therein extending from the outer surface of the substrate main body to a portion of the conductive bump portion exposed to the outside of the resin portion, and a connection wiring portion electrically connected to the conductive bump portion is formed inside the hole portion.

13. The circuit board according to claim 10, wherein the semiconductor device is attached to one surface of the board body.

14. A method for manufacturing the circuit board according to claim 12, comprising forming the hole by irradiating the conductive bump with laser light.

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