Semiconductor device, power device, and power module

Abstract

A semiconductor device according to an embodiment of the present invention comprises a semiconductor chip 10 and a first conductive layer 12B provided on a first surface side of the semiconductor chip 10. The first conductive layer 12B includes an intermetallic compound layer containing copper (Cu), tin (Sn), and silver (Ag), and the concentration of silver relative to tin in the first conductive layer 12B is 1.0 at% to 7.9 at%.

Description

Semiconductor devices, power devices, and power modules

[0001] FIELD Embodiments of the present invention relate to a semiconductor device, a power device, and a power module.

[0002] 2. Description of the Related Art A power device having a structure in which a semiconductor chip is bonded to a copper member by an intermetallic compound is known.

[0003] “Evaluation of Ag-sinter and CuSn-TLP base joining technologies on lead frame”, A. Otto, et. al., Proc. PCIM Europe2018 (2018), 691-698. “Reliability modeling of Sn-Ag transient liquid phase die-bonds for high-power SiC devices”, AA Bajwa and J. Wilde, Microelectronics Reliability, 60(2016), 116-125. “Formation of Initial Defects in Solid-Liquid Reaction Diffusion Bonding of Cu Using Sn Film”, S. Fukumoto, et. al., Proc. MSES2017(2017), 61-64.

[0004] To improve the reliability of semiconductor devices.

[0005] A semiconductor device according to an embodiment includes a semiconductor chip and a first conductive layer provided on a first surface side of the semiconductor chip, the first conductive layer including an intermetallic compound layer containing copper (Cu), tin (Sn), and silver (Ag), and the concentration of the silver relative to the tin in the first conductive layer is 1.0 at% or more and 7.9 at% or less.

[0006] FIG. 1 is a cross-sectional view showing an example of the configuration of a semiconductor device according to an embodiment. FIG. 2 is a diagram showing experimental results of the semiconductor device according to an embodiment. FIG. 3 is a cross-sectional view showing a specific example of the semiconductor device according to an embodiment. FIG. 4 is a cross-sectional view showing a specific example of the semiconductor device according to an embodiment. FIG. 5 is a cross-sectional view showing a specific example of the semiconductor device according to an embodiment. FIG. 6 is a cross-sectional view showing a specific example of the semiconductor device according to an embodiment. FIG. 7 is a cross-sectional view showing a specific example of the semiconductor device according to an embodiment. FIG. 8 is a cross-sectional view showing a specific example of the semiconductor device according to an embodiment. FIG. 9 is a cross-sectional view showing a modified example of the semiconductor device according to an embodiment. FIG. 10 is a cross-sectional view showing a modified example of the semiconductor device according to an embodiment. Embodiment

[0007] Hereinafter, embodiments will be described with reference to the drawings. In the following description, elements having the same function and configuration will be given the same reference numerals. Furthermore, in the following embodiments, when components (e.g., circuits, wiring, various voltages and signals, etc.) are given reference numerals with distinguishing numbers / letters at the end, and do not need to be distinguished from one another, the reference numerals will be omitted. The dimensions and proportions of the drawings are not necessarily the same as those in reality.

[0008] Embodiment A semiconductor device according to an embodiment will be described with reference to FIGS. 1 to 10. FIG.

[0009] (1) Basic Example A basic example of a semiconductor device according to an embodiment will be described with reference to FIGS.

[0010] (Configuration) FIG. 1 is a cross-sectional view for explaining the structure of a basic example of a semiconductor device according to this embodiment.

[0011] 1A is a cross-sectional view showing the semiconductor device of this embodiment before being bonded to a copper base material, and FIG. 1B is a cross-sectional view showing the semiconductor device of this embodiment after being bonded to a copper base material.

[0012] 1, a semiconductor device 1 according to the embodiment is provided on a copper layer (Cu layer) 20, which is a copper-based material. The semiconductor device 1 includes a semiconductor chip 10, a conductive layer 11, conductive layers 12 (12A and 12B), and a pad (electrode) 19.

[0013] The semiconductor chip 10 has a cubic or rectangular parallelepiped structure and has a front surface (top surface) and a back surface (bottom surface) that extend in the XY plane.

[0014] The semiconductor chip 10 includes a silicon substrate (Si substrate) or a silicon carbide substrate (SiC substrate).

[0015] The semiconductor chip 10 is a chip for a vertical power device. An output current of the vertical power device flows between the front and back surfaces of the semiconductor chip 10. The semiconductor chip 10 includes an element section 100. The element section 100 includes a semiconductor element such as a MOS field effect transistor, an IGBT (Insulated Gate Bipolar Transistor), or a diode.

[0016] A lateral power device chip may be used as the semiconductor chip 10. In this case, no current flows through the copper base material side, and the copper base material serves as a heat sink.

[0017] For example, the power device formed on the semiconductor chip 10 is a Si device having a breakdown voltage of 20V to 200V, or a SiC device having a breakdown voltage of 600V to 4500V.

[0018] The pads 19 are provided on the surface of the semiconductor chip 10. The pads 19 are electrically connected to the element portion 100 via contact portions (not shown) and wiring (not shown) within the semiconductor chip 10.

[0019] The conductive layer 11 and the conductive layer 12 are provided on the back surface side of the semiconductor chip 10 in the Z direction.

[0020] The conductive layer 11 is provided between the semiconductor chip 10 and the conductive layer 12. The conductive layer 11 is provided under the back surface of the semiconductor chip 10. The conductive layer 11 is electrically connected to the element portion 100. The conductive layer 11 includes two metal layers 110 and 111 stacked in the Z direction.

[0021] The metal layer 110 contacts the back surface of the semiconductor chip 10. The metal layer 110 is provided to improve the bonding between the semiconductor chip 10 and the conductive layer 12 and to improve the electrical characteristics between the semiconductor chip 10 and the conductive layer 12. The metal layer 110 is, for example, a titanium layer (Ti layer).

[0022] The metal layer 111 is provided between the metal layer 110 and the conductive layer 12. The metal layer 111 functions as a barrier metal that prevents a chemical reaction between the conductive layer 12 and the metal layer (Ti layer) 110 and the diffusion of components (atoms) between the conductive layer 12 and the metal layer 110. The metal layer 111 is, for example, a nickel layer (Ni layer).

[0023] Hereinafter, the conductive layer 11 is also referred to as a back metal layer 11 .

[0024] The conductive layer 12 is provided between the back metal layer 11 and the Cu layer 20. The conductive layer 12 is in contact with the Cu layer 20.

[0025] As shown in FIG. 1A, before the semiconductor device 1 is bonded to the Cu layer 20, the conductive layer 12A includes metal layers 120 and 121 stacked in the Z direction.

[0026] The metal layer 120 is in contact with the back metal layer 11. The metal layer 120 is, for example, a silver layer (Ag layer).

[0027] The metal layer 121 is provided between the metal layer (Ag layer) 120 and the Cu layer 20. For example, the metal layer 121 is a tin layer (Sn layer).

[0028] The Ag layer 120 has a thickness T1. The Sn layer 121 has a thickness T2. The thickness T1 is thinner than the thickness T2. For example, when the area of ​​the front surface (and back surface) of the semiconductor chip 10 is 0.8 mm × 0.8 mm, the thickness T2 of the Sn layer 121 is set to about 5.0 μm. When the thickness T2 of the Sn layer 121 is 5.0 μm, the thickness T1 of the Ag layer 120 is, for example, 30 nm or more and 100 nm or less. In this case, the thickness T1 of the Ag layer 120 is preferably set to, for example, about 60 nm.

[0029] For example, the Ag layer 120 is formed on the Ni layer 111 of the back metal layer 11 by vacuum evaporation or sputtering.

[0030] For example, the Sn layer 121 is a metal paste, and may be formed on the Ag layer 120 by vacuum deposition or sputtering.

[0031] The semiconductor device 1 in FIG. 1A is, for example, a bare chip.

[0032] 1B, the conductive layer 12B becomes an intermetallic compound layer after the semiconductor device 1 is bonded to the Cu layer 20. The conductive layer 12B is a layer formed by, for example, transient liquid phase sintering (TLPS) bonding between the member constituting the conductive layer 12A and the Cu layer.

[0033] To bond the semiconductor device 1 to the Cu layer 20, a heat treatment for TLPS is performed on the semiconductor device 1 and the Cu layer 20. A chemical reaction caused by the heat treatment bonds the Ag layer 120, the Sn layer 121, and the Cu layer 20 shown in FIG. 1A. For example, the conductive layer 12B after the heat treatment contains a metal compound of Ag, Cu, and Sn.

[0034] In this embodiment, the conductive layer 12B is a CuSn layer containing Ag, and is also referred to as an AgCuSn layer.

[0035] The conductive layer 12B and the Cu layer 20 are integrated by intermetallic bonding due to heat treatment. For example, the conductive layer 12B is continuous with the Cu layer 20.

[0036] Hereinafter, the conductive layer 12 (12A, 12B) will also be referred to as a mounting layer 12.

[0037] The thickness of the AgCuSn layer 12B is 3 μm or more and 50 μm or less. For example, the thickness of the AgCuSn layer 12B is preferably 5 μm or more and 15 μm or less. When the thickness of the AgCuSn layer 12B is 5 μm or more and 15 μm or less, the heat dissipation properties of the semiconductor device 1 and the reliability of the bond between the mounting layer 12 and the Cu layer 20 can be more ensured.

[0038] When forming the AgCuSn layer 12B, it is preferable to subject the conductive layer (Ag / Sn layer) 12A and the Cu layer 20 to a heat treatment at a temperature equal to or higher than the melting point of Sn. This promotes the diffusion of Ag, Sn, and Cn between the conductive layer 12A and the Cu layer 20. As a result, the mounting layer 12 and the Cu layer 20 of the semiconductor device 1 can be integrated through the formation of an intermetallic compound.

[0039] For example, in this embodiment, the conductive layer 12B containing the CuSn intermetallic compound to which Ag is added as the mounting layer 12 is a layer made of hypoeutectic AgSn and CuSn. For example, the AgCuSn layer 12B is made of Ag ３ Sn and Ag ５ For example, the AgCuSn layer 12B contains at least one of Cu and Sn. ３ Sn, Cu ６ Sn ５ , and Cu ７ Sn ２ It includes at least one of the following.

[0040] In the present embodiment, the concentration of Ag relative to Sn in the conductive layer 12B made of a CuSn metal compound containing Ag is 1.0 at% or more and 7.9 at% or less. For example, the concentration of Ag relative to Sn is preferably lower than 7.9 at%.

[0041] For example, in this embodiment, the AgCuSn layer 12B can achieve a thermal conductivity of 34 W / mK or more.

[0042] For example, the AgCuSn layer 12B may further contain Ni. The AgCuSn layer 12B as the mounting layer 12 may contain other elements in trace concentrations below the eutectic point of AgCuSn.

[0043] The Ag layer may remain between the AgCuSn layer 12B and the Ni layer 111.

[0044] With the above configuration, the reliability of the semiconductor device 1 of this embodiment can be improved.

[0045] (Manufacturing Method) A method for manufacturing a semiconductor device according to this embodiment will be described with reference to FIG.

[0046] 1A, an element section 100 including a semiconductor element such as a MOSFET or an IGBT is formed on a semiconductor substrate (e.g., a Si substrate or a SiC substrate). Then, pads 19 are formed on the front surface side of the semiconductor substrate. This completes the semiconductor chip 10.

[0047] A back metal layer 11 made of a laminate of a Ti layer 110 and a Ni layer 111 is formed on the back surface of the semiconductor chip 10 by sputtering or vacuum deposition.

[0048] On the back surface side of the semiconductor chip 10, an Ag layer 120 is formed by sputtering or vacuum deposition on the Ni layer 111 of the back metal layer 11. The Ag layer 120 has a thickness of, for example, 60 nm.

[0049] The Sn layer 121 is formed on the Ag layer 120 by applying a metal paste, sputtering, or vacuum deposition. The Sn layer 121 has a thickness of, for example, 5 μm.

[0050] As a result, the mounting layer 12 made of a laminate of the Ag layer 120 and the Sn layer 121 is formed on the back metal layer 11 on the back surface side of the semiconductor chip 10 .

[0051] Through the above steps, the bare chip semiconductor device 1 is formed.

[0052] The bare chip semiconductor device 1 is mounted on the Cu layer (Cu base material) 20 so that the Sn layer 121 of the mount layer 12 is in contact with the Cu layer 20 .

[0053] With the Sn layer 121 in contact with the Cu layer 20, a heat treatment (hereinafter also referred to as a mount bonding process) for bonding the semiconductor device 1 and the Cu layer 20 is carried out at a temperature equal to or higher than the melting point of Sn.

[0054] The heat treatment causes diffusion of the constituent elements Ag, Sn, and Cu between the mounting layer 12 and the Cu layer 20 .

[0055] 1B, an intermetallic compound layer 12B containing Ag, Cu, and Sn is formed between the semiconductor device 1 and the Cu layer 20. The AgCuSn layer 12B, which is an intermetallic compound layer, is partially integrated with the Cu layer 20. The AgCuSn layer 12B and the Cu layer 20 form a continuous layer (region) in which no cracks occur at the interface.

[0056] The semiconductor device 1 (semiconductor chip 10) is bonded to the Cu layer 20 via the AgCuSn layer 12B.

[0057] Through the above steps, the semiconductor device 1 of this embodiment is completed.

[0058] (Experiment) With reference to FIG. 2, the characteristics of the semiconductor device of this embodiment will be described.

[0059] FIG. 2 shows cross-sectional images of the semiconductor device of this embodiment and the semiconductor device of the comparative example when various heat treatments are performed.

[0060] 2A is a cross-sectional image of the vicinity of the boundary between the mounting layer and the Cu layer of a semiconductor device of a comparative example, which includes a CuSn-based metal compound layer to which no Ag is added in the mounting layer.

[0061] FIG. 2B is a cross-sectional image of the vicinity of the boundary between the mounting layer and the Cu layer of the semiconductor device of this embodiment.

[0062] 2A and 2B show cross-sectional images of the mounting layer of an experimental sample in an initial state, an experimental sample after pretreatment, an experimental sample after a thermal cycle test, and an experimental sample after high-temperature exposure treatment, respectively.

[0063] In the comparative example and the experimental sample of this embodiment, the thickness of the Sn layer of the mounting layer was set to 5.0 μm before the mounting layer was bonded to the Cu layer. In the experimental sample of this embodiment, the thickness of the Ag layer of the mounting layer was set to 60 nm before the mounting layer was bonded to the Cu layer. In the experimental sample of this embodiment, the concentration of Ag relative to Sn in the mounting layer was 1.9 at%.

[0064] In an experimental sample of the semiconductor device of the comparative example, the conductive layer 90 not containing Ag is bonded to the Cu layer at a mounting temperature of 380° C. In an experimental sample of the semiconductor device of this embodiment, the conductive layer 12B containing Ag is bonded to the Cu layer at a mounting temperature of 380° C.

[0065] The pretreatment performed on the experimental samples of the semiconductor devices of the comparative example and this embodiment is a treatment related to the moisture sensitivity level (MSL).

[0066] A thermal cycle test (TCT) of 1000 cycles and a thermal cycle test of 2000 cycles are performed on experimental samples of the semiconductor devices of the comparative example and the present embodiment, respectively.

[0067] Heat treatment at 150°C for 1000 hours, heat treatment at 150°C for 2000 hours, heat treatment at 175°C for 1000 hours, and heat treatment at 175°C for 2000 hours are performed on experimental samples of the semiconductor devices of the comparative example and this embodiment, respectively, as high-temperature exposure treatments.

[0068] 2A, in the semiconductor device of the comparative example, in the initial state after bonding to the Cu layer 20X, a mount layer (hereinafter referred to as a CuSn layer) 90 made of a Cu—Sn intermetallic compound is formed. The Cu—Sn layer 90 is integrated with the Cu layer 20X.

[0069] For example, in the semiconductor device of the comparative example, Kirkendall voids 99X occur between the CuSn layer 90 and the Cu layer 20X in a 2000-cycle thermal cycle test.

[0070] When the semiconductor device of the comparative example is subjected to a high-temperature exposure treatment at 150° C., Kirkendall voids 99X are generated between the CuSn layer 90 and the Cu layer 20X. In the comparative example, the Kirkendall voids 99X generated by the heat treatment at 150° C. for 2000 hours are larger than the Kirkendall voids generated by the heat treatment at 150° C. for 1000 hours.

[0071] When the semiconductor device of the comparative example was subjected to a high-temperature exposure treatment at 175°C, Kirkendall voids 99X were generated between the CuSn layer 90 and the Cu layer 20X. The Kirkendall voids 99X generated by the heat treatment at 175°C for 2000 hours were larger than the Kirkendall voids 99X generated by the heat treatment at 175°C for 1000 hours. Furthermore, the Kirkendall voids 99X generated by the heat treatment at 175°C were larger than the Kirkendall voids 99X generated by the heat treatment at 150°C.

[0072] Thus, when the semiconductor device of the comparative example is left in a high temperature state of 150° C. or more, relatively large Kirkendall voids are generated between the CuSn layer 90 and the Cu layer 20X.

[0073] Therefore, when Ag is not added to the mounting layer 90 made of a CuSn-based intermetallic compound, as in the comparative example, cracks (e.g., voids) occur between the mounting layer 90 and the Cu layer 20X. Therefore, the semiconductor device of the comparative example suffers from a deterioration in the strength of the bond between the semiconductor chip and the Cu base material.

[0074] 2B, in the semiconductor device 1 of this embodiment, in the initial state after bonding, a mounting layer (AgCuSn layer) 12B made of a CuSn intermetallic compound to which Ag is added is formed. The AgCuSn layer 12B is integrated with the Cu layer 20.

[0075] When a thermal cycle test is performed on the semiconductor device 1 of this embodiment, no Kirkendall voids are generated between the mounting layer 12B and the Cu layer 20.

[0076] Even when the semiconductor device 1 of this embodiment is subjected to a heat treatment (high-temperature exposure treatment) under conditions of 150° C. and 1000 hours, no Kirkendall voids are generated between the mounting layer 12B and the Cu layer 20.

[0077] When the semiconductor device 1 of this embodiment is subjected to a heat treatment at 150° C. for 2000 hours, Kirkendall voids 99 are generated between the mounting layer 12 B and the Cu layer 20 .

[0078] Furthermore, when heat treatments at 175° C. and 1000 hours and heat treatments at 175° C. and 2000 hours, respectively, are performed on the semiconductor device 1 of this embodiment, Kirkendall voids 99 occur between the mounting layer 12B and the Cu layer 20.

[0079] However, for each of the heat treatments performed under the same conditions, the size of the Kirkendall voids generated in the semiconductor device 1 of the embodiment is smaller than the size of the Kirkendall voids generated in the semiconductor device of the comparative example.

[0080] When a semiconductor device bonded to a Cu layer is left at high temperatures, Cu is supplied from the Cu layer to the mounting layer. This causes Cu to bond with Sn in the mounting layer, forming CuSn. Kirkendall voids occur between the Cu layer and the mounting layer depending on the amount of Cu diffused from the Cu layer to the mounting layer.

[0081] When Ag is added to the mounting layer 12 as in this embodiment, the amount of Cu consumed (Cu diffusion) during the formation of the intermetallic compound is less than when the metal layer that forms the base of the mounting layer is made of only Sn.

[0082] As a result, Kirkendall voids are less likely to occur in the semiconductor device 1 of this embodiment, as in the experimental sample shown in FIG. 2(b).

[0083] (Summary) By adding Ag to the CuSn intermetallic compound layer as in the semiconductor device 1 of this embodiment, the size of Kirkendall voids that occur between the mounting layer and the Cu layer when left at high temperatures is reduced.

[0084] Therefore, the semiconductor device 1 of this embodiment can suppress the occurrence of cracks at the boundary between the mounting layer and the Cu layer, thereby improving the bonding strength between the mounting layer and the Cu layer.

[0085] As a result, the semiconductor device 1 of this embodiment can reduce poor bonding between the semiconductor device and the Cu layer.

[0086] In this embodiment, the AgCuSn layer 12B serving as the mounting layer includes an AgSn phase and a CuSn phase. The Young's modulus of AgSn is lower than that of CuSn.

[0087] This improves the stress resistance of the mounting layer in the semiconductor device 1 of this embodiment.

[0088] Therefore, the semiconductor device 1 of this embodiment can prevent peeling (or fracture) from occurring between the semiconductor chip and the base layer made of Cu.

[0089] The semiconductor device 1 of this embodiment uses a CuSn-based intermetallic compound to bond the semiconductor device to the Cu material. This allows the semiconductor device 1 of this embodiment to have high heat resistance, with a melting point of 400°C or higher. Furthermore, the semiconductor device 1 of this embodiment can reduce the cost of the mounting layer bonded to the Cu layer. The semiconductor device 1 of this embodiment can bond the semiconductor device to the Cu material without using lead (Pb).

[0090] In the semiconductor device 1 of this embodiment, the film thickness of the AgCuSn mounting layer is controlled to 5 μm to 15 μm. This allows the semiconductor device 1 of this embodiment to improve heat dissipation. Furthermore, in the semiconductor device of this embodiment, the thermal resistance can be reduced by making the mounting layer thinner.

[0091] As described above, the reliability of the semiconductor device 1 of this embodiment can be improved.

[0092] (2) Specific Examples Specific examples (application examples) of the semiconductor device of this embodiment will be described with reference to FIGS.

[0093] FIG. 3 is a cross-sectional view showing a specific example of the semiconductor device of this embodiment.

[0094] Before the semiconductor device 1 of this embodiment is mounted in a package, the semiconductor device 1 is provided in a state in which the mounting layer 12 has not yet formed a metal compound with Cu.

[0095] In this case, the semiconductor device 1 of the embodiment includes a mounting layer 12A including an Ag layer 120 and an Sn layer 121. The mounting layer 12A is a laminate (Ag / Sn layer) of the Ag layer 120 and the Sn layer 121. The Ag layer 120 contacts the Ni layer 111 of the back metal layer 11. The Ag layer 120 is provided between the Ni layer 111 and the Sn layer 121. One surface of the Sn layer 121 contacts the Ag layer 120. The surface opposite to the one surface of the Sn layer 121 is exposed.

[0096] The Ag layer 120 may be provided within the Sn layer 121. In this case, the Ag layer 120 is sandwiched between two portions (Sn portions) within the Sn layer 121. The Sn layer 121 may be provided between the Ag layer 120 and the Ni layer 111.

[0097] The Ag layer 120 is formed by a film formation technique such as vacuum evaporation or sputtering.

[0098] The Sn layer 121 may be a layer formed from a metal paste or may be a layer formed by a film forming technique.

[0099] The thickness T1 of the Ag layer 120 is thinner than the thickness T2 of the Sn layer 121. It is desirable to set the thickness T1 of the Ag layer 120 and the thickness T2 of the Sn layer 121 so that the concentration of Ag relative to Sn is 1.0 at% or more and 7.9 at% or less. For example, when the thickness T2 of the Sn layer 121 is 5.0 μm, the thickness T1 of the Ag layer 120 is 60 nm.

[0100] FIG. 4 is a cross-sectional view showing a specific example of the semiconductor device of this embodiment.

[0101] As shown in FIG. 4, in the mounting layer 12A, a metal layer 123 may be provided between the Ag layer 120 and the Sn layer 121.

[0102] The metal layer 123 is a layer containing at least one of gold (Au), palladium (Pd), and Ni.

[0103] The metal layer 123 is an Au layer, a Pd layer, or a Ni layer. The metal layer 123 may be a laminated film containing two or more selected from Au, Pd, and Ni, or an intermetallic compound layer containing two or more selected from Au, Pd, and Ni.

[0104] The thickness T 3 of the metal layer 123 is equal to or smaller than the thickness T 1 of the Ag layer 120 .

[0105] When the mount layer 12A and the Cu layer are joined, the metal layer 123 is melted by heat, and the constituent elements of the metal layer 123 are diffused and added into the CuSn layer together with Ag.

[0106] As a result, the mounting layer 12B in FIG. 1B contains elements other than Ag, Cu, and Sn in the AgCuSn layer.

[0107] At least one of the Ag layer 120 and the Sn layer 121 may contain at least one of Au, Pd, and Ni. The metal layer 123 may be provided between the back metal layer 11 and the Ag layer 120. The Sn layer 121 may be provided between the Ag layer 120 and the metal layer 123.

[0108] FIG. 5 is a cross-sectional view showing a specific example of the semiconductor device of this embodiment.

[0109] As shown in FIG. 5, the semiconductor device 1 of this embodiment can be provided as a packaged power device 5A.

[0110] For example, the semiconductor device 1 is mounted on a lead frame 2A.

[0111] The lead frame 2A includes a mount portion (die mount portion) 20A and a plurality of lead portions (connection terminals) 21. The mount portion 20A and the lead portions 21 are Cu layers.

[0112] The semiconductor device 1 is provided on a mounting portion (Cu layer) 20A.

[0113] The pad 19 is electrically connected to the lead portion 21 via a bonding wire 30 .

[0114] The semiconductor device 1 mounted on the lead frame 2A is sealed with a sealing material (insulator) 39. The semiconductor device 1 is covered with the sealing material 39.

[0115] When the semiconductor device 1 is mounted on the lead frame 2, the mounting layer of the semiconductor device 1 is bonded to the mounting portion 20A of the lead frame 2A by heat treatment. By bonding the conductive layer including the Ag layer and the Sn layer to the mounting portion 20A, a mounting layer 12B including an AgCuSn layer is formed on the back surface side of the semiconductor chip 10. The AgCuSn layer 12B as the mounting layer is integrated with the mounting portion 20A made of Cu.

[0116] The semiconductor device 1 is bonded to the lead frame 2A by the AgCuSn layer 12B.

[0117] FIG. 6 is a cross-sectional view showing an example of the semiconductor device of this embodiment.

[0118] As shown in FIG. 6, in a power device 5B, a conductive layer 12Z made of AgCuSn may be provided on the front surface side of a semiconductor chip 10.

[0119] The lead frame 2B includes lead portions (connection terminals) 23. The lead portions 23 are Cu layers. The lead portions 23 extend from the bottom surface of the sealing material 39 to the top surface of the semiconductor chip 10. One end of the lead portions 23 is adjacent to the mount portion 20A. The other end of the lead portions 23 is provided above the pads 19 via the conductive layer 12Z.

[0120] During the manufacture of the semiconductor device 1, for example, a conductive layer including an Ag layer and an Sn layer is provided on the pad 19. On the front surface side of the semiconductor chip 10, the Ag layer is provided between the Sn layer and the pad 19.

[0121] When the semiconductor device 1 is mounted on the lead frame 2, the semiconductor device 1 is mounted on the mounting portion 20A, and the other end of the lead portion 23 is provided on the conductive layer (Sn / Ag layer) on the upper surface of the semiconductor chip 10.

[0122] By the heat treatment, an AgCuSn layer 12B is formed between the semiconductor chip 10 and the mount portion 20A, and an AgCuSn layer 12Z is ​​formed between the pad 19 and the lead portion 23.

[0123] As a result, the AgCuSn layer 12Z is ​​bonded to the lead portion 23 of the Cu layer on the front surface side of the semiconductor chip 10. The AgCuSn layer 12Z is ​​integrated with the Cu layer of the lead portion 23. The AgCuSn layer 12Z may also be integrated with the pad 19 by bonding the AgCuSn layer 12Z and the pad 19 together using heat.

[0124] FIG. 7 is a cross-sectional view showing a specific example of the semiconductor device of this embodiment.

[0125] As shown in FIG. 7, a power device 5C including the semiconductor device 1 of this embodiment may be provided without being sealed with a sealing material.

[0126] On the front surface side of the semiconductor chip 10, external connection terminals 29 are connected to the pads 19. The external connection terminals 29 are conductors containing Sn. The external connection terminals 29 are, for example, solder balls or bumps.

[0127] The Cu layer 20B is provided on the back surface side of the semiconductor chip 10. The Cu layer 20B is connected to the mount layer 12B. The mount layer 12B is an AgCuSn layer. The AgCuSn layer 12B is integrated with the Cu layer 20B.

[0128] For example, the Cu layer 20B functions as an electrode and a heat sink of the power device 5C. The power device 5C in Fig. 7 may be a horizontal power device. When the power device 5C is a horizontal power device, no current flows through the Cu layer 20B, and the Cu layer 20B functions as a heat sink.

[0129] FIG. 8 is a cross-sectional view showing a specific example of the semiconductor device of this embodiment.

[0130] As shown in FIG. 8, the semiconductor device 1 of this embodiment may be used in a power module 6.

[0131] The power module 6 is, for example, a DC-DC converter, an inverter, or a switch.

[0132] In the power module 6 , the semiconductor device 1 of the multiple embodiments is provided on a circuit board 3 .

[0133] The circuit board 3 on which the semiconductor device 1 is mounted is provided on a base substrate 50 .

[0134] A case 51 is provided on the base substrate 50 so as to surround the circuit board 3. For example, an insulator (not shown) is provided in the space surrounded by the case 51 on the base substrate 50. The semiconductor device 1 in the case 51 is sealed by the insulator.

[0135] A lid 52 is provided on the case 51. The lid 52 covers the semiconductor device 1 and the circuit board 3 from above.

[0136] An external connection terminal 59 is provided inside the case 51. The external connection terminal 59 extends from the case 51 side toward the circuit board 3. One end of the external connection terminal 59 is connected to the wiring 27 (or the Cu layer 20) of the circuit board 3. The other end of the external connection terminal 59 protrudes from, for example, the lid 52. The other end of the external connection terminal 59 is connected to a device (for example, a control device) external to the power module 6.

[0137] The circuit board 3 includes a metal plate 26 , a ceramic plate 25 , a Cu layer 20 , and wiring 27 .

[0138] The metal plate 26 is a Cu plate. The metal plate 26 functions as a heat sink. The ceramic plate 25 is provided on the metal plate 26. The ceramic plate 25 electrically isolates the metal plate 26 from the Cu layer 20 and the wiring 27. The ceramic plate 25 functions as a heat sink.

[0139] The Cu layer 20 and the wiring 27 are provided on a ceramic plate 25 .

[0140] The semiconductor device 1 is provided on a Cu layer 20. The semiconductor device 1 is bonded to the Cu layer 20 via a mount layer (intermetallic compound layer) 12B made of AgCuSn. The AgCuSn layer 12B is integrated with the Cu layer 20. For example, the Cu layer 20 may be used as wiring.

[0141] The wiring 27 electrically connects the plurality of semiconductor devices 1 to one another. The wiring 27 is connected to the semiconductor devices 1 via bonding wires 30. The plurality of semiconductor devices 1 on the circuit board 3 are connected to one another via bonding wires 30. The wiring 27 connects the plurality of semiconductor devices 1 to external connection terminals 59.

[0142] The output current (or output voltage) of the semiconductor device 1 is output to the outside of the power module 6 via the bonding wires 30 , the wiring 27 and the external connection terminals 59 .

[0143] 3 to 8, the semiconductor device 1 of this embodiment is applied to an apparatus including a Cu member. The semiconductor device 1 of this embodiment is bonded to the Cu member via a mount layer 12B including AgCuSn.

[0144] Therefore, the reliability of the device including the semiconductor device 1 of this embodiment can be improved.

[0145] (3) Modifications A modification of the semiconductor device of this embodiment will be described with reference to FIGS.

[0146] FIG. 9 is a cross-sectional view showing an example of a modified example of the semiconductor device of the embodiment.

[0147] 9, Sn grains (Sn crystals) 125 may be provided in the AgCuSn layer 12B as a mounting layer. For example, the Sn grains 125 are randomly arranged in the AgCuSn layer 12B.

[0148] FIG. 10 is a cross-sectional view showing an example of a modified example of the semiconductor device of this embodiment.

[0149] 10, voids 129 may be provided in the AgCuSn layer 12B as a mounting layer. For example, the voids 129 may be formed at random positions or in accordance with the positions where pins are applied during heating.

[0150] Even when Sn grains 125 or voids 129 are provided in the mounting layer 12B as shown in FIGS. 9 and 10, the semiconductor device according to the modification of this embodiment can achieve the above-described effects.

[0151] (4) Others In the above-described embodiment, a structure in which the Ag-added CuSn layer is used in a power device or a power module is illustrated. However, the Ag-added CuSn layer may also be used in semiconductor devices other than power devices, such as analog circuits and logic circuits.

[0152] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims.

Claims

1. A semiconductor device comprising: a semiconductor chip; and a first conductive layer provided on a first surface side of the semiconductor chip, wherein the first conductive layer includes an intermetallic compound layer containing copper (Cu), tin (Sn), and silver (Ag), and a concentration of the silver relative to the tin in the first conductive layer is 1.0 at% or more and 7.9 at% or less.

2. The semiconductor device according to claim 1, wherein the first conductive layer is provided between the semiconductor chip and a copper layer.

3. The semiconductor device according to claim 1, wherein the first conductive layer further comprises at least one of nickel (Ni), gold (Au) and palladium (Pd).

4. The semiconductor device of claim 1, further comprising a second conductive layer provided between said semiconductor chip and said first conductive layer, said second conductive layer including a nickel layer and a titanium layer between said nickel layer and said semiconductor chip.

5. The semiconductor device according to claim 1, wherein the first conductive layer includes an AgSn phase and a CuSn phase.

6. The AgSn phase is Ag ３ Sn and Ag ５ Sn, and the CuSn phase contains at least one of Cu, ３ Sn, Cu ６ Sn ５ , and Cu ７ Sn ２ The semiconductor device of claim 5 , comprising at least one of:

7. A power device comprising: the semiconductor device of claim 1; and a lead frame including a mount portion bonded to the semiconductor device via the first conductive layer, and a terminal connected to a pad provided on a second surface of the semiconductor device opposite to the first surface, wherein each of the mount portion and the terminal includes copper.

8. The power device according to claim 7, wherein the semiconductor device further comprises a third conductive layer provided between the pad and the terminal, the third conductive layer including an intermetallic compound layer containing copper, tin, and silver, and a concentration of the silver relative to the tin in the third conductive layer is 1.0 at% or more and 7.9 at% or less.

9. A power module comprising: the semiconductor device of claim 1; and a circuit board including a copper layer bonded to the semiconductor device via the first conductive layer.

10. A semiconductor device comprising: a semiconductor chip; and a first conductive layer provided on a first surface side of the semiconductor chip, the first conductive layer including a tin layer and a silver layer between the tin layer and the semiconductor chip, the silver layer having a thickness thinner than that of the tin layer.

11. The semiconductor device of claim 10, wherein the first conductive layer further comprises a metal layer, the metal layer comprising at least one of nickel, gold and palladium, and the thickness of the metal layer is equal to or less than the thickness of the silver layer.

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