Semiconductor device and light detection device

Abstract

This semiconductor device includes: a trench which is provided from a first surface of a substrate toward a second surface that is opposite to the first surface; an insulated gate field effect transistor which is provided in a lower part of the trench and has a gate electrode that is embedded in the trench sidewall with a gate insulating film being interposed therebetween; a sidewall insulator which is provided on the trench sidewall in an upper part of the trench and has a thickness that is larger than the thickness of the gate insulating film in the same direction; and an electrode which is embedded in the upper part of the trench with the sidewall insulator being interposed therebetween and is electrically connected to the gate electrode.

Description

Semiconductor device and photodetector

[0001] The present disclosure relates to a semiconductor device and a photodetector device.

[0002] Patent Document 1 discloses a solid-state imaging device. The solid-state imaging device has a pixel array in which a plurality of pixels are arranged. Each pixel includes a photoelectric conversion element and a transfer transistor. The photoelectric conversion element is made up of a photodiode. The photoelectric conversion element converts light into electric charges. The transfer transistor transfers the electric charges converted by the photoelectric conversion element to a signal processing circuit.

[0003] The gate electrode of the transfer transistor is disposed in a trench formed in the semiconductor substrate with a gate insulating film interposed therebetween, that is, the transfer transistor is configured as a vertical transistor.

[0004] Japanese Patent Application Laid-Open No. 2018-148116

[0005] In the solid-state imaging device disclosed in Patent Document 1, one of a pair of main electrodes of the transfer transistor is electrically connected to a photoelectric conversion element disposed in a semiconductor substrate. Meanwhile, the other main electrode is electrically connected to a signal processing circuit through a floating diffusion. An insulating film formed on the sidewall of the trench is disposed between the floating diffusion and a part of the extraction electrode that supplies a transfer signal to the gate electrode of the transfer transistor. This insulating film is thin because it is formed in the same manufacturing process as the gate insulating film of the transfer transistor.

[0006] In a solid-state imaging device configured in this way, a parasitic capacitance is added to the floating diffusion, with the floating diffusion as one electrode, the insulator as the dielectric, and the extraction electrode as the other electrode. This slows down the charge transfer speed in the transfer transistor in response to the input of a transfer signal, making it difficult to expect sufficient characteristics.

[0007] Therefore, there has been a demand for the development of a semiconductor device and a photodetector that can effectively improve transistor characteristics.

[0008] A semiconductor device according to a first embodiment of the present disclosure includes: a trench extending from a first surface of a substrate toward a second surface opposite the first surface; an insulated gate field effect transistor disposed in a lower portion of the trench and having a gate electrode embedded on a sidewall of the trench with a gate insulating film interposed therebetween; a sidewall insulator disposed on the sidewall of the trench in an upper portion of the trench and having a thickness greater in the same direction than that of the gate insulating film; and an electrode embedded in an upper portion of the trench with the sidewall insulator interposed therebetween and electrically connected to the gate electrode.

[0009] In the semiconductor device according to the second embodiment of the present disclosure, in the semiconductor device according to the first embodiment, the lower part of the trench is formed in an inverted pyramid shape with the apex on the second surface side, and the gate electrode is formed in an inverted pyramid shape buried in the lower part of the trench with a gate insulating film interposed therebetween.

[0010] A semiconductor device according to a third embodiment of the present disclosure includes: a first trench disposed from a first surface of a substrate toward a second surface opposite to the first surface; a second trench disposed in the first surface from the first surface toward the second surface of the substrate, spaced apart from the first trench; a third trench disposed from the first surface toward the second surface, having a depth shallower than the first and second trenches and connecting the first and second trenches; and an insulated gate field effect transistor having: a first gate electrode disposed in a lower portion of the first trench and embedded in a sidewall of the first trench with a first gate insulating film interposed therebetween; a second gate electrode disposed in a lower portion of the second trench and embedded in a sidewall of the second trench with a second gate insulating film interposed therebetween; and a third gate electrode embedded in a bottom of the third trench with a third gate insulating film interposed therebetween and electrically connecting the first gate electrode and the second gate electrode.

[0011] A photodetector according to a fourth embodiment of the present disclosure includes: a groove disposed from a first surface of a substrate toward a second surface opposite the first surface; a transfer transistor disposed in a lower portion of the groove and having a gate electrode embedded on a side wall of the groove with a gate insulating film interposed therebetween; a sidewall insulator disposed in an upper portion of the groove on the side wall of the groove and having a thickness in the same direction greater than that of the gate insulating film; an electrode buried in an upper portion of the groove with the sidewall insulator interposed therebetween and electrically connected to the gate electrode; a floating diffusion disposed on the first surface side of the substrate with the sidewall insulator interposed between the electrode and electrically connected to one end of the transfer transistor; and a photoelectric conversion element disposed in the substrate and electrically connected to the other end of the transfer transistor, which converts light into electric charges.

[0012] a second groove in the first surface, the second groove being spaced apart from the first groove and extending from the first surface toward the second surface of the substrate; a third groove extending from the first surface toward the second surface, the third groove having a depth shallower than the first and second grooves and connecting the first and second grooves; a transfer transistor having a first gate electrode disposed in a lower portion of the first groove and embedded in a sidewall of the first groove with a first gate insulating film interposed therebetween, a second gate electrode disposed in a lower portion of the second groove and embedded in a sidewall of the second groove with a second gate insulating film interposed therebetween, and a third gate electrode embedded in a bottom portion of the third groove with a third gate insulating film interposed therebetween and electrically connecting the first gate electrode and the second gate electrode; The semiconductor device includes: sidewall insulators disposed on the first groove sidewalls and the second groove sidewalls at the upper portions thereof, respectively, within the first groove and the second groove, and having a thickness in the same direction greater than that of the first gate insulating film and the second gate insulating film; electrodes buried in the upper portions thereof, respectively, within the first groove and the second groove, with the sidewall insulators interposed therebetween, and electrically connected to the first gate electrode and the second gate electrode; a floating diffusion disposed on the first surface side of the substrate with the sidewall insulator interposed between the electrode and electrically connected to one end of the transfer transistor; and a photoelectric conversion element disposed in the substrate, electrically connected to the other end of the transfer transistor, and converting light into electric charges.

[0013] FIG. 1 is a schematic system configuration diagram of a photodetector according to a first embodiment of the present disclosure. FIG. 2 is a schematic exploded plan configuration diagram of the photodetector shown in FIG. 1. FIG. 3 is a circuit configuration diagram of a pixel and a pixel circuit of the photodetector shown in FIG. 1. FIG. 4 is a plan configuration diagram of a pixel of the photodetector shown in FIG. 1. FIG. 5 is a cross-sectional configuration diagram of a pixel of the photodetector shown in FIG. 1 (a cross-sectional view taken along the A-A section line shown in FIG. 4). FIG. 6A is a first process cross-sectional view (a cross-sectional view taken along the A-A section line shown in FIG. 4; hereinafter, referred to as "Cross Section A") illustrating a method for manufacturing a photodetector according to the first embodiment. FIG. 6B is a first process cross-sectional view (a cross-sectional view taken along the B-B section line shown in FIG. 4; hereinafter, referred to as "Cross Section B") illustrating a method for manufacturing a photodetector according to the first embodiment. FIG. 7A is a cross-sectional view at Cross Section A at a second process. FIG. 7B is a cross-sectional view at Cross Section B at a second process. FIG. 8A is a cross-sectional view at Cross Section A at a third process. 8B is a cross-sectional view of cross section B at a third step. FIG. 9A is a cross-sectional view of cross section A at a fourth step. FIG. 9B is a cross-sectional view of cross section B at a fourth step. FIG. 10A is a cross-sectional view of cross section A at a fifth step. FIG. 10B is a cross-sectional view of cross section B at a fifth step. FIG. 11A is a cross-sectional view of cross section A at a sixth step. FIG. 11B is a cross-sectional view of cross section B at a sixth step. FIG. 12A is a cross-sectional view of cross section A at a seventh step. FIG. 12B is a cross-sectional view of cross section B at a seventh step. FIG. 13A is a cross-sectional view of cross section A at an eighth step. FIG. 13B is a cross-sectional view of cross section B at an eighth step. FIG. 14A is a cross-sectional view of cross section A at a ninth step. FIG. 14B is a cross-sectional view of cross section B at a ninth step. FIG. 15A is a cross-sectional view of cross section A at a tenth step. FIG. 15B is a cross-sectional view of cross section B at a tenth step. FIG. 16 is a cross-sectional configuration view corresponding to FIG. 5 of a pixel of a photodetector device according to a second embodiment of the present disclosure. Fig. 17 is a cross-sectional configuration diagram of a pixel of a photodetector according to a third embodiment of the present disclosure, corresponding to Fig. 5. Fig. 18 is a plan configuration diagram of a pixel of a photodetector according to a fourth embodiment of the present disclosure, corresponding to Fig. 4. Fig. 19 is a cross-sectional configuration diagram of a pixel of a photodetector according to the fourth embodiment, corresponding to Fig. 5 (a cross-sectional view taken along the CC cutting line shown in Fig. 18).FIG. 20 is a plan view of a pixel of a photodetector according to a fifth embodiment of the present disclosure, corresponding to FIG. 4 . FIG. 21 is a cross-sectional view of a pixel of a photodetector according to the fifth embodiment, corresponding to FIG. 5 (a cross-sectional view taken along the D1-D1 section line shown in FIG. 20 ). FIG. 22 is a cross-sectional view of a pixel of a photodetector according to a sixth embodiment of the present disclosure, corresponding to FIG. 5 (a cross-sectional view taken along the D2-D2 section line shown in FIG. 20 ). FIG. 23A is a cross-sectional view illustrating a first step of a method for manufacturing a photodetector according to the sixth embodiment. FIG. 23B is a cross-sectional view illustrating a second step. FIG. 23C is a cross-sectional view illustrating a third step. FIG. 23D is a cross-sectional view illustrating a fourth step. FIG. 24 is a plan view of a pixel of a photodetector according to a seventh embodiment of the present disclosure, corresponding to FIG. 4 . FIG. 25 is a plan view of a pixel of a photodetector according to an eighth embodiment of the present disclosure, corresponding to FIG. 4 . FIG. 26 is a cross-sectional view of a pixel of a photodetector according to the eighth embodiment, corresponding to FIG. 5 (a cross-sectional view taken along the E-E section line shown in FIG. 25 ). 27 is a plan view of a pixel of a photodetector according to a ninth embodiment of the present disclosure, corresponding to FIG. 4 . FIG. 28 is a plan view of a pixel of a photodetector according to a tenth embodiment of the present disclosure, corresponding to FIG. 4 . FIG. 29 is a cross-sectional view of a pixel of a photodetector according to the tenth embodiment, corresponding to FIG. 5 (a cross-sectional view taken along the F-F line shown in FIG. 28 ). FIG. 30 is a cross-sectional view of a first step (a cross-sectional view taken along the F-F line shown in FIG. 28 ) illustrating a method for manufacturing a photodetector according to the tenth embodiment. FIG. 31 is a cross-sectional view of a second step. FIG. 32 is a cross-sectional view of a third step. FIG. 33 is a cross-sectional view of a fourth step. FIG. 34 is a cross-sectional view of a fifth step. FIG. 35 is a cross-sectional view of a sixth step. FIG. 36 is a cross-sectional view of a seventh step. FIG. 37 is a cross-sectional view of an eighth step. FIG. 38 is a cross-sectional view of a ninth step. FIG. 39 is a cross-sectional view of a tenth step. FIG. 40 is a plan view of a pixel of a photodetector according to an eleventh embodiment of the present disclosure, corresponding to FIG. 4 . Fig. 41 is a cross-sectional configuration diagram (a cross-sectional view taken along the G-G cutting line shown in Fig. 40) of a pixel of a photodetector according to an eleventh embodiment, corresponding to Fig. 5. Fig. 42 is a cross-sectional configuration diagram of a pixel of a photodetector according to a twelfth embodiment of the present disclosure, corresponding to Fig. 5.FIG. 43 is a plan view of a pixel of a photodetector according to a thirteenth embodiment of the present disclosure, corresponding to FIG. 4 . FIG. 44 is a cross-sectional view of a pixel of a photodetector according to the thirteenth embodiment, corresponding to FIG. 5 (a cross-sectional view taken along the H-H section line shown in FIG. 43 ). FIG. 45 is a cross-sectional view of a pixel of a photodetector according to the thirteenth embodiment, corresponding to FIG. 5 (a cross-sectional view taken along the I-I section line shown in FIG. 43 ). FIG. 46 is a cross-sectional view of a first step (a cross-sectional view taken along the I-I section line shown in FIG. 43 ) illustrating a method for manufacturing a photodetector according to the thirteenth embodiment. FIG. 47 is a cross-sectional view of a second step. FIG. 48 is a cross-sectional view of a third step. FIG. 49 is a cross-sectional view of a fourth step. FIG. 50 is a cross-sectional view of a fifth step. FIG. 51 is a cross-sectional view of a sixth step. FIG. 52 is a cross-sectional view of a seventh step. FIG. 53 is a cross-sectional view of an eighth step. FIG. 54 is a cross-sectional view of a ninth step. FIG. 55 is a cross-sectional view of a tenth step. FIG. 56A is a cross-sectional view of another region at a fifth step in the step shown in FIG. 50 . FIG. 56B is a cross-sectional view of another region at a sixth step in the step shown in FIG. 51 . FIG. 56C is a cross-sectional view of a first step corresponding to the step shown in FIG. 50 describing a manufacturing method of a photodetector according to a modified example of the thirteenth embodiment. FIG. 56D is a cross-sectional view of a second step. FIG. 57 is a plan configuration diagram corresponding to FIG. 4 of a pixel of a photodetector according to a fourteenth embodiment of the present disclosure. FIG. 58 is a cross-sectional configuration diagram corresponding to FIG. 5 of a pixel of a photodetector according to the fourteenth embodiment (a cross-sectional view taken along the J-J line shown in FIG. 57 ). FIG. 59 is a cross-sectional configuration diagram corresponding to FIG. 5 of a pixel of a photodetector according to the fourteenth embodiment (a cross-sectional view taken along the K-K line shown in FIG. 58 ). FIG. 60 is a block diagram showing the configuration of an electronic device according to a fifteenth embodiment of the present disclosure. FIG. 61 is a block diagram showing an example of a schematic configuration of a vehicle control system. FIG. 62 is an explanatory diagram showing an example of the installation positions of an outside vehicle information detection unit and an imaging unit. Fig. 63 is a diagram showing an example of a schematic configuration of an endoscopic surgery system, and Fig. 64 is a block diagram showing an example of a functional configuration of a camera head and a CCU.

[0014] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be made in the following order. 1. First Embodiment The first embodiment will describe a first example in which the present technology is applied to a photodetector. In the present technology, the photodetector is one aspect of a semiconductor device. The first embodiment will describe the overall system configuration of the photodetector, the configuration of pixels as photodetector elements that detect light, and the configuration of pixel circuits that read out signals detected in the pixels. Furthermore, the first embodiment will describe a method for manufacturing the photodetector. 2. Second Embodiment The second embodiment will describe a second example in which the pixel configuration is changed in the photodetector according to the first embodiment. 3. Third Embodiment The third embodiment will describe a third example in which the pixel configuration is changed in the photodetector according to the first embodiment. 4. Fourth Embodiment The fourth embodiment will describe a fourth example in which the pixel configuration is changed in the photodetector according to the first embodiment. 5. Fifth Embodiment The fifth embodiment will describe a fifth example in which the pixel configuration is changed in the photodetector according to the fourth embodiment. 6. Sixth Embodiment The sixth embodiment describes a sixth example in which the pixel configuration is changed in the photodetector device according to the first embodiment. 7. Seventh Embodiment The seventh embodiment describes a seventh example in which the pixel circuit configuration is changed in the photodetector device according to the first embodiment. 8. Eighth Embodiment The eighth embodiment describes an eighth example in which the pixel configuration is changed in the photodetector device according to the first embodiment. 9. Ninth Embodiment The ninth embodiment describes a ninth example in which the pixel configuration is changed in the photodetector device according to the first embodiment. 10. Tenth Embodiment The tenth embodiment describes a tenth example in which the pixel configuration is changed in the photodetector device according to the first embodiment. In particular, the tenth embodiment changes the structure of the transistors that constitute the pixels. The tenth embodiment also describes a method for manufacturing a photodetector device. 11. Eleventh Embodiment The eleventh embodiment describes an eleventh example in which the pixel configuration is changed in the photodetector device according to the tenth embodiment. 12. Twelfth Embodiment The twelfth embodiment describes a twelfth example in which the pixel configuration is changed in the photodetector device according to the tenth embodiment.13. Thirteenth Embodiment The thirteenth embodiment describes a thirteenth example in which the pixel configuration is changed in the photodetector according to the eighth embodiment. In particular, the thirteenth embodiment changes the structure of the transistors that constitute the pixels. The thirteenth embodiment further describes a method for manufacturing a photodetector. 14. Fourteenth Embodiment The fourteenth embodiment describes a fourteenth example in which the pixel configuration is changed in the photodetector according to the thirteenth embodiment. 15. Fifteenth Embodiment The fifteenth embodiment describes a fifteenth example in which the present technology is applied to an electronic device equipped with a photodetector according to any of the first to fourteenth embodiments. 16. Application Example to a Mobile Object This application example describes an example in which the present technology is applied to a vehicle control system, which is an example of a mobile object control system. 17. Application Example to an Endoscopic Surgery System This application example describes an example in which the present technology is applied to an endoscopic surgery system. 18. Other Embodiments

[0015] 1. First Embodiment A photodetector 1 according to a first embodiment of the present disclosure will be described with reference to FIGS. 1 to 5, 6A to 15A, and 6B to 15B.

[0016] Here, the arrow X direction shown as appropriate in the drawings indicates, for convenience, one planar direction of the photodetector 1 placed on a flat surface. The arrow Y direction indicates another planar direction perpendicular to the arrow X direction. The arrow Z direction indicates an upward direction perpendicular to the arrow X direction and the arrow Y direction. In other words, the arrow X direction, arrow Y direction, and arrow Z direction exactly correspond to the X-axis direction, Y-axis direction, and Z-axis direction, respectively, of a three-dimensional coordinate system. Note that these directions are shown for convenience to facilitate understanding of the explanation, and do not limit the directions of the present technology.

[0017] [Configuration of Photodetector 1] (1) Overall Configuration of Photodetector 1 Fig. 1 shows an example of a system configuration of a photodetector 1 according to a first embodiment. The photodetector 1 is one type of semiconductor device. Here, the photodetector 1 is constructed as a CMOS (Complementary Metal Oxide Semiconductor) solid-state imaging device. The solid-state imaging device detects light L (see Fig. 5) incident from the outside, converts the detected light L into electric charges, and generates an image such as a still image or a moving image based on the converted electric charges.

[0018] The photodetector 1 includes a pixel region (pixel array section) 100 having a plurality of pixels 10 regularly arranged two-dimensionally within a plane in the directions of arrows X and Y, and peripheral circuits.

[0019] As will be explained later, the pixel 10 includes a photoelectric conversion element PD (see FIG. 3) and a transfer transistor TR (see FIG. 3). The photoelectric conversion element PD is configured by, for example, a photodiode. The photoelectric conversion element PD converts light L into electric charges. The transfer transistor TR transfers the electric charges converted by the photoelectric conversion element PD. In addition, a pixel circuit 20 (see FIG. 3) is electrically connected to the pixel 10. The pixel circuit 20 reads out the electric charges converted in the pixel 10.

[0020] The peripheral circuits are configured to include a vertical drive circuit VD, a column signal processing circuit CS, a horizontal drive circuit HD, an output circuit Out, a control circuit CC, and the like.

[0021] The control circuit CC receives an input clock and data instructing the operation mode, etc., and outputs data such as internal information of the photodetector 1. That is, the control circuit CC generates clock signals and control signals that serve as the basis for the operation of the vertical drive circuit VD, column signal processing circuit CS, horizontal drive circuit HD, etc., based on a vertical synchronization signal, a horizontal synchronization signal, and a master clock. These signals are then input to the vertical drive circuit VD, column signal processing circuit CS, horizontal drive circuit HD, etc.

[0022] The vertical drive circuit VD is configured, for example, by a shift register. The vertical drive circuit VD selects a pixel drive line Ld and supplies a pulse to the selected pixel drive line Ld to drive the pixels 10. The pixels 10 are driven row by row. That is, the vertical drive circuit VD sequentially selects and scans each pixel 10 in the pixel region 100 row by row in the vertical direction. Signal charges generated in the photoelectric conversion element PD of each pixel 10 according to the amount of light received are supplied as pixel signals to the column signal processing circuit CS via the vertical signal line Lv.

[0023] The column signal processing circuit CS is arranged, for example, for each column of pixels 10. The column signal processing circuit CS performs signal processing such as noise removal on signals output from one row of pixels 10 for each pixel column. That is, the column signal processing circuit CS performs signal processing such as CDS (Correlated Double Sampling) that removes fixed pattern noise specific to the pixels 10, signal amplification, and AD (Analog-Digital) conversion. A horizontal selection switch (not shown) is connected between the output stage of the column signal processing circuit CS and the horizontal signal line Lh.

[0024] The horizontal drive circuit HD is configured by, for example, a shift register, and sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits CS in turn, and outputs pixel signals from each of the column signal processing circuits CS to the horizontal signal line Lh.

[0025] The output circuit Out processes and outputs signals sequentially supplied from each of the column signal processing circuits CS through the horizontal signal line Lh. For example, the output circuit Out may perform only buffering, or may perform black level adjustment, column variation correction, various digital signal processing, etc. The input / output terminal In exchanges signals between the photodetector 1 and the outside.

[0026] (2) Device Configuration of Light Detecting Device 1 FIG. 2 shows an example of a schematic exploded planar configuration of the light detecting device 1 shown in FIG. 1. The light detecting device 1 has a three-layer structure in which a first base 1A, a second base 1B, and a third base 1C are stacked and bonded together. Here, the third base 1C, the second base 1B, and the first base 1A are stacked in order in the direction of the arrow Z. Note that in the first embodiment and in embodiments based on the first embodiment described below, the light detecting device 1 has a three-layer structure. Furthermore, in a seventh embodiment (see FIG. 24) described below, the light detecting device 1 has a two-layer structure in which the first base 1A and the second base 1B are combined into a single base.

[0027] The first substrate 1A is formed in a rectangular shape when viewed in the direction of arrow Z or the direction opposite to the direction of arrow Z (hereinafter simply referred to as "in a plan view"). More specifically, the first substrate 1A is formed in a square shape here. The first substrate 1A includes a semiconductor substrate (see reference numeral 30 in FIGS. 4 and 5 ) made of, for example, single-crystal silicon. A photoelectric conversion element PD and a transfer transistor TR that constitute a pixel 10 are disposed on the semiconductor substrate of the first substrate 1A. A pixel region 100 is disposed over substantially the entire area of ​​the first substrate 1A. As described above, a plurality of pixels 10 are arranged in the pixel region 100. In other words, the first substrate 1A constitutes a photodetection surface that serves as an imaging surface for capturing an image.

[0028] The second substrate 1B is formed in a rectangular shape similar to the first substrate 1A in plan view and has the same planar size as the first substrate 1A. Like the first substrate 1A, the second substrate 1B includes a semiconductor substrate made of, for example, single-crystal silicon. A plurality of pixel transistors (not shown) constituting a pixel circuit 20 are arranged on the semiconductor substrate of the second substrate 1B. While the number of pixel transistors is not particularly limited, in the first embodiment, one pixel circuit 20 is arranged for four pixels 10. The pixel transistors constituting the pixel circuit 20 will be described later. The second substrate 1B also includes pixel drive wiring Ld and vertical signal lines Lv that overlap the pixel region 100 in plan view and extend through the pixel region 100 in the X direction and the Y direction, respectively. In the case of a photodetector 1 having a two-layer structure, the pixel circuit 20 is arranged on a substrate that combines the first substrate 1A and the second substrate 1B.

[0029] The third substrate 1C is formed in a rectangular shape in plan view similar to that of the first substrate 1A, and is formed to have the same planar size as that of the first substrate 1A. Like the first substrate 1A, the third substrate 1C includes a semiconductor substrate formed of, for example, single crystal silicon. Peripheral circuits are disposed on the semiconductor substrate of the third substrate 1C. As described above, the peripheral circuits include the vertical drive circuit VD, column signal processing circuit CS, horizontal drive circuit HD, output circuit Out, control circuit CC, etc.

[0030] In the first embodiment, each circuit in the peripheral circuit is a logic circuit. The logic circuit is constructed to include one or more semiconductor elements selected from a transistor, a capacitor, and a resistor. The transistor is an insulated gate field effect transistor (IGFET). At least one pair of main electrodes of the transistor has a surface coated with CoSi ２ A low resistance layer is formed using a salicide (self-aligned silicide) process of NiSi, etc. For example, the resistance value of the low resistance layer is smaller than the resistance value of the semiconductor layer.

[0031] 3 shows an example of the circuit configuration of the pixels 10 and pixel circuits 20 of the photodetector 1. In the first embodiment, four pixels 10 are electrically connected to one pixel circuit 20, and the four pixels 10 share one pixel circuit 20. In other words, the electric charges converted from light L in each of the four pixels 10 are read out in one pixel circuit 20.

[0032] Each pixel 10 includes a photoelectric conversion element PD and a transfer transistor TR, configured as a series circuit of the two. More specifically, the photoelectric conversion element PD is configured as a photodiode. The photodiode includes an anode region and a cathode region. Meanwhile, the transfer transistor TR is an IGFET. The IGFET includes a pair of main electrodes (a source region and a drain region) and a gate electrode. The anode region of the photoelectric conversion element PD is electrically connected to a reference voltage GND. The cathode region is electrically connected to one main electrode of the transfer transistor TR. The other main electrode of the transfer transistor TR is electrically connected to one end of a floating diffusion FD. A control signal (transfer signal) that controls conduction or non-conduction is input to the gate electrode.

[0033] As described above, four pixels 10 are arranged for one pixel circuit 20, and therefore, the identification numbers 1, 2, 3, and 4 are added to the end of the reference numerals of the components within the pixels 10 to distinguish them from one another. For example, one of the four pixels 10 is configured to include a photoelectric conversion element PD1 and a transfer transistor TR1. Note that, if there is no need to distinguish them from one another, no identification number is added.

[0034] Although a detailed structure will be described later, in the first embodiment, the transfer transistor TR is configured as a vertical transistor. That is, the transfer transistor TR is configured as a vertical IGFET. The transfer transistor TR corresponds to the "transfer transistor" according to the present technology, and corresponds to the "insulated gate field effect transistor (IGFET)" according to the present technology in the semiconductor device.

[0035] The pixel circuit 20 is constructed of a plurality of pixel transistors. Here, the pixel transistors include a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL. As will be explained in a seventh embodiment below, each of the pixel transistors is formed of, for example, a lateral IGFET.

[0036] One main electrode of the reset transistor RST is electrically connected to the other end of the floating diffusion FD, and the other main electrode is electrically connected to the power supply voltage VDD. A reset signal is input to the gate electrode. When the reset transistor RST is turned on, it resets the floating diffusion FD to a potential corresponding to the power supply voltage VDD.

[0037] One main electrode of the amplifier transistor AMP is electrically connected to one main electrode of the select transistor SEL, and the other main electrode is electrically connected to the power supply voltage VDD. One main electrode of the reset transistor RST and the other end of the floating diffusion FD are electrically connected to the gate electrode of the amplifier transistor AMP. The amplifier transistor AMP forms a source follower amplifier. In other words, the amplifier transistor AMP generates a pixel signal according to the charge transferred through the floating diffusion FD.

[0038] The other main electrode of the selection transistor SEL is electrically connected to a vertical signal line Lv. A selection signal is input to the gate electrode of the selection transistor SEL. The selection transistor SEL outputs the generated pixel signal to the vertical signal line Lv.

[0039] (4) Device Configuration of Pixel 10 Fig. 4 shows an example of a planar configuration of the pixel 10 of the photodetector 1. Fig. 5 shows an example of a cross-sectional configuration of the pixel 10. As described above, the photodetector 1 according to the first embodiment has a three-layer structure. The pixel 10 is disposed on a semiconductor substrate 30 that forms a first base 1A that constitutes the three-layer structure.

[0040] In the first embodiment, in the pixel region 100, a plurality of pixels 10 are regularly arranged in the directions of the arrow X and the arrow Y. In a plan view, the planar shape of the pixel 10 is formed into a rectangular shape. More specifically, the planar shape of the pixel 10 is formed into an effective square shape. A pixel isolation region 31 is disposed around each pixel 10. The pixel isolation region 31 extends in the direction of the arrow X and is disposed at regular intervals in the direction of the arrow Y, and further extends in the direction of the arrow Y and is disposed at regular intervals in the direction of the arrow X. In other words, in a planar view, the planar shape of the pixel isolation region 31 is formed into a lattice shape.

[0041] The pixel isolation region 31 includes a groove 311 and a filler 312. The groove 311 is formed by digging down in the thickness direction of the semiconductor substrate 30 from the surface 30A of the semiconductor substrate 30 toward the other surface 30B opposite the surface 30A. In the first embodiment, the groove 311 is configured by connecting and combining a first groove 311A ​​and a second groove 311B. The first groove 311A ​​is a deep groove that penetrates the semiconductor substrate 30 in the thickness direction from the surface 30A toward the surface 30B and is dug down to the vicinity of the surface 30B. On the other hand, the second groove 311B is a shallow groove that is dug down part of the semiconductor substrate 30 in the thickness direction from the surface 30B toward the surface 30A. Here, the surface 30A corresponds to the "second surface" according to the present technology. On the other hand, the surface 30B corresponds to the "first surface" according to the present technology.

[0042] The grooves 311 are filled with a filler 312. The filler 312 may be, for example, a SiO 2 film that can optically and electrically separate adjacent pixels 10. ２ Insulating materials such as

[0043] Each pixel 10 includes a photoelectric conversion element PD and a transfer transistor TR. As described above, four pixels 10 are electrically connected to one pixel circuit 20 (see FIG. 3 ). In other words, a total of four pixels 10, two adjacent pixels 10 in the direction of the arrow X and two adjacent pixels 10 in the direction of the arrow Y, constitute a unit pixel. The four pixels 10 are formed in a line-symmetrical shape with respect to a center line Cx extending in the direction of the arrow X and a center line Cy extending in the direction of the arrow Y, which are shown for convenience between adjacent pixels 10.

[0044] (4-1) Device Configuration of Photoelectric Conversion Element PD Although detailed structural illustration and description are omitted, the photoelectric conversion element PD is disposed inside the semiconductor substrate 30 in an area surrounded by pixel isolation regions 31 in the directions of arrows X and Y. In other words, the pixel 10 is constructed in the area surrounded by the pixel isolation region 31.

[0045] The photoelectric conversion element PD includes a p-type semiconductor region 301 as an anode region and an n-type semiconductor region 302 as a cathode region. The p-type semiconductor region 301 is also used as a p-type well region. A p-type semiconductor region 303 having a higher impurity density than the p-type semiconductor region 301 and the same conductivity type as the p-type semiconductor region 301 is disposed on the surface portion of the p-type semiconductor region 301 along the pixel isolation region 31. The p-type semiconductor region 303 is used as a pinning region.

[0046] Furthermore, in a plan view, a p-type semiconductor region 304 is disposed on a diagonal line of the pixel 10, for example, on a diagonal line coinciding with the A-A cutting line of the pixel 10 including the photoelectric conversion element PD4 and the transfer transistor TR4, in a surface 30B portion of the p-type semiconductor region 301. The p-type semiconductor region 304 has a higher impurity density than the p-type semiconductor region 301, has the same conductivity type as the p-type semiconductor region 301, and is used as a p-type contact region (well contact region).

[0047] (4-2) Device Configuration of Transfer Transistor TR The transfer transistor TR is disposed closer to the surface 30B of the semiconductor substrate 30 than the photoelectric conversion element PD is, within the pixel isolation region 31. The transfer transistor TR includes, as its main components, a channel formation region 30c, a gate insulating film 5, a gate electrode 6, and a pair of main electrodes (source region and drain region).

[0048] The gate insulating film 5 and gate electrode 6 of the transfer transistor TR are disposed in a trench 4. More specifically, the trench 4 is disposed along the diagonal of the pixel 10, closer to one side than the center of the diagonal. As shown in FIG. 4 , in the pixel 10 including the photoelectric conversion element PD1 and the transfer transistor TR1, the trench 4 is disposed at the bottom left along the diagonal. In the pixel 10 including the photoelectric conversion element PD2 and the transfer transistor TR2, the trench 4 is disposed at the bottom right along the diagonal. In the pixel 10 including the photoelectric conversion element PD3 and the transfer transistor TR3, the trench 4 is disposed at the top left along the diagonal. In the pixel 10 including the photoelectric conversion element PD4 and the transfer transistor TR4, the trench 4 is disposed at the top right along the diagonal.

[0049] In plan view, the opening shape of the groove 4 is rectangular with the longitudinal direction perpendicular to the diagonal line. The actual opening shape of the groove 4 is polygonal with rounded corners due to the adjacency effect during mask formation, etching, etc. in the manufacturing process. The opening shape of the groove 4 may also be triangular, square, polygonal with pentagons or more, circular, or elliptical.

[0050] The trench 4 is disposed from the surface 30B toward the surface 30A of the semiconductor substrate 30. The trench 4 is formed by connecting and combining a trench lower portion 4A and an upper portion 4B. The trench upper portion 4B is dug from the surface 30B toward the surface 30A. The cross-sectional shape of the trench upper portion 4B, when viewed in the direction of arrow X or arrow Y (hereinafter simply referred to as "in a side view"), is formed as a tapered shape in which the opening dimension on the surface 30A side is smaller than the opening dimension on the surface 30B side. The depth of the trench upper portion 4B from the surface 30B is formed, for example, 50 nm to 900 nm. The trench lower portion 4A is dug further from the trench upper portion 4B toward the surface 30A side. The cross-sectional shape of the trench lower portion 4A is formed so that the opening dimension on the surface 30B side is equal to the opening dimension on the surface 30A side in a side view. The total depth of the trench 4, which is the depth of the trench upper portion 4B plus the depth of the trench lower portion 4A, is formed, for example, 100 nm to 1000 nm.

[0051] The channel formation region 30c of the transfer transistor TR is formed by a p-type semiconductor region 301 along the sidewall of the trench lower portion 4A.

[0052] The gate insulating film 5 is disposed along the sidewall of the trench lower portion 4A. The gate insulating film 5 is made of, for example, SiO ２ When this insulating material is used, the gate insulating film 5 is formed to have a thickness t1 in a direction from the sidewall of the trench lower portion 4A toward the center of the trench lower portion 4A, which is, for example, 2 nm or more and 20 nm or less.

[0053] The gate electrode 6 is buried in the trench lower portion 4A with a gate insulating film 5 interposed therebetween. The gate electrode 6 is made of a gate electrode material such as polycrystalline silicon. When polycrystalline silicon is used as the gate electrode material, impurities that reduce the resistance value are added to the polycrystalline silicon.

[0054] One of the pair of main electrodes is electrically connected to the cathode region (n-type semiconductor region 302) of the photoelectric conversion element PD. In other words, the cathode region is used as one main electrode of the transfer transistor TR. Meanwhile, the other of the pair of main electrodes is electrically connected to the floating diffusion FD. Similarly, the floating diffusion FD is used as the other main electrode of the transfer transistor TR.

[0055] (4-3) Device Configuration of Floating Diffusion FD The floating diffusion FD is disposed within a region surrounded by the pixel isolation region 31. More specifically, the floating diffusion FD is disposed along a diagonal of the pixel 10, facing the transfer transistor TR and closer to the other side of the center of the diagonal. As shown in FIG. 4 , in the pixel 10 including the photoelectric conversion element PD1 and the transfer transistor TR1, the floating diffusion FD is disposed at the top right along the diagonal. In the pixel 10 including the photoelectric conversion element PD2 and the transfer transistor TR2, the floating diffusion FD is disposed at the top left along the diagonal. In the pixel 10 including the photoelectric conversion element PD3 and the transfer transistor TR3, the floating diffusion FD is disposed at the bottom right along the diagonal. In the pixel 10 including the photoelectric conversion element PD4 and the transfer transistor TR4, the floating diffusion FD is disposed at the bottom left along the diagonal.

[0056] The floating diffusion FD is formed by an n-type semiconductor region 8 disposed in a p-type semiconductor region 301 on the surface 30B side of the semiconductor substrate 30. The n-type semiconductor region 8 is electrically isolated from the p-type semiconductor region 301 by a pn junction.

[0057] (4-4) Device Configuration of Electrode 60 The electrode 60 is electrically connected to the gate electrode 6 of the transfer transistor TR. The electrode 60 is embedded in the upper portion 4B of the trench 4 with a sidewall insulator 7 interposed therebetween, and is drawn out along the sidewall insulator 7 at the surface 30B.

[0058] The electrode 60 is formed from the same gate electrode material as the gate electrode 6, and is formed integrally with the gate electrode 6. The electrode 60 is formed as an extraction electrode (extraction wiring) of the gate electrode 6. The electrode 60 is used as a connection region with wiring (not shown). An extraction dimension L1 (see FIG. 5 ) of the electrode 60 extracted from the periphery of the opening of the trench 4 to the surface 30B is set to be equal to or smaller than a dimension L2 corresponding to a thickness t2 of the sidewall insulator 7 in the same direction, at least in the region facing the floating diffusion FD.

[0059] (4-5) Device Configuration of Sidewall Insulator 7 The sidewall insulator 7 is disposed on the sidewall of the trench 4 in the trench upper portion 4B. The sidewall insulator 7 is disposed at least between the electrode 60 and the floating diffusion FD and between the electrode 60 and the p-type semiconductor region 304. The thickness t2 of the sidewall insulator 7 in the same direction is formed to be thicker than the thickness t1 of the gate insulating film 5 of the transfer transistor TR. The thickness t2 of the sidewall insulator 7 is formed by adding a thickness of, for example, 10 nm to 50 nm to the thickness t1 of the gate insulating film 5. In the first embodiment, the sidewall insulator 7 is formed of, for example, SiO ２ The sidewall insulator 7 is made of an insulating material such as SiN or SiO ２ , and SiN may be laminated to form a composite film.

[0060] Furthermore, the sidewall insulator 7 is formed in self-alignment with the upper portion 4B of the trench 4. That is, the thickness t2 of the sidewall insulator 7 is a constant value corresponding to the deposited thickness, without being affected by misalignment in the manufacturing process. Since the sidewall insulator 7 is formed in self-alignment with the trench 4, the electrode 60 is consequently formed in self-alignment with both the trench 4 and the sidewall insulator 7.

[0061] Furthermore, the depth h2 of the sidewall insulator 7 from the surface 30B toward the surface 30A is equal to the depth of the upper portion 4B of the trench and is equal to or greater than the depth h1 of the floating diffusion FD in the same direction (h2≧h1). The depth h1 is the pn junction depth of the n-type semiconductor region 8 relative to the p-type semiconductor region 301.

[0062] In the first embodiment, the floating diffusion FD is disposed at a position spaced apart from the sidewall insulator 7 or the sidewall of the upper portion of the trench 4B. In the present technology, the floating diffusion FD may be disposed in contact with the sidewall insulator 7. In this case, the floating diffusion FD is formed in self-alignment with the sidewall insulator 7.

[0063] (4-6) Device Configuration of Shared Wiring 61 and Shared Wiring 62 The floating diffusions FD of four adjacent pixels 10 that form a unit pixel are electrically connected to one shared wiring (shared electrode) 61. The shared wiring 61 is embedded in the surface 30B side of the pixel isolation region 31, and is electrically connected to the side surfaces of multiple floating diffusions FD (n-type semiconductor regions 8). The shared wiring 61 is formed of a gate electrode material such as polycrystalline silicon. Wiring not shown is electrically connected to the shared wiring 61.

[0064] In four unit pixels adjacent to each other in the directions of arrows X and Y, the p-type semiconductor regions 304 of four adjacent pixels 10 are electrically connected to one shared wiring (shared electrode) 62. Like the shared wiring 61, the shared wiring 62 is embedded in the surface 30B side of the pixel isolation region 31 and is electrically connected to the side surfaces of the plurality of p-type semiconductor regions 304. The shared wiring 62 is formed from the same gate electrode material as the shared wiring 61. Wiring (not shown) is electrically connected to the shared wiring 62.

[0065] (5) Configuration of Optical Filter 140 In the pixel 10, an optical filter 140 and an optical lens 150 are sequentially disposed on the surface 30A of the semiconductor substrate 30 with a protective film 130 interposed therebetween. The optical filter 140 is formed, for example, as a red color filter that transmits light L in the red light band, a green color filter that transmits light L in the green light band, or a blue color filter that transmits light L in the blue light band. The optical filter 140 may also be a filter that transmits near-infrared light. The optical filter 140 is formed, for example, from a resin material to which an organic pigment is added. Examples of the resin material that can be used include acrylic resins and styrene-based resins.

[0066] (6) Configuration of Optical Lens 150 In side view, the optical lens 150 is disposed for each pixel 10 or for each set of multiple pixels 10. In side view, the optical lens 150 is formed in a curved shape that protrudes in the direction of the arrow Z. The optical lens 150 is formed, for example, from a light-transmitting resin material. Note that, although not shown in the drawings or in detailed description, an anti-reflection film may be formed on the optical lens 150. The optical lens 150 is connected to other adjacent optical lenses 150, and multiple optical lenses 150 are formed integrally. The optical lens 150 is configured as an on-chip lens.

[0067] It should be noted that illustration and detailed description of the pixel circuit 200 disposed on the second substrate 1B of the photodetector 1 and the peripheral circuit disposed on the third substrate 1C will be omitted.

[0068] 6A to 15A illustrate an example of a cross section taken along the line A-A in FIG. 4, which explains the manufacturing method of the photodetector 1 step by step. FIGS. 6B to 15B illustrate an example of a cross section taken along the line B-B in FIG. 4, which explains the manufacturing method of the photodetector 1 step by step. The manufacturing method of the photodetector 1 according to the first embodiment is mainly a method of manufacturing the transfer transistor TR of the pixel 10. The manufacturing method of the photodetector 1 is as follows.

[0069] First, a semiconductor substrate 30 is prepared (see FIGS. 6A and 6B). This semiconductor substrate 30 is in the state of a semiconductor wafer before a dicing process, and has pixel isolation regions 31 and photoelectric conversion elements PD (see FIG. 5), not shown, formed thereon.

[0070] 6A and 6B, a mask 310 is formed on the surface 30B of the semiconductor substrate 30. For example, SiN is used as a hard mask for the mask 310. Subsequently, as shown in FIGS. 7A and 7B, a mask 314 is formed on the mask 310. For example, photoresist is used for the mask 314. An opening 314H is formed in the mask 314 in a region where the gate electrode 6 of the transfer transistor TR is to be formed.

[0071] Using the mask 314, the upper portion 4B of the trench is formed from the surface 30B of the semiconductor substrate 30 toward the surface 30A (see FIGS. 8A and 8B). Anisotropic etching such as RIE (Reactive Ion Etching) is used to form the upper portion 4B of the trench. Here, the upper portion 4B of the trench is formed in a tapered shape when viewed from the side. As shown in FIGS. 8A and 8B, the mask 314 is removed.

[0072] 9A and 9B, an insulator 7S is formed on the mask 310, including the sidewalls and bottom surface of the upper portion 4B of the trench. The insulator 7S is formed by using, for example, a chemical vapor deposition (CVD) method. The insulator 7S is made of, for example, SiO ２ is used.

[0073] An etch-back process is performed on the entire surface 30B side of the semiconductor substrate 30 to remove the insulator 7S. For example, anisotropic etching is used for the etch-back process. As a result, as shown in FIGS. 10A and 10B, a sidewall insulator 7 is formed on the sidewall of the trench upper portion 4B from the insulator 7S. The sidewall insulator 7 is formed on the sidewall of the trench upper portion 4B in a self-aligned manner with the trench upper portion 4B.

[0074] 11A and 11B, the semiconductor substrate 30 is further dug down from the bottom surface of the trench upper portion 4B using the mask 310 and the sidewall insulator 7 as a mask, thereby forming the trench lower portion 4A. For example, anisotropic etching is used to form the trench lower portion 4A. Once the trench lower portion 4A is formed, the trench 4 consisting of the trench lower portion 4A and the trench upper portion 4B is completed. Here, the trench lower portion 4A is formed in self-alignment with the sidewall insulator 7 using the sidewall insulator 7 as a mask, and as a result, is formed in self-alignment with the trench upper portion 4B.

[0075] 12A and 12B, a gate insulating film 5 is formed on the sidewalls and bottom surface of the trench lower portion 4A. The gate insulating film 5 is formed by, for example, thermal oxidation. In this example, SiO ２ Since the mask 310 is formed on the surface 30B of the semiconductor substrate 30, the gate insulating film 5 is not formed thereon. The sidewall insulator 7 is slightly grown by thermal oxidation.

[0076] 13A and 13B, the mask 310 is removed. Subsequently, as shown in Figures 14A and 14B, a gate electrode material 600 is formed on the surface 30B of the semiconductor substrate 30 including the inside of the trench 4. The gate electrode material 600 is formed using, for example, a CVD (Chemical Vapor Deposition) method, and is formed of polycrystalline silicon in this example.

[0077] 15A and 15B, photolithography and etching techniques are used to pattern the gate electrode material 600. As a result, a gate electrode 6 is formed from the gate electrode material 600 with a gate insulating film 5 interposed between at least the sidewalls of the trench lower portion 4A. Furthermore, an electrode 60 is formed from the gate electrode material 600 with a sidewall insulator 7 interposed between the sidewalls of the trench upper portion 4B.

[0078] Thereafter, as shown in FIGS. 4 and 5, the floating diffusion FD is formed, and the transfer transistor TR is completed.

[0079] When the manufacturing process including the series of manufacturing steps is completed, the photodetector 1 according to the first embodiment is completed.

[0080] [Operation and Effect] As shown in FIGS. 4 and 5 , the photodetector (semiconductor device) 1 according to the first embodiment includes a trench 4, a transfer transistor TR (IGFET), a sidewall insulator 7, and an electrode 60. The trench 4 is disposed from the surface 30B of the semiconductor substrate 30 toward the surface 30A opposite the surface 30B. The transfer transistor TR is disposed in a trench lower portion 4A within the trench 4 and has a gate electrode 6 embedded in the sidewall of the trench lower portion 4A with a gate insulating film 5 interposed therebetween. The sidewall insulator 7 is disposed on the sidewall of the trench upper portion 4B within the trench 4 and has a thickness t2 in the same direction that is greater than the thickness t1 of the gate insulating film 5. The electrode 60 is embedded in the trench upper portion 4B within the trench 4 with the sidewall insulator 7 interposed therebetween and is electrically connected to the gate electrode 6. The photodetector 1 further includes a floating diffusion FD and a photoelectric conversion element PD.

[0081] The floating diffusion FD is disposed on the surface 30B side of the semiconductor substrate 30 with the sidewall insulator 7 interposed between the electrode 60 and the electrode 60, and is electrically connected to one end of the transfer transistor TR. The photoelectric conversion element PD is disposed within the semiconductor substrate 30, is electrically connected to the other end of the transfer transistor TR, and converts light into electric charges.

[0082] Here, the photoelectric conversion element PD is configured by a photodiode having an anode region and a cathode region, and the transfer transistor TR has a pair of main electrodes, one of which is configured by a floating diffusion FD and the other main electrode is configured by the cathode region.

[0083] In the photodetector 1 configured in this manner, the capacitance value of the parasitic capacitance, with the floating diffusion FD as one electrode, the sidewall insulator 7 as the dielectric, and the electrode 60 as the other electrode, is reduced. More specifically, the sidewall insulator 7, which has a thickness t2 greater than the thickness t1 of the gate insulating film 5 of the transfer transistor TR, serves as the dielectric of the parasitic capacitance. This reduces the parasitic capacitance applied to the floating diffusion FD and the electrode 60, thereby improving the transfer speed of the charge converted by the photoelectric conversion element PD in response to the input of a transfer signal in the transfer transistor TR. In other words, the characteristics of the transfer transistor TR, or in other words, the IGFET mounted on the semiconductor device, can be improved.

[0084] In addition, the sidewall insulator 7 having the thickness t2 can effectively suppress or prevent the influence of the electric field generated from the electrode 60 to the floating diffusion FD. Therefore, the occurrence of white spots can be effectively suppressed or prevented in the photodetector 1. As an IGFET, the occurrence of signal noise can be effectively suppressed or prevented.

[0085] Furthermore, in the photodetector 1, as shown in FIG. 5 , the electrode 60 is extended to the surface 30B within the thickness L2 of the sidewall insulator 7 disposed between the floating diffusion FD and the electrode 60. In other words, the extension dimension L1 of the electrode 60 is formed to be equal to or less than the thickness L2 of the sidewall insulator 7. In the photodetector 1 configured in this manner, the shielding effect of the sidewall insulator 7 can effectively suppress or prevent the influence of the electric field generated on the floating diffusion FD from the region of the electrode 60 extended to the surface 30B. Therefore, the photodetector 1 can effectively suppress or prevent the occurrence of white spots. As an IGFET, the occurrence of signal noise can be effectively suppressed or prevented. Note that, because the electrode 60 has a region extended to the surface 30B, a sufficient area for connection to wiring (not shown) can be secured for the electrode 60.

[0086] 5, in the photodetector 1, the thickness of the sidewall insulator 7 on the surface 30B side is thicker than that on the surface 30A side, and the cross-sectional shape of the sidewall insulator 7 is tapered in side view. In the photodetector 1 configured in this manner, charges (electrons: e) converted by the photoelectric conversion element PD are transferred to the floating diffusion FD through the channel formation region 30c of the transfer transistor TR. At this time, the charges are transferred obliquely from the channel formation region 30c toward the floating diffusion FD, as indicated by the arrow marked with symbol e in FIG. 5. This effectively shortens the charge transfer path, thereby improving the transfer efficiency of the transfer transistor TR.

[0087] 5, in the photodetector 1, the depth h2 of the sidewall insulator 7 from the surface 30B toward the surface 30A is deeper than the junction depth h1 of the floating diffusion FD. In the photodetector 1 configured in this manner, the influence of the electric field generated from the electrode 60 to the floating diffusion FD can be effectively suppressed or prevented by the shielding effect of the sidewall insulator 7. Therefore, the photodetector 1 can effectively suppress or prevent the occurrence of white spots. As an IGFET, it can effectively suppress or prevent the occurrence of signal noise.

[0088] 8A to 10A and 8B to 10B, the sidewall insulators 7 are formed in a self-aligned manner with respect to the grooves 4. In the photodetector 1 configured in this manner, there is no misalignment of the sidewall insulators 7 with respect to the grooves 4, and therefore the pixel 10 can be reduced in size.

[0089] 2. Second Embodiment A photodetector 1 according to a second embodiment of the present disclosure will be described with reference to Fig. 16. In the second embodiment and subsequent embodiments, components that are the same as or substantially the same as components of the photodetector 1 according to the first embodiment are denoted by the same reference numerals, and duplicated descriptions will be omitted.

[0090] 16 shows an example of a cross-sectional configuration of a pixel 10 of the photodetector 1. In the photodetector 1 according to the second embodiment, the thickness of the sidewall insulator 7 on the surface 30A side is equal to the thickness of the gate insulating film 5 in the photodetector 1 according to the first embodiment, and the thickness of the sidewall insulator 7 gradually increases toward the surface 30B. In a side view, the cross-sectional shape of the sidewall insulator 7 is formed to be tapered.

[0091] The components of the second embodiment other than those described above are the same or substantially the same as the components of the photodetector 1 according to the first embodiment, and therefore a duplicated description will be omitted.

[0092] [Operational Effects] According to the photodetector 1 of the second embodiment, it is possible to obtain the same operational effects as those obtained by the photodetector 1 of the first embodiment.

[0093] 16, in the photodetector 1, the sidewall insulator 7 is formed to have a thickness equal to that of the gate insulating film 5 of the transfer transistor TR, and gradually becomes thicker toward the surface 30B. In the photodetector 1 configured in this manner, the transfer path of the charges converted by the photoelectric conversion element PD is further shortened. In addition, there is no difference in thickness between the gate insulating film 5 and the sidewall insulator 7. This makes it possible to further improve the transfer efficiency of the transfer transistor TR.

[0094] 3. Third Embodiment A photodetector 1 according to a third embodiment of the present disclosure will be described with reference to FIG.

[0095] [Device Configuration of Photodetector 1] Figure 17 shows an example of the cross-sectional configuration of a pixel 10 of the photodetector 1. In the photodetector 1 according to the third embodiment, the opening dimension of the groove upper portion 4B on the surface 30B side is equal to the opening dimension of the groove upper portion 4B on the surface 30A side in the photodetector 1 according to the first embodiment. In other words, the sidewall of the groove upper portion 4B is formed in a non-tapered shape. In addition, the thickness of the sidewall insulator 7 on the surface 30B side is equal to the thickness of the sidewall insulator 7 on the surface 30A side.

[0096] The components of the third embodiment other than those described above are the same or substantially the same as the components of the photodetector 1 according to the first embodiment, and therefore a duplicated description will be omitted.

[0097] [Operational Effects] According to the photodetector 1 of the third embodiment, it is possible to obtain the same operational effects as those obtained by the photodetector 1 of the first embodiment.

[0098] 17, in the photodetector 1, the thickness of the sidewall insulator 7 (t2: see FIG. 5) is formed to be uniform in the depth direction. This can further reduce the capacitance value of the parasitic capacitance added to the floating diffusion FD, etc. In addition, it can more effectively suppress or prevent the electric field generated from the electrode 60 to the floating diffusion FD.

[0099] 4. Fourth Embodiment A photodetector 1 according to a fourth embodiment of the present disclosure will be described with reference to FIGS. 18 and 19 .

[0100] [Device Configuration of Photodetector 1] Fig. 18 shows an example of a planar configuration of a pixel 10 of the photodetector 1. Fig. 19 shows an example of a cross-sectional configuration of a pixel 10 of the photodetector 1. In the photodetector 1 according to the fourth embodiment, a part of the electrode 60 in the photodetector 1 according to the first embodiment is extended to a position where it overlaps with the pixel isolation region 31.

[0101] The electrode 60 is drawn out until it overlaps the pixel isolation region 31 in a direction intersecting the diagonal line along which the floating diffusion FD and p-type semiconductor region 304 of the pixel 10 are arranged, in this case, a direction perpendicular to the diagonal line. In the fourth embodiment, the pixel isolation region 31 is arranged in contact with or spaced apart from the sidewall of the groove upper portion 4B of the groove 4.

[0102] The components of the fourth embodiment other than those described above are the same or substantially the same as the components of the photodetector 1 according to the first embodiment, and therefore a duplicated description will be omitted.

[0103] [Operational Effects] According to the photodetector 1 of the fourth embodiment, it is possible to obtain the same operational effects as those obtained by the photodetector 1 of the first embodiment.

[0104] 18 and 19, in the photodetector 1, a part of the electrode 60 extends to the pixel isolation region 31. In the photodetector 1 configured in this manner, the connection region of the electrode 60 with wiring (not shown) can be expanded, thereby improving the degree of freedom in the wiring layout.

[0105] 5. Fifth Embodiment A photodetector 1 according to a fifth embodiment of the present disclosure will be described with reference to FIGS. 20 and 21 .

[0106] [Device Configuration of Photodetection Device 1] Fig. 20 shows an example of the planar configuration of a pixel 10 of the photodetection device 1. Fig. 21 shows an example of the cross-sectional configuration of a pixel 10 of the photodetection device 1. The photodetection device 1 according to the fifth embodiment is an application example of the photodetection device 1 according to the fourth embodiment. As with the photodetection device 1 according to the fourth embodiment, a part of the electrode 60 is drawn out to a position where it overlaps with the pixel isolation region 31. In the fifth embodiment, the sidewall of the groove upper portion 4B of the groove 4 is arranged by removing a part of the pixel isolation region 31.

[0107] The components of the fifth embodiment other than those described above are the same or substantially the same as the components of the photodetector 1 according to the fourth embodiment, and therefore a duplicated description will be omitted.

[0108] [Operational Effects] According to the photodetector 1 of the fifth embodiment, it is possible to obtain the same operational effects as those obtained by the photodetector 1 of the fourth embodiment.

[0109] 6. Sixth Embodiment A photodetector 1 according to a sixth embodiment of the present disclosure will be described with reference to FIG. 22 and FIGS. 23A to 23D.

[0110] [Device Configuration of Photodetection Device 1] Figure 22 shows an example of the cross-sectional configuration of a pixel 10 of the photodetection device 1. The planar configuration of the pixel 10 is the same as that of Figure 18, and therefore is not shown here. In the photodetection device 1 according to the sixth embodiment, as in the photodetection device 1 according to the fourth or fifth embodiment, a part of the electrode 60 is extended to a position where it overlaps with the pixel isolation region 31. Furthermore, in the portion where the electrode 60 and the pixel isolation region 31 overlap, a part of the surface of the pixel isolation region 31 is removed, and the height is formed to be lower than the height of the other regions.

[0111] 23A to 23D illustrate an example of a cross section taken along the D2-D2 cutting line shown in FIG. 20 , illustrating each step of the method for manufacturing the photodetector 1. The method for manufacturing the photodetector 1 according to the sixth embodiment is mainly a method for manufacturing the transfer transistor TR of the pixel 10. The method for manufacturing the photodetector 1 is as follows.

[0112] 7B in the manufacturing method of the photodetector 1 according to the first embodiment (hereinafter simply referred to as the "first manufacturing method"), a mask 314 is formed on a mask 310 as shown in FIG. 23A. The mask 314 is made of, for example, photoresist. An opening 314H is formed in the mask 314 in a region where the gate electrode 6 of the transfer transistor TR is to be formed. A part of this opening 314H is also formed on the pixel isolation region 31 to which the gate electrode 6 extends.

[0113] 8B of the first manufacturing method, an upper portion 4B of the trench is formed from the front surface 30B toward the front surface 30A of the semiconductor substrate 30 using a mask 314 (see FIG. 23B ). Anisotropic etching, for example, is used to form the upper portion 4B of the trench. Here, as the upper portion 4B of the trench is formed, a portion of the surface of the pixel isolation region 31 exposed from the opening 314H of the mask 314 is removed. As shown in FIG. 23B , the mask 314 is peeled off.

[0114] 9B of the first manufacturing method, as shown in FIG. 23C, an insulator 7S is formed on the mask 310, including the sidewalls and bottom surface of the upper portion 4B of the trench. The insulator 7S is formed by, for example, a CVD method. The insulator 7S may be made of, for example, SiO ２ is used.

[0115] 10B of the first manufacturing method, as shown in FIG. 23D, an etch-back process is performed on the entire surface 30B side of the semiconductor substrate 30 to remove the insulator 7S. For example, anisotropic etching is used for the etch-back process. As a result, the sidewall insulator 7 is formed on the sidewall of the trench upper portion 4B from the insulator 7S. The sidewall insulator 7 is formed on the sidewall of the trench upper portion 4B in a self-aligned manner with the trench upper portion 4B.

[0116] Thereafter, by performing the step shown in FIG. 11B and subsequent steps of the first manufacturing method, the transfer transistor TR shown in FIG. 22 is completed, and the photodetector 1 according to the sixth embodiment is completed.

[0117] The components of the sixth embodiment other than those described above are the same or substantially the same as the components of the photodetector 1 according to the first embodiment, and therefore a duplicated description will be omitted.

[0118] [Operational Effects] According to the photodetector 1 of the sixth embodiment, it is possible to obtain the same operational effects as those obtained by the photodetector 1 of the first embodiment.

[0119] 7. Seventh Embodiment A photodetector 1 according to a seventh embodiment of the present disclosure will be described with reference to FIG.

[0120] [Device Configuration of Photodetector 1] Fig. 24 shows an example of the planar configuration of the pixel 10 of the photodetector 1. The photodetector 1 according to the seventh embodiment has a two-layer structure in which the first base 1A and the second base 1B shown in Fig. 2 are combined into one base.

[0121] The pixel circuit 20 is disposed adjacent to the pixel 10 on the surface 30B side of the semiconductor substrate 30. A detailed description will be given below. Here, the pixel circuit 20 is disposed adjacent to the unit pixel. As shown in FIG. 3 above, the pixel circuit 20 includes a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL. These transistors are configured as lateral IGFETs.

[0122] The reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are each disposed in a p-type semiconductor region 301 surrounded by a pixel isolation region (isolation region) 31 on the surface 30B side of the semiconductor substrate 30. That is, these transistors each include a channel formation region, a gate insulating film, a gate electrode 65, and a pair of main electrodes (not shown). The main electrodes are formed by an n-type semiconductor region 85 disposed in the p-type semiconductor region 301.

[0123] The components of the seventh embodiment other than those described above are the same or substantially the same as the components of the photodetector 1 according to the first embodiment, and therefore a duplicated description will be omitted.

[0124] [Operational Effects] According to the photodetector 1 of the seventh embodiment, it is possible to obtain the same operational effects as those obtained by the photodetector 1 of the first embodiment.

[0125] Furthermore, in the photodetector 1, as shown in FIG. 24, even in a two-layer structure in which the first substrate 1A and the second substrate 1B are combined into one substrate, it is possible to obtain the same effects as those obtained by the photodetector 1 according to the first embodiment.

[0126] 8. Eighth Embodiment A photodetector 1 according to an eighth embodiment of the present disclosure will be described with reference to FIGS. 25 and 26. FIG.

[0127] [Device Configuration of Photodetector 1] Fig. 25 shows an example of a planar configuration of a pixel 10 of the photodetector 1. Fig. 26 shows an example of a cross-sectional configuration of a pixel 10 of the photodetector 1. In the photodetector 1 according to the eighth embodiment, the gate electrode 6 of the transfer transistor TR of the pixel 10 has a multi-gate electrode structure.

[0128] A detailed description will be given. In the region of the transfer transistor TR of the pixel 10, a plurality of first grooves 41 and second grooves 42 are arranged from the surface 30B of the semiconductor substrate 30 toward the surface 30A. The cross-sectional shapes of the first grooves 41 and second grooves 42 are similar to the cross-sectional shapes of the grooves 4 of the photodetector 1 according to the first embodiment. That is, the first groove 41 has a groove lower portion 4A and a groove upper portion 4B. Similarly, the second groove 42 has a groove lower portion 4A and a groove upper portion 4B. Here, the second groove 42 is arranged spaced apart from the first groove 41. Furthermore, the planar shapes of the first groove 41 and the second groove 42 are each formed to be hexagonal.

[0129] The gate electrode 6 includes a first gate electrode 601 and a second gate electrode 602. That is, in the eighth embodiment, the transfer transistor TR has a twin-gate structure. The first gate electrode 601 is embedded in the lower portion 4A of the first trench 41 with a gate insulating film 5 interposed between the sidewalls and bottom surface of the lower portion 4A of the trench. Similarly, the second gate electrode 602 is embedded in the lower portion 4A of the second trench 42 with a gate insulating film 5 interposed between the sidewalls and bottom surface of the lower portion 4A of the trench. The electrode 60 is embedded in the upper portion 4B of the first trench 41 with a sidewall insulator 7 interposed between them, and is embedded in the upper portion 4B of the second trench 42 with a sidewall insulator 7 interposed between them, and is integrally formed on the surface 30B. That is, the electrode 60 electrically connects the first gate electrode 601 and the second gate electrode 602.

[0130] The components of the eighth embodiment other than those described above are the same or substantially the same as the components of the photodetector 1 according to the first embodiment, and therefore a duplicated description will be omitted.

[0131] [Operational Effects] According to the photodetector 1 of the eighth embodiment, it is possible to obtain the same operational effects as those obtained by the photodetector 1 of the first embodiment.

[0132] 25 and 26, the transfer transistor TR in the photodetector 1 has a multi-gate electrode structure. Since the photodetector 1 has a multi-gate electrode structure, the transfer path width (channel width) of the transfer transistor TR can be increased, thereby improving the transfer efficiency.

[0133] 9. Ninth Embodiment A photodetector 1 according to a ninth embodiment of the present disclosure will be described with reference to FIG.

[0134] 27 shows an example of a planar configuration of the pixels 10 of the photodetection device 1. In the photodetection device 1 according to the ninth embodiment, some or all of the pixels 10 in the pixel region 100 (see FIG. 1 or 2 ) are configured as phase difference detection pixels. One pixel 10 is configured by a first pixel 10A and a second pixel 10B arranged adjacent to each other in the direction of the arrow X.

[0135] In a plan view, the first pixel 10A is formed in a rectangular shape with its short side in the direction of the arrow X and its long side in the direction of the arrow Y. A pixel isolation region 31 is disposed around the first pixel 10A. Similarly, the second pixel 10B is formed in a rectangular shape with its short side in the direction of the arrow X and its long side in the direction of the arrow Y. A pixel isolation region 31 is disposed around the second pixel 10B. The second pixel 10B is formed in a line-symmetrical shape with respect to the first pixel 10A, with a center line CL, shown for convenience, extending between the first pixel 10A and the second pixel 10B in the direction of the arrow Y as the center.

[0136] The first pixel 10A includes a photoelectric conversion element PD and a transfer transistor TR. The photoelectric conversion element PD and the transfer transistor TR have the same structures as the photoelectric conversion element PD and the transfer transistor TR of the photodetector 1 according to the first embodiment. The second pixel 10B also includes a photoelectric conversion element PD and a transfer transistor TR, similar to the first pixel 10A.

[0137] The components of the ninth embodiment other than those described above are the same or substantially the same as the components of the photodetector 1 according to the first embodiment, and therefore a duplicated description will be omitted.

[0138] [Operational Effects] According to the photodetector 1 of the ninth embodiment, it is possible to obtain the same operational effects as those obtained by the photodetector 1 of the first embodiment.

[0139] 27 , in the photodetector 1, the pixel 10 includes a first pixel 10A and a second pixel 10B that constitute a phase difference detection pixel. In the photodetector 1 configured in this manner, phase difference information can be obtained from the photodetection information (image information) of each of the first pixel 10A and the second pixel 10B that serve as phase difference detection pixels, and therefore autofocus can be realized.

[0140] 10. Tenth Embodiment A photodetector 1 according to a tenth embodiment of the present disclosure will be described with reference to FIGS.

[0141] [Device Configuration of Photodetector 1] Fig. 28 shows an example of the planar configuration of a pixel 10 of the photodetector 1. Fig. 29 shows an example of the cross-sectional configuration of a pixel 10 of the photodetector 1. In the photodetector 1 according to the tenth embodiment, the trench lower portion 4A of the trench 4 in which the transfer transistor TR is formed is formed in an inverted pyramid shape with the apex on the surface 30A side. The extension surface of at least one sidewall formed in the inverted isosceles triangle shape of the trench lower portion 4A reaches the floating diffusion FD. The planar shape of the trench upper portion 4B is formed in a square shape.

[0142] In the tenth embodiment, the surface 30B of the semiconductor substrate 30 is formed in a (100) crystal plane. The pyramidal surfaces that form the sidewalls of the trench lower portion 4A are formed as (111) crystal planes of the semiconductor substrate 30. The (111) crystal planes have an inclination angle of, for example, 54 degrees or more and 56 degrees or less with respect to the (100) crystal plane. The outline of the bottom surface of the inverted pyramidal shape of the trench lower portion 4A is formed within the range of the thickness t2 of the sidewall insulator 7 in a plan view. In other words, the opening shape of the trench lower portion 4A on the surface 30B side is formed within the range of the thickness t2 of the sidewall insulator 7.

[0143] The gate electrode 6 of the transfer transistor TR is buried in the trench lower portion 4A with a gate insulating film 5 interposed therebetween. Since the trench lower portion 4A is formed in an inverted pyramid shape, the gate electrode 6 is also formed in an inverted pyramid shape. In other words, the gate electrode 6 is formed in an inverted pyramid shape.

[0144] 30 to 39 show an example of cross sections illustrating each step in the method for manufacturing the photodetector 1. Similar to the method for manufacturing the photodetector 1 according to the first embodiment, the method for manufacturing the photodetector 1 according to the tenth embodiment is mainly a method for manufacturing the transfer transistor TR of the pixel 10. The method for manufacturing the photodetector 1 is as follows.

[0145] First, a semiconductor substrate 30 is prepared (see FIG. 30). As in the first manufacturing method, this semiconductor substrate 30 is in the state of a semiconductor wafer before the dicing process, and has pixel isolation regions 31 and photoelectric conversion elements PD (see FIG. 5), not shown, formed thereon. Furthermore, a surface 30B of the semiconductor substrate 30 has a (100) crystal plane.

[0146] 6A and 6B of the first manufacturing method, a mask 310 is formed on the surface 30B of the semiconductor substrate 30 as shown in Fig. 30. Subsequently, similar to the steps shown in Fig. 8A and 8B of the first manufacturing method, an upper portion 4B of the trench is formed from the surface 30B toward the surface 30A of the semiconductor substrate 30 as shown in Fig. 31. Anisotropic etching, for example, is used to form the upper portion 4B of the trench.

[0147] 9A and 9B of the first manufacturing method, an insulator 7S is formed on the mask 310, including the sidewalls and bottom surface of the upper portion 4B of the trench, as shown in FIG. 32. The insulator 7S is formed by, for example, a CVD method. The insulator 7S may be made of, for example, SiO ２ is used.

[0148] An etch-back process is performed on the entire surface 30B side of the semiconductor substrate 30 to remove the insulator 7S. For example, anisotropic etching is used for the etch-back process. As a result, as in the steps shown in FIGS. 10A and 10B of the first manufacturing method, sidewall insulators 7 are formed from the insulator 7S on the sidewalls of the trench upper portions 4B, as shown in FIG. 33. The sidewall insulators 7 are formed on the sidewalls of the trench upper portions 4B in a self-aligned manner with the trench upper portions 4B. Thereafter, as shown in FIG. 34, the mask 310 is removed.

[0149] 35, a mask 315 is embedded in the upper portion 4B of the trench with a sidewall insulator 7 therebetween. The mask 315 is made of a photoresist formed by, for example, photolithography and etching.

[0150] 36, a mask 316 is formed on the surface 30B of the semiconductor substrate 30 except for the trench upper portion 4B. The mask 316 is made of, for example, SiN, which has an etching selectivity with respect to the sidewall insulator 7 and the mask 315.

[0151] 37 , the mask 316 and the sidewall insulator 7 are used as a mask to further dig down the semiconductor substrate 30 from the bottom surface of the trench upper portion 4B, thereby forming the trench lower portion 4A. For example, isotropic etching is used to form the trench lower portion 4A. For example, a tetramethylammonium hydroxide aqueous solution (TMAH) is used as the isotropic etching. As a result, the trench lower portion 4A is formed into an inverted pyramidal shape with the (111) crystal plane of the semiconductor substrate 30 as the pyramidal surface.

[0152] Similar to the steps shown in FIGS. 14A, 14B, 15A, and 15B of the first manufacturing method, as shown in FIG. 38, after a gate insulating film 5 is formed on the side wall of the trench lower portion 4A, a gate electrode 6 is formed in the trench lower portion 4A, and an electrode 60 is formed in the trench upper portion 4B.

[0153] 4 and 5, the floating diffusion FD is formed, completing the transfer transistor TR. In the method for manufacturing the photodetector 1 according to the tenth embodiment, the floating diffusion FD is formed along the sidewall insulator 7 and is formed in self-alignment with the sidewall insulator 7 (or the upper portion 4B of the trench).

[0154] When the manufacturing process including the series of manufacturing steps is completed, the photodetector 1 according to the tenth embodiment is completed.

[0155] The components of the tenth embodiment other than those described above are the same or substantially the same as the components of the photodetector 1 according to the first embodiment, and therefore a duplicated description will be omitted.

[0156] [Operational Effects] According to the photodetector 1 of the tenth embodiment, it is possible to obtain the same operational effects as those obtained by the photodetector 1 of the first embodiment.

[0157] Furthermore, in the photodetector 1, as shown in FIGS. 28 and 29 , the trench lower portion 4A of the trench 4 in which the transfer transistor TR is formed is formed in an inverted pyramidal shape with the apex on the surface 30A side. The gate electrode 6 of the transfer transistor TR is embedded in the trench lower portion 4A with a gate insulating film 5 interposed between the sidewalls of the trench lower portion 4A. The gate electrode 6 is also formed in an inverted pyramidal shape, similar to the inverted pyramidal shape of the trench lower portion 4A. In the photodetector 1 configured in this manner, at least the sidewalls of the trench lower portion 4A corresponding to the channel formation region 30c are formed to have flat surfaces. For example, if the gate insulating film 5 is formed on the flat sidewalls by thermal oxidation, variations in the thickness of the gate insulating film 5 can be effectively suppressed or prevented. On the other hand, if a curved surface is formed on the sidewall of the trench lower portion 4A by, for example, an etching process, variations in the thickness of the gate insulating film 5 occur depending on the crystal plane of the semiconductor substrate 30. Since variations in the thickness of the gate insulating film 5 can be effectively suppressed or prevented, the voltage-current characteristics of the transfer transistor TR can be stabilized and the characteristics of the transfer transistor TR can be improved.

[0158] 28 and 29, in the photodetector 1, the semiconductor substrate 30 is a single-crystal silicon substrate with the surface 30B being a (100) crystal plane. The trench lower portion 4A is formed in an inverted quadrangular pyramid shape with four pyramidal faces being (111) crystal planes. In the photodetector 1 configured in this manner, the sidewalls of the trench lower portion 4A can be formed into flat pyramidal faces. This makes it possible to more effectively suppress or prevent variations in the film thickness of the gate insulating film 5, thereby further improving the characteristics of the transfer transistor TR.

[0159] 28 and 29 , in the photodetector 1, the outline of the bottom surface of the inverted pyramid shape of the trench lower portion 4A is formed within the range of the thickness of the sidewall insulator 7 in plan view. Therefore, the inverted pyramid shape of the trench lower portion 4A can be reliably formed.

[0160] 11. Eleventh Embodiment A photodetector 1 according to an eleventh embodiment of the present disclosure will be described with reference to FIGS. 40 and 41. FIG.

[0161] [Device Configuration of Photodetector 1] Fig. 40 shows an example of the planar configuration of a pixel 10 of the photodetector 1. Fig. 41 shows an example of the cross-sectional configuration of a pixel 10 of the photodetector 1. In the photodetector 1 according to the eleventh embodiment, a pixel isolation region 31 is arranged in contact with the sidewall insulator 7 in a region other than the charge transfer surface of the transfer transistor TR. In other words, the pixel isolation region 31 is arranged in contact with the sidewall insulator 7 in a region other than the region in which the floating diffusion FD or the p-type semiconductor region 304 is arranged.

[0162] The components of the eleventh embodiment other than those described above are the same or substantially the same as the components of the photodetector 1 according to the tenth embodiment, and therefore a duplicated description will be omitted.

[0163] [Operational Effects] According to the photodetector 1 of the eleventh embodiment, it is possible to obtain the same operational effects as those obtained by the photodetector 1 of the tenth embodiment.

[0164] 12. Twelfth Embodiment A photodetector 1 according to a twelfth embodiment of the present disclosure will be described with reference to FIG.

[0165] 42 shows an example of a cross-sectional configuration of a pixel 10 of the photodetector 1. In the photodetector 1 according to the twelfth embodiment, the outline of the bottom surface of the inverted pyramid shape of the groove lower portion 4A is smaller than the opening shape of the groove upper portion 4B on the surface 30A side.

[0166] The components of the twelfth embodiment other than those described above are the same or substantially the same as the components of the photodetector 1 according to the tenth embodiment, and therefore a duplicated description will be omitted.

[0167] [Operational Effects] According to the photodetector 1 of the twelfth embodiment, it is possible to obtain the same operational effects as those obtained by the photodetector 1 of the tenth embodiment.

[0168] 13. Thirteenth Embodiment A photodetector 1 according to a thirteenth embodiment of the present disclosure will be described with reference to FIGS.

[0169] [Device Configuration of Photodetector 1] Fig. 43 shows an example of the planar configuration of a pixel 10 of the photodetector 1. Figs. 44 and 45 show an example of the cross-sectional configuration of a pixel 10 of the photodetector 1. In the photodetector 1 according to the thirteenth embodiment, the transfer transistor TR in the photodetector 1 according to the eighth embodiment is constructed to have a multi-gate electrode structure.

[0170] In the formation region of the transfer transistor TR, a first groove 41, a second groove 42, and a third groove 43 are arranged on the surface 30B side of the semiconductor substrate 30. The first groove 41 is arranged from the surface 30B toward the surface 30A of the semiconductor substrate 30. As described above, the first groove 41 has a groove lower portion 4A and a groove upper portion 4B. The second groove 42 is spaced apart from the first groove 41 on the surface 30B and arranged from the surface 30B toward the surface 30A of the semiconductor substrate 30. Like the first groove 41, the second groove 42 has a groove lower portion 4A and a groove upper portion 4B. The third groove 43 is arranged from the surface 30B toward the surface 30A of the semiconductor substrate 30, has a depth shallower than the first groove 41 and the second groove 42, and communicates with the first groove 41 and the second groove 42. In the thirteenth embodiment, the third groove 43 is formed to have the same structure as the groove upper portions 4B of the first groove 41 and the second groove 42. The depth of the third groove 43 is equal to the depth of the sidewall insulator 7.

[0171] The gate electrode 6 of the transfer transistor TR includes a first gate electrode 601, a second gate electrode 602, and a third gate electrode 603. The first gate electrode 601 is disposed in the trench lower portion 4A of the first trench 41 and is embedded in the sidewalls and bottom surface of the trench lower portion 4A with a gate insulating film (first gate insulating film) 5 interposed therebetween. An electrode 60 is electrically connected to the first gate electrode 601. The second gate electrode 602 is disposed in the trench lower portion 4A of the second trench 42 and is embedded in the sidewalls and bottom surface of the trench lower portion 4A with a gate insulating film (second gate insulating film) 5 interposed therebetween. An electrode 60 is electrically connected to the second gate electrode 602. The third gate electrode 603 is embedded in the bottom of the third trench 43 with a gate insulating film (third gate insulating film) 5 interposed therebetween. The third gate electrode 603 is electrically connected to the first gate electrode 601 and the second gate electrode 602 through the electrode 60.

[0172] The third gate electrode 603 and the electrode 60 of the gate electrode 6 are not limited to single-layer polycrystalline silicon. For example, the third gate electrode 603 and the electrode 60 may each be formed of a composite film in which a high-melting-point metal or a high-melting-point metal silicide is laminated on polycrystalline silicon. Furthermore, a metal film such as a barrier metal may be formed on the surface portions of the third gate electrode 603 and the electrode 60.

[0173] 46 to 55 show an example of cross sections illustrating each step in the method for manufacturing the photodetector 1. Similar to the method for manufacturing the photodetector 1 according to the first embodiment, the method for manufacturing the photodetector 1 according to the thirteenth embodiment is mainly a method for manufacturing the transfer transistor TR of the pixel 10. The method for manufacturing the photodetector 1 is as follows.

[0174] First, a semiconductor substrate 30 is prepared (see FIG. 46). As in the first manufacturing method, this semiconductor substrate 30 is in the state of a semiconductor wafer before the dicing process, and is in a state in which pixel isolation regions 31 and photoelectric conversion elements PD (see FIG. 5), not shown, are formed.

[0175] 7A and 7B of the first manufacturing method, a mask 310 and a mask 314 are sequentially formed on the front surface 30B of the semiconductor substrate 30 as shown in Fig. 46. Subsequently, similar to the steps shown in Fig. 8A and 8B of the first manufacturing method, an upper portion 4B of the trench is formed from the front surface 30B toward the front surface 30A of the semiconductor substrate 30 as shown in Fig. 47. Anisotropic etching, for example, is used to form the upper portion 4B of the trench.

[0176] 9A and 9B of the first manufacturing method, an insulator 7S is formed on the mask 310, including the sidewalls and bottom surface of the upper portion 4B of the trench, as shown in FIG. 48. The insulator 7S is formed by, for example, a CVD method. The insulator 7S may be made of, for example, SiO ２ is used.

[0177] An etch-back process is performed on the insulator 7S over the entire surface 30B of the semiconductor substrate 30. For example, anisotropic etching is used for the etch-back process. As a result, as in the steps shown in FIGS. 10A and 10B of the first manufacturing method, sidewall insulators 7 are formed from the insulator 7S on the sidewalls of the trench upper portions 4B, as shown in FIG. 49. The sidewall insulators 7 are formed on the sidewalls of the trench upper portions 4B in a self-aligned manner with the trench upper portions 4B.

[0178] 50, a mask 317 is formed. The mask 317 has openings 317H in the regions where the first grooves 41 and the second grooves 42 are to be formed. The mask 317 is made of, for example, a photoresist formed by photolithography and etching.

[0179] Using the mask 317 and the sidewall insulator 7 as a mask, the semiconductor substrate 30 is dug further from the bottom surface of the trench upper portion 4B to form the trench lower portion 4A (see FIG. 51). To form the trench lower portion 4A, for example, anisotropic etching is used.

[0180] 51, the mask 317 is peeled off, thereby completing the first groove 41 having a groove lower portion 4A and a groove upper portion 4B, the second groove 42 having a groove lower portion 4A and a groove upper portion 4B, and the third groove 43 having a groove upper portion 4B.

[0181] 12A and 12B of the first manufacturing method, as shown in Fig. 52, a gate insulating film 5 is formed on the sidewalls and bottom surface of the trench lower portions 4A of the first trench 41 and the second trench 42. Furthermore, a gate insulating film 5 is formed on the bottom surface of the third trench 43. The gate insulating film 5 is formed of, for example, SiO ２ It is formed by

[0182] Similar to the steps shown in FIGS. 14A and 14B of the first manufacturing method, a gate electrode material 600 is formed on the mask 310, including in the first groove 41, the second groove 42, and the third groove 43, as shown in FIG. 53.

[0183] 54 , the gate electrode material 600 is patterned, and a gate electrode 6 is formed from the gate electrode material 600. That is, the gate electrode 6 is formed by the first gate electrode 601 and the electrode 60 buried in the first groove 41, the second gate electrode 602 and the electrode 60 buried in the second groove 42, and the third gate electrode 603 buried in the third groove 43.

[0184] 55, the surface of the gate electrode 6 is planarized and the mask 310 is removed. For example, a CMP (Chemical Mechanical Polisher) method is used for this planarization.

[0185] Thereafter, as shown in FIGS. 4 and 5, the floating diffusion FD is formed, and the transfer transistor TR is completed.

[0186] When the manufacturing process including this series of manufacturing steps is completed, the photodetector 1 according to the thirteenth embodiment is completed. Note that, since the components of the thirteenth embodiment other than those described above are the same or substantially the same as the components of the photodetector 1 according to the eighth embodiment, redundant explanations will be omitted.

[0187] In the process shown in FIG. 50 described above, if there is an area where part of the mask 317 covers the sidewall insulator 7, as shown in FIG. 56A, when the trench lower portion 4A is formed, a step is formed at the boundary between the trench lower portion 4A and the trench upper portion 4B, as shown in FIG. 56B.

[0188] [Operational Effects] According to the photodetector 1 of the thirteenth embodiment, it is possible to obtain the same operational effects as those obtained by the photodetector 1 of the eighth embodiment.

[0189] 43 to 45, the photodetector 1 includes a first groove 41 and a second groove 42, and further includes a third groove 43. The third groove 43 is disposed from the surface 30B toward the surface 30A of the semiconductor substrate 30, has a depth shallower than the first groove 41 and the second groove 42, and connects the first groove 41 and the second groove 42. The gate electrode 6 of the transfer transistor TR includes a first gate electrode 601 and a second gate electrode 602, and further includes a third gate electrode 603. The third gate electrode 603 is buried in the bottom of the third groove 43 with a gate insulating film (third gate insulating film) 5 interposed therebetween, and electrically connects the first gate electrode 601 and the second gate electrode 602.

[0190] In the photodetector 1 configured in this manner, the transfer transistor TR is provided with the third gate electrode 603, so that a channel formation region can be formed in the bulk from the surface 30B to the surface 30A of the semiconductor substrate 30. In other words, the third gate electrode 603 can transfer (modulate) charges in the bulk, which can further improve the transfer efficiency of the transfer transistor TR. In other words, the characteristics of the transfer transistor TR can be improved.

[0191] 44 and 45 , in the photodetector 1, the depth of the third groove 43 is the same as the depth of the sidewall insulator 7 in the same direction. In other words, the third groove 43 has the same structure as the groove upper portions 4B of the first groove 41 and the second groove 42, and is formed by the same manufacturing process. In the photodetector 1 configured in this manner, the characteristics of the transfer transistor TR can be improved with a simple structure or a simple manufacturing method.

[0192] 56C and 56D, a method for manufacturing a photodetector 1 according to a modification of the thirteenth embodiment will be described. 56C and 56D show an example of cross sections illustrating steps in the method for manufacturing the photodetector 1.

[0193] In the manufacturing method of the photodetector 1 according to the modification of the thirteenth embodiment, a mask 318 is formed as shown in FIG. 56C , similar to the process shown in FIG. 50 of the manufacturing method of the photodetector 1 according to the thirteenth embodiment. The mask 318 is formed after the groove upper portion 4B is formed and covers the formation region of the third groove 43. The mask 318, the mask 310, and the sidewall insulator 7 are used as masks in subsequent processes to form the groove lower portions 4A of the first groove 41 and the second groove 42 (see FIG. 56D ). At this time, the mask 318 is used to form the third groove 43 as well as the first groove 41 and the second groove 42. For the mask 318, a photoresist formed by photolithography and etching techniques, for example, is used. As shown in FIG. 56C , the mask 318 is peeled off. Thereafter, the process shown in FIG. 52 and subsequent processes are performed to complete the photodetector 1 according to the modification.

[0194] 56C and 56D , the manufacturing method of the photodetector 1 uses a mask 318, a mask 310, and a sidewall insulator 7 to form the first groove 41 and the second groove 42. The boundary portions between the sidewall insulator 7 and each of the first groove 41 and the second groove 42 are formed to have a smooth cross-sectional shape without any steps, because the first groove 41 and the second groove 42 are formed by self-alignment with the sidewall insulator 7.

[0195] [Operational Effects] According to the photodetector 1 according to the modified example of the thirteenth embodiment, it is possible to obtain the same operational effects as those obtained by the photodetector 1 according to the thirteenth embodiment.

[0196] 14. Fourteenth Embodiment A photodetector 1 according to a fourteenth embodiment of the present disclosure will be described with reference to FIGS.

[0197] [Device Configuration of Photodetection Device 1] Fig. 57 shows an example of a planar configuration of a pixel 10 of the photodetection device 1. Figs. 58 and 59 show examples of a cross-sectional configuration of a pixel 10 of the photodetection device 1. In the photodetection device 1 according to the fourteenth embodiment, similar to the photodetection device 1 according to the thirteenth embodiment, the gate electrode 6 of the transfer transistor TR includes a first gate electrode 601, a second gate electrode 602, and a third gate electrode 603. Here, similar to the photodetection device 1 according to the above-described ninth embodiment, the pixel 10 is configured by a first pixel 10A and a second pixel 10B that constitute a phase difference detection pixel.

[0198] The first gate electrode 601 of the gate electrode 6 is formed in a rectangular shape with its longitudinal direction aligned with the arrow Y direction in a plan view. The second gate electrode 602 is spaced apart from the first gate electrode 601 in the arrow X direction and is disposed in a position that sandwiches the floating diffusion FD therebetween. Like the first gate electrode 601, the second gate electrode 602 is formed in a rectangular shape with its longitudinal direction aligned with the arrow Y direction in a plan view. The third gate electrode 603 is disposed in a position that connects one end of the first gate electrode 601 opposite to the arrow Y direction with one end of the second gate electrode 602 opposite to the arrow Y direction.

[0199] In other words, the first gate electrode 601, the second gate electrode 602, and the third gate electrode 603 are formed in a C-shape surrounding the floating diffusion FD in a plan view.

[0200] The components of the fourteenth embodiment other than those described above are the same or substantially the same as the components of the photodetector 1 according to the thirteenth embodiment, and therefore a duplicated description will be omitted.

[0201] [Operational Effects] According to the photodetector 1 of the modified example of the fourteenth embodiment, it is possible to obtain the same operational effects as those obtained by the photodetector 1 of the thirteenth embodiment.

[0202] 15. Fifteenth embodiment A photodetector 1 according to a fifteenth embodiment of the present disclosure will be described with reference to Fig. 60. Fig. 60 shows an example of a block configuration of an electronic device 700.

[0203] 60 , electronic device 700 includes photodetector 1 according to any one of the first to fourteenth embodiments as photodetector 70. Photodetector 70 is applied to various electronic devices, such as imaging systems such as digital still cameras and digital video cameras, mobile phones with imaging functions, and other devices with imaging functions.

[0204] The electronic device 700 includes an optical system 71, a photodetector 70, and a DSP (Digital Signal Processor) 72. In the electronic device 700, the DSP 72, a display device 73, an operation system 74, a memory 75, a recording device 76, and a power supply system 77 are connected via a bus 78. The electronic device 700 is capable of capturing still images and moving images.

[0205] The optical system 71 includes one or more lenses. The optical system 71 guides image light (incident light) from a subject to the photodetector 70, and forms an image on the light-receiving surface (sensor portion) of the photodetector 70.

[0206] The photodetector 70 uses, for example, the photodetector 1 according to any one of the first to fourteenth embodiments. In the photodetector 70, electrons are accumulated for a certain period of time in accordance with an image formed on a light-receiving surface through an optical system 71. Then, a signal in accordance with the electrons accumulated in the photodetector 70 is supplied to a DSP 72.

[0207] The DSP 72 performs various signal processing on the signal from the photodetector 70 to acquire an image, and temporarily stores the image data in the memory 75. The image data stored in the memory 75 is recorded in the recording device 76. The image data stored in the memory 75 is also supplied to the display device 73, which displays the image. The operation system 74 accepts various operations by the user and supplies operation signals to each block of the electronic device 700. The power supply system 77 supplies the power necessary to drive each block of the electronic device 700.

[0208] 60, an electronic device 700 according to the fifteenth embodiment includes a photodetector 70. As described in the photodetector 1 according to any one of the first to twelfth embodiments, the photodetector 70 is formed to include pixels 10 as phase difference detection pixels over the entire surface of the pixel region 100, for example. This allows the phase difference detection accuracy of the electronic device 700 to be improved.

[0209] 16. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0210] FIG. 61 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology of the present disclosure can be applied.

[0211] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 61 , the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0212] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0213] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0214] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0215] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0216] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0217] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0218] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0219] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12030 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0220] The audio / video output unit 12052 transmits at least one output signal of audio and / or video to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 61, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0221] FIG. 62 is a diagram showing an example of the installation position of the imaging unit 12031.

[0222] In FIG. 62, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0223] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0224] 62 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0225] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0226] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation.

[0227] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0228] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0229] The above describes an example of a vehicle control system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to the imaging unit 12031 among the components described above. By applying the technology according to the present disclosure to the imaging unit 12031, it is possible to realize an imaging unit 12031 that can improve the characteristics of the transfer transistor.

[0230] 17. Application Example to Endoscopic Surgery System The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be applied to an endoscopic surgery system.

[0231] FIG. 63 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0232] Figure 63 shows an operator (doctor) 11131 performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 is composed of an endoscope 11100, other surgical tools 11110 such as an insufflation tube 11111 and an energy treatment tool 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.

[0233] The endoscope 11100 is composed of a lens barrel 11101, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 11132, and a camera head 11102 connected to the base end of the lens barrel 11101. In the example shown, the endoscope 11100 is configured as a so-called rigid scope having a rigid lens barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible scope having a flexible lens barrel.

[0234] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 11101, and is irradiated via the objective lens toward an object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0235] An optical system and an image sensor are provided inside the camera head 11102, and light reflected from the object of observation (observation light) is collected onto the image sensor by the optical system. The observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The image signal is sent to a camera control unit (CCU) 11201 as RAW data.

[0236] The CCU 11201 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and comprehensively controls the operations of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102 and performs various types of image processing on the image signal, such as development processing (demosaic processing), to display an image based on the image signal.

[0237] Under the control of the CCU 11201, the display device 11202 displays an image based on an image signal that has been subjected to image processing by the CCU 11201.

[0238] The light source device 11203 is composed of a light source such as an LED (light emitting diode), and supplies irradiation light to the endoscope 11100 when photographing the surgical site, etc.

[0239] The input device 11204 is an input interface for the endoscopic surgery system 11000. A user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs an instruction to change the imaging conditions (type of irradiation light, magnification, focal length, etc.) of the endoscope 11100.

[0240] The treatment tool control device 11205 controls the driving of the energy treatment tool 11112 for cauterizing tissue, incising, sealing blood vessels, etc. The insufflation device 11206 inflates the body cavity of the patient 11132 through the insufflation tube 11111 in order to ensure a clear field of view for the endoscope 11100 and a working space for the surgeon. The recorder 11207 is a device capable of recording various types of information related to the surgery. The printer 11208 is a device capable of printing various types of information related to the surgery in various formats such as text, images, or graphs.

[0241] The light source device 11203, which supplies illumination light to the endoscope 11100 when photographing the surgical site, can be configured from a white light source, such as an LED, a laser light source, or a combination of these. When the white light source is configured from a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, allowing the light source device 11203 to adjust the white balance of the captured image. In this case, it is also possible to time-share images corresponding to each RGB by irradiating the object of observation with laser light from each RGB laser light source and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, color images can be obtained without providing a color filter to the image sensor.

[0242] Furthermore, the light source device 11203 may be controlled to change the intensity of light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity to acquire images in a time-division manner and combining the images, it is possible to generate an image with a high dynamic range that is free from so-called blocked-up shadows and blown-out highlights.

[0243] The light source device 11203 may also be configured to supply light in a predetermined wavelength band corresponding to special light observation. Special light observation, for example, utilizes the wavelength dependence of light absorption in body tissues to irradiate light with a narrower band than the light irradiated during normal observation (i.e., white light), thereby capturing high-contrast images of specific tissues, such as blood vessels on the surface of mucous membranes, known as narrow-band imaging. Alternatively, special light observation may involve fluorescence observation, in which images are obtained using fluorescence generated by irradiating excitation light. Fluorescence observation may involve irradiating excitation light onto body tissues and observing the fluorescence from the tissue (autofluorescence observation), or by locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the tissue with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 11203 may be configured to supply narrow-band light and / or excitation light corresponding to such special light observation.

[0244] Figure 64 is a block diagram showing an example of the functional configuration of the camera head 11102 and CCU 11201 shown in Figure 63.

[0245] The camera head 11102 has a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 has a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other via a transmission cable 11400 so that they can communicate with each other.

[0246] The lens unit 11401 is an optical system provided at the connection portion with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses including a zoom lens and a focus lens.

[0247] The imaging unit 11402 may include one imaging element (a so-called single-chip type) or multiple imaging elements (a so-called multi-chip type). When the imaging unit 11402 is configured as a multi-chip type, for example, each imaging element may generate an image signal corresponding to each of RGB, and a color image may be obtained by combining these signals. Alternatively, the imaging unit 11402 may be configured to have a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to a 3D (dimensional) display. The 3D display allows the surgeon 11131 to more accurately grasp the depth of the biological tissue at the surgical site. Note that when the imaging unit 11402 is configured as a multi-chip type, multiple lens units 11401 may be provided corresponding to each imaging element.

[0248] Furthermore, the imaging unit 11402 does not necessarily have to be provided in the camera head 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101, immediately after the objective lens.

[0249] The driving unit 11403 is configured by an actuator, and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera head control unit 11405. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted appropriately.

[0250] The communication unit 11404 is configured by a communication device for transmitting and receiving various types of information to and from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0251] Furthermore, the communication unit 11404 receives a control signal for controlling the driving of the camera head 11102 from the CCU 11201 and supplies the control signal to the camera head control unit 11405. The control signal includes information on the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of imaging, and / or information specifying the magnification and focus of the captured image.

[0252] The image capturing conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by the user, or may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 is equipped with a so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.

[0253] The camera head control unit 11405 controls the driving of the camera head 11102 based on a control signal received from the CCU 11201 via the communication unit 11404 .

[0254] The communication unit 11411 is configured by a communication device for transmitting and receiving various information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.

[0255] Furthermore, the communication unit 11411 transmits to the camera head 11102 a control signal for controlling the driving of the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0256] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data transmitted from the camera head 11102 .

[0257] The control unit 11413 performs various controls related to the imaging of the surgical site, etc. by the endoscope 11100 and the display of the captured image obtained by imaging the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.

[0258] Furthermore, the control unit 11413 displays the captured image showing the surgical site, etc., on the display device 11202 based on the image signal subjected to image processing by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical tools such as forceps, specific biological parts, bleeding, mist generated when using the energy treatment tool 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When displaying the captured image on the display device 11202, the control unit 11413 may use the recognition results to superimpose various surgical support information on the image of the surgical site. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery reliably.

[0259] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable for electrical signal communication, an optical fiber for optical communication, or a composite cable of these.

[0260] In the illustrated example, communication is performed wired using a transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may also be performed wirelessly.

[0261] The above describes an example of an endoscopic surgery system to which the technology according to the present disclosure can be applied. Of the above-described configurations, the technology according to the present disclosure can be applied to the imaging unit 11402 of the camera head 11102. By applying the technology according to the present disclosure to the imaging unit 11402, it is possible to realize an imaging unit 11402 that can improve the characteristics of the transfer transistor.

[0262] Although an endoscopic surgery system has been described as an example here, the technology disclosed herein may also be applied to other systems, such as a microsurgery system.

[0263] 18. Other Embodiments The present technology is not limited to the above-described embodiments and may be modified in various ways without departing from the spirit of the present technology. For example, among the photodetection devices according to the first to fourteenth embodiments, photodetection devices according to two or more of the above-described embodiments may be combined.

[0264] A semiconductor device according to a first embodiment of the present disclosure includes: a trench extending from a first surface of a substrate toward a second surface opposite the first surface; an insulated gate field effect transistor disposed in a lower portion of the trench and having a gate electrode embedded on a sidewall of the trench with a gate insulating film interposed therebetween; a sidewall insulator disposed in an upper portion of the trench on the sidewall of the trench and having a thickness greater in the same direction than that of the gate insulating film; and an electrode embedded in an upper portion of the trench with the sidewall insulator interposed therebetween and electrically connected to the gate electrode. Since the semiconductor device according to the first embodiment includes the sidewall insulator, it is possible to reduce the capacitance value of parasitic capacitance and improve the characteristics of the insulated gate field effect transistor.

[0265] In a semiconductor device according to a second embodiment of the present disclosure, the lower portion of the trench in the semiconductor device according to the first embodiment is formed in an inverted pyramidal shape with the apex on the second surface side, and the gate electrode is also formed in an inverted pyramidal shape buried in the lower portion of the trench with a gate insulating film interposed therebetween. The semiconductor device according to the second embodiment can effectively suppress variations in the gate insulating film, thereby improving the characteristics of the insulated gate field effect transistor.

[0266] A semiconductor device according to a third embodiment of the present disclosure includes: a first trench disposed from a first surface of a substrate toward a second surface opposite to the first surface; a second trench in the first surface, spaced apart from the first trench, disposed from the first surface toward the second surface of the substrate; a third trench disposed from the first surface toward the second surface, having a depth shallower than the first and second trenches, and connecting the first and second trenches; an insulated gate field effect transistor having: a first gate electrode disposed in a lower portion of the first trench and embedded in a sidewall of the first trench with a first gate insulating film interposed therebetween; a second gate electrode disposed in a lower portion of the second trench and embedded in a sidewall of the second trench with a second gate insulating film interposed therebetween; and a third gate electrode embedded in a bottom of the third trench with a third gate insulating film interposed therebetween, electrically connecting the first gate electrode and the second gate electrode; The semiconductor device according to the third embodiment includes: sidewall insulators disposed on the first trench sidewalls and the second trench sidewalls at upper portions of the first trench and the second trench, respectively, and having a thickness in the same direction greater than that of the first gate insulating film and the second gate insulating film; and electrodes embedded in the upper portions of the first trench and the second trench, respectively, with the sidewall insulators interposed therebetween, and electrically connected to the first gate electrode and the second gate electrode, respectively. According to the semiconductor device according to the third embodiment, a channel formation region can be formed in the bulk by the third gate electrode embedded in the third trench, thereby improving the characteristics of the insulated gate field effect transistor.

[0267] A photodetector according to a fourth embodiment of the present disclosure includes: a groove extending from a first surface of a substrate toward a second surface opposite the first surface; a transfer transistor disposed in a lower portion of the groove and having a gate electrode embedded on a sidewall of the groove with a gate insulating film interposed therebetween; a sidewall insulator disposed in an upper portion of the groove and on the sidewall of the groove with a thickness greater in the same direction than that of the gate insulating film; an electrode embedded in an upper portion of the groove with the sidewall insulator interposed and electrically connected to the gate electrode; a floating diffusion disposed on the first surface side of the substrate with the sidewall insulator interposed between the electrode and electrically connected to one end of the transfer transistor; and a photoelectric conversion element disposed in the substrate and electrically connected to the other end of the transfer transistor for converting light into electric charges. The photodetector according to the fourth embodiment includes the sidewall insulator, which reduces the capacitance value of parasitic capacitance and improves the characteristics of the transfer transistor.

[0268] a second groove in the first surface, the second groove being spaced apart from the first groove and extending from the first surface toward the second surface of the substrate; a third groove extending from the first surface toward the second surface, the third groove having a depth shallower than the first and second grooves and connecting the first and second grooves; a transfer transistor having a first gate electrode disposed in a lower portion of the first groove and embedded in a sidewall of the first groove with a first gate insulating film interposed therebetween, a second gate electrode disposed in a lower portion of the second groove and embedded in a sidewall of the second groove with a second gate insulating film interposed therebetween, and a third gate electrode embedded in a bottom portion of the third groove with a third gate insulating film interposed therebetween and electrically connecting the first gate electrode and the second gate electrode; a photodiode disposed in the first groove and a photodiode disposed in the second groove, the photodiode being electrically connected to the first gate electrode and the second gate electrode ...

[0269] <Configuration of the Present Technology> The present technology has the following configuration: According to the present technology having the following configuration, it is possible to improve the characteristics of a transistor in a semiconductor device or a photodetector.

[0270] (1-1: Claim 1) A semiconductor device comprising: a trench disposed from a first surface of a substrate toward a second surface opposite the first surface; an insulated gate field effect transistor disposed in a lower part of the trench and having a gate electrode buried on a sidewall of the trench with a gate insulating film interposed therebetween; a sidewall insulator disposed in an upper part of the trench on the sidewall of the trench and having a thickness greater in the same direction than a thickness of the gate insulating film; and an electrode buried in an upper part of the trench with the sidewall insulator interposed therebetween and electrically connected to the gate electrode. (1-2: Claim 2) The semiconductor device according to (1-1), wherein the insulated gate field effect transistor has a pair of main electrodes, and the sidewall insulator is disposed between one of the main electrodes disposed on the first surface side and the electrode. (1-3: Claim 3) The semiconductor device according to (1-2), wherein the electrode is extended to the first surface within a range of the thickness of the sidewall insulator disposed between one of the main electrodes and the electrode. (1-4: Claim 4) The semiconductor device according to (1-3), further comprising an isolation region surrounding the insulated gate field effect transistor for electrically isolating the insulated gate field effect transistor, and wherein the electrode is drawn to the isolation region in a region other than the sidewall insulator disposed between one of the main electrodes and the electrode. (1-5: Claim 5) The semiconductor device according to any one of (1-1) to (1-4), further comprising: a thickness of the sidewall insulator on the first surface side greater than that on the second surface side; and a cross-sectional shape of the sidewall insulator formed in a tapered shape. (1-6: Claim 6) The semiconductor device according to any one of (1-2) to (1-5), further comprising: a depth of the sidewall insulator from the first surface to the second surface side greater than a junction depth of one of the main electrodes. (1-7: Claim 7) The semiconductor device according to any one of (1-1) to (1-6), further comprising: a sidewall insulator formed in self-alignment with the groove.(1-8) The semiconductor device according to (1-1), wherein the trench comprises: a first trench; a second trench in the first surface spaced apart from the first trench; and a third trench having a depth shallower than the first trench and the second trench and communicating with the first trench and the second trench; and the gate electrode comprises: a first gate electrode disposed in a lower part of the first trench and embedded in a sidewall of the first trench with a first gate insulating film interposed therebetween; a second gate electrode disposed in a lower part of the second trench and embedded in a sidewall of the second trench with a second gate insulating film interposed therebetween; and a third gate electrode embedded in a bottom part of the third trench with a third gate insulating film interposed therebetween and electrically connecting the first gate electrode and the second gate electrode.

[0271] (2-1: Claim 8) The semiconductor device according to any one of (1-1) to (1-7), wherein the lower part of the trench is formed in an inverted pyramid shape having an apex on the second surface side, and the gate electrode is formed in an inverted pyramid shape buried in the lower part of the trench with the gate insulating film interposed therebetween. (2-2: Claim 9) The semiconductor device according to (2-1), wherein the substrate is a single crystal silicon substrate having the first surface as a (100) crystal plane, and the lower part of the trench is formed in an inverted square pyramid shape having four pyramidal faces as (111) crystal planes. (2-3: Claim 10) The semiconductor device according to (2-1) or (2-2), wherein the outline of the bottom surface of the inverted pyramid shape at the lower part of the trench is formed within a range of the thickness of the sidewall insulator when viewed from the first surface side to the second surface side.

[0272] (3-1: Claim 11) A semiconductor device comprising: a first trench disposed from a first surface of a substrate toward a second surface opposite to the first surface; a second trench in the first surface, spaced apart from the first trench, and disposed from the first surface toward the second surface of the substrate; a third trench disposed from the first surface toward the second surface, having a depth shallower than the first and second trenches, and connecting the first and second trenches; and an insulated gate field effect transistor having: a first gate electrode disposed in a lower part of the first trench and embedded in a sidewall of the first trench with a first gate insulating film interposed therebetween; a second gate electrode disposed in a lower part of the second trench and embedded in a sidewall of the second trench with a second gate insulating film interposed therebetween; and a third gate electrode embedded in a bottom of the third trench with a third gate insulating film interposed therebetween, electrically connecting the first gate electrode and the second gate electrode. (3-2: Claim 12) The semiconductor device according to (3-1), further comprising: sidewall insulators disposed on the first trench sidewalls and the second trench sidewalls at upper portions of the first trench and the second trench, respectively, and having a thickness in the same direction greater than that of the first gate insulating film and the second gate insulating film; and electrodes embedded in upper portions of the first trench and the second trench, respectively, with the sidewall insulators interposed therebetween, and electrically connected to the first gate electrode and the second gate electrode, respectively. (3-3: Claim 13) The semiconductor device according to (3-2), wherein the depth of the third trench is the same as the depth of the sidewall insulator in the same direction. (3-4) The semiconductor device according to any one of (3-1) to (3-3), wherein the first gate electrode, the second gate electrode, and the third gate electrode are formed in a C-shape when viewed from the first surface side to the second surface side.

[0273] (1-8: Claim 14) A photodetector comprising: a groove disposed from a first surface of a substrate toward a second surface opposite the first surface; a transfer transistor disposed in a lower part of the groove and having a gate electrode buried on a side wall of the groove with a gate insulating film interposed therebetween; a sidewall insulator disposed in an upper part of the groove on the side wall of the groove and having a thickness in the same direction greater than that of the gate insulating film; an electrode buried in an upper part of the groove with the sidewall insulator interposed therebetween and electrically connected to the gate electrode; a floating diffusion disposed on the first surface side of the substrate with the sidewall insulator interposed between the electrode and electrically connected to one end of the transfer transistor; and a photoelectric conversion element disposed in the substrate, electrically connected to the other end of the transfer transistor, and converting light into electric charges. (1-9: Claim 15) The photodetector according to (1-8), wherein the photoelectric conversion element is configured by a photodiode having an anode region and a cathode region, the transfer transistor has a pair of main electrodes, one of the main electrodes being configured by the floating diffusion, and the other of the main electrodes being configured by the cathode region. (1-10: Claim 16) The photodetector according to (1-9), wherein the electrode is extended to the first surface within a thickness range of the sidewall insulator disposed between the floating diffusion and the electrode. (1-11: Claim 17) The photodetector according to (1-10), wherein a pixel isolation region is provided around the photoelectric conversion element and the transfer transistor, electrically and optically isolating the photoelectric conversion element and the transfer transistor, and the electrode is extended to the pixel isolation region in a region other than the sidewall insulator disposed between the floating diffusion and the electrode. (1-12) The photodetector according to any one of (1-8) to (1-11), wherein the thickness of the sidewall insulator on the first surface side is greater than that on the second surface side, and the cross-sectional shape of the sidewall insulator is formed into a tapered shape.(1-13: Claim 18) The photodetector according to any one of (1-8) to (1-13), wherein the depth of the sidewall insulator from the first surface to the second surface is deeper than the junction depth of the floating diffusion. (1-14) The photodetector according to any one of (1-8) to (1-13), wherein the sidewall insulator is formed by self-alignment with the groove.

[0274] (2-4) The photodetector according to any one of (1-8) to (1-14), wherein the lower part of the trench is formed in an inverted pyramid shape having an apex on the second surface side, and the gate electrode is formed in an inverted pyramid shape buried in the lower part of the trench with the gate insulating film interposed therebetween. (2-5) The photodetector according to (2-4), wherein the substrate is a single-crystal silicon substrate having the first surface as a (100) crystal plane, and the lower part of the trench is formed in an inverted square pyramid shape with four pyramidal faces as (111) crystal planes. (2-6) The semiconductor device according to (2-4) or (2-5), wherein the outline of the bottom surface of the inverted pyramid shape at the lower part of the trench is formed within a range of the thickness of the sidewall insulator when viewed from the first surface side to the second surface side.

[0275] (3-4: Claim 19) A transfer transistor comprising: a first trench disposed from a first surface of a substrate toward a second surface opposite to the first surface; a second trench in the first surface, spaced apart from the first trench, and disposed from the first surface of the substrate toward the second surface; a third trench disposed from the first surface toward the second surface, having a depth shallower than the first and second trenches, and communicating with the first and second trenches; and a transfer transistor including: a first gate electrode disposed in a lower part of the first trench and embedded in a sidewall of the first trench with a first gate insulating film interposed therebetween; a second gate electrode disposed in a lower part of the second trench and embedded in a sidewall of the second trench with a second gate insulating film interposed therebetween; and a third gate electrode embedded in a bottom of the third trench with a third gate insulating film interposed therebetween, electrically connecting the first gate electrode and the second gate electrode. a sidewall insulator disposed on each of the first and second trench sidewalls at an upper portion of each of the first and second trenches, the sidewall insulator having a thickness in the same direction greater than that of each of the first and second gate insulating films; an electrode embedded in each of the first and second trenches with the sidewall insulator interposed therebetween and electrically connected to each of the first and second gate electrodes; a floating diffusion disposed on the first surface side of the substrate with the sidewall insulator interposed between the electrode and the electrode, and electrically connected to one end of the transfer transistor; and a photoelectric conversion element disposed in the substrate, electrically connected to the other end of the transfer transistor, and converting light into electric charges. (3-5: Claim 20) The photodetector according to (3-4), wherein the depth of the third trench is the same as the depth of the sidewall insulator in the same direction. (3-6) The photodetector according to (3-4) or (3-5), wherein the first gate electrode, the second gate electrode, and the third gate electrode are formed in a C-shape when viewed from the first surface side to the second surface side.

[0276] This application claims priority based on Japanese Patent Application No. 2023-123874, filed on July 28, 2023, in the Japan Patent Office, the entire contents of which are incorporated herein by reference.

[0277] Those skilled in the art will recognize that various modifications, combinations, subcombinations, and variations may occur depending on design requirements and other factors, and are intended to be within the scope of the appended claims and their equivalents.

Claims

1. A semiconductor device comprising: a trench disposed from a first surface of a substrate toward a second surface opposite to the first surface; an insulated gate field effect transistor disposed in a lower part of the trench and having a gate electrode embedded in a sidewall of the trench with a gate insulating film interposed therebetween; a sidewall insulator disposed in an upper part of the trench on the sidewall of the trench and having a thickness greater in the same direction than that of the gate insulating film; and an electrode buried in an upper part of the trench with the sidewall insulator interposed therebetween and electrically connected to the gate electrode.

2. The semiconductor device according to claim 1, wherein the insulated gate field effect transistor has a pair of main electrodes, and the sidewall insulator is disposed between one of the main electrodes disposed on the first surface side and the electrode.

3. The semiconductor device according to claim 2, wherein the electrode is extended onto the first surface within a range of the thickness of the sidewall insulator disposed between one of the main electrodes and the electrode.

4. The semiconductor device according to claim 3, further comprising an isolation region surrounding said insulated gate field effect transistor for electrically isolating said insulated gate field effect transistor, said electrode being extended to said isolation region in a region other than said sidewall insulator disposed between one of said main electrodes and said electrode.

5. The semiconductor device according to claim 1, wherein the thickness of the sidewall insulator on the first surface side is greater than the thickness of the sidewall insulator on the second surface side, and the cross-sectional shape of the sidewall insulator is formed into a tapered shape.

6. The semiconductor device according to claim 2, wherein a depth of said sidewall insulator from said first surface to said second surface is deeper than a junction depth of one of said main electrodes.

7. The semiconductor device according to claim 1, wherein said sidewall insulator is formed by self-alignment with said groove.

8. The semiconductor device according to claim 1, wherein a lower portion of the trench is formed into an inverted pyramid shape having an apex on the second surface side, and the gate electrode is formed into an inverted pyramid shape buried in the lower portion of the trench with the gate insulating film therebetween.

9. The semiconductor device according to claim 8, wherein the substrate is a single crystal silicon substrate having the first surface as a (100) crystal plane, and the lower portion of the groove is formed into an inverted square pyramid shape having four pyramidal faces as (111) crystal planes.

10. The semiconductor device according to claim 8, wherein the contour of the bottom surface of the inverted pyramid shape at the lower part of the trench is formed within the range of the thickness of the sidewall insulator when viewed from the first surface side to the second surface side.

11. A semiconductor device comprising: a first trench disposed from a first surface of a substrate toward a second surface opposite to the first surface; a second trench spaced from the first trench in the first surface and disposed from the first surface toward the second surface of the substrate; a third trench disposed from the first surface toward the second surface, having a depth shallower than the first and second trenches and connecting the first and second trenches; and an insulated gate field effect transistor having a first gate electrode disposed in a lower part of the first trench and embedded in a sidewall of the first trench with a first gate insulating film interposed therebetween, a second gate electrode disposed in a lower part of the second trench and embedded in a sidewall of the second trench with a second gate insulating film interposed therebetween, and a third gate electrode embedded in a bottom of the third trench with a third gate insulating film interposed therebetween and electrically connecting the first gate electrode and the second gate electrode.

12. The semiconductor device according to claim 11, further comprising: sidewall insulators disposed on the first trench sidewalls and the second trench sidewalls at the upper portions of the first trench and the second trench, the sidewall insulators having a thickness in the same direction greater than that of the first gate insulating film and the second gate insulating film; and electrodes embedded in the upper portions of the first trench and the second trench with the sidewall insulators interposed therebetween, the electrodes being electrically connected to the first gate electrode and the second gate electrode, respectively.

13. The semiconductor device according to claim 12, wherein the depth of said third trench is the same as the depth of said sidewall insulator in the same direction.

14. A photodetector comprising: a groove disposed from a first surface of a substrate toward a second surface opposite to the first surface; a transfer transistor disposed in a lower part of the groove and having a gate electrode embedded in a side wall of the groove with a gate insulating film interposed therebetween; a sidewall insulator disposed in an upper part of the groove on the side wall of the groove and having a thickness in the same direction greater than that of the gate insulating film; an electrode embedded in an upper part of the groove with the sidewall insulator interposed and electrically connected to the gate electrode; a floating diffusion disposed on the first surface side of the substrate with the sidewall insulator interposed between the electrode and electrically connected to one end of the transfer transistor; and a photoelectric conversion element disposed in the substrate, electrically connected to the other end of the transfer transistor, and converting light into an electric charge.

15. The photodetection device according to claim 14, wherein the photoelectric conversion element is a photodiode having an anode region and a cathode region, the transfer transistor has a pair of main electrodes, one of the main electrodes being formed by the floating diffusion, and the other of the main electrodes being formed by the cathode region.

16. The photodetector device according to claim 15, wherein the electrode is extended to the first surface within a range of the thickness of the sidewall insulator disposed between the floating diffusion and the electrode.

17. The photodetection device according to claim 16, further comprising a pixel isolation region surrounding the photoelectric conversion element and the transfer transistor for electrically and optically isolating the photoelectric conversion element and the transfer transistor, and the electrode is extended to the pixel isolation region in a region other than the sidewall insulator disposed between the floating diffusion and the electrode.

18. The photodetector device according to claim 14, wherein the depth of the sidewall insulator from the first surface to the second surface is deeper than the junction depth of the floating diffusion.

19. A transfer transistor having: a first trench disposed from a first surface of a substrate toward a second surface opposite to the first surface; a second trench spaced apart from the first trench on the first surface and disposed from the first surface toward the second surface of the substrate; a third trench disposed from the first surface toward the second surface, having a depth shallower than the first and second trenches, and communicating with the first and second trenches; a first gate electrode disposed in a lower portion of the first trench and embedded in a side wall of the first trench with a first gate insulating film interposed therebetween, a second gate electrode disposed in a lower portion of the second trench and embedded in a side wall of the second trench with a second gate insulating film interposed therebetween, and a third gate electrode embedded in a bottom of the third trench with a third gate insulating film interposed therebetween and electrically connecting the first gate electrode and the second gate electrode. a sidewall insulator disposed on each of the first groove sidewalls and the second groove sidewalls at an upper portion of each of the first groove and the second groove, the sidewall insulator having a thickness in the same direction greater than a thickness of each of the first gate insulating film and the second gate insulating film; an electrode buried in each of the first groove and the second groove with the sidewall insulator interposed therebetween and electrically connected to each of the first gate electrode and the second gate electrode; a floating diffusion disposed on the first surface side of the substrate with the sidewall insulator interposed between the electrode and the floating diffusion electrically connected to one end of the transfer transistor; and a photoelectric conversion element disposed in the substrate, electrically connected to the other end of the transfer transistor, and converting light into an electric charge.

20. The photodetector device according to claim 19, wherein the depth of said third groove is the same as the depth of said sidewall insulator in the same direction.

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