Semiconductor module and power conversion device

Abstract

A semiconductor module (30) constitutes two inverters connected to a common rotary electric machine. The semiconductor module (30) is provided with: a semiconductor element (41) constituting a first inverter; a semiconductor element (42) constituting a second inverter; a current path part (43) including the semiconductor element (41); and a current path part (44) including the semiconductor element (42). In the X direction, semiconductor elements (41, 42), the on-timings of which are at least partially overlapped are disposed adjacent to each other. The current path parts (43, 44) are arranged side by side in the X direction so that the currents flowing in mutually opposite directions face each other.

Description

Semiconductor module and power conversion device CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based on Patent Application No. 2023-127316 filed in Japan on August 3, 2023, and the contents of the original application are incorporated by reference in their entirety.

[0002] The disclosure herein relates to a semiconductor module and a power conversion device.

[0003] Patent Document 1 discloses a power conversion device having two inverters connected to a common rotating electric machine. The contents of the prior art document are incorporated by reference as an explanation of the technical elements in this specification.

[0004] Japanese Patent Application Laid-Open No. 2022-179964

[0005] The inverter includes a semiconductor module having a semiconductor element. In the power conversion device of Patent Document 1, for example, the first inverter includes a first semiconductor module, and the second inverter includes a second semiconductor module. In this configuration, when a current flows between the first inverter and the second inverter, a current also flows between the first semiconductor module and the second semiconductor module, resulting in a problem of large inductance. In terms of the above and other aspects not mentioned, further improvements are required in semiconductor modules and power conversion devices.

[0006] One disclosed object is to provide a semiconductor module and a power conversion device that can reduce inductance.

[0007] The symbols in parentheses in the claims, this section, and the technical concept section are examples showing the correspondence with the specific means described in the embodiments below as one aspect. The symbols in parentheses do not limit the technical scope.

[0008] One aspect of the disclosure is a semiconductor module that constitutes two inverters connected to a common rotating electric machine, comprising: a first semiconductor element that constitutes a first inverter, which is one of the inverters; a second semiconductor element that constitutes a second inverter, which is the other of the inverters, and whose on-timing at least partially overlaps with the on-timing of the first semiconductor element; a first current path portion that includes the first semiconductor element; and a second current path portion that includes the second semiconductor element, wherein the second semiconductor element is arranged next to the first semiconductor element in a predetermined direction, and the first current path portion and the second current path portion run side by side in the predetermined direction so that the currents flowing therethrough are opposite to each other.

[0009] According to the disclosed semiconductor module, the above arrangement allows the current flowing through the first current path portion and the current flowing through the second current path portion to flow in opposite directions when both the first semiconductor element and the second semiconductor element are turned on, thereby canceling out the magnetic flux and reducing inductance.

[0010] Another embodiment of the disclosure is a power conversion device comprising: a first inverter connected to a rotating electric machine; and a second inverter connected to the rotating electric machine, wherein the first inverter and the second inverter are configured to include semiconductor modules, and the semiconductor module has: a first semiconductor element constituting the first inverter; a second semiconductor element constituting the second inverter, the second semiconductor element having at least a portion of its on-timing overlapping with the on-timing of the first semiconductor element; a first current path portion including the first semiconductor element; and a second current path portion including the second semiconductor element, wherein the second semiconductor element is arranged next to the first semiconductor element in a predetermined direction, and the first current path portion and the second current path portion run side by side in the predetermined direction so that the currents flowing therethrough are opposite to each other.

[0011] According to the disclosed power conversion device, the above arrangement causes the current flowing through the first current path portion and the current flowing through the second current path portion to oppose each other in opposite directions when both the first semiconductor element and the second semiconductor element are turned on, thereby canceling out the magnetic flux and reducing inductance.

[0012] The various aspects disclosed in this specification employ different technical means to achieve their respective objectives. The reference numerals in parentheses in the claims and in this section are intended to exemplify correspondences with the following embodiments and are not intended to limit the technical scope. The objectives, features, and advantages disclosed in this specification will become more apparent by reference to the following detailed description and the accompanying drawings.

[0013] FIG. 1 is a diagram showing a drive system according to a first embodiment. FIG. 2 is a diagram showing an example of an operating point map of a rotating electric machine. FIG. 3 is a diagram showing star connection drive. FIG. 4 is a diagram showing open connection drive. FIG. 5 is a plan view showing an example of a power conversion device. FIG. 6 is a plan view showing an example of a semiconductor module. FIG. 7 is a plan view showing another example of a semiconductor device. FIG. 8 is a plan view showing another example of a semiconductor device. FIG. 9 is a plan view showing another example of a semiconductor device. FIG. 10 is a diagram showing magnetic flux cancellation during open connection drive. FIG. 11 is a diagram showing magnetic flux cancellation during star connection drive. FIG. 12 is a diagram showing a drive system according to a second embodiment. FIG. 13 is a plan view showing an example of a semiconductor module.

[0014] Hereinafter, several embodiments will be described with reference to the drawings. Note that in each embodiment, corresponding components are designated by the same reference numerals, and redundant description may be omitted. When only a portion of the configuration is described in each embodiment, the configuration of another embodiment described previously can be applied to the remaining portions of the configuration. Furthermore, in addition to the combinations of configurations explicitly stated in the description of each embodiment, configurations of several embodiments can also be partially combined together even if not explicitly stated, as long as there is no particular problem with the combination. Note that the term "A and / or B" means at least one of A and B. In other words, it may include only A, only B, or both A and B.

[0015] The semiconductor device and the semiconductor module including the semiconductor device according to the present embodiment are applied to, for example, a power conversion device for a mobile object using a rotating electric machine as a drive source. The mobile object may be, for example, an electric vehicle such as a battery electric vehicle (BEV), a hybrid electric vehicle (HEV), or a plug-in hybrid electric vehicle (PHEV), an aircraft such as an electric vertical take-off and landing aircraft or a drone, a ship, a construction machine, or an agricultural machine.

[0016] First Embodiment First, a schematic configuration of a drive system for a moving body will be described with reference to FIG.

[0017] <Drive System for a Moving Body> As shown in FIG. 1 , a drive system 1 for a moving body includes a DC power supply 2 , a rotating electric machine 3 , and a power conversion circuit 4 .

[0018] The DC power supply 2 may be, for example, a rechargeable secondary battery such as a lithium ion battery, a nickel-metal hydride battery, etc. The DC power supply 2 may also be one that converts AC power into DC power and outputs it.

[0019] The rotating electric machine 3 is a three-phase open-winding type rotating electric machine with an open neutral point. The rotating electric machine 3 has a U-phase winding 3U, a V-phase winding 3V, and a W-phase winding 3W. Hereinafter, the U-phase winding 3U, the V-phase winding 3V, and the W-phase winding 3W may be simply referred to as windings 3U, 3V, and 3W.

[0020] The rotating electric machine 3 functions, for example, as a drive source for a moving body, that is, as an electric motor. If the moving body is a vehicle, the rotating electric machine 3 generates torque for driving drive wheels (not shown). The rotating electric machine 3 is not limited to an electric motor. The rotating electric machine 3 may be a motor generator that functions as both an electric motor and a generator, or may be a generator.

[0021] The power conversion circuit 4 performs power conversion between the DC power supply 2 and the rotating electric machine 3. The drive system 1 is a system of a common power supply type in which power is supplied from a common DC power supply 2 to two inverters 8 and 9, which will be described later. As illustrated in FIG. 1 , the drive system 1 may include only one common DC power supply 2 or multiple common DC power supplies 2. The drive system 1 may also include a power supply switch (not shown), such as an SMR, between the DC power supply 2 and the power conversion circuit 4. SMR is an abbreviation for System Main Relay. Turning on the power supply switch enables power supply from the DC power supply 2 to the rotating electric machine 3, and turning off the power supply switch cuts off the power supply from the DC power supply 2 to the rotating electric machine 3.

[0022] <Power Conversion Circuit> Fig. 1 shows an example of a power conversion circuit 4. The power conversion circuit 4 shown in Fig. 1 includes power lines 5 and 6, a smoothing capacitor 7, inverters 8 and 9, a switch 10, a control unit 11, and a current sensor 12 as elements related to power conversion.

[0023] The power supply line 5 is a high-potential power line. The power supply line 5 is connected to the positive electrode of the DC power supply 2. The power supply line 6 is a low-potential power line. The power supply line 6 is connected to the negative electrode of the DC power supply 2. The power supply lines 5 and 6 are provided by bus bars, which are, for example, metal plates.

[0024] The smoothing capacitor 7 mainly smoothes the DC voltage supplied from the DC power supply 2. The smoothing capacitor 7 is provided between the power supply lines 5 and 6. The positive electrode of the smoothing capacitor 7 is connected to the power supply line 5 between the DC power supply 2 and the inverters 8 and 9. The negative electrode of the smoothing capacitor 7 is connected to the power supply line 6 between the DC power supply 2 and the inverters 8 and 9. The smoothing capacitor 7 is connected in parallel to the inverters 8 and 9.

[0025] The inverters 8 and 9 are DC-AC conversion circuits. The inverter 8 is configured with upper and lower arm circuits 8HL for three phases. The upper and lower arm circuits 8HL are sometimes referred to as legs. The upper and lower arm circuit 8HL has an upper arm 8H and a lower arm 8L. The upper arm 8H and the lower arm 8L are connected in series between the power supply lines 5 and 6, with the upper arm 8H on the power supply line 5 side.

[0026] The connection point between the upper arm 8H and the lower arm 8L is connected to the winding of the corresponding phase in the rotating electric machine 3 via an output line 13. The inverter 8 has six arms. Each arm is configured with a switching element. The number of switching elements constituting each arm is not particularly limited. There may be one or more. When there are more than one switching elements, the multiple switching elements connected in parallel to each other are turned on and off at the same timing by a common gate drive signal (drive voltage).

[0027] 1, an n-channel MOSFET 14 is used as the switching element constituting each arm. MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor. In the upper arm 8H, the drain of the MOSFET 14 is connected to the power supply line 5. In the lower arm 8L, the source of the MOSFET 14 is connected to the power supply line 6. The source of the MOSFET 14 in the upper arm 8H and the drain of the MOSFET 14 in the lower arm 8L are connected to each other.

[0028] A freewheeling diode 15 is connected in antiparallel to each MOSFET 14. The diode 15 may be a parasitic diode (body diode) of the MOSFET 14 or may be provided separately from the parasitic diode. The anode of the diode 15 is connected to the source of the corresponding MOSFET 14, and the cathode is connected to the drain.

[0029] The inverter 9 has the same configuration as the inverter 8. The inverter 9 is configured with upper and lower arm circuits 9HL for three phases. The upper and lower arm circuits 9HL have an upper arm 9H and a lower arm 9L. The upper arm 9H and the lower arm 9L are connected in series between the power supply lines 5 and 6, with the upper arm 9H on the power supply line 5 side.

[0030] The connection point between the upper arm 9H and the lower arm 9L is connected to the winding of the corresponding phase in the rotating electric machine 3 via an output line 16. The inverter 9 also has six arms. Each arm is configured with a switching element. The number of switching elements constituting each arm is not particularly limited. It may be one or more.

[0031] 1, an n-channel MOSFET 17 is used as the switching element constituting each arm. In the upper arm 9H, the drain of the MOSFET 17 is connected to the power supply line 5. In the lower arm 9L, the source of the MOSFET 17 is connected to the power supply line 6. The source of the MOSFET 17 in the upper arm 9H and the drain of the MOSFET 17 in the lower arm 9L are connected to each other. A freewheeling diode 18 is connected in antiparallel to each MOSFET 17.

[0032] As described above, the high-potential terminals (drain terminals) of the upper arms 8H, 9H of the inverters 8, 9 are connected to the power supply line 5. The low-potential terminals (source terminals) of the lower arms 8L, 9L are connected to the power supply line 6. A node connecting the upper arm 8H and the lower arm 8L is connected to one end of the corresponding phase winding via an output line 13, and a node connecting the upper arm 9H and the lower arm 9L is connected to the other end of the corresponding phase winding via an output line 16. Specifically, one end of the U-phase winding 3U is connected to a node U1 of the U-phase upper and lower arm circuit 8HL, and the other end of the U-phase winding 3U is connected to a node U2 of the U-phase upper and lower arm circuit 9HL. One end of the V-phase winding 3V is connected to a node V1 of the V-phase upper and lower arm circuit 8HL, and the other end of the V-phase winding 3V is connected to a node V2 of the V-phase upper and lower arm circuit 9HL. One end of the W-phase winding 3W is connected to a node W1 of the W-phase upper and lower arm circuit 8HL, and the other end of the W-phase winding 3W is connected to a node W2 of the W-phase upper and lower arm circuit 9HL.

[0033] The switching elements constituting the inverters 8 and 9 are not limited to the above-described MOSFETs. For example, IGBTs may be used. IGBT is an abbreviation for Insulated Gate Bipolar Transistor. In the case of an IGBT, a freewheeling diode is connected in antiparallel. The types of switching elements constituting the inverters 8 and 9 may be the same or different. For example, one of the inverters 8 and 9 may be composed of a MOSFET and the other of an IGBT.

[0034] The switch 10 is provided on at least one of the power supply lines 5, 6, between the connection point of the inverter 8 and the connection point of the inverter 9. When the switch 10 is closed, it connects the high potential side terminal of the upper arm 9H of the inverter 9 to the smoothing capacitor 7. When the switch 10 is open, it cuts off the connection between the high potential side terminal of the upper arm 9H and the smoothing capacitor 7. For example, a semiconductor switch or a mechanical relay can be used as the switch 10.

[0035] In the example shown in FIG. 1 , a semiconductor switch, i.e., a switching element formed on a semiconductor chip, is used as the switch 10. The switching element is not particularly limited. It may have the same configuration as the switching element constituting at least one of the inverters 8 and 9, or it may have a different configuration. In FIG. 1 , the switching element constituting the switch 10 is a MOSFET 19. A diode is connected in antiparallel to the MOSFET 19. When the MOSFET 19 is turned on and the switch 10 is in a closed state, the high-potential side terminal of the upper arm 9H is electrically connected to the smoothing capacitor 7. When the MOSFET 19 is turned off and the switch 10 is in an open state, the electrical connection between the high-potential side terminal of the upper arm 9H and the smoothing capacitor 7 is interrupted.

[0036] The control unit (CTR) 11 may be configured to include, for example, a processor, memory, storage, etc. The processor executes various processes by accessing the memory. The memory is a rewritable volatile storage medium. The memory is, for example, RAM. RAM is an abbreviation for Random Access Memory. The storage is, for example, a rewritable non-volatile storage medium. The storage stores programs executed by the processor. The programs construct multiple functional units by causing the processor to execute multiple instructions. The processes executed by the control unit 11 may be realized by software processing in which the processor executes the above-mentioned programs, or may be realized by hardware processing using dedicated electronic circuits.

[0037] The control unit 11 may have a drive command generation unit and a drive circuit unit, both not shown. The drive command generation unit controls the inverters 8 and 9. The drive command generation unit generates drive commands (command signals) for controlling the on / off of the MOSFETs 14 and 17, and outputs the drive commands to the drive circuit unit. The drive command generation unit generates the drive commands based on drive requests for the rotating electric machine 3, such as torque command values ​​input from a higher-level ECU, also not shown, and signals detected by various sensors.

[0038] The various sensors may include, for example, a current sensor 12 illustrated in Fig. 1 , a rotation angle sensor, a voltage sensor, and the like (not shown). The current sensor 12 detects the phase currents flowing through the windings 3U, 3V, and 3W of each phase. The rotation angle sensor detects the rotation angle of the rotor of the rotating electric machine 3. The voltage sensor detects the voltage across the smoothing capacitor 7.

[0039] The drive command generation unit controls the switch 10. The drive command generation unit generates a drive command for controlling the on / off of the MOSFET 19 that constitutes the switch 10. This drive command is a switching command that switches the switch 10 between open and closed states.

[0040] The drive circuit unit is sometimes referred to as a driver. Based on a drive command, the drive circuit unit can independently control the on / off states of the six MOSFETs 14, the six MOSFETs 17, and the one MOSFET 19. The drive circuit unit outputs a drive signal, for example, so as to increase the drive voltage (gate voltage Vge) during the on period of the pulse-shaped drive command and decrease the drive voltage during the off period.

[0041] <Star Connection Drive and Open Connection Drive> Next, star connection drive and open connection drive will be described with reference to Figures 2, 3, and 4. Figure 2 is an operating point map of the rotating electric machine 3, with the horizontal axis representing rotation speed and the vertical axis representing torque. Figure 3 is a diagram showing star connection drive. Figure 4 is a diagram showing open connection drive.

[0042] As shown in Figure 2, the driving range of the rotating electric machine 3 is divided into two ranges depending on the rotation speed and torque. One of the driving ranges is the star connection driving range. The star connection driving range is a normal use range. The other driving range is the open connection driving range. The open connection driving range is a range of higher rotation speeds or higher torques than the star connection driving range.

[0043] When the operating point is in the star connection drive region, the control unit 11 executes star connection drive control. Star connection drive is sometimes referred to as Y drive. The control unit 11 controls the MOSFETs 14, 17, and 19 so that the windings 3U, 3V, and 3W are in a star connection state. Specifically, as shown in FIG. 3, the switch 10 is opened, i.e., the MOSFET 19 is turned off. The inverter 9 is also neutralized. As shown in FIG. 3, for example, the MOSFETs 17 of the upper arms 9H of all phases may be turned on and the MOSFETs 17 of the lower arms 9L of all phases may be turned off. The MOSFETs 17 of the upper arms 9H of all phases may be turned off and the MOSFETs 17 of the lower arms 9L of all phases may be turned on. The MOSFETs 14 of the inverter 8 are then controlled according to drive requirements, etc.

[0044] The dashed-dotted arrows in Figure 3 indicate an example of a current path. Figure 3 shows the current path when the MOSFET 14 of the U-phase upper arm 8H and the MOSFET 14 of the W-phase lower arm 8L are turned on. In the example shown in Figure 3, the upper arm 9H of the inverter 9 is turned on and the lower arm 9L is turned off. The current flows in the following order: U-phase upper arm 8H → node U1 → U-phase winding 3U → node U2 → U-phase upper arm 9H → W-phase upper arm 9H → node W2 → W-phase winding 3W → node W1 → W-phase lower arm 8L. In this way, the current flows without passing through the switch 10.

[0045] The control method of the inverter 8 by the control unit 11 is not particularly limited. For example, a PWM control method or an overmodulation PWM control method may be used. In the PWM control method or the overmodulation PWM control method, the drive command generation unit outputs a high-frequency carrier (carrier wave), such as a triangular wave, sawtooth wave, or rectangular wave. A pulse-shaped drive command is generated by comparing the voltage of a sinusoidal voltage signal serving as a torque command value with the carrier. For example, a square wave control method may be used. In the square wave control method, the drive command generation unit generates a square wave pulse as a drive command, with a one-to-one on-off period ratio within one control cycle, from the sinusoidal voltage signal serving as the torque command value. For example, the control method may be switched depending on the rotation speed of the rotating electric machine 3. Square wave control has a higher voltage utilization rate than PWM control. In the star-connection drive range, the PWM control method may be used in the low to medium rotation range and the square wave control method may be used in the high rotation range.

[0046] When the operating point is in the open connection drive region, the control unit 11 executes open connection drive control. Open connection drive is sometimes referred to as H drive. The control unit 11 closes the switch 10, i.e., turns on the MOSFET 19, and opens the neutral point of the inverter 9. Opening the neutral point forms an open connection circuit of the upper and lower arm circuits 8HL and 9HL of the U phase via the U-phase winding 3U. Similarly, an open connection circuit of the upper and lower arm circuits 8HL and 9HL of the V phase via the V-phase winding 3V is formed. An open connection circuit of the upper and lower arm circuits 8HL and 9HL of the W phase via the W-phase winding 3W is formed. The control unit 11 regards each phase as an independent open connection circuit and controls the applied voltage for each phase. In a common phase, the control unit 11 turns on the upper arms 8H and 9H of one of the inverters 8 and 9 and the lower arms 8L and 9L of the other of the inverters 8 and 9.

[0047] The dashed-double-dashed arrows in Fig. 4 indicate an example of a current path. Fig. 4 shows the current path when the MOSFET 14 in the W-phase lower arm 8L and the MOSFET 17 in the W-phase upper arm 9H are turned on. The current flows in the following order: switch 10 → W-phase upper arm 9H → node W2 → W-phase winding 3W → node W1 → W-phase lower arm 8L. In this way, the current flows via switch 10.

[0048] The control method of the inverters 8 and 9 by the control unit 11 is not particularly limited. For example, a PWM control method may be used. A square wave control method or an overmodulation PWM control method may also be used. The control method may be switched depending on the rotation speed of the rotating electric machine 3. As described above, the control unit 11 can independently control each of the six MOSFETs 14 and the six MOSFETs 17. Therefore, current can flow in either the positive or negative direction through the windings 3U, 3V, and 3W of each phase. The positive direction is the direction in which the current flows from the inverter 8 side to the inverter 9 side. The negative direction is the direction in which the current flows from the inverter 9 side to the inverter 8 side.

[0049] For example, the two MOSFETs 17 constituting the U-phase upper and lower arm circuit 9HL may be turned on and off in a complementary manner using PWM control, with the MOSFET 14 in the U-phase upper arm 8H turned off and the MOSFET 14 in the U-phase lower arm 8L turned on. This causes a negative current to flow through the U-phase winding 3U. Meanwhile, the two MOSFETs 14 constituting the U-phase upper and lower arm circuit 8HL may be turned on and off in a complementary manner using PWM control, with the MOSFET 17 in the U-phase upper arm 9H turned off and the MOSFET 17 in the U-phase lower arm 9L turned on. This causes a positive current to flow through the U-phase winding 3U.

[0050] As described above, the inverters 8 and 9 can switch between star connection drive and open connection drive. By performing open connection drive instead of star connection drive, it is possible to output a higher rotation speed range or a higher torque range.

[0051] <Power Conversion Device> Fig. 5 is a diagram showing an example of a power conversion device. For convenience, Fig. 5 shows elements covered by an encapsulant that constitute a semiconductor device in a see-through manner. The power conversion device provides at least a part of a power conversion circuit 4. The power conversion device provides at least inverters 8 and 9. The power conversion device 20 shown in Fig. 5 includes two inverters 21 and 22, a capacitor 23, an output terminal block 24, and a current sensor 25.

[0052] In the following, the thickness direction of a substrate (described later) constituting the semiconductor device is referred to as the Z direction, and one direction perpendicular to the Z direction is referred to as the X direction. The direction perpendicular to both the Z direction and the X direction is referred to as the Y direction. Unless otherwise specified, the shape viewed from the Z direction, in other words, the shape along the XY plane defined by the X and Y directions, is referred to as the planar shape. The planar view from the Z direction may also be simply referred to as the planar view.

[0053] The inverters 21 and 22 correspond to the inverters 8 and 9. The inverter 21 provides the inverter 8, and the inverter 22 provides the inverter 9. The inverters 21 and 22 are configured with a semiconductor module 30. The semiconductor module 30 includes at least one semiconductor device 40. In the example shown in FIG. 5 , the inverters 21 and 22 are configured with a semiconductor module 30 including six semiconductor devices 40. The semiconductor module 30 and the semiconductor device 40 will be described in detail later.

[0054] The capacitor 23 serves as the smoothing capacitor 7. The capacitor 23 includes, for example, a case (not shown) and a capacitor element housed in the case. The capacitor element is, for example, a film capacitor element. The capacitor element is formed by winding a film around an axis in a predetermined direction. The capacitor element has electrodes (not shown) on both end surfaces of the axis. The electrodes are sometimes called metallikon. The capacitor 23 includes a P bus bar 23P connected to the positive electrode and an N bus bar 23N connected to the negative electrode.

[0055] The P bus bar 23P and the N bus bar 23N are plate-shaped metal members. The P bus bar 23P and the N bus bar 23N are connected to the corresponding electrodes by soldering, resistance welding, laser welding, or the like. Fig. 5 illustrates terminal portions of the P bus bar 23P and the N bus bar 23N for connection to the semiconductor module 30 (semiconductor device 40). The P bus bar 23P and the N bus bar 23N have terminal portions (not shown) for electrically connecting the smoothing capacitor 7 and the DC power supply 2.

[0056] Although not shown, the semiconductor switch that provides the switch 10 is provided integrally with, for example, the capacitor 23. The semiconductor switch is provided, for example, in the P bus bar 23P, in a path that electrically connects a terminal connected to the inverter 21 with a terminal connected to the inverter 22. The semiconductor switch may also be provided, for example, in the N bus bar 23N, in a path that electrically connects a terminal connected to the inverter 21 with a terminal connected to the inverter 22.

[0057] The output terminal block 24 electrically connects the inverters 21 and 22 to the rotating electric machine 3. The output terminal block 24 is sometimes referred to as a motor terminal block. The output terminal block 24 includes an electrically insulating case made of resin or the like, and bus bars held in the case. The bus bar 24U1 provides the output line 13 connected to the node U1 of the inverter 8 (21). The bus bar 24U2 provides the output line 16 connected to the node U2 of the inverter 9 (22). The bus bar 24V1 provides the output line 13 connected to the node V1 of the inverter 8 (21). The bus bar 24V2 provides the output line 16 connected to the node V2 of the inverter 9 (22). The bus bar 24W1 provides the output line 13 connected to the node W1 of the inverter 8 (21). The bus bar 24W2 provides the output line 16 connected to the node W2 of the inverter 9 (22).

[0058] Bus bars 24U1H and 24U1L are electrically connected to bus bar 24U1. Bus bars 24U1H and 24U1L may be connected to bus bar 24U1 continuously or by joints. Bus bar 24U1H is electrically connected to the U-phase upper arm 8H of inverter 8 (21), and bus bar 24U1L is electrically connected to the U-phase lower arm 8L. Bus bars 24U2H and 24U2L are electrically connected to bus bar 24U2. Bus bar 24U2H is electrically connected to the U-phase upper arm 9H of inverter 9 (22), and bus bar 24U2L is electrically connected to the U-phase lower arm 9L.

[0059] Similarly, bus bars 24V1H and 24V1L are electrically connected to bus bar 24V1. Bus bar 24V1H is electrically connected to the V-phase upper arm 8H of inverter 8 (21), and bus bar 24U1L is electrically connected to the V-phase lower arm 8L. Bus bars 24V2H and 24V2L are electrically connected to bus bar 24V2. Bus bar 24V2H is electrically connected to the V-phase upper arm 9H of inverter 9 (22), and bus bar 24V2L is electrically connected to the V-phase lower arm 9L.

[0060] Bus bars 24W1H and 24W1L are electrically connected to bus bar 24W1. Bus bar 24W1H is electrically connected to the W-phase upper arm 8H of inverter 8 (21), and bus bar 24W1L is electrically connected to the W-phase lower arm 8L. Bus bars 24W2H and 24W2L are electrically connected to bus bar 24W2. Bus bar 24W2H is electrically connected to the W-phase upper arm 9H of inverter 9 (22), and bus bar 24W2L is electrically connected to the W-phase lower arm 9L.

[0061] The current sensor 25 serves as the current sensor 12. The current sensor 25 is disposed on the bus bars 24U2, 24V2, and 24W2 of the output terminal block 24. The current sensor 25 individually detects the phase currents flowing through each of the bus bars 24U2, 24V2, and 24W2. The current sensor 25 may be provided integrally with the output terminal block 24. The current sensor 25 may be disposed on the bus bars 24U1, 24V1, and 24W1, or on the bus bars 24U1, 24V1, 24W1, 24U2, 24V2, and 24W2.

[0062] In the power conversion device 20 described above, the semiconductor module 30 is disposed in the Y direction between the capacitor 23 and the output terminal block 24. The plurality of semiconductor devices 40 are disposed side by side in the X direction.

[0063] The power conversion device 20 may include a case that houses the inverters 21, 22, the capacitor 23, the output terminal block 24, and the current sensor 25. The power conversion device 20 may include a cooler that cools the semiconductor module 30 and the like. The cooler may have an internal flow path through which a refrigerant flows, or may be a heat sink equipped with fins or the like. The cooler may be provided integrally with the case that houses the inverters 21, 22. The power conversion device 20 may include an input terminal block that electrically connects the smoothing capacitor 7 (capacitor 23) and the DC power source 2. The power conversion device 20 may include a circuit board that provides the control unit 11.

[0064] <Semiconductor Module and Semiconductor Device> Fig. 6 is a plan view showing an example of a semiconductor module 30. Fig. 6 corresponds to Fig. 5. In Fig. 6, like Fig. 5, elements covered by a sealing body are shown in a see-through manner. As described above, the semiconductor module 30 provides two inverters 21, 22 (8, 9) connected to a common rotating electric machine 3. The semiconductor module 30 includes at least one semiconductor device 40.

[0065] In the example shown in FIG. 6 , the semiconductor module 30 includes a U-phase semiconductor module 30U, a V-phase semiconductor module 30V, and a W-phase semiconductor module 30W. The semiconductor module 30U provides the U-phase to the inverters 21 and 22. The semiconductor module 30V provides the V-phase to the inverters 21 and 22. The semiconductor module 30W provides the W-phase to the inverters 21 and 22. The semiconductor modules 30U, 30V, and 30W are aligned in the X direction. Each of the semiconductor modules 30U, 30V, and 30W includes two semiconductor devices 40. The semiconductor module 30 includes six semiconductor devices 40.

[0066] The semiconductor module 30U includes semiconductor devices 40, namely, semiconductor device 40U1 and semiconductor device 40U2. The semiconductor devices 40U1 and 40U2 are arranged side by side in the X direction so as to be adjacent to each other. The semiconductor module 30V includes semiconductor devices 40V1 and semiconductor device 40V2. The semiconductor devices 40V1 and 40V2 are arranged side by side in the X direction so as to be adjacent to each other. The semiconductor module 30W includes semiconductor devices 40W1 and semiconductor device 40W2. The semiconductor devices 40W1 and 40W2 are arranged side by side in the X direction so as to be adjacent to each other.

[0067] The semiconductor module 30 includes semiconductor elements 41 and 42 and current path portions 43 and 44. The semiconductor device 40 illustrated in FIG. 6 includes the semiconductor elements 41 and 42 and the current path portions 43 and 44 within a single semiconductor device 40. The semiconductor element 41 constitutes the inverter 21 (8). The semiconductor element 42 constitutes the inverter 22 (9). The current path portion 43 constitutes the inverter 21. The current path portion 44 constitutes the inverter 22.

[0068] The semiconductor elements 41 and 42 are vertical elements formed on a semiconductor substrate made of silicon (Si) or a wide bandgap semiconductor with a wider bandgap than silicon. Examples of wide bandgap semiconductors include silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), and diamond. The semiconductor elements 41 and 42 are sometimes called power elements or semiconductor chips.

[0069] The vertical elements are configured to pass a main current in the thickness direction of the semiconductor elements 41, 42 (semiconductor substrate). The semiconductor elements 41, 42 are arranged so that their thickness direction is approximately parallel to the Z direction. The semiconductor elements 41, 42 have main electrodes on both sides in the thickness direction. The semiconductor elements 41, 42 of this embodiment are formed by forming n-channel MOSFETs as vertical elements on a semiconductor substrate made of SiC. The semiconductor elements 41, 42 have a drain electrode on their bottom surface facing a substrate 45 (described below) and a source electrode on their top surface opposite the bottom surface.

[0070] When a MOSFET is turned on, a current (main current) flows between the main electrodes, that is, between the drain electrode and the source electrode. If the diode is a parasitic diode, the source electrode also serves as the anode electrode, and the drain electrode also serves as the cathode electrode. The diode may be formed on a chip separate from the MOSFET. The drain electrode is the main electrode on the high potential side, and the source electrode is the main electrode on the low potential side. The drain electrode is formed over almost the entire bottom surface. The source electrode is formed on a part of the top surface.

[0071] The semiconductor elements 41 and 42 are generally rectangular in plan view. The semiconductor elements 41 and 42 have pads, which are signal electrodes, on their upper surfaces. The pads are formed at positions on the upper surfaces that are different from the source electrodes. The pads include at least a gate pad.

[0072] The semiconductor element 41 includes a semiconductor element 41H that constitutes the upper arm 8H and a semiconductor element 41L that constitutes the lower arm 8L. The semiconductor element 42 includes a semiconductor element 42H that constitutes the upper arm 9H and a semiconductor element 42L that constitutes the lower arm 9L. The semiconductor elements 41 and 42 may have the same configuration or may differ from each other. The semiconductor element 41H includes semiconductor elements 41UH, 41VH, and 41WH. The semiconductor element 41L includes semiconductor elements 41UL, 41VL, and 41WL. The semiconductor element 42H includes semiconductor elements 42UH, 42VH, and 42WH. The semiconductor element 42L includes semiconductor elements 42UL, 42VL, and 42WL. Hereinafter, the semiconductor elements 41H, 41UH, 41VH, 41WH, 42H, 42UH, 42VH, and 42WH may be referred to as upper arm elements. The semiconductor elements 41L, 41UL, 41VL, 41WL, 42L, 42UL, 42VL, and 42WL may be referred to as lower arm elements.

[0073] The semiconductor elements 41 and 42 are aligned in the X direction. The semiconductor elements 41 and 42 are alternately arranged in the X direction. The semiconductor elements 41 and 42 are arranged so that elements whose on-timings at least partially overlap are adjacent to each other. For example, the semiconductor elements 41 and 42 constituting the U phase of the inverters 21 and 22, i.e., the semiconductor elements 41 and 42 constituting the semiconductor module 30U, are aligned in the order of semiconductor element 42UL, semiconductor element 41UH, semiconductor element 42UH, and semiconductor element 41UL from one end in the X direction. The semiconductor device 40U1 includes the semiconductor element 41UH and the semiconductor element 42UL. The semiconductor elements 41UH and 42UL are aligned in the X direction. The semiconductor device 40U2 includes the semiconductor element 41UL and the semiconductor element 42UH. The semiconductor elements 41UL and 42UH are aligned in the X direction. The semiconductor elements 41UH, 41UL, 42UH, and 42UL are arranged in the X direction such that the semiconductor elements 41UH and 42UH are adjacent to each other. The semiconductor devices 40U1 and 40U2 are arranged such that the semiconductor elements 41UH and 42UH are adjacent to each other.

[0074] The semiconductor elements 41 and 42 constituting the V-phase of the inverters 21 and 22, i.e., the semiconductor module 30V, are arranged in the same manner as the U-phase. The semiconductor elements 41 and 42 constituting the semiconductor module 30V are arranged in the following order from one end in the X direction: semiconductor element 42VL, semiconductor element 41VH, semiconductor element 42VH, and semiconductor element 41VL. Semiconductor element 42VL is arranged next to semiconductor element 41UL. The semiconductor device 40V1 includes semiconductor element 41VH and semiconductor element 42VL. The semiconductor elements 41VH and 42VL are arranged in the X direction. The semiconductor device 40V2 includes semiconductor element 41VL and semiconductor element 42VH. The semiconductor elements 41VL and 42VH are arranged in the X direction. The semiconductor elements 41VH, 41VL, 42VH, and 42VL are arranged in the X direction so that the semiconductor elements 41VH and 42VH are adjacent to each other. The semiconductor devices 40V1 and 40V2 are arranged such that the semiconductor elements 41VH and 42VH are adjacent to each other.

[0075] The semiconductor elements 41 and 42 constituting the W-phase of the inverters 21 and 22, i.e., the semiconductor module 30W, are arranged in the same manner as the U-phase. The semiconductor elements 41 and 42 constituting the semiconductor module 30W are arranged in the following order from one end in the X direction: semiconductor element 42WL, semiconductor element 41WH, semiconductor element 42WH, and semiconductor element 41WL. The semiconductor element 42WL is arranged next to the semiconductor element 41VL. The semiconductor device 40W1 includes a semiconductor element 41WH and a semiconductor element 42WL. The semiconductor elements 41WH and 42WL are arranged in the X direction. The semiconductor device 40W2 includes a semiconductor element 41WL and a semiconductor element 42WH. The semiconductor elements 41WL and 42WH are arranged in the X direction. The semiconductor elements 41WH, 41WL, 42WH, and 42WL are arranged in the X direction so that the semiconductor elements 41WH and 42WH are adjacent to each other. The semiconductor devices 40W1 and 40W2 are arranged such that the semiconductor elements 41WH and 42WH are adjacent to each other.

[0076] The current path portion 43 includes a current path portion 43H including the semiconductor element 41H and a current path portion 43L including the semiconductor element 41L. The current path portion 44 includes a current path portion 44H including the semiconductor element 42H and a current path portion 44L including the semiconductor element 42L. The semiconductor module 30 includes three current path portions 43H corresponding to the semiconductor elements 41UH, 41VH, and 41WH. The semiconductor module 30 includes three current path portions 43L corresponding to the semiconductor elements 41UL, 41VL, and 41WL. The semiconductor module 30 includes three current path portions 44H corresponding to the semiconductor elements 42UH, 42VH, and 42WH. The semiconductor module 30 includes three current path portions 44L corresponding to the semiconductor elements 42UL, 42VL, and 42WL. The current path portions 43 and 44 are aligned in the X direction corresponding to the alignment of the semiconductor elements 41 and 42.

[0077] The current path portions 43, 44 may be configured to include, for example, a substrate 45 and an external connection terminal 46. The substrate 45 is disposed on the drain electrode side of the semiconductor elements 41, 42. The substrate 45 is provided, for example, for each semiconductor device 40. The substrate 45 includes an insulating substrate 451 and wiring 452 disposed on one surface of the insulating substrate 451. The insulating substrate 451 is formed using an electrically insulating material such as ceramic or resin. The substrate 45 may include a metal body disposed on the surface opposite to the one surface in the Z direction.

[0078] The wiring 452 is formed from a metal such as Cu or Al that has good electrical and thermal conductivity. The wiring 452 may have a plating film of Ni or Au on its surface. In the example shown in FIG. 6 , the substrate 45 includes wirings 452H and 452L as the wiring 452. One semiconductor element 42 is mounted on each wiring 452. The wiring 452H constitutes the upper arm current path portions 43H and 44H. The upper arm element 41H or the upper arm element 42H is disposed on the wiring 452H. The drain electrode of the upper arm element 41H or the upper arm element 42H is bonded to the wiring 452H. The wiring 452L constitutes the lower arm current path portions 43L and 44H. The lower arm element 41L or the lower arm element 42L is disposed on the wiring 452L. The drain electrode of the lower arm element 41L or the lower arm element 42L is bonded to the wiring 452L.

[0079] The wirings 452H, 452L extend in the Y direction. In a single semiconductor device 40, the wirings 452H, 452L are aligned in the X direction, which is a direction perpendicular to the extension direction. The wirings 452H, 452L run parallel to each other. The wirings 452H and 452L are arranged opposite each other. In two adjacent semiconductor devices 40, the wirings 452H or the wirings 452L run parallel to each other.

[0080] The external connection terminals 46 are terminals for electrically connecting the semiconductor module 30 (semiconductor device 40) to an external device. The external connection terminals 46 are formed using a metal material with good conductivity, such as copper. The external connection terminals 46 are, for example, a plate material. The external connection terminals 46 include output terminals 461A and 462A, a P-terminal 46P, and an N-terminal 46N as main terminals electrically connected to the main electrodes of the semiconductor elements 41 and 42.

[0081] The output terminals 461A and 462A may also be referred to as AC terminals, O terminals, etc. The output terminals 461A and 462A are electrically connected to the windings 3U, 3V, and 3W of opposing phases of the rotating electric machine 3 via the output terminal block 24. The output terminals 461A and 462A are provided for each of the current path portions 43 and 44. In the example shown in FIG. 6 , one output terminal 461A is provided for each of the current path portions 43H and 44H, and one output terminal 462A is provided for each of the current path portions 43L and 44L. Each semiconductor device 40 includes one output terminal 461A and one output terminal 462A. The output terminals 461A and 462A extend in the Y direction. The output terminals 461A and 462A are arranged side by side in the X direction. The output terminals 461A and 462A are arranged opposite each other. In the current path portions 43H and 44H, the output terminal 461A is joined to the source electrode of the upper arm element, and in the current path portions 43L and 44L, the output terminal 462A is joined to the wiring 452L.

[0082] For example, the upper arm output terminal 461A of the semiconductor device 40U1 is joined to the bus bar 24U1H of the output terminal block 24, and the lower arm output terminal 462A is joined to the bus bar 24U2L. The upper arm output terminal 461A of the semiconductor device 40U2 is joined to the bus bar 24U2H, and the lower arm output terminal 462A is joined to the bus bar 24U1L. Similarly, the upper arm output terminal 461A of the semiconductor device 40V1 is joined to the bus bar 24V1H of the output terminal block 24, and the lower arm output terminal 462A is joined to the bus bar 24V2L. The upper arm output terminal 461A of the semiconductor device 40V2 is joined to the bus bar 24V2H, and the lower arm output terminal 462A is joined to the bus bar 24V1L. The output terminal 461A on the upper arm side of the semiconductor device 40W1 is joined to the bus bar 24W1H of the output terminal block 24, and the output terminal 462A on the lower arm side is joined to the bus bar 24W2L. The output terminal 461A on the upper arm side of the semiconductor device 40W2 is joined to the bus bar 24W2H, and the output terminal 462A on the lower arm side is joined to the bus bar 24W1L.

[0083] The P terminal 46P may be referred to as a positive terminal, a high-potential power supply terminal, etc. The P terminal 46P is electrically connected to the P bus bar 23P of the capacitor 23. The N terminal 46N may be referred to as a negative terminal, a low-potential power supply terminal, etc. The N terminal 46N is electrically connected to the N bus bar 23N of the capacitor 23. The P terminal 46P is provided for each of the current path portions 43H and 44H. The N terminal 46N is provided for each of the current path portions 43L and 44L. In the example shown in FIG. 6 , one P terminal 46P is provided for each of the current path portions 43H and 44H, and one N terminal 46N is provided for each of the current path portions 43L and 44L. Each semiconductor device 40 has one P terminal 46P and one N terminal 46N. In the semiconductor device 40, the P terminal 46P and the N terminal 46N extend in the Y direction. The P terminal 46P and the N terminal 46N are arranged side by side in the X direction. The P terminal 46P and the N terminal 46N are disposed opposite to each other.

[0084] The external connection terminals 46 include signal terminals (not shown) in addition to the main terminals described above. The signal terminals are electrically connected to the pads of the semiconductor elements 41 and 42. The signal terminals electrically connect the pads to, for example, a circuit board that provides the control unit 11. The signal terminals include at least terminals for applying a drive voltage to the gate electrodes of the semiconductor elements 41 and 42.

[0085] As illustrated in FIG. 6 , the semiconductor device 40 may include a sealing body 47. The sealing body 47 seals the elements of the semiconductor device 40. The sealing body 47 integrally seals the semiconductor elements 41 and 42, the substrate 45, and a portion of each of the external connection terminals 46. In the example illustrated in FIG. 6 , the sealing body 47 has a generally rectangular planar shape. Of the external connection terminals 46, output terminals 461A and 462A protrude to the outside from one of the side surfaces of the sealing body 47. The P-terminal 46P and the N-terminal 46N protrude to the outside from the side surface opposite the output terminals 461A and 462A in the Y direction.

[0086] In a configuration in which the substrate 45 is disposed on the case or cooler of the power conversion device 20, the sealant 47 may be, for example, a gel or a potting resin. The sealant 47 may also be a resin molded body. The sealant 47 may be provided for each semiconductor device 40 as illustrated in FIG. 6 , or may be provided for each semiconductor module 30U, 30V, and 30W. The sealant 47 may also be provided integrally in the semiconductor module 30.

[0087] In the semiconductor module 30 configured as described above, the current path portions 43 and 44 are arranged alternately. Each of the current path portions 43, 44 extends in the Y direction. The current path portions 43, 44 included in a single semiconductor device 40 are arranged adjacent to each other in the X direction. The current path portions 43, 44L run parallel to each other. The current path portions 43, 44 are arranged opposite each other. In two adjacent semiconductor devices 40, the current path portions 43H, 44H on the upper arm side or the current path portions 43L, 44L on the lower arm side run parallel to each other.

[0088] 6, in each of the semiconductor devices 40U1, 40V1, and 40W1, the current path portions 43H and 44L run parallel to one another. In each of the semiconductor devices 40U2, 40V2, and 40W2, the current path portions 43L and 44H run parallel to one another. In the adjacent semiconductor devices 40U1 and 40U2, the current path portions 43H and 44H run parallel to one another. In the adjacent semiconductor devices 40V1 and 40V2, the current path portions 43H and 44H run parallel to one another. In the adjacent semiconductor devices 40W1 and 40W2, the current path portions 43H and 44H run parallel to one another. In the adjacent semiconductor devices 40U2 and 40V1, the current path portions 43L and 44L run parallel to one another. In the adjacent semiconductor devices 40V2 and 40W1, the current path portions 43L and 44L run parallel to one another.

[0089] The semiconductor module 30 is not limited to the configuration illustrated in Fig. 6. As described above, the semiconductor module 30 that provides the inverters 21 and 22 may include at least one semiconductor device 40. The semiconductor device 40 is not limited to a configuration including one each of the semiconductor elements 41 and 42.

[0090] For example, as shown in FIG. 7 , a semiconductor device 40U1 may include, as the semiconductor elements 41, 42, two semiconductor elements 41UH that form the U-phase upper arm of the inverter 21 and two semiconductor elements 42UL that form the U-phase lower arm of the inverter 22. The two semiconductor elements 41UH are arranged on a wiring 452H that extends in the Y direction. The semiconductor elements 41UH are lined up in the Y direction. The output terminal 461A is joined to the source electrodes of the two semiconductor elements 41UH. The two semiconductor elements 41UH are connected in parallel to each other.

[0091] Similarly, the two semiconductor elements 42UL are arranged on a wiring 452L extending in the Y direction. The semiconductor elements 42UL are lined up in the Y direction. The N-terminal 46N is joined to the source electrodes of the two semiconductor elements 42UL. The two semiconductor elements 42UL are connected in parallel to each other. One of the semiconductor elements 41UH and one of the semiconductor elements 42UL are lined up in the X direction, and the other of the semiconductor elements 41UH and the other of the semiconductor elements 42UL are lined up in the X direction. A group of semiconductor elements 41UH and a group of semiconductor elements 42UL are lined up in the X direction. The current path portion 43H and the current path portion 43L run parallel to each other in the X direction.

[0092] The number of semiconductor elements 41, 42 connected in parallel is not limited to the example (two) shown in FIG. 7 . It may be three or more. While FIG. 7 illustrates an example in which the parallel-connected semiconductor elements 41, 42 are arranged side by side in the Y direction, this is not limiting. For example, as shown in FIG. 8 , two semiconductor elements 41UH may be arranged side by side in the X direction, and two semiconductor elements 42UL may be arranged side by side in the X direction. Four semiconductor elements 41, 42 may be arranged side by side in a row, with one semiconductor element 41UH adjacent to one semiconductor element 42UL. A group of semiconductor elements 41UH and a group of semiconductor elements 42UL are arranged side by side in the X direction. The current path portion 43H and the current path portion 43L run parallel to each other in the X direction. The other semiconductor devices 40 constituting the semiconductor module 30 may have a configuration similar to the semiconductor device 40U1 shown in FIGS. 7 and 8 .

[0093] The semiconductor device 40 is not limited to a configuration that provides two of the twelve arms of the inverters 21, 22 (8, 9). For example, as shown in FIG. 9 , a semiconductor device 40U may provide four arms that constitute the semiconductor module 30U. The semiconductor device 40U has a structure that integrates the two semiconductor devices 40U1, 40U2 described above. The semiconductor device 40U includes semiconductor elements 41UH, 41UL, 42UH, and 42UL. The semiconductor device 40U includes two output terminals 461A, two output terminals 462A, two P terminals 46P, and two N terminals 46N. In the example shown in FIG. 9 , two wirings 452H and two wirings 452L are provided on a single substrate 45. The semiconductor device 40U includes one each of current path portions 43H, 43L, 44H, and 44L.

[0094] The semiconductor elements 41UH, 41UL, 42UH, and 42UL are aligned in the X direction. In the X direction, the semiconductor elements 42UL, 41UH, 42UH, and 41UL are aligned in this order. The semiconductor element 42UL is arranged next to the semiconductor element 41UH. The semiconductor element 41UL is arranged next to the semiconductor element 42UH. The semiconductor element 41UH is arranged next to the semiconductor element 42UH. The current path portion 43H and the current path portion 44L run side by side in the X direction. The current path portion 43L and the current path portion 44H run side by side in the X direction. The current path portion 43H and the current path portion 44H run side by side in the X direction. The semiconductor devices 40 of the other phases that constitute the semiconductor module 30 may have a configuration similar to the semiconductor device 40U shown in FIG. 9 .

[0095] For example, as shown in Fig. 10, one semiconductor device 40S may provide one arm. The four semiconductor devices 40S shown in Fig. 10 constitute a semiconductor module 30U. One of the semiconductor devices 40S includes a semiconductor element 41UH and a current path portion 43H. Another of the semiconductor devices 40S includes a semiconductor element 41UL and a current path portion 43L. Another of the semiconductor devices 40S includes a semiconductor element 42UH and a current path portion 44H. Another of the semiconductor devices 40S includes a semiconductor element 42UL and a current path portion 44L.

[0096] The semiconductor elements 41UH, 41UL, 42UH, and 42UL are arranged in the X direction. In the X direction, the semiconductor elements 42UL, 41UH, 42UH, and 41UL are arranged in this order. The semiconductor element 42UL is arranged next to the semiconductor element 41UH. The semiconductor element 41UL is arranged next to the semiconductor element 42UH. The semiconductor element 42UH is arranged next to the semiconductor element 41UH. The current path portion 43H and the current path portion 44L run parallel to each other in the X direction. The current path portion 43L and the current path portion 44H run parallel to each other in the X direction. The other semiconductor devices 40 constituting the semiconductor module 30 may have a configuration similar to the semiconductor device 40S shown in FIG. 10 . That is, the semiconductor module 30 may include 12 semiconductor devices 40S.

[0097] Although not shown, the semiconductor module 30 may include only one semiconductor device 40. The semiconductor device 40 may have a structure in which, for example, the six semiconductor devices 40U1, 40U2, 40V1, 40V2, 40W1, and 40W2 described above are integrated together. Note that Figures 7 to 10 show other examples of the semiconductor device 40. Figures 7 to 10 correspond to Figure 6. Elements covered by the sealing body 47 are also shown in a see-through manner in Figures 7 to 10.

[0098] <Magnetic Flux Cancellation During Open Connection Drive> During open connection drive (H drive), one upper arm and the other lower arm are turned on in a common phase of inverters 21, 22 (8, 9). In the semiconductor module 30 described above, one upper arm element of inverters 21, 22 and the other lower arm element of inverters 21, 22 are arranged side by side in the common phase. A current path portion 43H including the upper arm element and a current path portion 44L including a lower arm element, or a current path portion 44H including the upper arm element and a current path portion 43L including a lower arm element, run parallel to each other.

[0099] FIG. 11 shows a semiconductor device 40W2 having the configuration shown in FIG. 6. In FIG. 11, dashed arrows indicate the current flowing when the W-phase lower arm 8L and the W-phase upper arm 9H are both ON, i.e., when both semiconductor elements 41WL and 42WH are ON, as illustrated in FIG. 4. In the semiconductor device 40W2, the semiconductor element 42WH is disposed adjacent to the semiconductor element 41WL. The current path portions 43L and 44H run parallel to each other. The current flowing through the current path portion 43H including the semiconductor element 42WH and the current flowing through the current path portion 43L including the semiconductor element 41WL are opposite to each other, as indicated by the dashed arrows. Therefore, magnetic flux cancellation can reduce inductance.

[0100] The same applies to the other semiconductor devices 40U1, 40U2, 40V1, 40V2, and 40W1, as well as to the configurations shown in other examples such as FIG.

[0101] <Magnetic Flux Cancellation During Star-Connection Drive> During star-connection drive (Y drive), the inverter 9 (22) is set to a neutral point, and the inverter 8 (21) is controlled according to drive requirements, etc. FIG. 12 shows a semiconductor module 30 having the configuration shown in FIG. 6. In FIG. 12, dashed arrows indicate the current that flows when all upper arms 9H of the inverter 9 are turned on to set the neutral point, and when both the U-phase upper arm 8H and the W-phase lower arm 8L of the inverter 8 are turned on, as shown in FIG. 3. In other words, the arrows indicate the current that flows when the semiconductor elements 42UH, 42VH, and 42WH are turned on to set the inverter 22 to a neutral point, and the semiconductor elements 41UH and 41WL are turned on.

[0102] In the X direction, semiconductor device 40U1 is disposed adjacent to semiconductor device 40U2. Semiconductor element 41UH is disposed adjacent to semiconductor element 42UH in the X direction. Current path portion 43H including semiconductor element 41UH and current path portion 44H including semiconductor element 42UH run parallel to each other. The current flowing through current path portion 43H including semiconductor element 41UH and the current flowing through current path portion 44H including semiconductor element 42UH are opposite in direction to each other, as indicated by the dashed arrows. Therefore, inductance can be reduced by magnetic flux cancellation.

[0103] In the semiconductor device 40W2, the semiconductor element 42WH is disposed adjacent to the semiconductor element 41WL. The current path portions 43L and 44H run parallel to each other. The current flowing through the current path portion 44H including the semiconductor element 42WH and the current flowing through the current path portion 43L including the semiconductor element 41WL are opposite to each other, as indicated by the dashed arrows. This allows for magnetic flux cancellation, thereby reducing inductance. The same applies to the configuration shown in other examples such as FIG. 10.

[0104] Summary of First Embodiment As described above, the power conversion device 20 of this embodiment includes two inverters 21, 22 (8, 9) connected to a common rotating electric machine 3. The inverters 21, 22 are configured to include a semiconductor module 30. The semiconductor module 30 includes semiconductor elements 41, 42 and current path portions 43, 44. In the X direction, the semiconductor element 42 that configures the inverter 22 is located next to the semiconductor element 41 that configures the inverter 21, and at least a portion of the on-timing of the semiconductor element 41 overlaps with the on-timing of the semiconductor element 41. Furthermore, the current path portion 43 including the semiconductor element 41 and the current path portion 44 including the semiconductor element 42 run side by side in the X direction so that the currents flowing therethrough are opposite to each other.

[0105] With this arrangement, when adjacent semiconductor elements 41 and 42 are both on, the current flowing through current path portion 43 and the current flowing through current path portion 44 face each other in opposite directions. This cancels out the magnetic flux, reducing inductance. Note that inverter 21 (8) corresponds to the first inverter, and inverter 22 (9) corresponds to the second inverter. Semiconductor element 41 corresponds to the first semiconductor element, and semiconductor element 42 corresponds to the second semiconductor element. Current path portion 43 corresponds to the first current path portion, and current path portion 44 corresponds to the second current path portion. The X direction corresponds to the predetermined direction.

[0106] The semiconductor element 41 may constitute a predetermined phase of the inverter 21, and the semiconductor element 42 may constitute a predetermined phase of the inverter 22. In other words, adjacent semiconductor elements 41 and 42 may constitute a common phase, for example, a U-phase, in the inverters 21 and 22. When the semiconductor elements 41 and 42 are both turned on and a current flows through the common phase of the inverters 21 and 22, the current flowing through the current path portion 43 and the current flowing through the current path portion 44 are opposite to each other in the opposite directions. Therefore, magnetic flux cancellation can reduce inductance.

[0107] The inverter 21 may be connected to one end of the windings 3U, 3V, and 3W of the rotating electric machine 3, and the inverter 22 may be connected to the other end of the windings 3U, 3V, and 3W. The inverters 21 and 22 may be configured to be switchable between star connection drive, in which the inverter 22 serves as a neutral point, and open connection drive, in which the neutral point of the inverter 22 is opened and the voltage applied to the windings 3U, 3V, and 3W is controlled for each phase. In this configuration, during star connection drive, a current flows through a common phase of the inverters 21 and 22. During open connection drive, a current flows through a common phase of the inverters 21 and 22. By arranging the semiconductor elements 41 and 42 constituting a common phase adjacent to each other as described above, magnetic flux cancellation can be eliminated, thereby reducing inductance.

[0108] One of the semiconductor elements 41, 42 may be an upper arm element, and the other of the semiconductor elements 41, 42 may be a lower arm element. In open connection drive, the upper arm of one of the inverters 21, 22 and the lower arm of the other inverter 21, 22 are turned on in a common phase. By combining adjacent semiconductor elements 41, 42 as semiconductor element 41H and semiconductor element 42L and / or semiconductor element 41L and semiconductor element 42H, both semiconductor elements 41, 42 are turned on in open connection drive. Therefore, inductance can be reduced by magnetic flux cancellation.

[0109] The semiconductor module 30 may include at least one semiconductor device 40 having semiconductor elements 41 and 42, a P terminal 46P, an N terminal 46N, and output terminals 461A and 462A. One of the current path portions 43 and 44 may have a P terminal 46P, an upper arm element, and an output terminal 461A, and the other of the current path portions 43 and 44 may have an N terminal 46N, a lower arm element, and an output terminal 462A. In this manner, in a single semiconductor device, currents flow in opposite directions through the current path portions 43 and 44 during open-circuit operation. This reduces inductance through magnetic flux cancellation. Since the single semiconductor device 40 includes the semiconductor elements 41 and 42 and the adjacent current path portions 43 and 44, the overall size can be reduced. This enhances the effect of magnetic flux cancellation, further reducing inductance. The output terminal 461A corresponds to the first output terminal, and the output terminal 462A corresponds to the second output terminal.

[0110] The semiconductor module 30 may include two semiconductor devices 40 that constitute a common phase of the inverters 21 and 22. One of the semiconductor devices 40 includes semiconductor elements 41H and 42L and current path portions 43H and 44L. The other of the semiconductor devices 40 includes semiconductor elements 41L and 42H and current path portions 43L and 44H. The two semiconductor devices 40 may be arranged so that a current flowing through one current path portion 43 of the semiconductor device 40 and a current flowing through the other current path portion 44 of the semiconductor device 40 are opposite and opposite to each other. In star connection driving, currents flowing through adjacent current path portions 43 and 44 of the two semiconductor devices 40 are opposite and opposite to each other. As described above, in open connection driving, currents flowing through adjacent current path portions 43 and 44 of each semiconductor device are opposite and opposite to each other. Therefore, in both star connection driving and open connection driving, magnetic flux cancellation can reduce inductance.

[0111] The semiconductor module 30 may include, for example, semiconductor devices 40U1 and 40U2. The semiconductor device 40U1 includes semiconductor elements 41UH and 42UL and current path portions 43H and 44L. The semiconductor device 40U2 includes semiconductor elements 41UL and 42UH and current path portions 43L and 44H. The semiconductor devices 40U1 and 40U2 are arranged so that the current flowing through one current path portion 43 of the semiconductor devices 40U1 and 40U2 and the current flowing through the other current path portion 44 of the semiconductor devices 40U1 and 40U2 are opposite and opposite to each other. During star-connection operation, the currents flowing through adjacent current path portions 43 and 44 of the two semiconductor devices 40U1 and 40U2 are opposite and opposite to each other. This allows for magnetic flux cancellation, thereby reducing inductance. The same applies to the semiconductor devices 40V1 and 40V2, and the semiconductor devices 40W1 and 40W2.

[0112] The two semiconductor devices 40 constituting the common phase of the inverters 21, 22 may be arranged side by side in the X direction such that the upper arm elements 41H, 42H or the lower arm elements 41L, 42L are adjacent to each other in the X direction. For example, by arranging the two semiconductor devices 40 on a common plane such as a case or a cooler, the two semiconductor devices 40 satisfy a predetermined positional relationship, and the currents flowing through the adjacent current path portions 43, 44 of the two semiconductor devices 40 face each other in opposite directions. Therefore, with a simple configuration, inductance can be reduced by magnetic flux cancellation.

[0113] The semiconductor elements 41, 42 adjacent to each other in the X direction may both be upper arm elements 41H, 42H, or both be lower arm elements 41L, 42L. When star-connected, currents flowing through adjacent current path portions 43, 44 of two semiconductor devices 40 face each other in opposite directions. This allows magnetic flux cancellation, reducing inductance. Although not shown, a single semiconductor device 40 may include upper arm elements 41H, 42H that form a common phase of the inverters 21, 22 as the adjacent semiconductor elements 41, 42. The semiconductor device 40 may also include lower arm elements 41L, 42L that form a common phase of the inverters 21, 22.

[0114] The semiconductor elements 41 and 42 may be formed by forming a MOSFET on a SiC substrate. This configuration reduces inductance and, in turn, switching surges. This, for example, increases switching speed. Furthermore, it is possible to suppress an increase in the number of elements.

[0115] Second Embodiment This embodiment is a modification of the preceding embodiment, and the description of the preceding embodiment can be used. In the preceding embodiment, an example was shown in which two inverters were connected to an open-winding rotating electric machine. Alternatively, two inverters are connected to a star-connected rotating electric machine. FIG. 13 shows a drive system 1 and a power conversion circuit 4 according to this embodiment. FIG. 13 shows the circuit configuration of the power conversion circuit 4. Like the preceding embodiment, the drive system 1 includes a DC power supply 2, a rotating electric machine 3, and a power conversion circuit 4. The rotating electric machine (REM) 3 is a star-connected rotating electric machine. The rotating electric machine 3 includes, for example, 2×3-phase windings. In the example shown in FIG. 13 , the rotating electric machine 3 includes six-phase windings: U1, V1, W1, U2, V2, and W2. The U2, V2, and W2 windings are wound so as not to cause a phase difference with respect to the corresponding U1, V1, and W1 windings.

[0116] As in the previous embodiment, the power conversion circuit 4 includes two inverters 8 and 9. Inverter 8 drives a three-phase rotating electric machine, and inverter 9 drives the remaining three-phase rotating electric machine. Node U1 of inverter 8 is connected to the U1-phase winding, node V1 is connected to the V1-phase winding, and node W1 is connected to the W1-phase winding. Node U2 of inverter 9 is connected to the U2-phase winding, node V2 is connected to the V2-phase winding, and node W2 is connected to the W2-phase winding.

[0117] The power conversion circuit 4 includes a smoothing capacitor 71 and a smoothing capacitor 72. The smoothing capacitor 71 is provided between the DC power supply 2 and the inverter 8. The smoothing capacitor 71 is connected in parallel to the inverter 8. The smoothing capacitor 72 is provided between the DC power supply 2 and the inverter 9. The smoothing capacitor 72 is connected in parallel to the inverter 9.

[0118] FIG. 14 shows an example of a power conversion device 20 and a semiconductor module 30. As in the preceding embodiment, the power conversion device 20 includes at least a semiconductor module 30 that constitutes inverters 21 and 22. The semiconductor module 30 includes at least one semiconductor device 40. The configuration of the semiconductor device 40 is the same as in the preceding embodiment. A single semiconductor device 40 may provide one arm or multiple arms. For convenience, the insulating base material 451 and the sealing body 47 that constitute the substrate 45 are omitted from FIG. 14.

[0119] Similar to the previous embodiment, the semiconductor module 30 includes semiconductor elements 41 and 42 and current path portions 43 and 44. The semiconductor element 41 constitutes the inverter 21 (8), and the semiconductor element 42 constitutes the inverter 22 (9). The semiconductor element 41 includes elements 41UH and 41UL that constitute the upper and lower arm circuit 8HL of the U1 phase, elements 41VH and 41VL that constitute the upper and lower arm circuit 8HL of the V1 phase, and elements 41WH and 41WL that constitute the upper and lower arm circuit 8HL of the W1 phase. The semiconductor element 42 includes elements 42UH and 42UL that constitute the upper and lower arm circuit 9HL of the U2 phase, elements 42VH and 42VL that constitute the upper and lower arm circuit 9HL of the V2 phase, and elements 42WH and 42WL that constitute the upper and lower arm circuit 9HL of the W2 phase.

[0120] The semiconductor elements 41 and 42 are aligned in the X direction. The semiconductor elements 41 and 42 are arranged alternately in the X direction. The semiconductor elements 41 and 42 are arranged so that elements whose on-timings at least partially overlap are adjacent to each other. In the example shown in Fig. 14, the upper arm elements 41H and 42H of a common phase are arranged adjacent to each other, and the lower arm elements 41L and 42L of a common phase are arranged adjacent to each other.

[0121] Specifically, semiconductor element 42UH is arranged next to semiconductor element 41UH. Semiconductor element 42VH is arranged next to semiconductor element 41VH. Semiconductor element 42WH is arranged next to semiconductor element 41WH. Semiconductor element 42UL is arranged next to semiconductor element 41UL. Semiconductor element 42VL is arranged next to semiconductor element 41VL. Semiconductor element 42WL is arranged next to semiconductor element 41WL. Semiconductor module 30 includes semiconductor module 30U that provides the U1 and U2 phases of inverters 21 and 22, semiconductor module 30V that provides the V1 and V2 phases, and semiconductor module 30W that provides the W1 and W2 phases. Semiconductor modules 30U, 30V, and 30W are aligned in the X direction.

[0122] As in the previous embodiment, the current path portion 43 includes a semiconductor element 41. The current path portion 44 includes a semiconductor element 42. The current path portions 43 and 44 run parallel to each other in the X direction so that currents flow in opposite directions. Specifically, the current path portions 43H and 44H of a common phase run parallel to each other. The current path portions 43L and 44 of a common phase run parallel to each other. The current path portions 43H and 44H have opposite arrangements of the P terminal 46P and the output terminals 461A and 462A in the Y direction so that the current flows in opposite directions. Similarly, the current path portions 43L and 44L have opposite arrangements of the N terminal 46N and the output terminals 461A and 462A in the Y direction so that the current flows in opposite directions.

[0123] Summary of Second Embodiment The power conversion device 20 of this embodiment also includes two inverters 21, 22 (8, 9) connected to a common rotating electric machine 3. The semiconductor modules 30 constituting the inverters 21, 22 include semiconductor elements 41, 42 and current path portions 43, 44. In the X direction, the semiconductor element 42 constituting the inverter 22 is located next to the semiconductor element 41 constituting the inverter 21, and at least a portion of the on-timing of the semiconductor element 41 overlaps with the on-timing of the semiconductor element 41. Furthermore, the current path portion 43 including the semiconductor element 41 and the current path portion 44 including the semiconductor element 42 run side by side in a predetermined direction so that the currents flowing therethrough are opposite to each other.

[0124] With this arrangement, when the adjacent semiconductor elements 41 and 42 are both turned on, the current flowing through the current path portion 43 and the current flowing through the current path portion 44 are opposite to each other in the opposite directions. Therefore, the magnetic fluxes are cancelled out, thereby reducing inductance.

[0125] The semiconductor element 41 may constitute a predetermined phase of the inverter 21, and the semiconductor element 42 may constitute a predetermined phase of the inverter 22. In other words, adjacent semiconductor elements 41 and 42 may constitute a common phase, for example, the U1 and U2 phases, of the inverters 21 and 22. When the semiconductor elements 41 and 42 are both turned on and a current flows through the common phase of the inverters 21 and 22, the current flowing through the current path portion 43 and the current flowing through the current path portion 44 are opposite to each other in the opposite directions. Therefore, magnetic flux cancellation can reduce inductance.

[0126] The dashed arrows in FIG. 14 indicate the currents that flow when the upper arm elements of the U1 and U2 phases and the lower arm elements of the W1 and W2 phases are turned on. In other words, they indicate the currents that flow when the semiconductor elements 41UH, 42UH, 41WL, and 42WL are turned on. The currents that flow through the current path portion 43H including the semiconductor element 41UH and the currents that flow through the current path portion 44H including the semiconductor element 42UH are opposite and flow in the same direction. Therefore, magnetic flux cancellation can reduce inductance. The currents that flow through the current path portion 43L including the semiconductor element 41WL and the current path portion 44L including the semiconductor element 42WL are opposite and flow in the same direction. Therefore, magnetic flux cancellation can reduce inductance.

[0127] Adjacent semiconductor elements 41, 42 are not limited to being of the same phase. It is sufficient that a semiconductor element 42 constituting inverter 22, at least a portion of whose on-timing overlaps with the on-timing of semiconductor element 41, is positioned adjacent to semiconductor element 41 constituting inverter 21. For example, a semiconductor element 42 providing a different phase from semiconductor element 41, at least a portion of whose on-timing overlaps with the on-timing of semiconductor element 41, may be positioned adjacent to semiconductor element 41. Then, current path portions 43, 44 may be positioned parallel to each other so that the currents flowing in opposite directions face each other.

[0128] (Other Embodiments) The disclosure in this specification and drawings, etc. is not limited to the exemplified embodiments. The disclosure encompasses the exemplified embodiments and modifications thereto by those skilled in the art. For example, the disclosure is not limited to the combinations of parts and / or elements shown in the embodiments. The disclosure can be implemented in various combinations. The disclosure can have additional parts that can be added to the embodiments. The disclosure encompasses the omission of parts and / or elements from the embodiments. The disclosure encompasses the substitution or combination of parts and / or elements between one embodiment and another embodiment. The disclosed technical scope is not limited to the description of the embodiments. Some disclosed technical scopes are defined by the claims, and should be interpreted as including all modifications within the meaning and scope equivalent to the claims.

[0129] The disclosure in the specification, drawings, etc. is not limited by the claims. The disclosure in the specification, drawings, etc. encompasses the technical ideas described in the claims, and extends to more diverse and broader technical ideas than the technical ideas described in the claims. Therefore, various technical ideas can be extracted from the disclosure in the specification, drawings, etc. without being bound by the claims.

[0130] When an element or layer is referred to as being "on," "coupled," "connected," or "coupled," it may be directly on, coupled, connected, or coupled to another element or layer, and intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly coupled," "directly connected," or "directly coupled" to another element or layer, there are no intervening elements or layers present. Other language used to describe relationships between elements should be construed in a similar manner (e.g., "between" vs. "directly between," "adjacent" vs. "directly adjacent," etc.). As used in this specification, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0131] Spatially relative terms such as "inside," "outside," "back," "below," "low," "top," "top," and the like are used herein to facilitate the description of one element or feature's relationship to other elements or features, as illustrated. Spatially relative terms may be intended to encompass different orientations of the device during use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures were turned over, elements described as "below" or "directly below" other elements or features would then be oriented "above" the other elements or features. Thus, the term "bottom" can encompass both an orientation of top and bottom. The device may also be oriented in other ways (rotated 90 degrees or at other orientations), and the spatially relative descriptors used in this specification would be interpreted accordingly.

[0132] (Disclosure of Technical Ideas) This specification discloses multiple technical ideas described in the following multiple clauses. Some clauses may be described in a multiple dependent form, with the subsequent clause alternatively referring to the preceding clause. Furthermore, some clauses may be described in a multiple dependent form, with the subsequent clause referring to another multiple dependent clause. These multiple dependent clauses define multiple technical ideas.

[0133] <Technical Idea 1> A semiconductor module constituting two inverters connected to a common rotating electric machine (3), comprising: a first semiconductor element (41, 41H, 41L) constituting a first inverter (8, 21) that is one of the inverters; a second semiconductor element (42, 42H, 42L) constituting a second inverter (9, 22) that is the other of the inverters, and having at least a portion of its on-timing overlapping with the on-timing of the first semiconductor element; a first current path portion (43, 43H, 43L) including the first semiconductor element; and a second current path portion (44, 44H, 44L) including the second semiconductor element, wherein the second semiconductor element is disposed next to the first semiconductor element in a predetermined direction, and the first current path portion and the second current path portion run side by side in the predetermined direction so that currents flow in opposite directions opposite to each other.

[0134] <Technical Concept 2> The semiconductor module according to Technical Concept 1, wherein the first semiconductor element constitutes a predetermined phase of the first inverter, and the second semiconductor element constitutes the predetermined phase of the second inverter.

[0135] <Technical Idea 3> The semiconductor module according to Technical Idea 2, wherein the first inverter is connected to one end of the windings (3U, 3V, 3W) of the rotating electric machine, and the second inverter is connected to the other end of the windings, and the first inverter and the second inverter are switchable between star connection drive in which the second inverter serves as a neutral point, and open connection drive in which the second inverter opens the neutral point and controls the voltage applied to the windings for each phase.

[0136] <Technical Concept 4> The semiconductor module according to Technical Concept 3, wherein one of the first semiconductor element and the second semiconductor element is an upper arm element, and the other of the first semiconductor element and the second semiconductor element is a lower arm element.

[0137] <Technical Idea 5> A semiconductor module according to Technical Idea 4, including at least one semiconductor device (40) including: the first semiconductor element; the second semiconductor element; a high potential power supply terminal (46P); a low potential power supply terminal (46N) arranged alongside the high potential power supply terminal in the predetermined direction; a first output terminal (461A) provided corresponding to the high potential power supply terminal; and a second output terminal (462A) provided corresponding to the low potential power supply terminal, wherein one of the first current path portion and the second current path portion has the high potential power supply terminal, the upper arm element, and the first output terminal, and the other of the first current path portion and the second current path portion has the low potential power supply terminal, the lower arm element, and the second output terminal.

[0138] <Technical Idea 6> A semiconductor module according to Technical Idea 4 or Technical Idea 5, comprising: a first semiconductor device (40U1, 40V1, 40W1) including the upper arm element of the first inverter, the lower arm element of the second inverter, the first current path portion, and the second current path portion, as semiconductor devices constituting a common phase of the first inverter and the second inverter; and a second semiconductor device (40U2, 40V2, 40W2) including the lower arm element of the first inverter, the upper arm element of the second inverter, the first current path portion, and the second current path portion, wherein the first semiconductor device and the second semiconductor device are arranged such that a current flowing through the first current path portion of one of the first semiconductor device and the second semiconductor device and a current flowing through the second current path portion of the other of the first semiconductor device and the second semiconductor device are opposite to each other in the opposite directions.

[0139] <Technical Idea 7> A semiconductor module according to Technical Idea 6, wherein the first semiconductor device and the second semiconductor device are arranged side by side in the predetermined direction such that the upper arm elements or the lower arm elements are adjacent to each other in the predetermined direction.

[0140] <Technical Concept 8> The semiconductor module according to Technical Concept 3, wherein the first semiconductor element and the second semiconductor element are both upper arm elements or both lower arm elements.

[0141] <Technical Concept 9> The semiconductor module according to any one of Technical Concepts 1 to 8, wherein the first semiconductor element and the second semiconductor element are MOSFETs formed on a SiC substrate.

Claims

1. A semiconductor module constituting two inverters connected to a common rotating electric machine (3), comprising: a first semiconductor element (41, 41H, 41L) constituting a first inverter (8, 21) that is one of the inverters; a second semiconductor element (42, 42H, 42L) constituting a second inverter (9, 22) that is the other of the inverters, and having at least a portion of its on-timing overlapping with the on-timing of the first semiconductor element; a first current path portion (43, 43H, 43L) including the first semiconductor element; and a second current path portion (44, 44H, 44L) including the second semiconductor element, wherein the second semiconductor element is disposed next to the first semiconductor element in a predetermined direction, and the first current path portion and the second current path portion run side by side in the predetermined direction such that currents flow in opposite directions facing each other.

2. The semiconductor module according to claim 1, wherein the first semiconductor element constitutes a predetermined phase of the first inverter, and the second semiconductor element constitutes the predetermined phase of the second inverter.

3. A semiconductor module as described in claim 2, wherein the first inverter is connected to one end of the windings (3U, 3V, 3W) of the rotating electric machine and the second inverter is connected to the other end of the windings, and the first inverter and the second inverter are switchable between star connection drive in which the second inverter serves as a neutral point and open connection drive in which the neutral point is opened by the second inverter and the voltage applied to the windings for each phase is controlled.

4. The semiconductor module according to claim 3, wherein one of the first semiconductor element and the second semiconductor element is an upper arm element, and the other of the first semiconductor element and the second semiconductor element is a lower arm element.

5. The semiconductor module according to claim 4, comprising at least one semiconductor device (40) comprising: the first semiconductor element; the second semiconductor element; a high potential power supply terminal (46P); a low potential power supply terminal (46N) arranged alongside the high potential power supply terminal in the specified direction; a first output terminal (461A) provided in correspondence with the high potential power supply terminal; and a second output terminal (462A) provided in correspondence with the low potential power supply terminal, wherein one of the first current path portion and the second current path portion has the high potential power supply terminal, the upper arm element, and the first output terminal, and the other of the first current path portion and the second current path portion has the low potential power supply terminal, the lower arm element, and the second output terminal.

6. The semiconductor module according to claim 4 or 5, comprising: a first semiconductor device (40U1, 40V1, 40W1) having the upper arm element of the first inverter, the lower arm element of the second inverter, the first current path portion, and the second current path portion, as semiconductor devices constituting a common phase of the first inverter and the second inverter; and a second semiconductor device (40U2, 40V2, 40W2) having the lower arm element of the first inverter, the upper arm element of the second inverter, the first current path portion, and the second current path portion, wherein the first semiconductor device and the second semiconductor device are arranged such that a current flowing through the first current path portion of one of the first semiconductor device and the second semiconductor device and a current flowing through the second current path portion of the other of the first semiconductor device and the second semiconductor device face each other in opposite directions.

7. The semiconductor module according to claim 6, wherein the first semiconductor device and the second semiconductor device are arranged side by side in the specified direction such that the upper arm elements or the lower arm elements are adjacent to each other in the specified direction.

8. The semiconductor module according to claim 3, wherein the first semiconductor element and the second semiconductor element are both upper arm elements or both lower arm elements.

9. The semiconductor module according to any one of claims 1 to 3, wherein the first semiconductor element and the second semiconductor element are MOSFETs formed on a SiC substrate.

10. A power conversion device comprising: a first inverter (8, 21) connected to a rotating electric machine (3); and a second inverter (9, 22) connected to the rotating electric machine, wherein the first inverter and the second inverter are configured to include a semiconductor module (30), wherein the semiconductor module has: a first semiconductor element (41, 41H, 41L) constituting the first inverter; a second semiconductor element (42, 42H, 42L) constituting the second inverter, the second semiconductor element having at least a portion of its on-timing overlapping with the on-timing of the first semiconductor element; a first current path portion (43, 43H, 43L) including the first semiconductor element; and a second current path portion (44, 44H, 44L) including the second semiconductor element, wherein the second semiconductor element is disposed next to the first semiconductor element in a predetermined direction, and the first current path portion and the second current path portion run side by side in the predetermined direction such that currents flow in opposite directions facing each other.

11. A power conversion device as described in claim 10, wherein the first inverter is connected to one end of the windings (3U, 3V, 3W) of the rotating electric machine and the second inverter is connected to the other end of the windings, the first inverter and the second inverter are switchable between star connection drive that neutralizes the second inverter and open connection drive that opens the neutral point by the second inverter and controls the voltage applied to the windings for each phase, the first semiconductor element constitutes a specified phase of the first inverter, and the second semiconductor element constitutes the specified phase of the second inverter.

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