Imaging device

Abstract

This imaging device is provided with: a first semiconductor substrate having a first surface and a second surface on the opposite side from the first surface; and a plurality of pixels. The first semiconductor substrate includes: a first-conductivity-type first impurity region which is at least partially positioned on the first surface; a first-conductivity-type second impurity region which is positioned closer to the second surface, as compared to the first impurity region; a first-conductivity-type third impurity region which is positioned between the first impurity region and the second impurity region; and at least one first-conductivity-type fourth impurity region which penetrates the third impurity region and which electrically connects the first impurity region and the second impurity region. Each of the plurality of pixels includes a photoelectric conversion unit which converts light into an electric charge, and a second-conductivity-type fifth impurity region which is positioned in the first impurity region and which accumulates the electric charge. The impurity concentration of the second impurity region is higher than the impurity concentration of the first impurity region.

Description

Imaging device

[0001] The present disclosure relates to an imaging device.

[0002] 2. Description of the Related Art Conventionally, an imaging device for capturing an image has been known, as described in, for example, Japanese Patent Application Laid-Open No. 2003-144996.

[0003] Japanese Patent Application Laid-Open No. 2019-029399

[0004] The present disclosure provides techniques suitable for improving image quality.

[0005] An imaging device according to the present disclosure includes a first semiconductor substrate having a first surface and a second surface opposite to the first surface, and a plurality of pixels. The first semiconductor substrate includes: a first impurity region of a first conductivity type, at least a portion of which is located in the first surface; a second impurity region of the first conductivity type located closer to the second surface than the first impurity region; a third impurity region of the first conductivity type located between the first impurity region and the second impurity region; and at least one fourth impurity region of the first conductivity type penetrating the third impurity region and electrically connecting the first impurity region and the second impurity region. Each of the plurality of pixels includes: a photoelectric conversion unit that converts light into electric charges; and a fifth impurity region of a second conductivity type that is located in the first impurity region and accumulates the electric charges. The impurity concentration of the second impurity region is higher than the impurity concentration of the first impurity region.

[0006] The technology according to the present disclosure is suitable for improving image quality.

[0007] FIG. 1 is a schematic diagram illustrating an exemplary configuration of an imaging device according to a first embodiment. FIG. 2 is a schematic diagram illustrating an exemplary circuit configuration of an imaging device according to the first embodiment. FIG. 3 is a plan view illustrating a layout within a pixel according to the first embodiment. FIG. 4 is a schematic cross-sectional view of a device structure obtained by cutting a pixel along line IV-IV in FIG. 3 and expanding it in the direction of the arrows. FIG. 5 is a cross-sectional view illustrating an exemplary configuration in which a well region is disposed in an area that occupies less than 100% of the area of ​​the pixel in a plan view. FIG. 6 is a plan view illustrating the layout within a plurality of pixels according to a second embodiment, showing the positions of a plurality of well contacts in a semiconductor substrate in a plan view. FIG. 7 is a plan view illustrating the layout within a plurality of pixels according to a third embodiment, showing the positions of a plurality of well contacts in a semiconductor substrate in a plan view. FIG. 8 is a schematic cross-sectional view of a device structure obtained by cutting a pixel along line VIII-VIII in FIG. 7 and expanding it in the direction of the arrows. FIG. 9 is a plan view illustrating the layout within a plurality of pixels according to a fourth embodiment, showing the positions of well contacts in a semiconductor substrate in a plan view. FIG. 10 is a plan view illustrating a specific example of the fourth embodiment. FIG. 11 is a plan view showing the layout of a plurality of pixels in the fifth embodiment, showing the positions of well contacts in a semiconductor substrate in a plan view. FIG. 12 is a plan view showing a specific example of the fifth embodiment. FIG. 13 is a plan view showing the layout of a plurality of pixels in a first example of the sixth embodiment, showing the positions of well contacts in a semiconductor substrate in a plan view. FIG. 14 is a plan view showing the layout of a plurality of pixels in a second example of the sixth embodiment, showing the positions of well contacts in a semiconductor substrate in a plan view. FIG. 15 is a plan view showing the layout of a plurality of pixels in the seventh embodiment, showing the positions of well contacts in a semiconductor substrate in a plan view. FIG. 16 is a plan view showing the layout of a plurality of pixels in the eighth embodiment, showing the positions of well contacts in a semiconductor substrate in a plan view and the positions of surface-side contacts in a plan view. FIG. 17 is a cross-sectional view for explaining the surface-side contact. FIG. 18 is a cross-sectional view of the ninth embodiment, showing the cross-section of the imaging region and the cross-section of the guard ring region.FIG. 19 is a cross-sectional view of a tenth embodiment showing a cross-section of the imaging region and a cross-section of the guard ring region. FIG. 20 is a cross-sectional view of an eleventh embodiment showing a cross-section of the imaging region and a cross-section of the peripheral region and the guard ring region. FIG. 21 is a cross-sectional view of a twelfth embodiment showing a cross-section of the imaging region and a cross-section of the guard ring region. FIG. 22 is a cross-sectional view of a thirteenth embodiment showing a cross-section of the imaging region and a cross-section of the guard ring region. FIG. 23 is a graph showing an example of impurity concentration distributions of a well contact, a well region, a semiconductor region, and a support substrate in a direction from the first surface to the second surface of a semiconductor substrate. FIG. 24 is a cross-sectional view of a fourteenth embodiment showing a cross-section of the imaging region and a cross-section of the guard ring region. FIG. 25 is a cross-sectional view of a fifteenth embodiment showing a cross-section of the imaging region and a cross-section of the guard ring region. FIG. 26 schematically shows an example of the configuration of a camera system according to a sixteenth embodiment.

[0008] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component arrangements, connection forms, etc. shown in the following embodiments are merely examples and are not intended to limit the present disclosure. The various aspects described in the embodiments can be combined with each other unless a contradiction occurs. Furthermore, the components in the following embodiments are merely illustrative. In each drawing, components having substantially the same function are designated by the same reference numerals, and redundant explanations may be omitted or simplified.

[0009] Furthermore, the various elements shown in the drawings are merely shown schematically to facilitate understanding of the present disclosure, and the dimensional ratios and appearances may differ from those of the actual objects.

[0010] In the embodiments, terms such as "upper," "lower," "front," and "rear" are used merely to specify the relative positions of components, and are not intended to limit the orientation of the imaging device when in use. In the embodiments, "planar view" refers to a view from a direction perpendicular to the semiconductor substrate.

[0011] In the embodiments, the terms "front surface contact" and "rear surface contact" may be used. The front surface contact can be used to fix the potential of the well from the front surface side of the substrate as viewed from the well of the substrate. The rear surface contact can be used to fix the potential of the well from the rear surface side of the substrate as viewed from the well. The front surface of the substrate is the first surface 60s1 in the configuration example of FIG. 4 etc., and is typically the surface on which elements are formed. The rear surface of the substrate is the second surface 60s2 in the configuration example of FIG. 4 etc., and is typically the surface on which elements are not formed. The front surface and rear surface are located on opposite sides of each other.

[0012] 1 is a schematic diagram illustrating an exemplary configuration of an image pickup device according to a first embodiment. The image pickup device 100 illustrated in FIG. 1 includes an image pickup region R1. Photoelectric conversion is performed in the image pickup region R1. The image pickup region R1 includes a plurality of pixels 10.

[0013] 1, a plurality of pixels 10 are arranged in a plurality of row directions and column directions. As a result, a pixel array made up of the plurality of pixels 10 is formed in the imaging region R1. The imaging region R1 is rectangular. The row direction and column direction refer to the directions in which the rows and columns extend, respectively.

[0014] The number and arrangement of the pixels 10 are not limited to the example shown in Fig. 1. In the example of Fig. 1, the center of each pixel 10 is located on a lattice point of a square lattice, but, for example, the plurality of pixels 10 may be arranged so that the center of each pixel 10 is located on a lattice point of a triangular lattice, a hexagonal lattice, or the like. For example, the pixels 10 may be arranged one-dimensionally, in which case the imaging device 100 may be used as a line sensor.

[0015] Each of the pixels 10 has a photoelectric conversion unit 12 and a signal detection circuit 14. The photoelectric conversion unit 12 is supported on a semiconductor substrate 60. The signal detection circuit 14 is provided on the semiconductor substrate 60 and is electrically connected to the photoelectric conversion unit 12.

[0016] The imaging device 100 includes a peripheral region R2. The peripheral region R2 is located outside the imaging region R1 in a plan view. The peripheral region R2 includes a peripheral circuit 40. The peripheral circuit 40 drives a plurality of pixels 10.

[0017] The peripheral circuit 40 includes a vertical scanning circuit 46, a horizontal signal readout circuit 44, a voltage supply circuit 48, a control circuit 42, an analog circuit 41, and a logic circuit 43. In the example of Fig. 1, some or all of these circuits are provided on the semiconductor substrate 60, similar to the signal detection circuit 14 of each pixel.

[0018] The arrangement of the peripheral region R2 and the peripheral circuit 40 is not limited to the example shown in FIG. 1 . For example, the imaging region R1 and the peripheral region R2 may be stacked on top of each other. In this case, the imaging region R1 and the peripheral circuit 40 may be stacked on top of each other. This stacked structure is exemplified, for example, in embodiments 10 and 11 shown in FIGS. 19 and 20 , which will be described later. In the example shown in FIGS. 19 and 20 , a semiconductor substrate 60 and a semiconductor substrate 260 are stacked on top of each other, a plurality of pixels are formed using the semiconductor substrate 60, and some or all of the vertical scanning circuit 46, the horizontal signal readout circuit 44, the voltage supply circuit 48, the control circuit 42, the analog circuit 41, and the logic circuit 43 are provided on the semiconductor substrate 260.

[0019] The imaging device 100 includes a guard ring region R3. In a plan view, the guard ring region R3 is disposed outside the imaging region R1. In the example of Fig. 1, the guard ring region R3 surrounds the imaging region R1 in a plan view. Also, in the example of Fig. 1, the guard ring region R3 is disposed between the imaging region R1 and the peripheral region R2 in a plan view.

[0020] The guard ring region R3 includes a well region 65p and a plurality of plugs px. The well region 65p is provided in the semiconductor substrate 60. The well region 65p is a p-type impurity region. The plugs px are connected to the semiconductor substrate 60.

[0021] The plurality of plugs px are electrically connected to the well region 65p. When the imaging device 100 is in operation, a predetermined voltage is applied from the voltage supply circuit 48 to the well region 65p via the plurality of plugs px.

[0022] An element isolation region 69 is provided in the boundary between the imaging region R1 and the guard ring region R3 in the semiconductor substrate 60. This element isolation region 69 can reduce noise from the peripheral circuit 40 to the pixel 10.

[0023] A guard ring region R3 is disposed outside the imaging region R1 in a plan view, and includes a well region 65p and a plurality of plugs px, allowing a voltage to be applied from the voltage supply circuit 48 to the well region 65p via the plurality of plugs px. Therefore, during operation of the imaging device 100, the potential of the well region 65p can be fixed to a predetermined potential. The predetermined potential is, for example, ground potential, i.e., 0 V.

[0024] The imaging device 100 has a plurality of address signal lines 34. A vertical scanning circuit 46 is connected to the plurality of address signal lines 34. These address signal lines 34 are provided corresponding to each row of a plurality of pixels 10. Each address signal line 34 is connected to one or more pixels 10 belonging to the corresponding row. The vertical scanning circuit 46 controls the timing of reading out signals from the pixels 10 to the vertical signal lines 35 by applying a row selection signal to the address signal line 34. The vertical scanning circuit 46 is also called a row scanning circuit. Note that the signal lines connected to the vertical scanning circuit 46 are not limited to the address signal lines 34. A plurality of types of signal lines may be connected to the vertical scanning circuit 46 for each row of a plurality of pixels 10.

[0025] The analog circuit 41 generates a reference signal, performs noise cancellation, etc. In this embodiment, the analog circuit 41 includes a column signal processing circuit 47 and a load circuit 45, which will be described later with reference to FIG.

[0026] The imaging device 100 has a plurality of vertical signal lines 35. The vertical signal lines 35 are provided for each column of the pixels 10. Each vertical signal line 35 is connected to one or more pixels belonging to the corresponding column. These vertical signal lines 35 are connected to a horizontal signal readout circuit 44.

[0027] The horizontal signal readout circuit 44 reads out signals from the pixels 10. The horizontal signal readout circuit 44 is also called a column scanning circuit. The output signals output from the horizontal signal readout circuit 44 are supplied to the logic circuit 43. The logic circuit 43 holds, rearranges, and performs parallel-to-serial conversion on the output signals.

[0028] The control circuit 42 controls the entire image pickup apparatus 100. In this control, the image pickup apparatus 100 receives and uses a clock, command data, etc. The clock and command data are provided from outside the image pickup apparatus 100, for example.

[0029] The control circuit 42 typically has a timing generator and supplies drive signals to the vertical scanning circuit 46, the horizontal signal readout circuit 44, the voltage supply circuit 48, etc. In FIG. 1 , arrows extending from the control circuit 42 schematically represent the flow of output signals from the control circuit 42. The control circuit 42 can be realized by, for example, a microcontroller including one or more processors. The functions of the control circuit 42 may be realized by a combination of a general-purpose processing circuit and software, or may be realized by hardware specialized for such processing.

[0030] The voltage supply circuit 48 is electrically connected to each pixel 10 in the imaging region R1. The voltage supply circuit 48 supplies a predetermined voltage to each pixel 10 via the voltage line 38. The voltage supply circuit 48 may supply a voltage to at least one circuit selected from the group consisting of the vertical scanning circuit 46, the horizontal signal readout circuit 44, the control circuit 42, the analog circuit 41, and the logic circuit 43. The voltage supply circuit 48 is not limited to a specific power supply circuit, and may be a circuit that converts a voltage supplied from a power source such as a battery into a predetermined voltage, or a circuit that generates a predetermined voltage. The voltage supply circuit 48 may be part of the vertical scanning circuit 46 described above.

[0031] In the example of FIG. 1 , vertical scanning by the vertical scanning circuit 46 outputs an analog signal (hereinafter, pixel signal) corresponding to the exposure state from each pixel 10. The analog circuit 41 converts the analog pixel signal into a digital pixel signal through analog-to-digital (AD) conversion. AD conversion is performed by comparing the voltage of a reference signal with the voltage of a pixel signal. Specifically, a reference signal is provided to one side of a comparator provided for each column, and a pixel signal is provided to the other side. The reference signal is an analog ramp signal whose voltage increases or decreases over time. In conjunction with the ramp signal, a counter starts counting from a reference time. When the sign of the difference obtained by subtracting the voltage of the reference signal from the voltage of the pixel signal is inverted, the comparator rises or falls, and the counter stops counting. The longer the counting period, the larger the value of the digital pixel signal generated. In this embodiment, the column signal processing circuit 47 of the analog circuit 41 includes a counter and performs AD conversion. The digital pixel signal is read out by the horizontal signal readout circuit 44. The horizontal signal readout circuit 44 stores in memory the pixel signal values ​​for each pixel 10. Thereafter, the pixel signal values ​​for each pixel 10 are sequentially output from the memory of the horizontal signal readout circuit 44 and are subjected to various corrections by the logic circuit 43.

[0032] 2 schematically illustrates an exemplary circuit configuration of the imaging device according to the first embodiment. To avoid complicating the drawing, four pixels 10 arranged in two rows and two columns are representatively illustrated in FIG. 2 . Each pixel 10 includes a signal detection circuit 14. The signal detection circuit 14 is electrically connected to the photoelectric conversion unit 12.

[0033] The photoelectric conversion unit 12 is connected to the counter electrode power supply wiring 31. When the imaging device 100 is in operation, a voltage is applied to the counter electrode power supply wiring 31. For example, if the positive charges of the positive and negative charges generated by photoelectric conversion in the photoelectric conversion unit 12 are used as signal charges, a positive voltage can be applied to the counter electrode power supply wiring 31 when the imaging device 100 is in operation. The following describes an example in which holes are used as signal charges.

[0034] Each pixel 10 includes a charge storage node 99. The charge storage node 99 stores electric charges. The charge storage node 99 includes a charge storage portion 67n, a gate electrode 22e of the amplification transistor 22, a pixel electrode 12a of the photoelectric conversion portion 12, wiring that electrically connects them, and the like. The charge storage node 99 is also called a floating diffusion node. The charge storage portion 67n is an impurity region provided in the semiconductor substrate 60.

[0035] The signal detection circuit 14 includes an amplifier transistor 22, a select transistor 24, and a reset transistor 26. The amplifier transistor 22, the select transistor 24, and the reset transistor 26 are typically field effect transistors provided on a semiconductor substrate 60. Unless otherwise specified, the following description will be given of an example in which an n-channel metal oxide semiconductor field effect transistor (MOSFET) is used as the transistor.

[0036] The gate electrode 22e of the amplification transistor 22 is electrically connected to the photoelectric conversion unit 12. The charge accumulation node 99 has a function of temporarily holding charges generated by the photoelectric conversion unit 12. By applying a voltage to the counter electrode power supply wiring 31 during operation, it is possible to accumulate, for example, holes as signal charges in the charge accumulation node 99.

[0037] One of the source and drain of the amplification transistor 22 is connected to a power supply wiring 32. The power supply wiring 32 supplies a power supply voltage VDD to each pixel 10 when the imaging device 100 is in operation. The power supply voltage VDD is, for example, about 3.3 V. The other of the source and drain of the amplification transistor 22 is connected to a vertical signal line 35 via a selection transistor 24. The potential of the charge accumulation node 99 or the potential of the charge accumulation unit 67 n takes a value corresponding to the amount of signal charge accumulated in the charge accumulation node 99. The amplification transistor 22 receives the power supply voltage VDD at one of its source and drain, and outputs a signal voltage corresponding to the above potential.

[0038] The selection transistor 24 is connected between the amplification transistor 22 and a vertical signal line 35. An address signal line 34 is connected to a gate electrode 24e of the selection transistor 24. The vertical scanning circuit 46 applies a row selection signal that controls the on / off of the selection transistor 24 to the address signal line 34, thereby reading out the output of the amplification transistor 22 of the selected pixel 10 to the corresponding vertical signal line 35. The position of the selection transistor 24 is not limited to the example shown in FIG. 2 , and may be between the amplification transistor 22 and the power supply line 32.

[0039] A load circuit 45 and a column signal processing circuit 47 are connected to each vertical signal line 35. The load circuit 45 and the amplifying transistor 22 form a source follower circuit. The column signal processing circuit 47 is also called a row signal accumulation circuit. The column signal processing circuit 47 performs noise canceling and AD conversion, as typified by correlated double sampling. The horizontal signal readout circuit 44 sequentially reads out signals from the multiple column signal processing circuits 47 to a horizontal common signal line 49.

[0040] A reset signal line 36 is connected to the gate electrode 26e of the reset transistor 26. The reset signal line 36 is connected to a vertical scanning circuit 46. Like the address signal lines 34, the reset signal lines 36 are provided for each row of pixels 10. The vertical scanning circuit 46 can select the pixels 10 to be reset on a row-by-row basis by applying a row selection signal to the address signal line 34, and can switch the reset transistors 26 of the selected row on and off by applying a reset signal to the gate electrode 26e of the reset transistor 26 via the reset signal line 36. When the reset transistor 26 is turned on, the potential of the charge storage node 99 is reset.

[0041] In this example, one of the source and drain of the reset transistor 26 is a charge storage unit 67 n. The other of the source and drain of the reset transistor 26 is connected to a corresponding one of feedback lines 53 provided for each column of multiple pixels 10. In this example, the voltage of the feedback line 53 is supplied to the charge storage node 99 as a reset voltage that initializes the charge of the photoelectric conversion unit 12.

[0042] The imaging device 100 has a feedback circuit 16. The feedback circuit 16 includes an inverting amplifier 50 and a feedback line 53. An inverting amplifier 50 is provided for each column of pixels 10. The feedback line 53 is connected to an output terminal of a corresponding one of the multiple inverting amplifiers 50. The inverting amplifier 50 can be included in the peripheral circuit 40.

[0043] The inverting input terminal of the inverting amplifier 50 is connected to the vertical signal line 35 of the corresponding column. A reference voltage Vref is supplied to the non-inverting input terminal of the inverting amplifier 50 during operation of the imaging device 100. The reference voltage Vref is, for example, a positive voltage of 1 V or close to 1 V. Turning on the selection transistor 24 and the reset transistor 26 forms a feedback path that negatively feeds back the output of the pixel 10. The formation of the feedback path causes the voltage of the vertical signal line 35 to converge to the reference voltage Vref input to the non-inverting input terminal of the inverting amplifier 50. In other words, the formation of the feedback path resets the voltage of the charge storage node 99 to a voltage that causes the voltage of the vertical signal line 35 to become Vref. The reference voltage Vref can be any voltage between the power supply voltage and ground. The formation of the feedback path reduces reset noise that occurs when the reset transistor 26 is turned off.

[0044] Fig. 3 is a plan view showing the layout within the pixel 10 in embodiment 1. Fig. 4 is a schematic cross-sectional view of the device structure when the pixel 10 is cut along line IV-IV in Fig. 3 and developed in the direction of the arrows. The cross section shown in Fig. 4 is a cross section parallel to the thickness direction of the semiconductor substrate 60.

[0045] In this embodiment, one pixel of the plurality of pixels 10 may be referred to as pixel 10a. The charge accumulation portion 67n in pixel 10a may be referred to as charge accumulation portion 67n1. The impurity region 68bn in pixel 10a may be referred to as impurity region 68bn1. The impurity region 68dn in pixel 10a may be referred to as impurity region 68dn1.

[0046] In each pixel 10, the semiconductor substrate 60 includes a charge accumulation portion 67n, an impurity region 68an, an impurity region 68bn, an impurity region 68cn, and an impurity region 68dn. The charge accumulation portion 67n, the impurity region 68an, the impurity region 68bn, the impurity region 68cn, and the impurity region 68dn are n-type impurity regions. The charge accumulation portion 67n is one of the source and drain of the reset transistor 26. The impurity region 68an is the other of the source and drain of the reset transistor 26. The impurity region 68bn is one of the source and drain of the amplifier transistor 22. The impurity region 68cn is the other of the source and drain of the amplifier transistor 22 and also the source and drain of the select transistor 24. The impurity region 68dn is the other of the source and drain of the select transistor 24.

[0047] The semiconductor substrate 60 includes an isolation region 69. The isolation region 69 has, for example, an STI (shallow trench isolation) structure. In a plan view, the isolation region 69 surrounds each of the amplifier transistor 22, the select transistor 24, and the reset transistor 26. An insulating layer 70 is provided on the semiconductor substrate 60. A portion of the insulating layer 70 between the gate electrode 26e of the reset transistor 26 and the semiconductor substrate 60 functions as a gate insulating film for the reset transistor 26. A portion of the insulating layer 70 between the gate electrode 22e of the amplifier transistor 22 and the semiconductor substrate 60 functions as a gate insulating film for the amplifier transistor 22. A portion of the insulating layer 70 between the gate electrode 24e of the select transistor 24 and the semiconductor substrate 60 functions as a gate insulating film for the select transistor 24.

[0048] The semiconductor substrate 60 includes a support substrate 61p, a semiconductor region 63p, a well region 65p, and a well contact 64. The support substrate 61p, the semiconductor region 63p, the well region 65p, and the well contact 64 are p-type impurity regions. Here, a p-type silicon (Si) substrate is exemplified as the support substrate 61p.

[0049] The semiconductor region 63p is disposed above the support substrate 61p. The well region 65p is disposed above the semiconductor region 63p. Specifically, the support substrate 61p, the semiconductor region 63p, and the well region 65p are disposed adjacent to each other in this order. In this way, a p-type three-layer structure, i.e., a "ppp layer," is formed.

[0050] The well contact 64 penetrates the semiconductor region 63p from the support substrate 61p side to the well region 65p side. The well contact 64 electrically connects the support substrate 61p and the well region 65p. The well contact 64 constitutes a back surface side contact.

[0051] Provided in the well region 65p are a charge accumulation portion 67n, impurity regions 68an to 68dn, and an element isolation region 69. Specifically, the well region 65p is provided across the entirety of the plurality of pixels 10 in plan view.

[0052] As described above, the impurity regions 68bn, 68cn, and 68dn are provided in the well region 65p, which is a common well. This allows the amplifier transistor 22 and the select transistor 24 to be arranged in series. Furthermore, the gate electrode 22e and the charge storage portion 67n are connected by wiring. This allows the amplifier transistor 22 and the reset transistor 26 to be arranged apart from each other.

[0053] As shown in FIG. 4 , the pixel 10 includes an interlayer insulating layer 90 and a wiring structure 80. The interlayer insulating layer 90 is provided between the photoelectric conversion unit 12 and the semiconductor substrate 60. The wiring structure 80 includes a portion disposed within the interlayer insulating layer 90. In the example of FIG. 4 , the interlayer insulating layer 90 has a stacked structure including four insulating layers: insulating layers 90a, 90b, 90c, and 90d (hereinafter, insulating layers 90a to 90d). The wiring structure 80 includes four wiring layers: wiring layers 80a, 80b, 80c, and 80d (hereinafter, wiring layers 80a to 80d), and plugs pa1, pa2, pb, pc, and pd (hereinafter, plugs pa1 to pd). Note that the number of insulating layers in the interlayer insulating layer 90 and the number of wiring layers in the wiring structure 80 are not limited to this example and can be set arbitrarily.

[0054] The photoelectric conversion unit 12 is disposed on the interlayer insulating layer 90. The photoelectric conversion unit 12 includes a pixel electrode 12a, a counter electrode 12c, and a photoelectric conversion layer 12b. The pixel electrode 12a is provided on the interlayer insulating layer 90. The counter electrode 12c faces the pixel electrode 12a.

[0055] The photoelectric conversion layer 12b is disposed between the pixel electrode 12a and the counter electrode 12c. The photoelectric conversion layer 12b contains, for example, an organic material or an inorganic material such as amorphous silicon. The photoelectric conversion layer 12b receives light incident through the counter electrode 12c and generates positive and negative charges by photoelectric conversion. The photoelectric conversion layer 12b is typically provided across multiple pixels 10. The photoelectric conversion layer 12b may include a layer containing an organic material and a layer containing an inorganic material.

[0056] The counter electrode 12c includes a transparent conductive material such as ITO (indium tin oxide). The counter electrode 12c is disposed on the light-receiving surface side of the photoelectric conversion layer 12b. The counter electrode 12c is typically provided across multiple pixels 10, similar to the photoelectric conversion layer 12b. Although not shown in FIG. 4 , the counter electrode 12c is connected to a counter electrode power supply wiring 31. During operation of the imaging device 100, the potential of the counter electrode power supply wiring 31 is controlled to make the potential of the counter electrode 12c different from the potential of the pixel electrode 12a, thereby allowing the pixel electrode 12a to collect signal charges generated by photoelectric conversion. For example, the potential of the counter electrode power supply wiring 31 is controlled so that the potential of the counter electrode 12c is higher than the potential of the pixel electrode 12a. This allows the pixel electrode 12a to collect holes from the hole-electron pairs generated in the photoelectric conversion layer 12b. The signal charges collected by the pixel electrode 12 a are accumulated in the charge accumulation portion 67 n via the wiring structure 80 .

[0057] The pixel electrode 12a is an electrode containing, for example, an elemental metal such as aluminum or copper, a metal nitride, or polysilicon doped with impurities to be rendered conductive. The pixel electrode 12a is spatially separated from the pixel electrodes 12a of other adjacent pixels 10, and is thereby electrically isolated from the pixel electrodes 12a of other pixels 10.

[0058] In this embodiment, each of the multiple pixels 10 includes a microlens 130 and a color filter 120. In each of the multiple pixels 10, light passes through the microlens 130, the color filter 120, and the counter electrode 12c in this order, and enters the photoelectric conversion layer 12b. The photoelectric conversion layer 12b converts the incident light into signal charges. The signal charges are collected by the pixel electrode 12a and stored in the charge storage unit 67n via the wiring structure 80. Note that the microlens 130 and the color filter 120 are not shown in figures other than FIG. 4.

[0059] The plugs pa1 to pd and the wiring layers 80a to 80d include, for example, at least one selected from the group consisting of a metal and a metal compound. The metal is, for example, copper, tungsten, etc. The metal compound is, for example, a metal nitride, a metal oxide, etc.

[0060] The pixel 10 includes contact plugs cp1, cp2, cp3, cp4, cp5, cp6, and cp7 (hereinafter referred to as contact plugs cp1 to cp7). The contact plugs cp1 to cp7 include, for example, polysilicon doped with p-type impurities.

[0061] The charge accumulation portion 67n is electrically connected to the pixel electrode 12a via the wiring layer 80a, contact plug cp5, plug pa1, wiring layer 80b, plug pb, wiring layer 80c, plug pc, wiring layer 80d, and plug pd, in this order. The impurity region 68an is electrically connected to the feedback line 53 via contact plug cp7. The impurity region 68bn is electrically connected to the power supply wiring 32 via contact plug cp1. The impurity region 68dn is electrically connected to the vertical signal line 35 via contact plug cp4.

[0062] The gate electrode 22e is electrically connected to the pixel electrode 12a via a contact plug cp2, a plug pa2, a wiring layer 80b, a plug pb, a wiring layer 80c, a plug pc, a wiring layer 80d, and a plug pd, in this order. The gate electrode 24e is electrically connected to an address signal line 34 via a contact plug cp3. The gate electrode 26e is electrically connected to a reset signal line 36 via a contact plug cp6.

[0063] Each of the semiconductor region 63p and the well region 65p is typically formed by ion implantation of impurities into a semiconductor layer formed by epitaxial growth.

[0064] In this embodiment, the impurity concentration of the support substrate 61p is higher than the impurity concentration of the well region 65p, which is higher than the impurity concentration of the semiconductor region 63p. When there is such a magnitude relationship between the impurity concentrations, it is easy to realize a configuration in which the resistivity of the support substrate 61p is lower than the resistivity of the well region 65p, and the resistivity of the well region 65p is lower than the resistivity of the semiconductor region 63p. In this embodiment, there is actually such a magnitude relationship between the resistivities.

[0065] In this embodiment, the impurity concentration of the well contact 64 is higher than the impurity concentration of the semiconductor region 63p. When there is such a magnitude relationship between the impurity concentrations, it is easy to realize a configuration in which the resistivity of the well contact 64 is lower than the resistivity of the semiconductor region 63p. In this embodiment, there is actually such a magnitude relationship between the resistivities.

[0066] However, images obtained by an imaging device may contain noise. Noise can degrade image quality. Known types of noise include shading and streaking. Shading appears as unevenness in an image. Streaking appears as bands in an image.

[0067] Shading can be caused by non-uniform output signals from multiple pixels. For example, consider the case where a voltage is propagated from the periphery of a pixel array to the center through a semiconductor substrate. In this case, due to a voltage drop during voltage propagation, the output signal at the center of the pixel array may be smaller than the output signal at the periphery of the pixel array. This can result in shading.

[0068] Streaking can be caused by the unintended propagation of voltage from one pixel to an adjacent pixel. For example, consider a case in which a charge generated by photoelectric conversion in a pixel is input to a charge storage section in a semiconductor substrate. During this input, the voltage of the charge storage section may fluctuate. Also, consider a case in which the charge from the charge storage section is output via an amplifier transistor. During this output, the voltage of the charge storage section may fluctuate. The voltage fluctuations during input and output can propagate to an adjacent pixel through the semiconductor substrate. Also, consider a case in which the charge storage section is coupled to a horizontal common line or a vertical signal line 35. This coupling can cause the voltage fluctuation to propagate to an adjacent pixel. Because the horizontal common line and the vertical signal line are interconnects that span the pixel array, streaking can appear in a band-like pattern. Examples of horizontal common lines include the address signal line 34, the reset signal line 36, and the interconnects through which the RAMP signal propagates. This propagation can cause a "false" output signal to be output from the adjacent pixel. This is how streaking occurs.

[0069] Shading and streaking are noises caused by non-uniformity of output signals from multiple pixels. In this embodiment, the non-uniformity can be suppressed by utilizing low-resistivity regions in the semiconductor substrate. This can suppress shading and streaking.

[0070] Specifically, in this embodiment, the support substrate 61p has low resistance. The support substrate 61p is electrically connected to the well region 65p via the well contact 64. With this configuration, by taking advantage of the low resistance of the support substrate 61p, voltage can be supplied to the well region 65p via the support substrate 61p with a limited voltage drop. This is advantageous from the viewpoint of suppressing shading.

[0071] More specifically, in this embodiment, the well region 65p also has a low resistance. In a plan view, such a well region 65p is provided over the entire pixel array formed by a plurality of pixels 10. Furthermore, a low-resistance support substrate 61p is electrically connected to the well region 65p. In this configuration, the combined resistance of the well region 65p and the support substrate 61p can be reduced. This is advantageous from the viewpoint of suppressing a voltage drop in the combined resistance and suppressing shading.

[0072] In this embodiment, as described above, the support substrate 61p has a low resistance. The support substrate 61p is electrically connected to the well region 65p via the well contact 64. With this configuration, the low resistance of the support substrate 61p can contribute to fixing the potential of the well region 65p. This is advantageous from the viewpoint of suppressing streaking.

[0073] More specifically, in this embodiment, as described above, the well region 65p also has a low resistance, which is advantageous from the viewpoint of fixing the potential of the well region 65p and suppressing streaking.

[0074] As can be understood from the above description, the imaging device 100 includes a semiconductor substrate 60 and a plurality of pixels 10. The semiconductor substrate 60 has a first surface 60s1 and a second surface 60s2. The first surface 60s1 and the second surface 60s2 are surfaces of the semiconductor substrate 60 opposite to each other. The semiconductor substrate 60 includes a p-type well region 65p, a p-type support substrate 61p, a p-type semiconductor region 63p, and a p-type well contact 64. At least a portion of the well region 65p is located on the first surface 60s1. The support substrate 61p is located closer to the second surface 60s2 than the well region 65p. The semiconductor region 63p is located between the well region 65p and the support substrate 61p. The well contact 64 penetrates the semiconductor region 63p. The well contact 64 electrically connects the well region 65p and the support substrate 61p. Each of the multiple pixels 10 includes a photoelectric conversion unit 12 and an n-type charge accumulation unit 67n. The photoelectric conversion unit 12 converts light into electric charges. The charge accumulation unit 67n is located in the well region 65p. The charge accumulation unit 67n accumulates electric charges. In this embodiment, the impurity concentration of the support substrate 61p is higher than the impurity concentration of the well region 65p. This configuration is suitable for improving image quality. This point will be described in detail below.

[0075] That is, in the above configuration, the impurity concentration of the support substrate 61p is higher than the impurity concentration of the well region 65p. When the impurity concentrations have such a magnitude relationship, it is easy to realize a configuration in which the resistivity of the support substrate 61p is lower than the resistivity of the well region 65p. The support substrate 61p is electrically connected to the well region 65p via the well contact 64. With this configuration, the low resistance of the support substrate 61p can be utilized to supply voltage to the well region 65p via the support substrate 61p with a limited voltage drop. This is advantageous from the perspective of suppressing shading. Furthermore, with this configuration, the low resistance of the support substrate 61p can be used to contribute to fixing the potential of the well region 65p. This is advantageous from the perspective of suppressing streaking.

[0076] The impurity concentration of the support substrate 61p may be 5 times or more, or 10 times or more, the impurity concentration of the well region 65p. The impurity concentration of the support substrate 61p is, for example, 1×10 18 atoms / cm 3 The impurity concentration of the support substrate 61p may be 100 times or less the impurity concentration of the well region 65p.

[0077] Here, the expression "the well contact 64 penetrates the semiconductor region 63p" will be explained. This expression means that the well contact 64 is surrounded by the semiconductor region 63p. With respect to the thickness direction of the semiconductor substrate 60, it is not essential that the well contact 64 penetrates into the well region 65p from the semiconductor region 63p side. Also, with respect to the thickness direction of the semiconductor substrate 60, it is not essential that the well contact 64 penetrates into the support substrate 61p from the semiconductor region 63p side. With respect to the thickness direction of the semiconductor substrate 60, the well contact 64 may or may not penetrate into the well region 65p from the semiconductor region 63p side. With respect to the thickness direction of the semiconductor substrate 60, the well contact 64 may or may not penetrate into the support substrate 61p from the semiconductor region 63p side.

[0078] In the present embodiment, the plurality of pixels 10 includes two or more pixels 10. The support substrate 61p includes a spanning portion that extends across the two or more pixels 10. The imaging device 100 includes a first conductive path that passes through the spanning portion and the well contact 64 in this order and reaches the well region 65p. A voltage can be supplied to the well region 65p via the first conductive path.

[0079] In the present embodiment, the well region 65p includes a second conductive path that extends across two or more pixels 10. In the imaging device 100, a parallel path is formed in which the first conductive path and the second conductive path are connected in parallel, and a voltage can be supplied to the well region 65p through the parallel path.

[0080] In the present embodiment, the voltage from the voltage supply circuit 48 is supplied to the well region 65p via the first conductive path. Specifically, the voltage from the voltage supply circuit 48 is supplied to the well region 65p via a parallel path.

[0081] The number of pixels 10 that the spanning portion spans is, for example, 2 or more. This number may be 1000 or more.

[0082] The number of pixels 10 that the second conductive path spans is, for example, 2 or more. This number may be 1000 or more.

[0083] In the present embodiment, the voltage from the voltage supply circuit 48 is supplied to the well region 65p via the first conductive path, specifically via the first conductive path and the second conductive path. However, it is also possible to employ a configuration in which a voltage from a power source external to the imaging device 100 is supplied to the well region 65p via the first conductive path, specifically via the first conductive path and the second conductive path.

[0084] In this embodiment, the impurity concentration of the well contact 64 is higher than the impurity concentration of the semiconductor region 63p. When the impurity concentrations have such a magnitude relationship, it is easy to realize a configuration in which the resistivity of the well contact 64 is lower than the resistivity of the semiconductor region 63p. This configuration is advantageous from the viewpoint of allowing the low-resistance well contact 64 to function as a path for supplying voltage to the well region 65p and contributing to suppressing shading and streaking. Furthermore, this configuration allows the high-resistance semiconductor region 63p to function as a barrier that prevents impurities from diffusing from the support substrate 61p.

[0085] The impurity concentration of the well contact 64 may be at least twice, at least ten times, or at least one hundred times the impurity concentration of the semiconductor region 63p.

[0086] In this embodiment, the impurity concentration of the well contact 64 is higher than the impurity concentration of the well region 65p. When there is such a magnitude relationship between the impurity concentrations, it is easy to realize a configuration in which the resistivity of the well contact 64 is lower than the resistivity of the well region 65p. This configuration is advantageous from the viewpoint of allowing the low-resistance well contact 64 to function as a path for supplying voltage to the well region 65p and contributing to suppressing shading and streaking.

[0087] The impurity concentration of the well contact 64 may be more than 1 time, 2.5 times or more, or 5 times or more the impurity concentration of the well region 65p.

[0088] In this embodiment, the impurity concentration of the support substrate 61p is higher than the impurity concentration of the well contact 64. When there is such a magnitude relationship between the impurity concentrations, it is easy to realize a configuration in which the resistivity of the support substrate 61p is lower than the resistivity of the well contact 64. This configuration is advantageous from the viewpoint of increasing the proportion of voltage that passes through the support substrate 61p, which has a low resistivity, when supplying voltage over a long distance to the center of the pixel array, and making the support substrate 61p contribute to suppressing shading and streaking.

[0089] The impurity concentration of the well region 65p is higher than the impurity concentration of the semiconductor region 63p. When there is such a magnitude relationship between the impurity concentrations, it is easy to realize a configuration in which the resistivity of the well region 65p is lower than the resistivity of the semiconductor region 63p. This configuration is advantageous from the viewpoint of allowing the low-resistance well contact 64 to contribute to suppressing shading and streaking.

[0090] The impurity concentration of the well region 65p may be at least twice, at least ten times, or at least fifty times the impurity concentration of the semiconductor region 63p.

[0091] The impurity concentration of the support substrate 61p may be at least twice, at least ten times, or at least one hundred times the impurity concentration of the semiconductor region 63p.

[0092] In this embodiment, in each of the multiple pixels 10, the area of ​​the semiconductor region 63p in a planar view is larger than the area of ​​the well contact 64 in a planar view. This configuration, combined with the configuration in which the impurity concentration of the well contact 64 is larger than the impurity concentration of the semiconductor region 63p, allows the well contact 64 to function as a main path for supplying voltage to the well region 65p, while allowing the semiconductor region 63p to function as an auxiliary path for supplying voltage to the well region 65p. This auxiliary voltage supply path with a large area can stabilize the potential of the imaging region R1.

[0093] In each of the multiple pixels 10, the area of ​​the semiconductor region 63p in a planar view may be more than twice, more than 10 times, or more than 60 times the area of ​​the well contact 64 in a planar view.

[0094] In this embodiment, the semiconductor region 63p is a region having a lower impurity concentration than any of the well region 65p, the support substrate 61p, and the well contact 64. The well contact 64 is a region having a higher impurity concentration than the well region 65p and a lower impurity concentration than the support substrate 61p. In this embodiment, the semiconductor region 63p and the well contact 64 satisfy the magnitude relationship between their impurity concentrations, and also satisfy the above-mentioned magnitude relationship between the area of ​​the semiconductor region 63p and the area of ​​the well contact 64.

[0095] In this embodiment, one of the source and drain of the reset transistor 26 is an n-type charge accumulation portion 67n. The other of the source and drain of the reset transistor 26 is an n-type impurity region 68an. The charge accumulation portion 67n and the impurity region 68an are located within the well region 65p. The PN junction between the well region 65p and the charge accumulation portion 67n includes a first portion. The PN junction between the well region 65p and the impurity region 68an includes a second portion. The p-type impurity concentration in the first portion is equal to the p-type impurity concentration in the second portion. This configuration can stabilize the potential of the charge accumulation portion 67n. This stabilization can suppress streaking.

[0096] In this embodiment, in each of the multiple pixels 10, the well region 65p is arranged in an area that occupies 80% or more of the area of ​​the pixel 10 in a planar view. That is, in each of the multiple pixels 10, the area in which the well region 65p is arranged is 80% or more of the area of ​​the pixel 10 in a planar view. This configuration, combined with the configuration in which the well region 65p has a high impurity concentration, can make a wide area of ​​the well region 65p a low-resistance region. This is advantageous from the perspective of suppressing shading and streaking. In each of the multiple pixels 10, the well region 65p may be arranged in an area that occupies 90% or more of the area of ​​the pixel 10 in a planar view. In each of the multiple pixels 10, the well region 65p may be arranged in an area that occupies 95% or more of the area of ​​the pixel 10 in a planar view.

[0097] Here, the expression "in each of the plurality of pixels 10, the well region 65p is arranged in an area that occupies 80% or more of the area of ​​the pixel 10 in a plan view" will be explained. In this expression, the well region 65p has an impurity concentration of 2×10 16 atoms / cm 3 This refers to an area where the above is true.

[0098] 4, the well region 65p is arranged in an area that occupies 100% of the area of ​​the pixel 10 in a plan view. Fig. 5 is a cross-sectional view showing a configuration example in which the well region 65p is arranged in an area that occupies less than 100% of the area of ​​the pixel 10 in a plan view. The charge accumulation portion 67n may be located in the well region 65p, and an impurity region different from the charge accumulation portion 67n may be located in the semiconductor region 63p.

[0099] In this embodiment, the semiconductor region 63p separates the well region 65p and the support substrate 61p, thereby forming a p-type three-layer structure.

[0100] Here, the expression "the semiconductor region 63p separates the well region 65p and the support substrate 61p" will be explained. Specifically, this expression means that the semiconductor region 63p and the well region 65p are connected without an n-type region therebetween, and that the semiconductor region 63p and the support substrate 61p are connected without an n-type region therebetween. The configuration in which the well region 65p and the support substrate 61p are separated makes it difficult for a parasitic leakage current to be generated by an n-type region between the semiconductor region 63p and the well region 65p, or a parasitic leakage current to be generated by an n-type region between the semiconductor region 63p and the support substrate 61p. This can contribute to improving image quality. Furthermore, the absence of an n-type region has the advantage that a mask for forming an n-type region is not required during the manufacture of the imaging device 100.

[0101] In this embodiment, the support substrate 61p is a silicon substrate, and the semiconductor region 63p and the well region 65p are epitaxial layers.

[0102] In this embodiment, the ratio of the dimension of the well region 65p in the thickness direction of the semiconductor substrate 60 to the dimension of the support substrate 61p in the thickness direction of the semiconductor substrate 60 is 1 / 2 or less. This ratio may be 1 / 100 or less, or 1 / 700 or less. If the support substrate 61p is thick, the resistance becomes smaller, making it easier to suppress shading and streaking. The ratio may be 1 / 2000 or more.

[0103] In this embodiment, the well contact 64 does not overlap the charge storage portion 67n in plan view, which is advantageous from the viewpoint of reducing the leakage current flowing out from the charge storage portion 67n.

[0104] In this embodiment, in plan view, the well contact 64 does not overlap either the reset transistor 26 or the amplification transistor 22. This configuration is suitable for improving image quality. The reason for this will be explained below.

[0105] At a position in the semiconductor substrate 60 between the well contact 64 and the first surface 60s (hereinafter referred to as a position above the well contact 64), defects related to the well contact 64 may exist. For example, when the well contact 64 is formed by ion implantation, implantation defects resulting from the ion implantation may be formed at the position.

[0106] Defects can increase the variation in the threshold voltage of the amplifier transistor 22 and degrade image quality. However, the above configuration can prevent the channel region of the amplifier transistor 22 from overlapping with the well contact 64 in a plan view. This can suppress the variation in threshold voltage caused by defects, thereby improving image quality.

[0107] From the viewpoint of improving the driving force of the amplifier transistor 22, the impurity concentration in the source and drain of the amplifier transistor 22 is typically higher than the impurity concentration in the source and drain of the select transistor 24, etc. Furthermore, the conductivity type of the source and drain of the amplifier transistor 22 is opposite to that of the well contact 64, i.e., n-type. Defects can cause leakage current from such amplifier transistors 22 and degrade image quality. However, with the above configuration, it is possible to prevent the source and drain of the amplifier transistor 22 from overlapping with the well contact 64 in a plan view. This can suppress leakage current from the amplifier transistor 22, thereby improving image quality.

[0108] The reset transistor 26 includes a charge storage portion 67n. The charge storage portion 67n is a portion where charge obtained by photoelectric conversion is stored. The conductivity type of the charge storage portion 67n is opposite to that of the well contact 64, i.e., n-type. Defects can cause leakage current from such a reset transistor 26 and degrade image quality. However, the above configuration can prevent the reset transistor 26 and the well contact 64 from overlapping in a plan view. This can suppress leakage current from the reset transistor 26 and improve image quality.

[0109] Specifically, in this embodiment, the well contact 64 does not overlap any of the transistors in the multiple pixels 10 in a plan view. This configuration is suitable for improving image quality. Specifically, this configuration makes it easier to prevent defects from being formed under the transistors. This is advantageous from the viewpoint of suppressing leakage current of the transistors.

[0110] Other embodiments will be described below. In the following, elements common to the embodiment already described and the embodiment to be described thereafter will be given the same reference numerals, and their description may be omitted. The descriptions of the respective embodiments may be mutually applicable unless technically inconsistent. The respective embodiments may be combined with each other unless technically inconsistent.

[0111] Second Embodiment FIG. 6 is a plan view showing the layout in a plurality of pixels 10 in a second embodiment, and is a plan view showing the positions of a plurality of well contacts 64 in a semiconductor substrate 60 in a plan view.

[0112] In the second embodiment, the pixel of the plurality of pixels 10 that is located next to the pixel 10a may be referred to as the pixel 10b. The charge storage portion 67n in the pixel 10b may be referred to as the charge storage portion 67n2. The impurity region 68bn in the pixel 10b may be referred to as the impurity region 68bn2. The impurity region 68dn in the pixel 10b may be referred to as the impurity region 68dn2. In FIG. 6, the pixel 10a is drawn relatively lower, and the pixel 10b is drawn relatively upper.

[0113] In the second embodiment, the well contact 64 is included in each of the plurality of pixels 10. This configuration is advantageous from the viewpoint of suppressing streaking. In the example of Fig. 6, the well contacts 64 included in different pixels 10 are separated from each other in a plan view. The number of well contacts 64 included in each of the plurality of pixels 10 may be one, or two or more.

[0114] As can be understood from the above description, the amplification transistor 22 outputs a signal corresponding to the potential of the charge storage section 67n. The selection transistor 24 determines the timing at which the signal is output from the amplification transistor 22. The signal is typically a voltage. The selection transistor 24 includes an impurity region 68cn and an impurity region 68dn. The impurity region 68cn is one of the source and drain of the selection transistor 24. The impurity region 68dn is the other of the source and drain of the selection transistor 24. In the selection transistor 24, a signal flows in the order of the impurity region 68cn and the impurity region 68dn.

[0115] Here, distances L1, L2, L3, and L4 are defined as follows: Distance L1 is the distance between the well contact 64 and the impurity region 68bn1 of pixel 10a in a planar view, specifically, the distance between the outer edge of the well contact 64 and the outer edge of the impurity region 68bn1 of pixel 10a in a planar view. Distance L2 is the distance between the well contact 64 and the charge accumulation unit 67n1 of pixel 10a in a planar view, specifically, the distance between the outer edge of the well contact 64 and the outer edge of the charge accumulation unit 67n1 of pixel 10a in a planar view. Distance L3 is the distance between the well contact 64 and the impurity region 68dn2 of pixel 10b in a planar view, specifically, the distance between the outer edge of the well contact 64 and the outer edge of the impurity region 68dn2 of pixel 10b in a planar view. - Distance L4 is the distance between the well contact 64 and the charge storage section 67n2 of pixel 10b in a planar view, and more specifically, the distance between the outer edge of the well contact 64 and the outer edge of the charge storage section 67n2 of pixel 10b in a planar view.

[0116] In this embodiment, the outer edge of the charge accumulation portion 67n is the position of the PN junction between the charge accumulation portion 67n and the adjacent region. In this embodiment, the adjacent region is the well region 65p. This also applies to the impurity regions 68an to 68dn.

[0117] In this embodiment, the outer edge of the well contact 64 refers to a portion where the impurity concentration is a predetermined concentration. The predetermined concentration is, for example, 2×10 16atoms / cm 3 1x10 or more 18 atoms / cm 3 The same applies to a frame shape 98 and its corners and crosspieces, which will be described later.

[0118] In the second embodiment, the distance L1 is smaller than the distance L2. The distance L3 is smaller than the distance L2. The distance L1 is smaller than the distance L4. The distance L3 is smaller than the distance L4. This configuration is suitable for improving image quality. Specifically, while a potential fixing effect is exerted near the well contact 64, a leakage current may occur. From the viewpoint of improving image quality, it is advantageous to arrange the well contact 64 in a position where a potential fixing effect can be exerted near the electrical path passing through the source and drain of the amplifier transistor 22, thereby suppressing streaking, and where a leakage current from the charge accumulation portions 67n1 and 67n2 is unlikely to occur. Here, the electrical path includes not only the source and drain of the amplifier transistor 22 but also, for example, the source and drain of the select transistor 24. In this regard, the above configuration makes it easy to bring the well contact 64 close to the impurity region 68bn1 and the impurity region 68dn2. Therefore, the potential fixing effect of the well contact 64 is exerted near the impurity region 68bn1 and the impurity region 68dn2, which contributes to suppressing streaking. Furthermore, this configuration makes it easy to keep the well contact 64 away from the charge storage portions 67n1 and 67n2. Therefore, leakage current from the charge storage portions 67n1 and 67n2 due to the well contact 64 is unlikely to occur.

[0119] The distance L1 may be less than 1 time the distance L2 or may be 1 / 5 or less. The distance L3 may be less than 1 time the distance L2 or may be 1 / 5 or less. The distance L1 may be less than 1 time the distance L4 or may be 1 / 5 or less. The distance L3 may be less than 1 time the distance L4 or may be 1 / 5 or less.

[0120] 6, attention is focused on the well contact 64 (hereinafter referred to as well contact 64a) disposed in pixel 10a. The magnitude relationship of the above-described distances L1 to L4 is established for the well contact 64a.

[0121] The configurations of L1<L2, L3<L2, L1<L4, and L3<L4 may be combined with a configuration in which the well contact 64 is not included in each of the plurality of pixels 10.

[0122] 7 is a plan view showing the layout of a plurality of pixels 10 in a third embodiment, and is a plan view showing the positions of a plurality of well contacts 64 in a semiconductor substrate 60 in a plan view. FIG. 8 is a schematic cross-sectional view of the device structure when the pixel 10 is cut along line VIII-VIII in FIG. 7 and developed in the direction of the arrows. The cross section shown in FIG. 8 is a cross section parallel to the thickness direction of the semiconductor substrate 60.

[0123] In the third embodiment, as shown in FIG. 7 , the well contact 64 extends across at least two pixels 10 in a plan view. That is, the well contact 64 is disposed continuously across at least two pixels 10. This configuration can improve the potential fixing effect in the region spanning at least two pixels 10. This makes it difficult for a voltage fluctuation in one of the at least two pixels 10 to propagate to the other pixel 10, making it difficult for a "false" output signal to be output from the other pixel 10. In this way, streaking can be suppressed. Specifically, the well contact 64, which is a continuous, unified region in a plan view, extends across at least two pixels 10. In the example of FIG. 7 , the well contact 64m extends across pixel 10a and pixel 10b.

[0124] In the third embodiment, the pixels 10 are arranged in a first direction D1 and a second direction D2 to form a pixel array. The first direction D1 and the second direction D2 are different directions. In the example of FIG. 7, the first direction D1 and the second direction D2 are directions perpendicular to each other.

[0125] In embodiment 3, the first direction D1 is one of the horizontal and vertical directions. The second direction D2 is the other of the horizontal and vertical directions. The horizontal direction is the direction in which rows extend, i.e., the row direction, and is the left-right direction in FIG. 1. The vertical direction is the direction in which columns extend, i.e., the column direction, and is the up-down direction in FIG. 1. Below, an example will be described in which the first direction D1 is the horizontal direction and the second direction D2 is the vertical direction.

[0126] In the third embodiment, the dimension of the well contact 64 in the first direction D1 is less than the dimension of the pixel 10 in the first direction D1.

[0127] In the third embodiment, the imaging device 100 includes a plurality of well contacts 64. The plurality of well contacts 64 are arranged in the second direction D2 so that each of the plurality of well contacts 64 extends in the first direction D1. Each of the plurality of well contacts 64 extends across two pixels 10 adjacent to each other in the second direction D2. In other words, each of the plurality of well contacts 64 is continuously arranged across two pixels 10 adjacent to each other in the second direction D2.

[0128] In the third embodiment, the high impurity concentration of the well region 65p can also exert a potential fixing effect near the center of the pixel 10 in the second direction D2.

[0129] Fourth Embodiment FIG. 9 is a plan view showing the layout of a plurality of pixels 10 in a fourth embodiment, and is a plan view showing the positions of well contacts 64 in a semiconductor substrate 60 in a plan view.

[0130] In the fourth embodiment, among the plurality of pixels 10, a pixel located adjacent to pixel 10a in the second direction D2 may be referred to as pixel 10b. Among the plurality of pixels 10, a pixel located adjacent to pixel 10a in the first direction D1 may be referred to as pixel 10c. Among the plurality of pixels 10, a pixel located adjacent to pixel 10b in the first direction D1 may be referred to as pixel 10d. The charge accumulation portion 67n in pixel 10c may be referred to as charge accumulation portion 67n3. The impurity region 68dn in pixel 10c may be referred to as impurity region 68dn3. The charge accumulation portion 67n in pixel 10d may be referred to as charge accumulation portion 67n4. The impurity region 68dn in pixel 10d may be referred to as impurity region 68dn4. In FIG. 9, pixel 10a is drawn relatively on the upper left side, pixel 10b is drawn relatively on the lower left side, pixel 10c is drawn relatively on the upper right side, and pixel 10d is drawn relatively on the lower right side.

[0131] In the fourth embodiment, as shown in FIG. 9 , the well contact 64 extends across the four pixels 10a, 10b, 10c, and 10d in a plan view. That is, the well contact 64 is continuously disposed across the four pixels 10a, 10b, 10c, and 10d. A configuration in which only one well contact 64 is applied to the four pixels 10a, 10b, 10c, and 10d facilitates suppression of leakage current from the charge storage unit 67n. Furthermore, this configuration utilizes limited space to fix the potentials of the four pixels 10a, 10b, 10c, and 10d, thereby suppressing streaking. This is in line with the current trend toward miniaturization of imaging devices.

[0132] Here, distances X1, Y1, X2, Y2, X3, Y3, X4, and Y5 are defined as follows: distance X1 is the distance between the well contact 64 and the impurity region 68dn1 of the pixel 10a in a planar view, specifically, the distance between the center of the well contact 64 and the center of the impurity region 68dn1 of the pixel 10a in a planar view. distance Y1 is the distance between the well contact 64 and the charge accumulation unit 67n1 of the pixel 10a in a planar view, specifically, the distance between the center of the well contact 64 and the center of the charge accumulation unit 67n1 of the pixel 10a in a planar view. distance X2 is the distance between the well contact 64 and the impurity region 68dn2 of the pixel 10b in a planar view, specifically, the distance between the center of the well contact 64 and the center of the impurity region 68dn2 of the pixel 10b in a planar view. The distance Y2 is the distance between the well contact 64 and the charge accumulation unit 67n2 of the pixel 10b in a planar view, specifically, the distance between the center of the well contact 64 and the center of the charge accumulation unit 67n2 of the pixel 10b in a planar view. The distance X3 is the distance between the well contact 64 and the impurity region 68dn3 of the pixel 10c in a planar view, specifically, the distance between the center of the well contact 64 and the center of the impurity region 68dn3 of the pixel 10c in a planar view. The distance Y3 is the distance between the well contact 64 and the charge accumulation unit 67n3 of the pixel 10c in a planar view, specifically, the distance between the center of the well contact 64 and the center of the charge accumulation unit 67n3 of the pixel 10c in a planar view. The distance X4 is the distance between the well contact 64 and the impurity region 68dn4 of the pixel 10d in a planar view, specifically, the distance between the center of the well contact 64 and the center of the impurity region 68dn4 of the pixel 10d in a planar view. The distance Y4 is the distance between the well contact 64 and the charge storage unit 67n4 of the pixel 10d in a planar view, specifically, the distance between the center of the well contact 64 and the center of the charge storage unit 67n4 of the pixel 10d in a planar view.

[0133] In the fourth embodiment, the distance X1 is smaller than the distance Y1. The distance X2 is smaller than the distance Y2. The distance X3 is smaller than the distance Y3. The distance X4 is smaller than the distance Y4. However, it is not necessary for all of these magnitude relationships to be satisfied. A configuration in which at least one of these magnitude relationships is satisfied may be employed.

[0134] 9, the arrangement of the combination of the amplification transistor 22, the selection transistor 24, and the reset transistor 26 is flipped between the pixels 10. Specifically, the arrangement of this combination is flipped between the pixel 10a and the pixel 10b in the second direction D2. The arrangement of this combination is flipped between the pixel 10a and the pixel 10c in the first direction D1. The arrangement of this combination is flipped between the pixel 10b and the pixel 10d in the first direction D1. However, it is not necessary for all of these flips to be performed. A configuration in which at least one of these flips is performed may be adopted.

[0135] In the pixel 10a of the example shown in FIG. 9 , the well contact 64, the impurity region 68dn, the impurity region 68cn, and the impurity region 68bn are arranged in this order in the second direction D2 in a plan view. The same applies to the pixels 10b, 10c, and 10d. The configuration of FIG. 9 may be modified so that the positions of the amplifier transistor 22 and the selection transistor 24 in the second direction D2 are reversed. In the pixel 10a of this modified example in which this reversal is performed, the well contact 64, the impurity region 68bn, the impurity region 68cn, and the impurity region 68dn are arranged in this order in the second direction D2 in a plan view. The same applies to the pixels 10b, 10c, and 10d. In the description of the example shown in FIG. 9 , the description of the amplifier transistor 22 and its components and the description of the selection transistor 24 and its components can be interchanged to provide a description of the modified example.

[0136] FIG. 10 is a plan view showing a specific example of the fourth embodiment. In the specific example of FIG. 10, a plurality of quad pixels (Quad Pixels) 95 are arranged in an array in a first direction D1 and a second direction D2. Each quad pixel 95 includes four pixels 10a, 10b, 10c, and 10d. In each quad pixel 95, the pixels 10a, 10b, 10c, and 10d are sensitive to light of the same color. In the specific example of FIG. 10, streaking can be suppressed in units of quad pixels 95. The plurality of quad pixels 95 are arranged in, for example, a Bayer array.

[0137] 10 , the multiple quad pixels 95 include quad pixels 95a, quad pixels 95b, quad pixels 95c, and quad pixels 95d. The quad pixels 95a and 95b are adjacent to each other in the second direction D2. The quad pixels 95a and 95c are adjacent to each other in the first direction D1. The quad pixels 95b and 95d are adjacent to each other in the first direction D1. In the quad pixels 95a and 95d, pixels 10a, 10b, 10c, and 10d are Gr pixels sensitive to green light. In the quad pixel 95b, pixels 10a, 10b, 10c, and 10d are B pixels sensitive to blue light. In the quad pixel 95c, the pixels 10a, 10b, 10c, and 10d are R pixels that are sensitive to red light.

[0138] In the specific example of FIG. 10 , the transistor layout in each quad pixel 95 is the same. However, the transistor layout in each quad pixel 95 may be different. For example, the flipping may be performed only in specific quad pixels 95 that are sensitive to light of a predetermined color among the multiple quad pixels 95. The specific quad pixels 95 may be, for example, quad pixels 95 a and quad pixels 95 d that are sensitive to green light. The human eye has a high sensitivity to green. Therefore, it may be beneficial to adjust the characteristics of the quad pixels 95 a and quad pixels 95 d that are sensitive to green light by adopting a different transistor layout from that of the other quad pixels 95 b and quad pixels 95 c.

[0139] Fifth Embodiment FIG. 11 is a plan view showing the layout of a plurality of pixels 10 in a fifth embodiment, and is a plan view showing the positions of well contacts 64 in a semiconductor substrate 60 in a plan view.

[0140] In the fifth embodiment, the impurity region 68bn in pixel 10a may be referred to as an impurity region 68bn1. The impurity region 68bn in pixel 10b may be referred to as an impurity region 68bn2. The impurity region 68bn in pixel 10c may be referred to as an impurity region 68bn3. The impurity region 68bn in pixel 10d may be referred to as an impurity region 68bn4. The impurity region 68cn in pixel 10a may be referred to as an impurity region 68cn1. The impurity region 68cn in pixel 10b may be referred to as an impurity region 68cn2. The impurity region 68cn in pixel 10c may be referred to as an impurity region 68cn3. The impurity region 68cn in pixel 10d may be referred to as an impurity region 68cn4.

[0141] In the fifth embodiment, the dimension of the well contact 64 in the first direction D1 is equal to or greater than the dimension of the pixel 10 in the first direction D1. This configuration is advantageous from the viewpoint of suppressing shading. As described above, the first direction D1 may be either the horizontal direction or the vertical direction.

[0142] In the example of Fig. 11, the arrangement of the combination of the amplification transistor 22, the selection transistor 24, and the reset transistor 26 is flipped between the pixels 10. Specifically, the arrangement of this combination is flipped between the pixel 10a and the pixel 10b in the second direction D2. The arrangement of this combination is flipped between the pixel 10a and the pixel 10c in the first direction D1. The arrangement of this combination is flipped between the pixel 10b and the pixel 10d in the first direction D1. However, it is not necessary for all of these flips to be performed. A configuration in which at least one of these flips is performed may be adopted.

[0143] In the fifth embodiment, as shown in FIG. 11 , the well contact 64 includes a closed frame shape 98 in plan view. In plan view, the frame shape 98 surrounds a pixel transistor group of four pixels 10 a, 10 b, 10 c, and 10 d. The pixel transistor group includes, for example, an amplifier transistor 22, a selection transistor 24, and a reset transistor 26. This configuration makes it easy to ensure the area of ​​the well contact 64, which is advantageous from the perspective of suppressing shading. A combination of the four pixels 10 a, 10 b, 10 c, and 10 d can form a quad pixel 95, which will be described later.

[0144] In a plan view, the frame shape 98 has a corner 96a, a crosspiece 97a, a corner 96b, a crosspiece 97b, a corner 96d, a crosspiece 97d, a corner 96c, and a crosspiece 97c arranged in this order. The corner 96a is located at a corner of the pixel 10a. The corner 96b is located at a corner of the pixel 10b. The corner 96c is located at a corner of the pixel 10c. The corner 96d is located at a corner of the pixel 10d. The crosspiece 97a extends across the pixels 10a and 10b. The crosspiece 97b extends across the pixels 10b and 10d. The crosspiece 97c extends across the pixels 10a and 10c. The crosspiece 97d extends across the pixels 10c and 10d.

[0145] Here, distances S1, T1, U1, V1, W1, S2, T2, U2, V2, W2, S3, T3, U3, V3, W3, S4, T4, U4, V4, and W4 are defined as follows: distance S1 is the distance between the corner 96a and the impurity region 68dn1 of the pixel 10a in a planar view, specifically, the distance between the outer edge of the corner 96a and the outer edge of the impurity region 68dn1 of the pixel 10a in a planar view. distance T1 is the distance between the corner 96a and the charge storage unit 67n1 of the pixel 10a in a planar view, specifically, the distance between the outer edge of the corner 96a and the outer edge of the charge storage unit 67n1 of the pixel 10a in a planar view. The distance U1 is the distance between the crosspiece 97a and the impurity region 68bn1 of the pixel 10a in a planar view, specifically the distance between the outer edge of the crosspiece 97a and the outer edge of the impurity region 68bn1 of the pixel 10a in a planar view. The distance V1 is the distance between the crosspiece 97a and the impurity region 68cn1 of the pixel 10a in a planar view, specifically the distance between the outer edge of the crosspiece 97a and the outer edge of the impurity region 68cn1 of the pixel 10a in a planar view. The distance W1 is the distance between the crosspiece 97a and the charge accumulation portion 67n1 of the pixel 10a in a planar view, specifically the distance between the outer edge of the crosspiece 97a and the outer edge of the charge accumulation portion 67n1 of the pixel 10a in a planar view. The distance S2 is the distance between the corner 96b and the impurity region 68dn2 of the pixel 10b in a planar view, specifically the distance between the outer edge of the corner 96b and the outer edge of the impurity region 68dn2 of the pixel 10b in a planar view. The distance T2 is the distance between the corner 96b and the charge accumulation unit 67n2 of the pixel 10b in a planar view, specifically the distance between the outer edge of the corner 96b and the outer edge of the charge accumulation unit 67n2 of the pixel 10b in a planar view. The distance U2 is the distance between the crosspiece 97a and the impurity region 68bn2 of the pixel 10b in a planar view, specifically the distance between the outer edge of the crosspiece 97a and the outer edge of the impurity region 68bn2 of the pixel 10b in a planar view. Distance V2 is the distance between the crosspiece 97a and the impurity region 68cn2 of pixel 10b in a planar view, specifically, the distance between the outer edge of the crosspiece 97a and the outer edge of the impurity region 68cn2 of pixel 10b in a planar view.The distance W2 is the distance between the crosspiece 97a and the charge accumulation unit 67n2 of the pixel 10b in a plan view, specifically, the distance between the outer edge of the crosspiece 97a and the outer edge of the charge accumulation unit 67n2 of the pixel 10b in a plan view. The distance S3 is the distance between the corner 96c and the impurity region 68dn3 of the pixel 10c in a plan view, specifically, the distance between the outer edge of the corner 96c and the outer edge of the impurity region 68dn3 of the pixel 10c in a plan view. The distance T3 is the distance between the corner 96c and the charge accumulation unit 67n3 of the pixel 10c in a plan view, specifically, the distance between the outer edge of the corner 96c and the outer edge of the charge accumulation unit 67n3 of the pixel 10c in a plan view. The distance U3 is the distance between the crosspiece 97d and the impurity region 68bn3 of the pixel 10c in a planar view, specifically, the distance between the outer edge of the crosspiece 97d and the outer edge of the impurity region 68bn3 of the pixel 10c in a planar view. The distance V3 is the distance between the crosspiece 97d and the impurity region 68cn3 of the pixel 10c in a planar view, specifically, the distance between the outer edge of the crosspiece 97d and the outer edge of the impurity region 68cn3 of the pixel 10c in a planar view. The distance W3 is the distance between the crosspiece 97d and the charge accumulation unit 67n3 of the pixel 10c in a planar view, specifically, the distance between the outer edge of the crosspiece 97d and the outer edge of the charge accumulation unit 67n3 of the pixel 10c in a planar view. The distance S4 is the distance between the corner 96d and the impurity region 68dn4 of the pixel 10d in a planar view, specifically the distance between the outer edge of the corner 96d and the outer edge of the impurity region 68dn4 of the pixel 10d in a planar view. The distance T4 is the distance between the corner 96d and the charge accumulation unit 67n4 of the pixel 10d in a planar view, specifically the distance between the outer edge of the corner 96d and the outer edge of the charge accumulation unit 67n4 of the pixel 10d in a planar view. The distance U4 is the distance between the crosspiece 97d and the impurity region 68bn4 of the pixel 10d in a planar view, specifically the distance between the outer edge of the crosspiece 97d and the outer edge of the impurity region 68bn4 of the pixel 10d in a planar view. Distance V4 is the distance between the crosspiece 97d and the impurity region 68cn4 of pixel 10d in a planar view, and more specifically, the distance between the outer edge of the crosspiece 97d and the outer edge of the impurity region 68cn4 of pixel 10d in a planar view.- Distance W4 is the distance between the crosspiece 97d and the charge storage section 67n4 of pixel 10d in a planar view, specifically, the distance between the outer edge of the crosspiece 97d and the outer edge of the charge storage section 67n4 of pixel 10d in a planar view.

[0146] In embodiment 5, distance S1 is smaller than distance T1. Distance S2 is smaller than distance T2. Distance S3 is smaller than distance T3. Distance S4 is smaller than distance T4. Distance U1 is smaller than distance W1. Distance V1 is smaller than distance W1. Distance U2 is smaller than distance W2. Distance V2 is smaller than distance W2. Distance U3 is smaller than distance W3. Distance V3 is smaller than distance W3. Distance U4 is smaller than distance W4. Distance V4 is smaller than distance W4. However, not all of these magnitude relationships need to be satisfied. A configuration in which at least one of these magnitude relationships is satisfied may be employed.

[0147] In the fifth embodiment, as shown in FIG. 11 , a frame shape 98 of the well contact 64 surrounds a group of pixel transistors of four pixels 10a, 10b, 10c, and 10d in a plan view. The corners 96a, 96b, 96c, and 96d may cause leakage current in their vicinity. Due to the flip, a selection transistor 24 is disposed in each vicinity. Because the leakage current of the selection transistor 24 has a limited effect on image quality, this configuration is advantageous from the viewpoint of suppressing image quality degradation caused by the corners 96a, 96b, 96c, and 96d. In the fifth embodiment, as shown in FIG. 11 , the four charge accumulation portions 67n1, 67n2, 67n3, and 67n4 are concentrated toward the center of the combination of the four pixels 10a, 10b, 10c, and 10d in a plan view. This configuration makes it easy to ensure the area of ​​the well contact 64 while suppressing leakage current flowing out from the charge storage portions 67n1, 67n2, 67n3, and 67n4 by separating the charge storage portions 67n1, 67n2, 67n3, and 67n4 from the frame shape 98. By ensuring the area, the combined resistance of the semiconductor substrate 60 can be reduced and shading can be suppressed.

[0148] Furthermore, this configuration makes it possible to utilize a limited space and fix the potentials of the four pixels 10 a, 10 b, 10 c, and 10 d to suppress streaking, which is in line with the current trend of miniaturization of imaging devices.

[0149] Furthermore, in the fifth embodiment, the distances S1, U1, V1, S2, U2, V2, S3, U3, V3, S4, U4, and V4 can be reduced. This means that the frame shape 98 can be arranged along the impurity regions 68bn, 68cn, and 68dn of the amplifier transistor 22 and the select transistor 24. The impurity regions 68bn, 68cn, and 68dn are electrical paths in which large voltage fluctuations can occur. With this configuration, the frame shape 98 can easily fix the potential in these electrical paths.

[0150] In the pixel 10a of the example shown in FIG. 11 , the well contact 64, the impurity region 68dn, the impurity region 68cn, and the impurity region 68bn are arranged in this order in the second direction D2 in a plan view. The same applies to the pixels 10b, 10c, and 10d. The configuration of FIG. 11 may be modified so that the positions of the amplifier transistor 22 and the selection transistor 24 in the second direction D2 are reversed. In the pixel 10a of this modified example in which this reversal is performed, the well contact 64, the impurity region 68bn, the impurity region 68cn, and the impurity region 68dn are arranged in this order in the second direction D2 in a plan view. The same applies to the pixels 10b, 10c, and 10d. In the description of the example shown in FIG. 11 , the description of the amplifier transistor 22 and its components and the description of the selection transistor 24 and its components can be interchanged to provide a description of the modified example.

[0151] FIG. 12 is a plan view showing a specific example of the fifth embodiment. In the specific example of FIG. 12, a plurality of quad pixels 95 are arranged in an array in a first direction D1 and a second direction D2. Each quad pixel 95 includes four pixels 10a, 10b, 10c, and 10d. In each quad pixel 95, the pixels 10a, 10b, 10c, and 10d are sensitive to light of the same color. In the specific example of FIG. 12, streaking can be suppressed in units of quad pixels 95. The plurality of quad pixels 95 are arranged, for example, in a Bayer array.

[0152] 12 , the multiple quad pixels 95 include quad pixels 95a, quad pixels 95b, quad pixels 95c, and quad pixels 95d. The quad pixels 95a and 95b are adjacent to each other in the second direction D2. The quad pixels 95a and 95c are adjacent to each other in the first direction D1. The quad pixels 95b and 95d are adjacent to each other in the first direction D1. In the quad pixels 95a and 95d, pixels 10a, 10b, 10c, and 10d are Gr pixels sensitive to green light. In the quad pixel 95b, pixels 10a, 10b, 10c, and 10d are B pixels sensitive to blue light. In the quad pixel 95c, the pixels 10a, 10b, 10c, and 10d are R pixels that are sensitive to red light.

[0153] 12, the transistor layout in each quad pixel 95 is the same. However, the transistor layout in each quad pixel 95 may be different. For example, the flip may be performed only in specific quad pixels 95 that are sensitive to light of a predetermined color among the multiple quad pixels 95. The specific quad pixels 95 are, for example, quad pixel 95a and quad pixel 95d that are sensitive to green light.

[0154] With respect to the first direction D1, the well contact 64 may extend across two or more pixels 10, may extend across three or more pixels 10, or may extend across ten or more pixels 10. With respect to the second direction D2, the well contact 64 may extend across two or more pixels 10, may extend across three or more pixels 10, or may extend across ten or more pixels 10.

[0155] The well contact 64 may have an open frame shape instead of a closed frame shape in a plan view. Of the multiple quad pixels 95, specific quad pixels 95 sensitive to light of a predetermined color may be surrounded by an open frame shape, and the other quad pixels 95 may be surrounded by a closed frame shape. In this way, the leakage current from the amplification transistor 22 and / or the leakage current from the reset transistor 26 described above can be suppressed in the specific quad pixels 95. The specific quad pixels 95 are, for example, the quad pixel 95a and the quad pixel 95d sensitive to green light.

[0156] 13 is a plan view showing the layout within a plurality of pixels 10 in a first example of embodiment 6, and is a plan view showing the positions in a plan view of a plurality of well contacts 64 in a semiconductor substrate 60. FIG. 14 is a plan view showing the layout within a plurality of pixels 10 in a second example of embodiment 6, and is a plan view showing the positions in a plan view of a plurality of well contacts 64 in a semiconductor substrate 60.

[0157] 13 , in a plan view, the well contact 64 extends over a range including a first end to a second end in the vertical direction of the pixel array. In a plan view, the well contact 64 has a plurality of portions. Each of the plurality of portions extends across adjacent pixels 10 in the horizontal direction. The plurality of portions includes a first portion 64x1 and a second portion 64x2. In a plan view, the first portion 64x1 extends across pixels 10a and 10c. In a plan view, the second portion 64x2 extends across pixels 10b and 10d.

[0158] Specifically, the imaging device 100 includes a plurality of well contacts 64. In a first example shown in Fig. 13 , the plurality of well contacts 64 are arranged in the horizontal direction so that each of the plurality of well contacts 64 extends in a range including a first end to a second end in the vertical direction of the pixel array. In the example of Fig. 13 , the plurality of well contacts 64 are arranged in the horizontal direction at the same pitch as the pitch at which the pixels 10 are arranged in the horizontal direction in the pixel array. Each of the plurality of well contacts 64 has a plurality of portions. Each of the plurality of portions extends across adjacent pixels 10 in the horizontal direction.

[0159] 14 , in a plan view, the well contact 64 extends in a range including the third end to the fourth end in the horizontal direction of the pixel array. In a plan view, the well contact 64 has multiple portions. Each of the multiple portions extends across vertically adjacent pixels 10. The multiple portions include a third portion 64x3 and a fourth portion 64x4. In a plan view, the third portion 64x3 extends across pixels 10a and 10b. In a plan view, the fourth portion 64x4 extends across pixels 10c and 10d.

[0160] Specifically, the imaging device 100 includes a plurality of well contacts 64. In a second example shown in FIG. 14 , the plurality of well contacts 64 are arranged in the vertical direction so that each of the plurality of well contacts 64 extends in a range including the third end to the fourth end in the horizontal direction of the pixel array. In the example of FIG. 14 , the plurality of well contacts 64 are arranged in the vertical direction at the same pitch as the pitch at which the pixels 10 are arranged in the vertical direction in the pixel array. Each of the plurality of well contacts 64 has a plurality of portions. Each of the plurality of portions extends across adjacent pixels 10 in the vertical direction. In other words, each of the plurality of portions is continuous across adjacent pixels 10 in the vertical direction.

[0161] In the first and second examples of the sixth embodiment, the well contact 64 extends across the entire pixel array in plan view, which is advantageous from the viewpoint of suppressing shading.

[0162] In the pixel arrays according to the first and second examples of the sixth embodiment, the pixels 10 are arranged in a first direction D1 and a second direction D2. The well contacts 64 are arranged in the second direction D2, with the first direction D1 being the longitudinal direction of each well contact 64.

[0163] Seventh Embodiment FIG. 15 is a plan view showing the layout in a plurality of pixels 10 in a seventh embodiment, and is a plan view showing the positions of well contacts 64 in a semiconductor substrate 60 in a plan view.

[0164] In the seventh embodiment, the well contact 64 has a lattice shape 64L in a plan view. The lattice shape 64L includes a plurality of first bars 64A extending in a first direction D1 and a plurality of second bars 64B extending in a second direction D2. The pixels 10 are arranged in each region partitioned by the lattice shape 64L.

[0165] The well contact 64 having the lattice shape 64L of the seventh embodiment makes it easy to ensure the area of ​​the well contact 64. This is advantageous from the viewpoint of suppressing shading. Furthermore, the well contact 64 having the lattice shape 64L of the seventh embodiment is suitable for suppressing shading in both the first direction D1 and the second direction D2.

[0166] 16 is a plan view showing the layout in a plurality of pixels 10 in an embodiment 8, and showing the positions in a plan view of a plurality of well contacts 64 in a semiconductor substrate 60 and the positions in a plan view of a plurality of front surface side contacts 94. FIG. 17 is a cross-sectional view for explaining the front surface side contacts 94.

[0167] 16, the contact wiring 200 is connected to a plurality of front-side contacts 94. Each front-side contact 94 electrically connects the contact wiring 200 to a well region 65p. A voltage can be supplied to the well region 65p via the contact wiring 200 and the front-side contacts 94 in this order. This voltage supply contributes to fixing the potential of the well region 65p. In the example of FIG. 17, at least a portion of the contact wiring 200 is included in the wiring layer 80b.

[0168] The front-side contact 94 includes at least one selected from the group consisting of, for example, a metal and a metal compound. The metal is, for example, copper or tungsten. The metal compound is, for example, a metal nitride or a metal oxide. The front-side contact 94 may include the same material as the material included in the wiring layer 80b.

[0169] In the eighth embodiment, a voltage from the voltage supply circuit 48 is supplied to the well region 65p via the contact wiring 200 and the front surface side contact 94 in this order. However, it is also possible to employ a configuration in which a voltage from a power source external to the imaging device 100 is supplied to the well region 65p via the contact wiring 200 and the front surface side contact 94 in this order.

[0170] 17 , in this embodiment, the surface-side contact 94 includes a plug portion 94a and a pad portion 94b. The well region 65p includes a first region 65p1 and a second region 65p2. The second region 65p2 is surrounded by the first region 65p1. The impurity concentration of the second region 65p2 is higher than the impurity concentration of the first region 65p1. The contact wiring 200, the plug portion 94a, the pad portion 94b, and the second region 65p2 are electrically connected in this order.

[0171] 17, the front surface contact 94 is in contact with the well region 65p. Specifically, the pad portion 94b is in contact with the second region 65p2.

[0172] In the pixel array of embodiment 8, the pixels 10 are aligned in a first direction D1 and a second direction D2. In a plan view, the multiple well contacts 64 are aligned in the second direction D2, with the first direction D1 being the longitudinal direction of each well contact 64. In the example of Fig. 16, a surface-side contact 94 is electrically connected to the well region 65p of each pixel 10. The number of surface-side contacts 94 electrically connected to the well region 65p of each pixel 10 may be one or may be two or more.

[0173] 16, the first direction D1 is the horizontal direction and the second direction D2 is the vertical direction, but the first direction D1 may be the vertical direction and the second direction D2 may be the horizontal direction.

[0174] Here, the seventh embodiment and the eighth embodiment will be compared.

[0175] Unlike the eighth embodiment, the seventh embodiment does not require the front surface side contact 94. This is advantageous from the viewpoint of reducing the material for the front surface side contact 94. Furthermore, according to the seventh embodiment, the layout of the wiring layer 80b is less likely to be restricted than in the eighth embodiment.

[0176] According to the eighth embodiment, it is easier to reduce the area occupied by the multiple well contacts 64 compared to the seventh embodiment. This is advantageous from the viewpoint of reducing implantation defects when forming the well contacts 64 by ion implantation. Fewer implantation defects can contribute to improving image quality. Furthermore, when a configuration is adopted in which the well contacts 64 and the transistors do not overlap in a plan view, the small area occupied by the multiple well contacts 64 is advantageous from the viewpoint of miniaturization of the imaging device.

[0177] Ninth Embodiment FIG. 18 is a cross-sectional view of a ninth embodiment showing a cross-section of the imaging region R1 and a cross-section of the guard ring region R3.

[0178] In the ninth embodiment, the guard ring region R3 includes a plug px, a silicide region 55, a p-type semiconductor implantation region 56, an insulating region 57, a well region 65p, a support substrate 61p, a semiconductor region 63p, and a well contact 64. The plug px is connected to a semiconductor substrate 60. In the guard ring region R3, the silicide region 55, the semiconductor implantation region 56, the insulating region 57, the well region 65p, the support substrate 61p, the semiconductor region 63p, and the well contact 64 are included in the semiconductor substrate 60. In a plan view, the silicide region 55 and the semiconductor implantation region 56 are surrounded by the insulating region 57.

[0179] The plug px includes, for example, at least one selected from the group consisting of a metal and a metal compound. The metal is, for example, copper, tungsten, etc. The metal compound is, for example, a metal nitride, a metal oxide, etc.

[0180] In the ninth embodiment, the plug px in the guard ring region R3, the silicide region 55 in the guard ring region R3, the semiconductor implantation region 56 in the guard ring region R3, the well region 65p in the guard ring region R3, the well contact 64 in the guard ring region R3, the support substrate 61p in the guard ring region R3, the support substrate 61p in the imaging region R1, the well contact 64 in the imaging region R1, and the well region 65p in the imaging region R1 are electrically connected in this order. In a plan view, the guard ring region R3 is located outside the imaging region R1. This makes it easy to distance the well contact 64 in the guard ring region R3 from various transistors in the imaging region R1, including the charge storage portion 67n, in a plan view. Therefore, in this configuration, by employing a well contact 64 with a large area in a plan view in the guard ring region R3, it is possible to suppress the resistance of the well contact 64 in the guard ring region R3 while suppressing the leakage current of the transistors. This is advantageous from the perspective of suppressing shading. In this embodiment, the area of ​​the well contact 64 in the guard ring region R3 in a plan view is larger than the area of ​​the well contact 64 in the imaging region R1 in a plan view.

[0181] Silicide is a compound of metal and silicon. Silicon is a concept that encompasses polysilicon. The silicide region 55 reduces the contact resistance between the plug px and the semiconductor substrate 60. This is advantageous from the viewpoint of suppressing shading and streaking.

[0182] Tenth Embodiment FIG. 19 is a cross-sectional view of a tenth embodiment showing a cross-section of the imaging region R1 and a cross-section of the guard ring region R3.

[0183] In the tenth embodiment, the imaging region R1 includes a top layer 221 and a bottom layer 223. In the bottom layer 223, a reset transistor 26 is provided on a semiconductor substrate 60. In the top layer 221, an amplification transistor 22 and a selection transistor 24 are provided on a semiconductor substrate 160. The semiconductor substrate 60 and the semiconductor substrate 160 each extend into both the imaging region R1 and the guard ring region R3. The semiconductor substrate 60 and the semiconductor substrate 160 are stacked on top of each other. Here, "the semiconductor substrate 60 and the semiconductor substrate 160 are stacked on top of each other" encompasses both a configuration in which another layer is interposed between the semiconductor substrate 60 and the semiconductor substrate 160 and a configuration in which no other layer is interposed between them.

[0184] The semiconductor substrate 160 includes the silicide region 55, the p-type semiconductor implantation region 56, the insulating region 57, and the well region 65p. However, the semiconductor substrate 160 does not include the support substrate 61p, the semiconductor region 63p, or the well contact 64.

[0185] A connection portion 170 is provided in the imaging region R1, and a connection portion 270 is provided in the guard ring region R3. The connection portion 170 and the connection portion 270 each electrically connect the support substrate 61p of the semiconductor substrate 60 to the well region 65p of the semiconductor substrate 160. Therefore, the effect of suppressing shading and streaking due to the low resistance of the support substrate 61p of the semiconductor substrate 60 can also be exerted in the semiconductor substrate 160.

[0186] 19 , at least a portion of the connection portion 170 is provided outside the semiconductor substrate 60 and the semiconductor substrate 160. At least a portion of the connection portion 270 is provided outside the semiconductor substrate 60 and the semiconductor substrate 160. The connection portion 170 and the connection portion 270 include a plug px and a plug py, respectively. The plug px is connected to the semiconductor substrate 60. The plug py is connected to the semiconductor substrate 160.

[0187] The plug py includes, for example, at least one selected from the group consisting of a metal and a metal compound. The metal is, for example, copper, tungsten, etc. The metal compound is, for example, a metal nitride, a metal oxide, etc.

[0188] In the imaging region R1, the connection portion 170 electrically connects the support substrate 61p of the semiconductor substrate 60, the well contact 64 of the semiconductor substrate 60, the well region 65p of the semiconductor substrate 60, the semiconductor injection region 56 of the semiconductor substrate 60, the silicide region 55 of the semiconductor substrate 60, the plug px, the plug py, the silicide region 55 of the semiconductor substrate 160, the semiconductor injection region 56 of the semiconductor substrate 160, and the well region 65p of the semiconductor substrate 160 in this order. The connection portion 270 electrically connects the support substrate 61p of the semiconductor substrate 60, the well contact 64 of the semiconductor substrate 60, the well region 65p of the semiconductor substrate 60, the semiconductor injection region 56 of the semiconductor substrate 60, the silicide region 55 of the semiconductor substrate 60, the plug px, the plug py, the silicide region 55 of the semiconductor substrate 160, the semiconductor injection region 56 of the semiconductor substrate 160, and the well region 65p of the semiconductor substrate 160 in this order in the guard ring region R3.

[0189] 19 , in each of the connection portion 170 and the connection portion 270, the plug px is in contact with the silicide region 55 of the semiconductor substrate 60. The plug py is in contact with the silicide region 55 of the semiconductor substrate 160. The silicide region 55 of the semiconductor substrate 60 reduces the contact resistance between the plug px and the semiconductor substrate 60. The silicide region 55 of the semiconductor substrate 160 reduces the contact resistance between the plug py and the semiconductor substrate 160. These are advantageous from the viewpoint of realizing, in the semiconductor substrate 160, the effect of suppressing shading and streaking due to the low resistance of the support substrate 61p of the semiconductor substrate 60.

[0190] The configuration of the top layer 221 and the configuration of the bottom layer 223 may be interchanged in the example of Fig. 19. In the example of Fig. 19, the imaging region R1 is made up of two layers. The imaging region R1 may also be made up of three or more layers.

[0191] Eleventh Embodiment FIG. 20 is a cross-sectional view of an eleventh embodiment showing a cross-section of the imaging region R1, as well as cross-sections of the peripheral region R2 and the guard ring region R3.

[0192] In the eleventh embodiment, the imaging region R1 includes a top layer 221 and a middle layer 222. The peripheral region R2 includes a bottom layer 223. The top layer 221 of the eleventh embodiment shown in Fig. 20 has a configuration similar to that of the top layer 221 of the tenth embodiment shown in Fig. 19. The middle layer 222 of the eleventh embodiment shown in Fig. 20 has a configuration similar to that of the bottom layer 223 of the tenth embodiment shown in Fig. 19.

[0193] In the bottom layer 223 of embodiment 11, the transistor 27a and the transistor 27b are provided on a semiconductor substrate 260. The transistor 27a and the transistor 27b are logic transistors. The transistor 27a is an n-channel MOSFET. The transistor 27b is a p-channel MOSFET. A logic circuit including the transistor 27a and the transistor 27b is configured in the bottom layer 223. The semiconductor substrate 260 extends into both the peripheral region R2 and the guard ring region R3. The semiconductor substrate 60, the semiconductor substrate 160, and the semiconductor substrate 260 are stacked on top of each other.

[0194] The semiconductor substrate 260 includes a silicide region 55, a p-type semiconductor implantation region 56, an insulating region 57, a p-type well region 65p, an n-type well region 110, a semiconductor region 111, a support substrate 61p, a semiconductor region 63p, and a well contact 64. The well region 65p and the well region 110 are separated by an insulating region 57. The well contact 64 penetrates the semiconductor region 63p and electrically connects the well region 65p and the support substrate 61p.

[0195] The semiconductor substrate 260 includes impurity regions 71an, 71bn, 72an, 72bn, 73an, 73bn, 74an, and 74bn. The impurity regions 71an, 71bn, 72an, and 72bn are n-type impurity regions and are located within the p-type well region 65p. The impurity regions 73an, 73bn, 74an, and 74bn are p-type impurity regions and are located within the n-type well region 110.

[0196] The impurity region 71an is one of the source and drain of the transistor 27a. The impurity region 71bn is the other of the source and drain of the transistor 27a. The impurity region 74an is one of the source and drain of the transistor 27b. The impurity region 74bn is the other of the source and drain of the transistor 27b.

[0197] The impurity region 71an is connected to the plug via an impurity region 72an. The impurity region 71bn is connected to the plug via an impurity region 72bn. The impurity region 74an is connected to the plug via an impurity region 73an. The impurity region 74bn is connected to the plug via an impurity region 73bn. The gate electrode 27ae of the transistor 27a is connected to the plug. The gate electrode 27be of the transistor 27b is connected to the plug.

[0198] A connection portion 170 is provided in the imaging region R1, and a connection portion 370 is provided so as to straddle the peripheral region R2 and the guard ring region R3. The connection portion 170 and the connection portion 370 each electrically connect the support substrate 61p of the semiconductor substrate 60 to the well region 65p of the semiconductor substrate 160. Therefore, the effect of suppressing shading and streaking due to the low resistance of the support substrate 61p of the semiconductor substrate 60 can also be exerted in the semiconductor substrate 160.

[0199] Furthermore, the connection portion 370 is also electrically connected to the well contact 64 of the semiconductor substrate 260. This makes it possible to suppress the variation in potential between the well region 65p in the imaging region R1 and the well region 65p in the peripheral region R2. This can reduce noise in the transistors and improve image quality.

[0200] At least a portion of the connection portion 370 is provided outside the semiconductor substrate 60, the semiconductor substrate 160, and the semiconductor substrate 260. The connection portion 370 includes a plug px, a plug py, a plug pz1, and a plug pz2. The plugs px, py, and pz1 of the connection portion 370 are located in the guard ring region R3. The plug pz2 of the connection portion 370 is located in the peripheral region R2. The plug px of the connection portion 370 is connected to the semiconductor substrate 60. The plug py of the connection portion 370 is connected to the semiconductor substrate 160. The plugs pz1 and pz2 of the connection portion 370 are connected to the semiconductor substrate 260.

[0201] The plugs pz1 and pz2 each include, for example, at least one selected from the group consisting of a metal and a metal compound. The metal is, for example, copper, tungsten, etc. The metal compound is, for example, a metal nitride, a metal oxide, etc.

[0202] The connection portion 370 electrically connects the support substrate 61p of the semiconductor substrate 60, the well contact 64 of the semiconductor substrate 60, the well region 65p of the semiconductor substrate 60, the semiconductor injection region 56 of the semiconductor substrate 60, the silicide region 55 of the semiconductor substrate 60, the plug px, the plug py, the silicide region 55 of the semiconductor substrate 160, the semiconductor injection region 56 of the semiconductor substrate 160, and the well region 65p of the semiconductor substrate 160 in this order.

[0203] The connection portion 370 electrically connects the support substrate 61p of the semiconductor substrate 60, the well contact 64 of the semiconductor substrate 60, the well region 65p of the semiconductor substrate 60, the semiconductor injection region 56 of the semiconductor substrate 60, the silicide region 55 of the semiconductor substrate 60, the plug px, the plug pz1, the silicide region 55 of the semiconductor substrate 260, the semiconductor injection region 56 of the semiconductor substrate 260, and the well contact 64 of the semiconductor substrate 260 in this order.

[0204] The connection portion 370 electrically connects the support substrate 61p of the semiconductor substrate 60, the well contact 64 of the semiconductor substrate 60, the well region 65p of the semiconductor substrate 60, the semiconductor injection region 56 of the semiconductor substrate 60, the silicide region 55 of the semiconductor substrate 60, the plug px, the plug pz2, the silicide region 55 of the semiconductor substrate 260, the semiconductor injection region 56 of the semiconductor substrate 260, and the well contact 64 of the semiconductor substrate 260 in this order.

[0205] 20 , in each of the connection portion 170 and the connection portion 370, the plug px is in contact with the silicide region 55 of the semiconductor substrate 60. The plug py is in contact with the silicide region 55 of the semiconductor substrate 160. In the connection portion 370, the plug pz1 and the plug pz2 are in contact with the silicide region 55 of the semiconductor substrate 260.

[0206] Twelfth Embodiment FIG. 21 is a cross-sectional view of a twelfth embodiment showing a cross-section of the imaging region R1 and a cross-section of the guard ring region R3.

[0207] In this embodiment, the well region 65p and the support substrate 61p may be connected by the well contact 64 throughout the entire imaging region R1 and the guard ring region R3. That is, the well contact 64 may be disposed above the support substrate 61p, and the well region 65p may be disposed above the well contact 64. Specifically, the support substrate 61p, the well contact 64, and the well region 65p may be disposed adjacent to one another in this order. In this embodiment, a p-type three-layer structure, i.e., a "ppp layer," is thus formed. Similar to the configuration of this embodiment, the well contact 64 of the middle layer 222 in FIG. 20 may connect the well region 65p and the support substrate 61p throughout the entire imaging region R1 and the guard ring region R3.

[0208] The arrangement of the imaging region R1, the peripheral region R2, the guard ring region R3, and the peripheral circuit 40 is not limited to the example shown in FIG. 1 . For example, the imaging region R1 and the peripheral region R2 may be stacked on top of each other. In this case, the imaging region R1 and the peripheral circuit 40 may be stacked on top of each other. This stacked structure is exemplified, for example, in the above-described embodiments 10 and 11 shown in FIGS. 19 and 20 .

[0209] In this embodiment, the impurity concentration of the well contact 64 is higher than the impurity concentration of the semiconductor region 63p. When the impurity concentrations have such a magnitude relationship, it is easy to realize a configuration in which the resistivity of the well contact 64 is lower than the resistivity of the semiconductor region 63p. The support substrate 61p is electrically connected to the well region 65p via the well contact 64. This configuration makes it possible to take advantage of the low resistance of the support substrate 61p to supply voltage to the well region 65p via the support substrate 61p with a limited voltage drop. This is advantageous from the perspective of suppressing shading. Furthermore, this configuration allows the low resistance of the support substrate 61p to contribute to fixing the potential of the well region 65p. This is advantageous from the perspective of suppressing streaking.

[0210] In this embodiment, the impurity concentration of the well contact 64 is uniform within the imaging region R1, so when the well contact 64 is formed by ion implantation, implantation defects are uniform within the imaging region R1, which is advantageous from the viewpoint of suppressing shading, which is non-uniformity within a pixel.

[0211] Thirteenth Embodiment FIG. 22 is a cross-sectional view of a thirteenth embodiment showing a cross-section of the imaging region R1 and a cross-section of the guard ring region R3.

[0212] In this embodiment, the well region 65p and the support substrate 61p may be connected by a well contact 64 having a concentration gradient. An example of the concentration gradient of the well contact 64 is shown in FIG.

[0213] 23 is a graph showing an example of the impurity concentration distribution of the well contact 64, well region 65p, semiconductor region 63p, and support substrate 61p in the direction from the first surface 60s1 toward the second surface 60s2 of the semiconductor substrate 60 along lines A-A' and B-B' in FIG. 22. In FIG. 23, the dashed-dotted line indicates the impurity concentration distribution of the well region 65p, the well contact 64 having the first concentration gradient, and the support substrate 61p in the direction from the first surface 60s1 toward the second surface 60s2 of the semiconductor substrate 60 along line A-A' in FIG. 22. As shown by the dashed-dotted line in FIG. 23, for example, the well contact 64 may include a region in which the impurity concentration monotonically increases in the direction from the first surface 60s1 toward the second surface 60s2 of the semiconductor substrate 60.

[0214] 23, the dashed lines indicate the impurity concentration distributions of the well region 65p, the well contact 64 having the second concentration gradient, and the support substrate 61p in the direction from the first surface 60s1 toward the second surface 60s2 of the semiconductor substrate 60 along line A-A' in FIG. 22. As indicated by the dashed lines in FIG. 23, for example, the well contact 64 may include a region having a lower impurity concentration than the well region 65p. Also, in FIG. 23, the solid lines indicate the impurity concentration distributions of the well region 65p, the semiconductor region 63p, and the support substrate 61p in the direction from the first surface 60s1 toward the second surface 60s2 of the semiconductor substrate 60 along line B-B' in FIG.

[0215] Furthermore, it is not essential that the well contact 64 penetrates from the semiconductor region 63p side into the support substrate 61p in the thickness direction of the semiconductor substrate 60. The well contact 64 may or may not penetrate from the semiconductor region 63p side into the well region 65p in the thickness direction of the semiconductor substrate 60. The well contact 64 may or may not penetrate from the semiconductor region 63p side into the support substrate 61p in the thickness direction of the semiconductor substrate 60.

[0216] This embodiment is advantageous in that it allows the impurity concentration of the well contact 64 to be changed, which can contribute to improving image quality. For example, if the well contact 64 includes a region with a lower impurity concentration than the well region 65p, when carriers diffuse from the support substrate 61p, the carriers diffused in the region with the lower impurity concentration are likely to be trapped. Therefore, leakage current via these carriers is less likely to reach the well region 65p, which can contribute to improving image quality.

[0217] For example, if the well contact 64 includes a region whose impurity concentration monotonically increases from the first surface 60s1 toward the second surface 60s2 of the semiconductor substrate 60, it is easy to realize a configuration in which the resistivity of the well contact 64 is lower than that of the semiconductor region 63p and lower than that of the well region 65p. The support substrate 61p is electrically connected to the well region 65p via the well contact 64. This configuration makes it possible to take advantage of the low resistance of the support substrate 61p to supply voltage to the well region 65p via the support substrate 61p with a limited voltage drop. This is advantageous from the perspective of suppressing shading. Furthermore, this configuration allows the low resistance of the support substrate 61p to contribute to fixing the potential of the well region 65p. This is advantageous from the perspective of suppressing streaking.

[0218] Furthermore, according to this embodiment, the impurity concentration of the well contact 64 can be changed depending on the physical distance between the well contact 64 and the transistor. For example, when the physical distance between the well contact 64 and the transistor is short, a low impurity concentration can be used to minimize leakage current via implantation defects, and when the physical distance between the well contact 64 and the transistor is long, a high impurity concentration can be used to reduce the resistance of the well contact 64. This configuration is suitable for improving image quality.

[0219] Fourteenth Embodiment FIG. 24 is a cross-sectional view of a fourteenth embodiment showing a cross-section of the imaging region R1 and a cross-section of the guard ring region R3.

[0220] In this embodiment, the well region 65p and the support substrate 61p may be connected by a well contact 64 having a concentration gradient throughout the entire imaging region R1 and guard ring region R3. That is, the well contact 64 having a concentration gradient may be disposed above the support substrate 61p, and the well region 65p may be disposed above the well contact 64 having a concentration gradient. Specifically, the support substrate 61p, the well contact 64 having a concentration gradient, and the well region 65p may be disposed adjacent to one another in this order. In this embodiment, a p-type three-layer structure, i.e., a "ppp layer," is configured in this way.

[0221] According to this embodiment, it is possible to change the impurity concentration of the well contact 64 even within a pixel. For example, by employing well contacts 64 with a high impurity concentration near the impurity regions 68bn, 68cn, and 68dn, which are electrical paths where large voltage fluctuations can occur, it is possible to achieve a potential fixing effect.

[0222] Furthermore, according to this embodiment, the impurity concentration of the well contact 64 can be changed depending on the physical distance between the well contact 64 and the transistor. For example, when the physical distance between the well contact 64 and the transistor is short, a low impurity concentration can be used to minimize leakage current via implantation defects, and when the physical distance between the well contact 64 and the transistor is long, a high impurity concentration can be used to reduce the resistance of the well contact 64. This configuration is suitable for improving image quality.

[0223] Furthermore, according to this embodiment, the impurity concentration of the well contact 64 can be changed depending on the intended use of the transistor.

[0224] The amplifier transistor 22 outputs a signal corresponding to the potential of the charge storage section 67n. To improve driving power, the impurity concentration in the source and drain of the amplifier transistor 22 is typically higher than the impurity concentration in the source and drain of the select transistor 24 and other transistors. Furthermore, the conductivity type of the source and drain of the amplifier transistor 22 is the opposite of that of the well contact 64, i.e., n-type. Defects can cause leakage current from such an amplifier transistor 22, degrading image quality. However, with the above configuration, the impurity concentration of the well contact 64 near the source and drain of the amplifier transistor 22 can be reduced. This can suppress leakage current from the amplifier transistor 22, improving image quality.

[0225] The reset transistor 26 includes a charge storage portion 67n. The charge storage portion 67n is a portion where charge obtained by photoelectric conversion is stored. The conductivity type of the charge storage portion 67n is opposite to that of the well contact 64, i.e., n-type. Defects can cause leakage current from such a reset transistor 26 and degrade image quality. However, with the above configuration, the impurity concentration of the well contact 64 near the source and drain of the reset transistor 26 can be reduced. This can suppress leakage current from the reset transistor 26 and improve image quality.

[0226] The selection transistor 24 includes an impurity region 68cn and an impurity region 68dn. Compared to the amplifier transistor 22, the influence of leakage current of the selection transistor 24 on image quality is limited, so the impurity concentration of the well contact 64 can be increased. The selection transistor 24 determines the timing of outputting a signal from the amplifier transistor 22. The signal is typically a voltage. In other words, it is an electrical path through which large voltage fluctuations can occur. By employing a high impurity concentration near the impurity regions 68bn, 68cn, and 68dn, a potential fixing effect can be achieved. This is advantageous from the perspective of suppressing streaking.

[0227] Fifteenth Embodiment FIG. 25 is a cross-sectional view of a fifteenth embodiment showing a cross-section of the imaging region R1 and a cross-section of the guard ring region R3.

[0228] 25, in the fifteenth embodiment, an impurity region 91n is disposed in the semiconductor region 63p. The impurity region 91n is an impurity region of the first conductivity type. Specifically, the support substrate 61p, the semiconductor region 63p, the impurity region 91n, the semiconductor region 63p, and the well region 65p may be disposed adjacent to one another in this order. In this manner, in the present embodiment, a five-layer structure of p-type and n-type layers, i.e., a "ppnpp layer," is formed.

[0229] The well contact 64 may have a concentration gradient or may have a constant concentration.

[0230] In this embodiment, an impurity region 91n may be disposed in the semiconductor region 63p. By applying a bias voltage to the impurity region 91n, carriers that may be generated from the support substrate 61p can be discharged to the power supply via the impurity region 91n. This configuration is advantageous from the viewpoint of reducing leakage current and improving image quality.

[0231] The arrangement of the peripheral region R2 and the peripheral circuit 40 is not limited to the example shown in FIG. 25 . For example, the imaging region R1 and the peripheral region R2 may be stacked on top of each other. In this case, the imaging region R1 and the peripheral circuit 40 may be stacked on top of each other. This stacked structure is exemplified, for example, in the above-described embodiments 10 and 11 shown in FIGS. 19 and 20 . In the example of FIG. 20 , a semiconductor substrate 60 and a semiconductor substrate 260 are stacked on top of each other, a plurality of pixels are formed using the semiconductor substrate 60, and some or all of the vertical scanning circuit 46, the horizontal signal readout circuit 44, the voltage supply circuit 48, the control circuit 42, the analog circuit 41, and the logic circuit 43 are provided on the semiconductor substrate 260. Furthermore, the semiconductor substrate 60 and the semiconductor substrate 160 are stacked on top of each other. Here, "the semiconductor substrate 60 and the semiconductor substrate 160 are stacked on top of each other" encompasses both a configuration in which another layer is interposed between the semiconductor substrate 60 and the semiconductor substrate 160 and a configuration in which no other layer is interposed between the semiconductor substrate 60 and the semiconductor substrate 160.

[0232] In the first to fifteenth embodiments, in a typical example, the boundary between adjacent pixels 10 in a plan view is included in an element isolation region 69 located outside a pixel transistor group, which is the smallest unit repeated in the pixel array. The pixel transistor group includes, for example, an amplifier transistor 22, a selection transistor 24, and a reset transistor 26.

[0233] In the first to fifteenth embodiments, the boundary between adjacent pixels 10 can be explained by at least one selected from the group consisting of the following first to third explanations. The concept of the boundary according to at least one selected from the group consisting of the first to third explanations includes, for example, the expression "the support substrate 61p includes a spanning portion extending across two or more pixels 10" in the first embodiment, the expression "the well contact 64 is included in each of the plurality of pixels 10" in the second embodiment, the expression "in a planar view, the well contact 64 extends across at least two pixels 10" in the third embodiment, the expression "in a planar view, the well contact 64 extends across four pixels 10a, 10b, 10c, and 10d" in the fourth embodiment, the expression "in a planar view, the first portion 64x1 extends across pixel 10a and pixel 10c" in the sixth embodiment, and the expression "in a planar view, the second portion 64x2 extends across pixel 10b and pixel 10d" in the sixth embodiment, The same can be applied to the expression "in plan view, the third portion 64x3 extends across the pixel 10a and the pixel 10b" in the sixth embodiment, and the expression "in plan view, the fourth portion 64x4 extends across the pixel 10c and the pixel 10d" in the sixth embodiment. The same applies to the concept of boundaries in the above typical examples.

[0234] In the first to fifteenth embodiments, each of the multiple pixels 10 includes a pixel electrode 12a. In the first description, in a plan view, the range of each pixel 10 is a range having the geometric center of the pixel electrode 12a as its geometric center. The boundary between adjacent pixels 10 is determined based on the range of the pixel 10 thus determined. In a plan view, the boundary between adjacent pixel electrodes 12a can be spatially separated. In a plan view, the boundary between adjacent pixels 10 can overlap with the region between adjacent spatially separated pixel electrodes 12a.

[0235] In the first to fifteenth embodiments, each of the multiple pixels 10 includes a microlens 130. In the second description, in a planar view, the range of each pixel 10 is a range having the geometric center of the microlens 130 as its geometric center. The boundary between adjacent pixels 10 is determined based on the range of the pixel 10 thus given. The microlens 130 has a convex shape, and adjacent microlenses 130 can be connected by a concave portion. In a planar view, the boundary between adjacent pixels 10 can overlap with the concave portion.

[0236] In the first to fifteenth embodiments, each of the multiple pixels 10 includes a color filter 120. In the third description, in a plan view, the range of each pixel 10 is a range having the geometric center of the color filter 120 as its geometric center. The boundary between adjacent pixels 10 is determined based on the range of the pixel 10 thus determined. In a plan view, adjacent color filters 120 may be sensitive to light of different colors. In a plan view, the boundary between adjacent pixels 10 may overlap with the boundary between adjacent color filters 120 that are sensitive to light of different colors.

[0237] In the above-described first to fifteenth embodiments, the photoelectric conversion unit 12 is located outside the semiconductor substrate 60. The photoelectric conversion unit 12 includes a pixel electrode 12 a, a counter electrode 12 c, and a photoelectric conversion layer 12 b. The photoelectric conversion layer 12 b is located between the pixel electrode 12 a and the counter electrode 12 c. However, the photoelectric conversion unit 12 may be a photodiode located within the semiconductor substrate 60.

[0238] In the above-described first to fifteenth embodiments, the n-channel and p-channel types of the various transistors may be interchanged. For example, in the first to fifteenth embodiments, the amplifier transistor 22, the select transistor 24, and the reset transistor 26 are each an n-channel MOSFET. However, the amplifier transistor 22, the select transistor 24, and the reset transistor 26 may each be a p-channel MOSFET. It is not necessary for all of these transistors to be unified as either an n-channel MOSFET or a p-channel MOSFET. When each of the transistors in a pixel is an n-channel MOSFET and electrons are used as signal charge, the source and drain positions of each of these transistors may be interchanged. The transistors 27a and 27b may also be n-channel MOSFETs or p-channel MOSFETs.

[0239] In the above-described first to fifteenth embodiments, the n-type and p-type impurity regions of the various impurity regions may be interchanged. For example, in the first to fifteenth embodiments, the charge accumulation portion 67n, the impurity region 68an, the impurity region 68bn, the impurity region 68cn, the impurity region 68dn, the impurity region 71an, the impurity region 71bn, the impurity region 72an, and the impurity region 72bn are n-type impurity regions. However, these impurity regions may be p-type impurity regions. Also, in the first to fifteenth embodiments, the support substrate 61p, the semiconductor region 63p, the well region 65p, the well contact 64, the impurity region 73an, the impurity region 73bn, the impurity region 74an, and the impurity region 74bn are p-type impurity regions. However, these impurity regions may be n-type impurity regions.

[0240] Sixteenth Embodiment A camera system 705 according to a sixteenth embodiment will be described with reference to FIG.

[0241] 26 schematically illustrates an exemplary configuration of a camera system 705 according to embodiment 16. The camera system 705 includes a lens optical system 701, an imaging device 702, a system controller 703, and a signal processing circuit 704. The camera system 705 may be, for example, a smartphone, a digital camera, a video camera, or an in-vehicle camera. The signal processing circuit 704 is also referred to as a camera signal processing unit.

[0242] The lens optical system 701 may include a lens group including, for example, an autofocus lens and a zoom lens, and an aperture. The lens optical system 701 focuses light onto the imaging surface of the imaging device 702. The imaging devices according to the first to fifteenth embodiments described above can be widely used as the imaging device 702.

[0243] The system controller 703 controls the entire camera system 705. The system controller 703 is typically a semiconductor integrated circuit, such as a CPU (Central Processing Unit).

[0244] The signal processing circuit 704 has a function of processing an output signal from the imaging device 702. The signal processing circuit 704 receives output data from the imaging device 702 and performs processes such as gamma correction, color interpolation, spatial interpolation, and auto white balance. The imaging device 702 and the signal processing circuit 704 may be realized as a single semiconductor device. The semiconductor device may be, for example, a so-called SoC (System on a Chip). This configuration allows electronic devices that include the imaging device 702 as a part thereof to be further miniaturized. The signal processing circuit 704 is, for example, a DSP (Digital Signal Processor).

[0245] As can be understood from the above description, a camera system can include a lens optical system, an imaging device, and a signal processing circuit. The imaging device receives light that has passed through the lens optical system and outputs a signal. The signal processing circuit processes the signal.

[0246] (Additional Notes) The present disclosure discloses the following technology. In the following, terms shown in " " are used. Terms shown in " " may correspond to terms in the above embodiments as follows: A "first conductivity type" may correspond to one of the p-type and n-type in the embodiments. A "second conductivity type" may correspond to the other of the p-type and n-type in the embodiments. A "first semiconductor substrate" may correspond to the semiconductor substrate 60 in the embodiments. A "second semiconductor substrate" may correspond to the semiconductor substrate 160 in the embodiments. A "first impurity region" may correspond to the well region 65p in the embodiments. A "second impurity region" may correspond to the support substrate 61p in the embodiments. A "third impurity region" may correspond to the semiconductor region 63p in the embodiments. A "fourth impurity region" may correspond to the well contact 64 in the embodiments. A "fifth impurity region" may correspond to the charge accumulation portion 67n in the embodiments. The "sixth impurity region" may correspond to the impurity region 68bn of the embodiment. The "seventh impurity region" may correspond to the impurity region 91n of the embodiment. The "eighth impurity region" may correspond to the impurity region 68dn of the embodiment. The "ninth impurity region" may correspond to the impurity region 68an of the embodiment. The "first transistor" may correspond to the reset transistor 26 of the embodiment. The "second transistor" may correspond to the amplifier transistor 22 of the embodiment. The "third transistor" may correspond to the select transistor 24 of the embodiment. The "first plug" may correspond to the plug px of the embodiment. The "second plug" may correspond to the plug py of the embodiment. The "first silicide region" may correspond to the silicide region 55 of the semiconductor substrate 60 of the embodiment. The "second silicide region" may correspond to the silicide region 55 of the semiconductor substrate 160 of the embodiment. In the description of the embodiments, the terms in the embodiments may be replaced with the terms shown in " ". In the description of the following technology, the terms shown in " " may be replaced with the terms in the embodiments. The correspondence between terms is not limited to these.

[0247] (Technology 1) An imaging device comprising: a first semiconductor substrate having a first surface and a second surface opposite to the first surface; and a plurality of pixels, wherein the first semiconductor substrate includes: a first impurity region of a first conductivity type, at least a portion of which is located in the first surface; a second impurity region of the first conductivity type located closer to the second surface than the first impurity region; a third impurity region of the first conductivity type located between the first impurity region and the second impurity region; and at least one fourth impurity region of the first conductivity type passing through the third impurity region and electrically connecting the first impurity region and the second impurity region; and each of the plurality of pixels includes: a photoelectric conversion unit that converts light into electric charges; and a fifth impurity region of a second conductivity type that is located in the first impurity region and accumulates the electric charges,

[0248] Technique 1 is suitable for improving image quality.

[0249] (Technology 2) The imaging device according to Technology 1, wherein the impurity concentration of the at least one fourth impurity region is higher than the impurity concentration of the third impurity region.

[0250] Technique 2 can improve image quality.

[0251] (Technology 3) The imaging device according to Technology 1 or 2, wherein the impurity concentration of the at least one fourth impurity region is higher than the impurity concentration of the first impurity region.

[0252] Technique 3 can improve image quality.

[0253] (Technology 4) The imaging device according to any one of Technologies 1 to 3, wherein the impurity concentration of the first impurity region is higher than the impurity concentration of the third impurity region.

[0254] Technique 4 can improve image quality.

[0255] (Technology 5) The imaging device according to any one of Techniques 1 to 4, wherein in each of the plurality of pixels, an area of ​​the third impurity region in a plan view is larger than an area of ​​the fourth impurity region in the plan view.

[0256] The configuration of Technique 5 is an example configuration.

[0257] (Technology 6) The imaging device according to any one of Techniques 1 to 5, wherein in each of the plurality of pixels, an area of ​​a region in which the first impurity region is arranged is 80% or more of an area of ​​each of the plurality of pixels in a plan view.

[0258] Technique 6 can improve image quality.

[0259] (Technology 7) The imaging device according to any one of Techniques 1 to 6, wherein the first impurity region is separated from the second impurity region by the third impurity region.

[0260] Technique 7 can improve image quality.

[0261] (Technology 8) The imaging device according to any one of Techniques 1 to 7, wherein the at least one fourth impurity region includes a plurality of fourth impurity regions, and each of the plurality of pixels includes at least one corresponding fourth impurity region among the plurality of fourth impurity regions.

[0262] Technique 8 can improve image quality.

[0263] (Technology 9) The imaging device according to any one of Techniques 1 to 8, wherein the plurality of pixels include at least two pixels adjacent to each other, and the at least one fourth impurity region is disposed continuously across the at least two pixels.

[0264] Technique 9 can improve image quality.

[0265] (Technology 10) The imaging device according to Technology 9, wherein the plurality of pixels are arranged in a first direction and a second direction, the plurality of pixels include at least three pixels arranged in the first direction, and the at least one fourth impurity region is disposed continuously across the at least three pixels.

[0266] Technique 10 may improve image quality.

[0267] (Technology 11) The imaging device described in any one of Technologies 1 to 10, wherein the first semiconductor substrate further includes an imaging region in which the plurality of pixels are arranged and a guard ring region located outside the imaging region, the at least one fourth impurity region includes a plurality of fourth impurity regions, one of the plurality of fourth impurity regions is located in the imaging region, and one of the plurality of fourth impurity regions is located in the guard ring region.

[0268] Technique 11 can improve image quality.

[0269] (Technology 12) The imaging device described in any one of Technologies 1 to 11, wherein each of the plurality of pixels further includes: a first transistor including the fifth impurity region as one of a source and a drain; and a second transistor outputting a signal according to the potential of the fifth impurity region, and in a planar view, the at least one fourth impurity region does not overlap with either the first transistor or the second transistor.

[0270] Technique 12 may improve image quality.

[0271] (Technology 13) The imaging device described in any one of Technologies 1 to 12, wherein the plurality of pixels include a first pixel, the first pixel includes a second transistor that outputs a signal according to the potential of the fifth impurity region and includes a sixth impurity region as a source or a drain, and in a planar view, a distance between the at least one fourth impurity region and the sixth impurity region of the first pixel is smaller than a distance between the at least one fourth impurity region and the fifth impurity region of the first pixel.

[0272] Technique 13 can improve image quality.

[0273] (Technology 14) The imaging device according to any one of Techniques 1 to 13, wherein the at least one fourth impurity region does not overlap the fifth impurity region in a plan view.

[0274] Technique 14 may improve image quality.

[0275] (Technology 15) The imaging device according to any one of Technologies 1 to 14, further comprising: a second semiconductor substrate stacked on the first semiconductor substrate; and a connection portion that electrically connects the first impurity region and the second semiconductor substrate.

[0276] The configuration of Technique 15 is an example configuration.

[0277] (Technology 16) The imaging device according to any one of Techniques 1 to 15, wherein the first semiconductor substrate further includes a seventh impurity region of a second conductivity type located within the third impurity region.

[0278] (Technology 17) An imaging device comprising: a first semiconductor substrate having a first surface and a second surface opposite to the first surface; and a plurality of pixels, wherein the first semiconductor substrate includes: a first impurity region of a first conductivity type, at least a portion of which is located on the first surface; a second impurity region of the first conductivity type, which is located closer to the second surface than the first impurity region; and at least one fourth impurity region of the first conductivity type, which electrically connects the first impurity region and the second impurity region; and each of the plurality of pixels includes: a photoelectric conversion unit that converts light into charges; and a fifth impurity region of a second conductivity type, which is located in the first impurity region and accumulates the charges, and an impurity concentration of the second impurity region is higher than an impurity concentration of the first impurity region.

[0279] (Technology 18) The imaging device according to Technology 17, wherein the at least one fourth impurity region includes a region in which an impurity concentration of the at least one fourth impurity region monotonically increases from the first surface toward the second surface of the first semiconductor substrate.

[0280] (Technique 19) The imaging device according to Technique 17 or 18, wherein the at least one fourth impurity region includes a region in which the impurity concentration of the at least one fourth impurity region is lower than the impurity concentration of the first impurity region.

[0281] (Technology 20) The plurality of pixels include a first pixel and a second pixel adjacent to each other, each of the first pixel and the second pixel including: a second transistor outputting a signal according to a potential of the fifth impurity region and including a sixth impurity region as a source or a drain; and a third transistor determining a timing of outputting the signal from the second transistor and including an eighth impurity region as a source or a drain, wherein, in a plan view, a distance between the at least one fourth impurity region and the sixth impurity region of the first pixel is defined as a first distance, a distance between the at least one fourth impurity region and the fifth impurity region of the first pixel is defined as a second distance, a distance between the at least one fourth impurity region and the eighth impurity region of the second pixel is defined as a third distance, and a distance between the at least one fourth impurity region and the fifth impurity region of the second pixel is defined as a fourth distance, the first distance is smaller than both the second distance and the fourth distance, and the third distance is smaller than both the second distance and the fourth distance. 20. The imaging device according to any one of claims 1 to 19.

[0282] (Technology 21) An imaging device according to any one of technologies 1 to 20, wherein each of the plurality of pixels comprises: a ninth impurity region of the second conductivity type located within the first impurity region; and a first transistor including a source and a drain, wherein one of the source and the drain is the fifth impurity region, and the other of the source and the drain is the ninth impurity region, a PN junction between the first impurity region and the fifth impurity region includes a first portion, and a PN junction between the first impurity region and the ninth impurity region includes a second portion, and an impurity concentration of the first conductivity type in the first portion is equal to an impurity concentration of the first conductivity type in the second portion.

[0283] Technique 21 may improve image quality.

[0284] (Technology 22) The imaging device according to any one of Techniques 1 to 21, wherein a ratio of a dimension of the first impurity region in the thickness direction of the first semiconductor substrate to a dimension of the second impurity region in the thickness direction of the first semiconductor substrate is ½ or less.

[0285] The configuration of technique 22 is an example configuration.

[0286] (Technology 23) The imaging device according to any one of Techniques 1 to 22, wherein the at least one fourth impurity region does not overlap any transistor in the plurality of pixels in a plan view.

[0287] Technique 23 may improve image quality.

[0288] (Technology 24) The imaging device according to any one of Technologies 1 to 23, further comprising: a second semiconductor substrate stacked on the first semiconductor substrate; and a connection portion electrically connecting the first impurity region and the second semiconductor substrate, wherein the connection portion includes at least one plug, and the imaging device has at least one configuration selected from the group consisting of: (a) a configuration in which the first semiconductor substrate includes a first silicide region, and the at least one plug includes a first plug in contact with the first silicide region; and (b) a configuration in which the second semiconductor substrate includes a second silicide region, and the at least one plug includes a second plug in contact with the second silicide region.

[0289] Technique 24 may improve image quality.

[0290] (Technology 25) The imaging device described in any one of Technologies 1 to 24, wherein the plurality of pixels include two or more pixels, the second impurity region includes a portion that extends continuously across the two or more pixels, and the imaging device further includes a conductive path that passes through the continuously extending portion and at least one fourth impurity region in this order to reach the first impurity region.

[0291] The configuration of Technique 25 is an example configuration.

[0292] The imaging device according to the present disclosure can be used in, for example, digital cameras, digital video cameras, camera-equipped mobile phones, medical cameras such as electronic endoscopes, vehicle-mounted cameras, and cameras for robots.

[0293] 10, 10a, 10b, 10c, 10d Pixel 12 Photoelectric conversion unit 12a Pixel electrode 12b Photoelectric conversion layer 12c Counter electrode 14 Signal detection circuit 16 Feedback circuit 22 Amplification transistor 24 Selection transistor 26 Reset transistor 27a, 27b Transistors 22e, 24e, 26e, 27ae, 27be Gate electrode 31 Counter electrode power supply wiring 32 Power supply wiring 34 Address signal line 35 Vertical signal line 36 Reset signal line 38 Voltage line 40 Peripheral circuit 41 Analog circuit 42 Control circuit 43 Logic circuit 44 Horizontal signal readout circuit 45 Load circuit 46 Vertical scanning circuit 47 Column signal processing circuit 48 Voltage supply circuit 49 Horizontal common signal line 50 Inverting amplifier 53 Feedback line 55 Silicide region 56 Semiconductor injection region 57 Insulating region 60 Semiconductor substrate 60s1 First surface 60s2 Second surface 61p Support substrate 63p Semiconductor region 64, 64a, 64m Well contact 64A First crosspiece 64B Second crosspiece 64L Lattice shape 64x1, 64x2, 64x3, 64x4 Part 65p Well region 65p1 First region 65p2 Second region 67n, 67n1, 67n2, 67n3, 67n4 Charge storage portion 68an, 68bn, 68bn1, 68bn2, 68bn3, 68bn4, 68cn, 68cn1, 68cn2, 68cn3, 68cn4, 68dn, 68dn1, 68dn2, 68dn3, 68dn4, 71an, 71bn, 72an, 72bn, 73an, 73bn, 74an, 74bn, 91n impurity region 69 element isolation region 70, 90a, 90b, 90c, 90d insulating layer 80 wiring structure 80a, 80b, 80c, 80d wiring layer 90 interlayer insulating layer 94 surface side contact 94a plug portion 94b pad portion 95, 95a, 95b, 95c, 95d quad pixel 96a, 96b, 96c, 96d: Corner portions 97a, 97b, 97c, 97c: Crosspiece portions 98: Frame shape 99: Charge storage node100 Imaging device 110 Well region 111 Semiconductor region 120 Color filter 130 Microlens 160 Semiconductor substrate 170, 270, 370 Connection portion 200 Contact wiring 221 Top layer 222 Middle layer 223 Bottom layer 260 Semiconductor substrate 701 Lens optical system 702 Imaging device 703 System controller 704 Signal processing circuit 705 Camera system D1 First direction D2 Second direction R1 Imaging region R2 Peripheral region R3 Guard ring region cp1, cp2, cp3, cp4, cp5, cp6, cp7 Contact plugs pa1, pa2, pb, pc, pd, px, py, pz1, pz2 Plugs

Claims

1. An imaging device comprising: a first semiconductor substrate having a first surface and a second surface opposite to the first surface; and a plurality of pixels, wherein the first semiconductor substrate includes: a first impurity region of a first conductivity type at least a portion of which is located on the first surface; a second impurity region of the first conductivity type located closer to the second surface than the first impurity region; a third impurity region of the first conductivity type located between the first impurity region and the second impurity region; and at least one fourth impurity region of the first conductivity type penetrating the third impurity region and electrically connecting the first impurity region and the second impurity region, wherein each of the plurality of pixels includes a photoelectric conversion unit that converts light into electric charges; and a fifth impurity region of a second conductivity type that is located in the first impurity region and accumulates the electric charges, and an impurity concentration of the second impurity region is greater than an impurity concentration of the first impurity region.

2. The imaging device according to claim 1, wherein the impurity concentration of the at least one fourth impurity region is greater than the impurity concentration of the third impurity region.

3. The imaging device according to claim 1, wherein an impurity concentration of the at least one fourth impurity region is greater than the impurity concentration of the first impurity region.

4. The imaging device according to claim 1, wherein the impurity concentration of the first impurity region is greater than the impurity concentration of the third impurity region.

5. The imaging device according to claim 1, wherein in each of the plurality of pixels, an area of ​​the third impurity region in a planar view is larger than an area of ​​the fourth impurity region in the planar view.

6. The imaging device according to claim 1, wherein in each of the plurality of pixels, an area of ​​a region in which the first impurity region is arranged is 80% or more of an area of ​​each of the plurality of pixels in a plan view.

7. The imaging device according to claim 1, wherein the first impurity region is separated from the second impurity region by the third impurity region.

8. The imaging device according to claim 1, wherein the at least one fourth impurity region includes a plurality of fourth impurity regions, and each of the plurality of pixels includes at least one corresponding fourth impurity region among the plurality of fourth impurity regions.

9. The imaging device according to claim 1, wherein the plurality of pixels include at least two pixels adjacent to each other, and the at least one fourth impurity region is disposed continuously across the at least two pixels.

10. The imaging device of claim 1, wherein the plurality of pixels are arranged in a first direction and a second direction, the plurality of pixels include at least three pixels arranged in the first direction, and the at least one fourth impurity region is disposed continuously across the at least three pixels.

11. The imaging device described in claim 1, wherein the first semiconductor substrate further includes an imaging region in which the plurality of pixels are arranged and a guard ring region located outside the imaging region, the at least one fourth impurity region includes a plurality of fourth impurity regions, one of the plurality of fourth impurity regions is located in the imaging region, and one of the plurality of fourth impurity regions is located in the guard ring region.

12. The imaging device of claim 1, wherein each of the plurality of pixels further includes a first transistor including the fifth impurity region as one of a source and a drain, and a second transistor outputting a signal according to the potential of the fifth impurity region, and in a planar view, the at least one fourth impurity region does not overlap either the first transistor or the second transistor.

13. The imaging device of claim 1, wherein the plurality of pixels include a first pixel, the first pixel includes a second transistor that outputs a signal according to the potential of the fifth impurity region and includes a sixth impurity region as a source or drain, and in a planar view, a distance between the at least one fourth impurity region and the sixth impurity region of the first pixel is smaller than a distance between the at least one fourth impurity region and the fifth impurity region of the first pixel.

14. The imaging device according to claim 1, wherein the at least one fourth impurity region does not overlap the fifth impurity region in a plan view.

15. The imaging device according to claim 1, further comprising: a second semiconductor substrate stacked on the first semiconductor substrate; and a connection portion electrically connecting the first impurity region and the second semiconductor substrate.

16. The imaging device according to claim 1, wherein the first semiconductor substrate further includes a seventh impurity region of the second conductivity type located within the third impurity region.

17. An imaging device comprising: a first semiconductor substrate having a first surface and a second surface opposite to the first surface; and a plurality of pixels, wherein the first semiconductor substrate includes: a first impurity region of a first conductivity type, at least a portion of which is located on the first surface; a second impurity region of the first conductivity type located closer to the second surface than the first impurity region; and at least one fourth impurity region of the first conductivity type electrically connecting the first impurity region and the second impurity region, wherein each of the plurality of pixels includes: a photoelectric conversion unit that converts light into charges; and a fifth impurity region of a second conductivity type that is located in the first impurity region and accumulates the charges, and an impurity concentration of the second impurity region is greater than an impurity concentration of the first impurity region.

18. The imaging device according to claim 17, wherein the at least one fourth impurity region includes a region in which the impurity concentration of the at least one fourth impurity region monotonically increases from the first surface to the second surface of the first semiconductor substrate.

19. The imaging device according to claim 17, wherein the at least one fourth impurity region includes a region in which the impurity concentration of the at least one fourth impurity region is lower than the impurity concentration of the first impurity region.

Images