Circuit board and manufacturing method therefor, and electronic device

Abstract

The present application discloses a circuit board and a manufacturing method therefor, and an electronic device. The disclosed circuit board comprises a circuit board body (100) and via hole structures (200); hole sections (101) and back drilling holes (102) communicated with each other are formed in the circuit board body (100); hole openings of the hole sections (101) are located on a first surface of the circuit board body (100); hole openings of the back drilling holes (102) are located on a second surface of the circuit board body (100); the first surface and the second surface are opposite to each other; a metal layer is provided on the inner walls of the hole sections (101) to form the via hole structures (200); the via hole structures (200) are each filled with a first filler (300); and the back drilling holes (102) are each filled with a second filler (400), wherein the dielectric constant of the second filler (400) is less than the dielectric constant of the circuit board body (100).

Description

Circuit board, manufacturing method thereof, and electronic device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on August 9, 2023, with application number 202311003272.2 and invention name “Circuit board, preparation method thereof and electronic device”. The entire contents of the Chinese patent application are incorporated herein by reference. Technical Field

[0003] The present application relates to the field of circuit board design, and in particular to a circuit board and a manufacturing method thereof, and an electronic device. Background Art

[0004] With the rapid development of the electronic communications industry, the complexity and integration of communications equipment have greatly increased, and signal rates have also gradually increased. 112Gbps products have now become commercially available, and the development of 224Gbps products is also urgent. Vias, a PCB structure that is inevitably used in high-speed, high-density designs, have a direct impact on the performance of these high-speed, high-density products. One of the key indicators of via performance is impedance continuity. The impedance of a via (via impedance) is generally much smaller than the characteristic impedance of the connected PCB transmission line, resulting in poor impedance continuity across the entire link, which can easily lead to signal integrity issues.

[0005] In the prior art, improving via impedance typically involves lowering the dielectric constant of the PCB body or reducing the stud length through backdrilling. However, using materials with lower dielectric constants to fabricate the PCB body results in higher costs due to the higher material grade. Reducing the stud length also hinders effective performance due to limitations in machining the stud. Therefore, effectively improving via impedance is a pressing technical challenge.

[0006] Summary of the Invention

[0007] In the first aspect, the present application discloses a circuit board, comprising a circuit board main body and a via structure, wherein the circuit board main body is provided with a connected hole section and a back-drilled hole, the opening of the hole section is located on the first surface of the circuit board main body, and the opening of the back-drilled hole is located on the second surface of the circuit board main body, the first surface and the second surface are opposite to each other, the inner wall of the hole section is provided with a metal layer to form the via structure, the via structure is filled with a first filler, and the back-drilled hole is filled with a second filler, wherein the dielectric constant of the second filler is smaller than the dielectric constant of the circuit board main body.

[0008] In a second aspect, the present application further discloses an electronic device, comprising the circuit board described in the first aspect.

[0009] In a third aspect, the present application also discloses a method for preparing a circuit board, wherein the circuit board includes a circuit board body, and the preparation method includes: opening a first through hole on the circuit board body; setting a metal layer on the inner wall of the first through hole to form a metallized via; filling a first filler into the metallized via; and back-drilling the metallized via on the second surface of the circuit board body to form a back-drilled hole, wherein the metallized via after back-drilling forms a via structure.

[0010] In a fourth aspect, the present application also discloses a method for preparing a circuit board, wherein the circuit board includes a circuit board body, and the preparation method includes: opening a first through hole on the circuit board body; setting a metal layer on the inner wall of the first through hole to form a metallized via; back-drilling the metallized via on the second surface of the circuit board body to form a back-drilled hole, wherein the metallized via after back-drilling forms a via structure; filling a first filler into the via structure, and filling a second filler into the back-drilled hole, wherein the dielectric constant of the first filler is equal to the dielectric constant of the second filler, and is smaller than the dielectric constant of the circuit board body. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] FIG1 is a schematic structural diagram of a first circuit board disclosed in an embodiment of the present application;

[0012] FIG2 is a schematic structural diagram of a second circuit board disclosed in an embodiment of the present application;

[0013] FIG3 is a comparison diagram of the impedance of a via hole in a circuit board disclosed in an embodiment of the present application and the impedance of a via hole in a circuit board in the related art; wherein the abscissa represents time, and the ordinate represents the impedance value detected by TDR (time domain reflectometry);

[0014] FIG4 is a comparison diagram of the insertion loss and return loss at the via structure location of the circuit board disclosed in the embodiment of the present application and the via structure location of the circuit board in the related art; wherein the abscissa represents the frequency, and the ordinate represents the logarithmic amplitude-frequency characteristic;

[0015] FIG5 is a comparison diagram of insertion loss at the via structure location of the circuit board disclosed in the embodiment of the present application and at the via structure location of the circuit board in the related art; wherein the abscissa represents frequency, and the ordinate represents logarithmic amplitude-frequency characteristics;

[0016] FIG6 is a flow chart of a method for preparing a circuit board disclosed in an embodiment of the present application.

[0017] Explanation of reference numerals: 100 - circuit board body, 101 - hole segment, 102 - back drilled hole, 200 - via structure, 300 - first filler, 400 - second filler, 500 - circuit layer, 600 - shielding layer, 700 - pad. DETAILED DESCRIPTION

[0018] To make the objectives, technical solutions, and advantages of this application more clear, the technical solutions of this application will be clearly and completely described below in conjunction with the specific embodiments of this application and the corresponding drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0019] The technical solutions disclosed in various embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0020] In common systems, such as signal interconnection of high-speed connectors, BGA (Ball Grid Array) and other components, and differential / single-ended layer switching on PCB (Printed Circuit Board), via structures play a vital role. As the signal rate increases, the system SI (Signal Integrity) performance becomes more sensitive to impedance continuity, and the impact of via impedance continuity on the channel is particularly significant. Via impedance is affected by many factors. Since this patent is mainly aimed at signal transmission systems with speeds of 112Gbps and above, in signal transmission systems with speeds of 112Gbps and above, the via impedance may be high or low. This application is mainly designed for situations where the via impedance is low.

[0021] 1 to 6 , an embodiment of the present application discloses a circuit board, which may be a multi-layer structure and includes a circuit board body 100 and a via structure 200 .

[0022] The circuit board body 100 is provided with a connected hole section 101 and a back-drilled hole 102. The opening of the hole section 101 is located on the first surface of the circuit board body 100, and the opening of the back-drilled hole 102 is located on the second surface of the circuit board body 100. The first surface and the second surface are opposite to each other.

[0023] The inner wall of the hole section 101 is provided with a metal layer to form a via structure 200. The via structure 200 can be used for signal interconnection of components such as high-speed connectors and BGAs, as well as differential / single-ended layer switching on the circuit board body 100.

[0024] The via structure 200 is filled with a first filler 300 , and the back-drilled hole 102 is filled with a second filler 400 , wherein the dielectric constant of the second filler 400 is smaller than the dielectric constant of the circuit board body 100 .

[0025] It should be noted that in the related art, in order to improve the via impedance, the related art improves the via impedance by reducing the dielectric constant of the circuit board body, that is, adjusting the materials, settings, etc. of the various components arranged horizontally (x and y directions in Figures 1 and 2) as shown in Figures 1 and 2 to improve the via impedance. Therefore, the related art improves the via impedance by adjusting the materials, settings, etc. of the various components arranged horizontally on the circuit board.

[0026] The circuit board disclosed in the embodiment of the present application changes the via impedance by adjusting the materials, arrangement, etc. of the components of the circuit board along the through-hole direction of the via structure 200 (i.e., the z-direction in Figures 1 and 2). It should be noted that the via impedance mentioned in the embodiment of the present application refers to the impedance of the circuit board at the position of the via structure 200. When the circuit board disclosed in the embodiment of the present application opens the connected hole segment 101 and the back-drilled hole 102, a first through hole is first opened on the circuit board, and a metal layer is provided on the inner wall of the first through hole to form a metallized via hole. The metallized via hole is back-drilled on the second surface of the circuit board body 100 to form the back-drilled hole 102, wherein the metallized via hole after the back-drilling process forms the via structure 200, and the remaining portion of the first through hole after the back-drilling process forms the hole segment 101.

[0027] The circuit board disclosed in the embodiment of the present application is provided with a connected hole section 101 and a back-drilled hole 102, and a metal layer is provided on the inner wall of the hole section 101 to form a via structure 200. The back-drilled hole 102 is formed by a back-drilling process, so that the back-drilled hole 102 can reduce the via residual column, thereby improving the via impedance to a certain extent. Furthermore, by filling the via structure 200 with a first filler 300 and the back-drilled hole 102 with a second filler 400, and the dielectric constant of the second filler 400 is smaller than the dielectric constant of the circuit board body 100, the problem of low via impedance caused by the dielectric constant of the second filler 400 being larger than the dielectric constant of the circuit board body 100 can be avoided, thereby further improving the via impedance relative to the circuit layer connected thereto, improving high-frequency return loss and insertion loss, and improving signal integrity and transmission structure bandwidth.

[0028] To further improve the via impedance, the dielectric constant of the first filler 300 can optionally be equal to the dielectric constant of the second filler 400. Since the dielectric constant of the second filler 400 is smaller than that of the circuit board body 100, the dielectric constant of the first filler 300 is also smaller than that of the circuit board body 100.

[0029] In another embodiment, the dielectric constant of the first filler 300 may be greater than the dielectric constant of the second filler 400 and smaller than the dielectric constant of the circuit board body 100 .

[0030] The circuit board disclosed in the embodiments of the present application utilizes a first filler 300 having a lower dielectric constant than the circuit board body 100, thereby further improving via impedance to a certain extent, thereby further improving high-frequency return loss and insertion loss, and enhancing signal integrity and transmission structure bandwidth. When the dielectric constant of the first filler 300 is equal to the dielectric constant of the second filler 400, the first filler 300 and the second filler 400 can be made of the same material, thereby facilitating simultaneous filling of the first filler 300 and the second filler 400, thereby improving filling efficiency.

[0031] In a simpler and more effective embodiment, the second filler 400 may be air. Since the dielectric constant of air is approximately the same as that of a vacuum, air has a lower dielectric constant, thereby effectively increasing the via impedance.

[0032] In other embodiments, the first filler 300 and the second filler 400 can be materials such as resin and green oil. Of course, the first filler 300 and the second filler 400 can also be other materials, as long as the dielectric constant of the material of the second filler 400 is smaller than the dielectric constant of the material of the circuit board body 100. The embodiments of the present application do not limit the specific materials of the first filler 300 and the second filler 400.

[0033] In a specific embodiment, the circuit board may include a solder ball array packaging area, and the via structure 200 may be located in the solder ball array packaging area. The via structure 200 is used to electrically connect to the solder ball array packaging structure.

[0034] It should be noted that when the circuit board includes a solder ball array packaging structure, the solder ball array packaging structure can be arranged in the solder ball array packaging area, and the solder ball array packaging structure is electrically connected to the via structure 200, so that the solder ball array packaging structure can be interconnected with other solder ball array packaging structures or high-speed connectors or other component signals through the via structure 200.

[0035] Optionally, the circuit board may include a connector mounting area, and the via structure 200 may be located in the connector mounting area. The via structure 200 is used to electrically connect to the connector.

[0036] It should be noted that when the circuit board includes a connector, the connector can be arranged in the connector mounting area, and the connector is electrically connected to the via structure 200, so that the connector can be interconnected with other connectors or solder ball array packaging structures or other component signals through the via structure 200.

[0037] In one embodiment, the via structure 200 may be one. For example, one via structure 200 may be used for single-end layer switching of a circuit board to achieve signal interconnection between multiple circuit layers 500 in the circuit board.

[0038] In another embodiment, the circuit board may include at least two via structures 200, wherein two via structures 200 of the at least two via structures 200 may form a differential pair. For example, a differential pair may be used for differential signal layer switching.

[0039] Specifically, the circuit board may further include a circuit layer 500, which is disposed within the circuit board body 100. The circuit layer 500 is electrically connected to the sidewalls of the via structure 200. The sidewalls of the via structure 200 refer to the metal layer that forms the via structure 200. The circuit board disclosed in the embodiment of the present application, by providing the circuit layer 500 electrically connected to the sidewalls of the via structure 200, enables the circuit layer 500 to interconnect signals with other circuit layers or other components through the via structure 200.

[0040] Specifically, there may be multiple circuit layers 500, and the multiple circuit layers 500 may be spaced apart along the through-hole direction of the via structure 200. It should be noted that, when there are multiple via structures 200, some of the multiple circuit layers 500 may be electrically connected to one of the via structures 200, and other circuit layers 500 may be electrically connected to other via structures 200, thereby interconnecting signals between the multiple circuit layers 500 and between the circuit layers 500 and other components.

[0041] In some cases, different areas of the circuit board body 100 need to be metal isolated to control the influence of electric fields, magnetic fields, electromagnetic waves, etc. between different areas. Optionally, the circuit board may also include a shielding layer 600. The shielding layer 600 may be arranged in the circuit board body 100. The shielding layer 600 may be provided with an avoidance structure 601. The via structure 200 may be located in the avoidance structure 601 and spaced apart from the shielding layer 600.

[0042] The circuit board disclosed in the embodiment of the present application is provided with a shielding layer 600 so that the shielding layer 600 can metal isolate different areas of the circuit board body 100, thereby avoiding the influence of electric fields, magnetic fields, electromagnetic waves, etc. between different areas.

[0043] It should be noted that the design of the shielding layer 600 can be arranged according to the specific design of the circuit board, and the embodiment of the present application does not limit the specific setting position of the shielding layer 600.

[0044] The circuit board disclosed in the embodiment of the present application may further include a pad 700 , which can be used to form a pad pattern of the circuit board, that is, a combination of pads designed for various special component types. The pad 700 can be provided on the first surface and connected to the via structure 200 .

[0045] Optionally, the via structure 200 in the circuit board disclosed in the embodiment of the present application may be a differential pair structure for a BGA or connector area with a 1.0 mm pitch or a 0.8 mm pitch.

[0046] As shown in Figure 3, Figure 3 shows a comparison diagram of the via impedance of the circuit board disclosed in the embodiment of the present application and the via impedance of the circuit board in the related art. It can be seen from Figure 3 that the via impedance of the circuit board in the embodiment of the present application is improved by about 3.5Ω than the via impedance of the circuit board in the related art, which significantly improves the continuity of the via impedance of the circuit board.

[0047] 3 a represents the via impedance in the circuit board disclosed in the embodiment of the present application, and FIG. 3 b represents the via impedance in the circuit board in the related art.

[0048] As shown in Figure 4, Figure 4 illustrates a comparison of the insertion loss and return loss of the circuit board disclosed in the embodiment of the present application at the position of the via structure 200 and the circuit board in the related art at the position of the via structure. It can be seen from Figure 4 that the return loss of the circuit board in the embodiment of the present application at the position of the via structure 200 is reduced by about 5 to 10 dB compared with the return loss of the circuit board in the related art at the position of the via structure. From the enlarged diagram of the comparison of the insertion loss of the circuit board disclosed in the embodiment of the present application at the position of the via structure 200 and the circuit board in the related art at the position of the via structure in Figure 5, it can be seen that the insertion loss of the circuit board in the embodiment of the present application at the position of the via structure 200 is improved by less than 5 dB compared with the insertion loss of the circuit board in the related art at the position of the via structure, which significantly improves the transmission bandwidth and signal integrity of the circuit board at the position of the via structure 200 and improves the system margin.

[0049] 4 c represents the return loss of the circuit board disclosed in the embodiment of the present application at the location of the via structure 200, and 4 d represents the return loss of the circuit board in the related art at the location of the via structure. 5 e represents the insertion loss of the circuit board disclosed in the embodiment of the present application at the location of the via structure 200, and 5 f represents the insertion loss of the circuit board in the related art at the location of the via structure.

[0050] Therefore, the circuit board disclosed in the embodiment of the present application has better signal integrity characteristics at the location of the via structure 200. Compared with the circuit boards in the related art, the circuit board disclosed in the embodiment of the present application can effectively increase the via impedance, improve the signal integrity of the circuit board at the location of the via structure 200, and increase the system margin.

[0051] The present application also discloses an electronic device, which includes the circuit board disclosed in the above embodiment.

[0052] The electronic device disclosed in the embodiment of the present application is configured to include the circuit board disclosed in the above embodiment, which can increase the via impedance of the circuit board, improve high-frequency return loss and insertion loss, and enhance signal integrity and transmission structure bandwidth.

[0053] In the embodiments of the present application, the electronic device may be a mobile phone, a tablet, a game console, a computer, etc. The embodiments of the present application do not limit the specific type of the electronic device.

[0054] The present application also discloses a method for manufacturing a circuit board. The disclosed circuit board includes a circuit board body 100. The disclosed method for manufacturing the circuit board includes:

[0055] S101 , a first through hole is opened on the circuit board body 100 .

[0056] S102 , disposing a metal layer on the inner wall of the first through hole to form a metallized through hole.

[0057] Specifically, the metal layer can be set on the inner wall of the first through hole by electroplating. Of course, the metal layer can also be set on the inner wall of the first through hole by other methods. This application does not impose any specific restrictions on the setting of the metal layer.

[0058] S103 , filling the metallized via hole with a first filler 300 .

[0059] S104 , back-drilling the metallized via hole on the second surface of the circuit board body 100 to form a back-drilled hole 102 .

[0060] The metallized conductive hole after back drilling forms a via structure 200 .

[0061] The circuit board prepared by the circuit board preparation method disclosed in the embodiment of the present application can improve the via resistance of the circuit board, improve high-frequency return loss and insertion loss, and enhance signal integrity and transmission structure bandwidth.

[0062] Furthermore, after backdrilling the metallized vias on the second surface of the circuit board body 100, the disclosed preparation method further includes:

[0063] In step A1 , a second filler 400 is filled into the back-drilled hole 102 , wherein the dielectric constant of the second filler 400 is smaller than the dielectric constant of the circuit board body 100 .

[0064] The present application also discloses a method for manufacturing a circuit board. The disclosed circuit board includes a circuit board body 100. The disclosed method for manufacturing the circuit board includes:

[0065] Step B1: opening a first through hole in the circuit board body 100 .

[0066] Step B2: Disposing a metal layer on the inner wall of the first through hole to form a metallized through hole.

[0067] In step B3 , backdrilling is performed on the second surface of the circuit board body 100 to form a backdrilled hole 102 . The backdrilled metallized via hole forms a via structure 200 .

[0068] In step B4 , the via structure 200 is filled with the first filler 300 , and the back-drilled hole 102 is filled with the second filler 400 .

[0069] The dielectric constant of the first filler 300 is equal to the dielectric constant of the second filler 400 and is smaller than the dielectric constant of the circuit board body 100 .

[0070] The circuit board prepared by the circuit board preparation method disclosed in the embodiment of the present application can improve the via impedance of the circuit board, improve high-frequency return loss and insertion loss, and enhance signal integrity and transmission structure bandwidth.

[0071] The above embodiments of this application focus on the differences between the various embodiments. As long as the different optimization features between the various embodiments are not contradictory, they can be combined to form a better embodiment. Considering the simplicity of the text, they will not be repeated here.

[0072] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are within the protection of this application.

Claims

1. A circuit board, comprising a circuit board body (100) and a via structure (200), wherein the circuit board body (100) is provided with a connected hole section (101) and a back-drilled hole (102), the hole opening of the hole section (101) is located on the first surface of the circuit board body (100), and the hole opening of the back-drilled hole (102) is located on the second surface of the circuit board body (100), the first surface and the second surface are opposite to each other, the inner wall of the hole section (101) is provided with a metal layer to form the via structure (200), the via structure (200) is filled with a first filler (300), and the back-drilled hole (102) is filled with a second filler (400), wherein: The dielectric constant of the second filler (400) is smaller than the dielectric constant of the circuit board body (100).

2. The circuit board according to claim 1, wherein: The dielectric constant of the first filler (300) is equal to the dielectric constant of the second filler (400).

3. The circuit board according to claim 1, wherein: The dielectric constant of the first filler (300) is greater than the dielectric constant of the second filler (400), and is less than the dielectric constant of the circuit board body (100).

4. The circuit board according to claim 1, wherein: The second filler (400) is air.

5. The circuit board according to claim 1, wherein: The circuit board comprises a solder ball array packaging area, and the via structure (200) is located in the solder ball array packaging area and is used for being electrically connected to the solder ball array packaging structure.

6. The circuit board according to claim 1, wherein: The circuit board comprises a connector mounting area, and the via structure (200) is located in the connector mounting area and is used for being electrically connected to the connector.

7. The circuit board according to claim 1, wherein: The circuit board comprises at least two via structures (200), wherein two via structures (200) of the at least two via structures (200) form a differential pair.

8. The circuit board according to claim 1, wherein: The circuit board further comprises a circuit layer (500), wherein the circuit layer (500) is arranged in the circuit board body (100), and the circuit layer (500) is electrically connected to the side wall of the via structure (200).

9. The circuit board according to claim 1, wherein: The circuit board further comprises a shielding layer (600), the shielding layer (600) being arranged in the circuit board body (100), the shielding layer (600) being provided with an avoidance structure (601), the via structure (200) being located in the avoidance structure (601) and being spaced apart from the shielding layer (600).

10. An electronic device comprising the circuit board according to any one of claims 1 to 9.

11. A method for preparing a circuit board, the circuit board comprising a circuit board body (100), the method comprising: A first through hole is provided on the circuit board body (100); Disposing a metal layer on the inner wall of the first through hole to form a metallized through hole; Filling a first filler (300) into the metallized via hole; The metallized via hole is back-drilled on the second surface of the circuit board body (100) to form a back-drilled hole (102), wherein the metallized via hole after the back-drilling process forms a via structure (200).

12. The preparation method according to claim 10, wherein: After back-drilling the metallized via hole on the second surface of the circuit board body (100), the preparation method further comprises: A second filler (400) is filled into the back-drilled hole (102), wherein the dielectric constant of the second filler (400) is smaller than the dielectric constant of the circuit board body (100).

13. A method for preparing a circuit board, the circuit board comprising a circuit board body (100), the method comprising: A first through hole is provided on the circuit board body (100); Disposing a metal layer on the inner wall of the first through hole to form a metallized through hole; Back-drilling the metallized via hole on the second surface of the circuit board body (100) to form a back-drilled hole (102), wherein the metallized via hole after the back-drilling process forms a via structure (200); A first filler (300) is filled into the via structure (200), and a second filler (400) is filled into the back-drilled hole (102), wherein the dielectric constant of the first filler (300) is equal to the dielectric constant of the second filler (400) and is smaller than the dielectric constant of the circuit board body (100).

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