Semiconductor device

Abstract

Provided is a novel semiconductor device. The present invention comprises a first transistor, a second transistor, and a third transistor, either the source or the drain of the first transistor being electrically connected to the gate of the second transistor, either the source or the drain of the second transistor being electrically connected to the gate of the third transistor, the gate of the first transistor being electrically connected to a first wiring to which a constant potential is applied, and the other of the source and the drain of the first transistor being electrically connected to a second wiring.

Description

Semiconductor Devices

[0001] One embodiment of the present invention relates to a semiconductor device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, a driving method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. More specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, optical devices, imaging devices, lighting devices, arithmetic units, control devices, memory devices, input devices, output devices, input / output devices, signal processing devices, arithmetic processing devices, electronic computers, electronic devices, and driving methods thereof or manufacturing methods thereof.

[0003] It is known that a transistor including an oxide semiconductor in a channel formation region has an extremely small off-state current. For example, Patent Document 1 discloses a low-power processing unit (e.g., a CPU) that utilizes the low off-state current of the transistor. Furthermore, Patent Document 2 discloses a storage device (e.g., a main memory, a cache memory, etc.) that can store data for a long period of time by utilizing the low off-state current of the transistor.

[0004] Furthermore, for example, Patent Document 3 discloses a technique for increasing the density of an integrated circuit by stacking the transistors.

[0005] JP 2012-257187 A JP 2011-151383 A International Publication No. 2021 / 053473

[0006] An object of one embodiment of the present invention is to provide a semiconductor device capable of increasing operation speed or a storage device including the semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device capable of reducing power consumption or a storage device including the semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device capable of increasing recording density or a storage device including the semiconductor device. Another object of one embodiment of the present invention is to provide a miniaturized semiconductor device or a storage device including the semiconductor device. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device or a storage device including the semiconductor device. Another object of one embodiment of the present invention is to provide a novel semiconductor device or a storage device including the semiconductor device.

[0007] Note that the above-mentioned problem does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of the above-mentioned problems. Note that problems other than the above-mentioned problem will become apparent from the description of this specification, drawings, claims, etc., and it is possible to extract problems other than the above-mentioned problem from the description of this specification, drawings, claims, etc.

[0008] (1) One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, and a third transistor, in which one of a source or a drain of the first transistor is electrically connected to a gate of the second transistor, one of a source or a drain of the second transistor is electrically connected to a gate of the third transistor, the gate of the first transistor is electrically connected to a first wiring to which a constant potential is applied, the other of the source or the drain of the first transistor is electrically connected to a second wiring, the other of the source or the drain of the second transistor is electrically connected to a third wiring, the one of the source or the drain of the third transistor is electrically connected to a fourth wiring, and the other of the source or the drain of the third transistor is electrically connected to a fifth wiring.

[0009] (2) Another embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, and a third transistor, in which the first transistor is located in an upper layer of the second transistor and the second transistor is located in an upper layer of the third transistor, the first transistor, the second transistor, and the third transistor have overlapping regions, one of a source or a drain of the first transistor is electrically connected to a gate of the second transistor, one of the source or the drain of the second transistor is electrically connected to a gate of the third transistor, the gate of the first transistor is electrically connected to a first wiring, the other of the source or the drain of the first transistor is electrically connected to a second wiring, the other of the source or the drain of the second transistor is electrically connected to a third wiring, the one of the source or the drain of the third transistor is electrically connected to a fourth wiring, and the other of the source or the drain of the third transistor is electrically connected to a fifth wiring.

[0010] (3) Another aspect of the present invention is a semiconductor device including a first transistor, a second transistor, a third transistor, a first conductor, a second conductor, a third conductor, a fourth conductor, a fifth conductor, a sixth conductor, and a seventh conductor, wherein the first conductor and the second conductor are located above the third conductor, the third conductor and the fourth conductor are located above the fifth conductor, and the fifth conductor and the sixth conductor are located above the seventh conductor, wherein the first conductor has a region above the second conductor that functions as a first wiring and a region below the second conductor that functions as a gate electrode of the first transistor, wherein the third conductor has a region above the fourth conductor that functions as one of a source electrode or a drain electrode of the first transistor and a region below the fourth conductor that functions as a gate electrode of the second transistor, and wherein the fifth conductor has a region above the sixth conductor that functions as one of a source electrode or a drain electrode of the second transistor and a region below the second conductor that functions as a gate electrode of the second transistor. the second conductor has a region that functions as the other of the source electrode or drain electrode of the first transistor and a region that functions as a second wiring; the fourth conductor has a region that functions as the other of the source electrode or drain electrode of the second transistor and a region that functions as a third wiring; the seventh conductor has a region that functions as one of the source electrode or drain electrode of the third transistor and a region that functions as the fourth wiring; the sixth conductor has a region that functions as the other of the source electrode or drain electrode of the third transistor and a region that functions as a fifth wiring; the first conductor, the second conductor, the third conductor, the fourth conductor, the fifth conductor, the sixth conductor, and the seventh conductor have regions that overlap with each other in a top view; and the channel length directions of the first transistor, the second transistor, and the third transistor are in a depth direction in a top view.

[0011] (4) In any one of (1) to (3), a channel formation region of the second transistor may include an oxide semiconductor.

[0012] (5) In the above (4), a channel formation region of the third transistor may include an oxide semiconductor, and the crystallinity of the oxide semiconductor in the channel formation region of the third transistor may be higher than the crystallinity of the oxide semiconductor in the channel formation region of the second transistor.

[0013] (6) In any one of (1) to (3) above, the channel length of each of the first transistor and the third transistor may be shorter than the channel length of the second transistor.

[0014] (7) In any one of (1) to (3), the first transistor, the second transistor, and the third transistor may each have a back gate, and a potential applied to the back gate of each of the first transistor and the third transistor may be higher than a potential applied to the back gate of the second transistor.

[0015] (8) In any one of (1) to (3) above, the direction in which the first wiring extends may be perpendicular to the direction in which the second wiring and the fourth wiring extend, and may be parallel to the direction in which the third wiring and the fifth wiring extend.

[0016] One embodiment of the present invention can provide a semiconductor device capable of increasing the operating speed or a storage device including the semiconductor device. Another embodiment of the present invention can provide a semiconductor device capable of reducing power consumption or a storage device including the semiconductor device. Another embodiment of the present invention can provide a semiconductor device capable of increasing the recording density or a storage device including the semiconductor device. Another embodiment of the present invention can provide a miniaturized semiconductor device or a storage device including the semiconductor device. Another embodiment of the present invention can provide a highly reliable semiconductor device or a storage device including the semiconductor device. Another embodiment of the present invention can provide a novel semiconductor device or a storage device including the semiconductor device.

[0017] Note that the above effects do not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of the above effects. Note that effects other than the above effects will become apparent from the description in this specification, drawings, claims, etc., and it is possible to extract effects other than the above effects from the description in this specification, drawings, claims, etc.

[0018] FIG. 1A is a circuit diagram showing a configuration example of a semiconductor device. FIG. 1B is a schematic diagram showing a configuration example of a semiconductor device. FIG. 2 is a timing chart showing an operation example of the semiconductor device. FIGS. 3A to 3F are circuit diagrams showing an operation example of the semiconductor device. FIG. 4A is a top view showing a configuration example of a semiconductor device. FIGS. 4B and 4C are cross-sectional views showing a configuration example of a semiconductor device. FIGS. 5A and 5B are cross-sectional views showing a configuration example of a semiconductor device. FIGS. 6A and 6B are cross-sectional views showing a configuration example of a semiconductor device. FIGS. 7A and 7B are cross-sectional views showing a configuration example of a semiconductor device. FIGS. 8A and 8B are top views showing a configuration example of a semiconductor device. FIG. 9 is a circuit diagram showing a configuration example of a semiconductor device. FIG. 10 is a cross-sectional view showing a configuration example of a semiconductor device. FIG. 11A is a top view showing a configuration example of a semiconductor device. FIGS. 11B and 11C are cross-sectional views showing a configuration example of a semiconductor device. FIG. 12 is a schematic diagram showing a configuration example of a memory device. FIG. 13 is a schematic diagram showing a configuration example of a memory device. FIG. 14A is a block diagram showing a configuration example of a memory device. FIG. 14B is a circuit diagram showing a configuration example of a memory device. FIG. 15 is a cross-sectional view showing an example of the configuration of a memory device. FIGS. 16A and 16B are cross-sectional views showing an example of the configuration of a memory device. FIG. 17 is a diagram showing various memory devices by layer. FIGS. 18A to 18H are diagrams explaining an example of the circuit configuration of a memory cell. FIGS. 19A and 19B are diagrams showing an example of an electronic component. FIGS. 20A and 20B are diagrams showing an example of an electronic device. FIGS. 20C to 20E are diagrams showing an example of a mainframe computer. FIG. 21A is a diagram showing an example of space equipment. FIG. 21B is a diagram showing an example of a storage system applicable to a data center. FIGS. 22A and 22B are diagrams showing circuit simulation results of a semiconductor device. FIGS. 23A and 23B are diagrams showing circuit simulation results of a semiconductor device.

[0019] In this specification, a semiconductor device refers to a device that utilizes semiconductor characteristics, such as a circuit including a semiconductor element (e.g., a transistor or a diode), or a device having such a circuit. It also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit including a semiconductor element, a chip equipped with an integrated circuit, an electronic component in which a chip is housed in a package, or an electronic device equipped with an electronic component are examples of semiconductor devices. Furthermore, for example, a display device, a light-emitting device, a power storage device, an optical device, an imaging device, a lighting device, an arithmetic device, a control device, a memory device, an input device, an output device, an input / output device, a signal processing device, an electronic computer, or an electronic device may be a semiconductor device and may also include a semiconductor device.

[0020] Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different ways. Therefore, it will be readily understood by those skilled in the art that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments.

[0021] In this specification and the like, the configuration shown in each embodiment can be appropriately combined with the configuration shown in another embodiment to form one aspect of the present invention. Furthermore, when multiple configurations are shown in one embodiment, these configurations can be appropriately combined to form one aspect of the present invention.

[0022] In addition, in the drawings illustrating the embodiments, the same reference numerals may be used in common between different drawings for the same parts or parts having similar functions in the configuration of the invention, thereby omitting repeated description thereof. Furthermore, when the drawings indicate similar functions, for example, the same hatching patterns may be used and no particular reference numerals may be used. Furthermore, in the drawings, for example, in perspective views or top views (also called "plan views"), the illustration of some components may be omitted for ease of understanding. Furthermore, in the drawings, for example, the illustration of some hidden lines may be omitted. Furthermore, in the drawings, for example, the illustration of hatching patterns may be omitted.

[0023] In addition, in the drawings, the size, layer thickness, or area may be exaggerated for clarity. Therefore, the drawings are not limited to, for example, their size or aspect ratio. Note that the drawings are schematic representations of ideal examples and are not limited to, for example, the shapes or values ​​shown in the drawings. For example, in an actual manufacturing process, layers or resist masks may be unintentionally thinned by processes such as etching, but these may not be reflected in the drawings to facilitate understanding. In addition, for example, in actual circuit operation, variations in voltage or current may occur due to noise or timing errors, but these may not be reflected in the drawings to facilitate understanding.

[0024] Furthermore, in this specification and drawings, components may be classified by function and shown as independent elements. However, it may be difficult to separate components by function, and one element may be involved in multiple functions, or one function may be involved across multiple elements. Therefore, the elements shown in this specification and drawings may not be limited to the descriptions therein, and may be rephrased appropriately depending on the situation.

[0025] Furthermore, in this specification and drawings, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, the reference numeral may be accompanied by an identifying symbol such as "A", "b", "_1", "[n]", or "[m, n]". Furthermore, when explaining matters common to multiple elements accompanied by identifying symbols, or when it is not necessary to distinguish between them, the elements may be described without the identifying symbol.

[0026] In this specification and the like, the "conductive state" or "on state" of a transistor refers to, for example, a state in which the source and drain of the transistor are considered to be electrically short-circuited, or a state in which current can flow between the source and drain. For example, a state in which the voltage between the gate and source of an n-channel transistor is higher than the threshold voltage, or a state in which the voltage between the gate and source of a p-channel transistor is lower than the threshold voltage, may be referred to as the "conductive state" or "on state." In addition, the "non-conductive state," "cut-off state," or "off state" of a transistor refers to a state in which the source and drain of the transistor are considered to be electrically cut off. For example, a state in which the voltage between the gate and source of an n-channel transistor is lower than the threshold voltage, or a state in which the voltage between the gate and source of a p-channel transistor is higher than the threshold voltage, may be referred to as the "non-conductive state," "cut-off state," or "off state."

[0027] In this specification and the like, the voltage between the gate and the source (gate-source) may be referred to as the "gate voltage," the voltage between the drain and the source (drain-source) may be referred to as the "drain voltage," and the voltage between the back gate and the source (back gate-source) may be referred to as the "back gate voltage." Also, the current flowing between the drain and the source may be referred to as the "drain current." Note that, for n-channel transistors, terms such as "high gate voltage," "high drain voltage," and "high back gate voltage" may be interchangeable with terms such as "low gate voltage," "low drain voltage," and "low back gate voltage" for p-channel transistors, as appropriate. Also, terms such as "low gate voltage," "low drain voltage," and "low back gate voltage" for n-channel transistors may be interchangeable with terms such as "high gate voltage," "high drain voltage," and "high back gate voltage" for p-channel transistors, as appropriate.

[0028] In this specification and the like, unless otherwise specified, the "off-state current" of a transistor refers to the drain current when the transistor is in an off state. Note that in this specification and the like, the off-state current and the current flowing between the gate and the source and drain (also referred to as gate leakage current) may also be referred to as leakage current.

[0029] Embodiment 1 A semiconductor device according to one embodiment of the present invention will be described with reference to the drawings. At least a part of the semiconductor device according to one embodiment of the present invention can be used for, for example, a memory cell included in the memory device.

[0030] <Structural Example 1 of Semiconductor Device> FIG. 1A is a circuit diagram illustrating a structural example of a semiconductor device of one embodiment of the present invention.

[0031] As shown in FIG. 1A, the semiconductor device 100 includes a transistor M11, a transistor M12, and a transistor M13.

[0032] One of the source or drain of the transistor M11 is electrically connected to the gate of the transistor M12. One of the source or drain of the transistor M12 is electrically connected to the gate of the transistor M13. The gate of the transistor M11 is electrically connected to a wiring BSL. The other of the source or drain of the transistor M11 is electrically connected to a wiring WWL. The other of the source or drain of the transistor M12 is electrically connected to a wiring WBL. One of the source or drain of the transistor M13 is electrically connected to a wiring RWL. The other of the source or drain of the transistor M13 is electrically connected to a wiring RBL. Here, one of the source or drain of the transistor M11 and the gate of the transistor M12 are electrically connected to each other by a wiring NL11. One of the source or drain of the transistor M12 and the gate of the transistor M13 are electrically connected to each other by a wiring NL12.

[0033] The semiconductor device 100 functions as a memory cell. That is, the semiconductor device 100 can store binary data by associating a high or low potential corresponding to the amount of charge stored in the wiring NL12 with "1" or "0." Note that, for example, ternary or more values ​​of data may also be stored. Furthermore, when writing data, the semiconductor device 100 controls the conduction state of the transistor M12 using a potential (e.g., the potential of a pulse signal) applied to the wiring WWL, thereby applying a potential corresponding to the data from the wiring WBL to the wiring NL12 and storing charge corresponding to the potential. Furthermore, when reading data, the semiconductor device 100 changes the potential (e.g., the potential of a pulse signal) applied to the wiring RWL and turns the transistor M13 on or off depending on the potential of the wiring NL12, thereby outputting a potential corresponding to the data to the wiring RBL.

[0034] Therefore, the transistor M12 functions as a write transistor, the transistor M13 functions as a read transistor, the wiring WWL functions as a write word line, the wiring WBL functions as a write bit line, the wiring RWL functions as a read word line, and the wiring RBL functions as a read bit line. That is, for example, a pulse signal that controls writing of data to the semiconductor device 100 is applied to the wiring WWL, and a potential corresponding to the data to be written to the semiconductor device 100 is applied to the wiring WBL. Also, for example, a pulse signal that controls reading of data from the semiconductor device 100 is applied to the wiring RWL, and a potential corresponding to the data held in the semiconductor device 100 is applied to the wiring RBL.

[0035] Here, the semiconductor device 100 includes a bootstrap circuit including the transistor M11 and the gate capacitance of the transistor M12 (here, including parasitic capacitance between the wiring NL11 and each of the wiring WBL and the wiring NL12). Therefore, a potential that allows the bootstrap circuit to operate correctly is applied to the wiring BSL. Note that, as will be described in detail later in the operation example, it is preferable to apply a constant potential to the wiring BSL.

[0036] In the semiconductor device 100, the transistors M11, M12, and M13 are either n-channel transistors or p-channel transistors. Here, the description will be given assuming that the transistors M11, M12, and M13 are all n-channel transistors. An n-channel transistor has a larger on-state current than a p-channel transistor. Therefore, the data read speed and data write speed of the semiconductor device 100 can be improved.

[0037] For example, each of the transistors M11, M12, and M13 can be a transistor including a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, or an amorphous semiconductor in a channel formation region. The semiconductor is not limited to a simple semiconductor whose main component is a single element (such as silicon or germanium), but can also be, for example, a compound semiconductor (such as silicon germanium or gallium arsenide), an oxide semiconductor, or the like.

[0038] Furthermore, various types of transistors can be used as the transistors M11, M12, and M13, such as MOS field-effect transistors, junction field-effect transistors, or bipolar transistors.

[0039] Furthermore, transistors with various structures can be used for each of the transistors M11, M12, and M13. For example, transistors with various structures can be used, such as top-gate transistors (e.g., planar transistors and staggered transistors), bottom-gate transistors (e.g., inverted planar transistors and inverted staggered transistors), dual-gate transistors (structures in which gates are arranged on both sides (e.g., above and below) of a channel formation region), fin transistors, and tri-gate transistors. Furthermore, for example, vertical transistors (transistors whose channel length direction is vertical (also referred to as the height direction or the direction perpendicular to the formation surface)) can be used.

[0040] Note that the semiconductors including the channel formation regions of the transistors M11, M12, and M13 may be made of the same material or different materials, and may have the same structure or different structures.

[0041] In one embodiment of the present invention, vertical transistors can be used as the transistors M11, M12, and M13, which can reduce the layout area of ​​the semiconductor device 100. That is, the storage density of a storage device including the semiconductor device 100 can be improved.

[0042] In one embodiment of the present invention, OS transistors (transistors including an oxide semiconductor in a channel formation region) can be used as the transistors M11, M12, and M13.

[0043] The OS transistor has a characteristic of having an extremely small off-state current because the band gap of the oxide semiconductor in which the channel is formed is 2 eV or more. The off-state current of an OS transistor per 1 μm of channel width in a room temperature environment is 1 aA (1×10 −１８ A) Below, 1zA (1×10 −２１ A) or less, or 1 yA (1 x 10 −２４In the case of a Si transistor (a transistor including silicon in a channel formation region), the off-state current per 1 μm of channel width in a room temperature environment can be 1 fA (1×10 −１５ A) or more and 1 pA (1 × 10 −１２ A) or less. Therefore, it can be said that the off-state current of an OS transistor is about 10 orders of magnitude smaller than that of a Si transistor. Therefore, for example, when a wiring electrically connected to one of the source and drain of an OS transistor is floating, charge accumulated in the wiring can be held for a long period of time. Therefore, for example, by configuring a memory cell using an OS transistor, data written to the memory cell can be stored for a long period of time.

[0044] Furthermore, the off-state current of an OS transistor hardly increases even in a high-temperature environment. Specifically, the off-state current hardly increases even in an environment of room temperature or higher and 200° C. or lower. The on-state current of an OS transistor is unlikely to decrease even in a high-temperature environment. On the other hand, the on-state current of a Si transistor decreases in a high-temperature environment. That is, the on-state current of an OS transistor is larger than that of a Si transistor in a high-temperature environment. Furthermore, an OS transistor can perform favorable switching operation even in an environment of 125° C. or higher and 150° C. or lower because of its large ratio of on-state current to off-state current. Therefore, a semiconductor device using an OS transistor can operate stably and with high reliability even in a high-temperature environment.

[0045] Furthermore, an OS transistor has a high withstand voltage between the source and the drain (also referred to as drain withstand voltage). Therefore, a semiconductor device including an OS transistor can operate stably and with high reliability even when driven at high voltage.

[0046] Here, the semiconductor device 100 is a gain cell type memory cell, and in particular, a configuration using an OS transistor as the write transistor (transistor M12) may be referred to as NOSRAM (registered trademark). NOSRAM is an abbreviation for Nonvolatile Oxide Semiconductor RAM. NOSRAM can store data for a long period of time because it uses an OS transistor with extremely low off-state current. It can also store multi-level data or analog data. Furthermore, because the write transistor (transistor M12) and the read transistor (transistor M13) are different, data can be read nondestructively. Therefore, the semiconductor device can be used, for example, as a nonvolatile memory.

[0047] A memory cell using an OS transistor writes or reads data by charging or discharging an electric charge, and therefore, data can be written or read a virtually unlimited number of times. Furthermore, a memory cell using an OS transistor does not undergo structural changes at the atomic level, unlike a magnetic memory or a resistance change memory, and therefore has excellent rewrite endurance. Furthermore, a memory cell using an OS transistor does not exhibit instability due to an increase in electron trap centers, unlike a flash memory, even after repeated writing, and therefore has excellent stability.

[0048] Furthermore, memory cells using OS transistors can be freely arranged on, for example, a silicon substrate on which Si transistors are provided, and therefore can be easily integrated. Furthermore, memory cells using OS transistors can be manufactured at low cost because they can be manufactured using the same manufacturing equipment as Si transistors.

[0049] Furthermore, since a memory cell using an OS transistor can be monolithically stacked, the memory cell using the memory cell can have improved recording density, improved bandwidth, and improved access latency.

[0050] Furthermore, in a memory cell using an OS transistor, the transistors constituting the memory cell can be stacked and arranged to have overlapping regions, which reduces the layout area and improves the recording density of a storage device using the memory cell.

[0051] 1B is a schematic diagram illustrating a configuration example of a semiconductor device according to one embodiment of the present invention. A semiconductor device 110 illustrated in FIG. 1B is a configuration example in which the transistors M11, M12, and M13 in the semiconductor device 100 are stacked.

[0052] 1B, the semiconductor device 110 includes a layer 190a, a layer 190b on the layer 190a, and a layer 190c on the layer 190b. The layer 190a includes a transistor M13, a wiring RWL, and a wiring RBL. The layer 190b includes a transistor M12 and a wiring WBL. The layer 190c includes a transistor M11, a wiring WWL, and a wiring BSL.

[0053] That is, the transistor M11 is located above the transistor M12, and the transistor M12 is located above the transistor M13.

[0054] Here, the transistors M11, M12, and M13 may be arranged to have overlapping regions with one another, thereby reducing the layout area of ​​the semiconductor device 110. As a result, the storage density of a storage device using the semiconductor device 110 can be improved.

[0055] In this specification and drawings, the X, Y, and Z directions may be defined to facilitate understanding of the positional relationships between the components. The X, Y, and Z directions are perpendicular to one another. The Z direction is the direction in which the layer 190a in which the transistor M13 is located, the layer 190b in which the transistor M12 is located, and the layer 190c in which the transistor M11 is located are stacked. The X and Y directions are the directions along the layers 190a, 190b, and 190c, respectively. In this specification and drawings, the Z direction may also be referred to as the vertical direction or the height direction.

[0056] Note that one embodiment of the present invention can have a structure in which, for example, layers 190a, 190b, and 190c are stacked over a substrate containing silicon in the semiconductor device 110. Here, for example, an OS transistor is provided in each of the layers 190a, 190b, and 190c. In this case, when the semiconductor device 110 is used as a memory device, for example, a driver circuit or the like included in the memory device can be provided on the substrate. Therefore, the memory device can be miniaturized. Furthermore, the wiring distance between the driver circuit and the semiconductor device 110 can be shortened. Therefore, the read speed and the write speed of the memory device can be improved.

[0057] Alternatively, for example, the layer 190a may include a portion of a substrate containing silicon, and layers 190b and 190c may be stacked on the layer 190a. Here, for example, OS transistors may be provided in each of the layers 190b and 190c. That is, OS transistors may be used as the transistors M11 and M12, and a Si transistor may be used as the transistor M13. By using a Si transistor as the transistor M13, which functions as a reading transistor, the data reading speed of the semiconductor device 110 can be improved.

[0058] In one embodiment of the present invention, vertical transistors can be used as the transistors M11, M12, and M13 in the semiconductor device 110. This enables the layout area of ​​the semiconductor device 110 to be reduced. That is, the storage density of a storage device including the semiconductor device 110 can be improved. Note that a structure example in which vertical transistors are used in the semiconductor device 110 will be described later.

[0059] <Operation Example of Semiconductor Device> Fig. 2 is a timing chart illustrating an operation example of writing and reading data in the semiconductor device 100. Fig. 3A to Fig. 3F are circuit diagrams illustrating the operation example.

[0060] In the following description, as potentials corresponding to binary data, a potential corresponding to binary data "1" is a high power supply potential VDD (sometimes simply referred to as VDD), and a potential corresponding to binary data "0" is a low power supply potential VSS (sometimes simply referred to as VSS). The difference between the potential VDD and the potential VSS is assumed to be greater than the threshold voltage of the transistor. Note that the potential VSS may be, for example, a ground potential.

[0061] In the description of the operation, when the potential changes, a rise time and a fall time may occur due to, for example, a load (parasitic capacitance and parasitic resistance) such as a wiring. Also, even if two different operations are shown to have the same timing, this does not necessarily mean that they are exactly the same timing. For example, even if there is a slight time difference due to signal delay in the wiring, they may be considered to have the same timing.

[0062] Furthermore, even if the timing chart shows each period as having the same length, the lengths of the periods may be different.

[0063] 2 shows the states of potentials (VDD or VSS) applied to the wirings BSL, WWL, WBL, and RWL in each period of data write and read operations. It also shows changes in the potentials of the wirings NL11, NL12, and RBL. Note that for the wirings WBL, NL11, NL12, and RBL, solid lines indicate the cases where data "1" is written and read, and dashed lines indicate the cases where data "0" is written and read.

[0064] 3A to 3F also show the potentials of the wirings BSL, WWL, WBL, RWL, NL11, NL12, and RBL at each point in time of the operation when writing and reading data "1." In this case, a symbol indicating a potential (also referred to as a potential symbol), such as "VDD" or "VSS," may be enclosed next to each wiring. An "x" symbol may be attached to a transistor in an off state. An arrow may be attached to a transistor through which a drain current is flowing.

[0065] In the period T11, VDD is applied to the wirings BSL and RWL, and VSS is applied to the wirings WWL and WBL. The potentials of the wirings NL11 and NL12 are VSS. The wiring RBL is precharged to VDD. The potentials of the wirings at this time are shown in FIG. 3A. In the following description, unless otherwise specified, the previous state is maintained.

[0066] In period T12, VDD is applied to the wiring WWL. Then, the potential of the wiring WWL is applied to the wiring NL11 via the transistor M11, and the transistor M12 is turned on. Here, if the threshold voltage of the transistor M11 is Vth, the potential of the wiring NL11 becomes "VDD-Vth." In other words, the potential of the wiring NL11 drops by the threshold voltage. Note that the potentials of the wirings at this time are shown in FIG. 3B.

[0067] In a period T13, data is written. For example, when data "0" is written, VSS remains applied to the wiring WBL. As a result, the potential of the wiring NL11 remains at "VDD-Vth," and the potential of the wiring NL12 remains at VSS.

[0068] Furthermore, for example, when writing data "1," VDD is applied to the wiring WBL. Then, the potential of the wiring WBL is applied to the wiring NL12 via the transistor M12. At this time, the potential of the wiring NL11 increases due to a bootstrap circuit formed by the transistor M11 and the gate capacitance of the transistor M12 (including the parasitic capacitance between the wiring NL11 and each of the wiring WBL and wiring NL12), so that the transistor M12 is fully turned on and the potential of the wiring NL12 becomes VDD. In other words, the potential of the wiring NL12 does not decrease by the threshold voltage. Note that the potentials of the wirings at this time are shown in FIG. 3C.

[0069] Here, if the potential of the wiring NL11 increases by ΔV due to the bootstrap circuit, ΔV is "(VDD - VSS) x gate capacitance of transistor M12 / (gate capacitance of transistor M12 + parasitic capacitance of the wiring NL11 other than the gate capacitance)".

[0070] That is, ΔV can be increased by either or both of increasing the gate capacitance of the transistor M12 and decreasing the parasitic capacitance of the wiring NL11 other than the gate capacitance. For example, ΔV can be increased by increasing the capacitance between the wiring NL11 and either or both of the wiring WBL and wiring NL12 depending on the device structure of each transistor. This means that, for example, even if VDD is reduced, the transistor M12 can be sufficiently turned on. Therefore, power consumption can be reduced.

[0071] In a period T14, VSS is applied to the wiring WWL. Then, VSS is applied to the wiring NL11 through the transistor M11, and the transistor M12 is turned off. As a result, data writing is completed, and the potential of the wiring NL12 is held. Note that the potentials of the wirings at this time are shown in FIG. 3D.

[0072] In a period T15, VSS is applied to the wiring WBL. At this time, the transistor M12 is off, so the potential of the wiring NL12 is maintained. Note that the potentials of the wirings at this time are shown in FIG. 3E.

[0073] Although not shown, in the period T15, the precharging of the wiring RBL is stopped, so that the wiring RBL is set to a floating state.

[0074] In a period T16, VSS is applied to the wiring RWL, and data is read. For example, when data “0” is read, the potential of the wiring NL12 is VSS and the transistor M13 is turned off, so that the potential of the wiring RBL remains at VDD.

[0075] Furthermore, for example, when reading data "1," the potential of the line NL12 is VDD and the transistor M13 is turned on, so that a drain current flows and the potential of the line RBL gradually drops from VDD to VSS. At this time, because the line NL12 is floating, the potential of the line NL12 also follows and gradually drops due to the gate capacitance of the transistor M13. The potentials of each line at this time are shown in FIG. 3F.

[0076] In this way, the potential of the wiring RBL differs between when data "0" is read and when data "1" is read. Therefore, for example, by reading the potential of the wiring RBL with a sense amplifier (not shown) electrically connected to the wiring RBL, a potential corresponding to data "0" or a potential corresponding to data "1" can be output.

[0077] The semiconductor device of one embodiment of the present invention includes a bootstrap circuit, so that when data is written, a potential corresponding to the data is applied without a drop in the threshold voltage of the writing transistor. This allows a sufficient drain current to flow through the reading transistor when data is read, thereby increasing the data read speed. In other words, VDD can be reduced while maintaining the data read speed. Therefore, power consumption can be reduced.

[0078] Although an operation example in which a constant potential of VDD is applied to the wiring BSL has been described here, a signal can also be applied to the wiring BSL. In this case, a signal can be applied to the wiring BSL so that the transistor M11 is turned on in the period T12 and the period T14 and turned off in the period T13. In this case, the transistor M13 can be turned off by applying VSS to the wiring BSL in the period T13. In this case, the gate voltage of the transistor M11 increases. Therefore, in order to improve reliability, VDD can be applied to the wiring BSL.

[0079] Note that, as in this operation example, by applying a constant potential of VDD to the wiring BSL, the wiring NL11 does not become floating during periods other than the period T13, and therefore, the transistor M12 can be prevented from being turned on due to noise or the like. Therefore, the semiconductor device of one embodiment of the present invention can be stabilized. Furthermore, a driver circuit for driving the semiconductor device of one embodiment of the present invention does not need to newly add a signal source for supplying a signal to the wiring BSL. Therefore, an increase in the area occupied by the driver circuit and an increase in power consumption can be suppressed.

[0080] Although an operation example in which a constant potential of VDD is applied to the wiring BSL and VDD is applied to the wiring WWL in the periods T12 and T13 has been described here, a potential higher than VDD can also be applied to each of the wirings, thereby improving the data writing speed and the data reading speed.

[0081] In the semiconductor device 100 of one embodiment of the present invention, the transistors may have the same size and characteristics or may have different sizes and characteristics. For example, the on-state current of the transistor M11 may be increased in order to improve the data writing speed. For example, the off-state current of the transistor M12 may be decreased in order to store data for a long period of time. For example, the on-state current of the transistor M13 may be increased in order to improve the data reading speed. In particular, in the semiconductor device 100, the data reading speed is likely to be more rate-determining than the data writing speed. Therefore, the on-state current of the transistor M13 may be increased more than the on-state current of the transistor M11.

[0082] For this purpose, for example, the channel length of each of the transistors M11 and M13 may be made shorter than the channel length of the transistor M12. Also, for example, the channel length of the transistor M13 may be made shorter than the channel length of the transistor M11.

[0083] For example, the channel width of each of the transistors M11 and M13 may be greater than the channel width of the transistor M12. For example, the channel width of the transistor M13 may be greater than the channel width of the transistor M11.

[0084] For example, the "channel width / channel length" of each of the transistors M11 and M13 may be greater than the "channel width / channel length" of the transistor M12. For example, the "channel width / channel length" of the transistor M13 may be smaller than the "channel width / channel length" of the transistor M11.

[0085] For example, the thickness of the gate insulating film of each of the transistors M11 and M13 may be smaller than that of the transistor M12. For example, the thickness of the gate insulating film of the transistor M13 may be smaller than that of the transistor M11.

[0086] For example, the dielectric constant of the gate insulating film of each of the transistors M11 and M13 may be set to be larger than the dielectric constant of the gate insulating film of the transistor M12. For example, the dielectric constant of the gate insulating film of the transistor M13 may be set to be larger than the dielectric constant of the gate insulating film of the transistor M11.

[0087] For example, the "dielectric constant / film thickness" of the gate insulating film of each of the transistors M11 and M13 may be set to be larger than the "dielectric constant / film thickness" of the gate insulating film of the transistor M12. For example, the "dielectric constant / film thickness" of the gate insulating film of the transistor M13 may be set to be larger than the "dielectric constant / film thickness" of the gate insulating film of the transistor M11.

[0088] For example, the field-effect mobility of each of the transistors M11 and M13 may be higher than that of the transistor M12. For example, the field-effect mobility of the transistor M13 may be higher than that of the transistor M11.

[0089] For example, the threshold voltages of the transistors M11 and M13 may be set lower than the threshold voltage of the transistor M12, and the threshold voltage of the transistor M13 may be set lower than the threshold voltage of the transistor M11.

[0090] For example, the crystallinity of the semiconductor layer including the channel formation region of each of the transistors M11 and M13 may be higher than that of the semiconductor layer including the channel formation region of the transistor M12. Also, the crystallinity of the semiconductor layer including the channel formation region of the transistor M13 may be higher than that of the semiconductor layer including the channel formation region of the transistor M11.

[0091] 4A to 4C are top views and cross-sectional views illustrating a structural example of a semiconductor device according to one embodiment of the present invention. A semiconductor device 120 illustrated in FIGS. 4A to 4C is a structural example of the semiconductor device 110 described above, in which a vertical transistor is used.

[0092] Fig. 4A is a top view of the semiconductor device 120. Fig. 4B is a cross-sectional view of the portion indicated by the dashed dotted line A1-A2 in Fig. 4A. Fig. 4C is a cross-sectional view of the portion indicated by the dashed dotted line A3-A4 in Fig. 4A. Note that some elements have been omitted from the top view of Fig. 4A for clarity.

[0093] 4B and 4C illustrate an insulator 620, transistors 600a, 600b, and 600c on the insulator 620, an insulator 640a on the insulator 620, an insulator 640b on the insulator 640a, an insulator 640c on the insulator 640b, and an insulator 678 on the transistors 600a, 600b, and 600c. The insulator 620, the insulator 640a, the insulator 640b, the insulator 640c, and the insulator 678 each function as an interlayer film.

[0094] The figure also shows a conductor 630 serving as one of the source and drain electrodes of the transistor 600a, a conductor 660a serving as the other of the source and drain electrodes, an oxide 650a serving as a semiconductor film including a channel formation region, and an insulator 672a serving as a gate insulating film. The figure also shows a conductor 670a serving as the gate electrode of the transistor 600a and also as one of the source and drain electrodes of the transistor 600b. The figure also shows a conductor 660b serving as the other of the source and drain electrodes of the transistor 600b, an oxide 650b serving as a semiconductor film including a channel formation region, and an insulator 672b serving as a gate insulating film. The figure also shows a conductor 670b serving as the gate electrode of the transistor 600b and also as one of the source and drain electrodes of the transistor 600c. The figure also shows a conductor 660c that functions as the other of the source electrode and the drain electrode of the transistor 600c, an oxide 650c that functions as a semiconductor film including a channel formation region, an insulator 672c that functions as a gate insulating film, and a conductor 670c that functions as a gate electrode. Note that the conductors 630, 660a, 660b, 660c, and 670c each also function as wirings.

[0095] Here, the semiconductor device 120 corresponds to the semiconductor device 100 and the semiconductor device 110 described above. That is, the transistor 600a corresponds to the transistor M13, the transistor 600b corresponds to the transistor M12, and the transistor 600c corresponds to the transistor M11. That is, it can be said that the transistor 600a is located on the layer 190a, the transistor 600b is located on the layer 190b, and the transistor 600c is located on the layer 190c. Furthermore, the conductor 630 corresponds to the wiring RWL, the conductor 660a corresponds to the wiring RBL, the conductor 670a corresponds to the wiring NL12, the conductor 660b corresponds to the wiring WBL, the conductor 670b corresponds to the wiring NL11, the conductor 660c corresponds to the wiring WWL, and the conductor 670c corresponds to the wiring BSL.

[0096] 4B and 4C , an opening 648a is provided in the insulator 640a and the conductor 660a, reaching the conductor 630, and at least a portion of the structure of the transistor 600a is disposed in the opening 648a. An opening 648b is provided in the insulator 640b and the conductor 660b, reaching the conductor 670a, and at least a portion of the structure of the transistor 600b is disposed in the opening 648b. An opening 648c is provided in the insulator 640c and the conductor 660c, reaching the conductor 670b, and at least a portion of the structure of the transistor 600c is disposed in the opening 648c.

[0097] Specifically, in the transistor 600a, a portion of the oxide 650a is provided along the side surface of the opening 648a, and a region of the oxide 650a along the opening 648a includes a channel formation region. In the transistor 600b, a portion of the oxide 650b is provided along the side surface of the opening 648b, and a region of the oxide 650b along the opening 648b includes a channel formation region. In the transistor 600c, a portion of the oxide 650c is provided along the side surface of the opening 648c, and a region of the oxide 650c along the opening 648c includes a channel formation region.

[0098] Therefore, in the semiconductor device 120, the area occupied by each of the transistors 600a, 600b, and 600c can be reduced when viewed from above.

[0099] Here, the channel length direction of the transistor 600a, the transistor 600b, and the transistor 600c can be said to have a component in the vertical direction (the Z direction in FIGS. 4A to 4C (i.e., the depth direction in a top view), which is also referred to as the height direction or the direction perpendicular to the surface where the transistor is formed). In other words, the channel length direction of the transistor 600a, the transistor 600b, and the transistor 600c can be said to have a component in the direction in which the layer 190a in which the transistor 600a is located, the layer 190b in which the transistor 600b is located, and the layer 190c in which the transistor 600c is located are stacked. In other words, it can be said that the source electrode and the drain electrode are located at different heights, and the drain current flows vertically. In this specification and the like, a transistor whose channel length direction has a vertical component (i.e., a transistor in which a drain current flows vertically) may be referred to as a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel transistor, or the like.

[0100] 4A to 4C, the transistors 600a, 600b, and 600c share part of their structures and are provided to overlap each other in a top view. That is, the openings 648a, 648b, and 648c have regions that overlap each other in a top view.

[0101] That is, in the semiconductor device 120 shown in Figures 4A to 4C, conductors 670c and 660c are located above conductor 670b, conductors 670b and 660b are located above conductor 670a, and conductors 670a and 660a are located above conductor 630. Furthermore, the conductor 670c has a region above the conductor 660c that functions as a wiring (corresponding to the wiring BSL) and a region below the conductor 660c that functions as a gate electrode of the transistor 600c. The conductor 670b has a region above the conductor 660b that functions as one of a source electrode or a drain electrode of the transistor 600c and a region below the conductor 660b that functions as the gate electrode of the transistor 600b. The conductor 670a has a region above the conductor 660a that functions as one of a source electrode or a drain electrode of the transistor 600b and a region below the conductor 660a that functions as the gate electrode of the transistor 600a. , the conductor 660c has a region functioning as the other of the source and drain electrodes of the transistor 600c and a region functioning as a wiring (corresponding to a wiring WWL), the conductor 660b has a region functioning as the other of the source and drain electrodes of the transistor 600b and a region functioning as a wiring (corresponding to a wiring WBL), the conductor 630 has a region functioning as one of the source and drain electrodes of the transistor 600a and a region functioning as a wiring (corresponding to a wiring RWL), and the conductor 660a has a region functioning as the other of the source and drain electrodes of the transistor 600a and a region functioning as a wiring (corresponding to a wiring RBL). In this case, the conductors 670c, 660c, 670b, 660b, 670a, 660a, and 630 have regions that overlap with each other in a top view. The channel length direction of each of the transistors 600c, 600b, and 600a is the depth direction (i.e., the Z direction) when viewed from above.

[0102] Each conductor included in the semiconductor device 120 may have a single layer structure or a stacked structure of two or more layers. For example, the conductor 630 may have a stacked structure of a conductor functioning as a wiring and a conductor functioning as one of the source and drain electrodes of the transistor 600a. For example, the conductor 660a may have a stacked structure of a conductor functioning as a wiring and a conductor functioning as the other of the source and drain electrodes of the transistor 600a. For example, the conductor 670a may have a stacked structure of a conductor functioning as the gate electrode of the transistor 600a and a conductor functioning as one of the source and drain electrodes of the transistor 600b. For example, the conductor 660b may have a stacked structure of a conductor functioning as a wiring and a conductor functioning as the other of the source and drain electrodes of the transistor 600b. For example, the conductor 670b may have a stacked structure including a conductor functioning as the gate electrode of the transistor 600b and a conductor functioning as one of the source and drain electrodes of the transistor 600c. For example, the conductor 660c may have a stacked structure including a conductor functioning as a wiring and a conductor functioning as the other of the source and drain electrodes of the transistor 600c. For example, the conductor 670c may have a stacked structure including a conductor functioning as the gate electrode of the transistor 600c and a conductor functioning as a wiring.

[0103] 4A to 4C, the conductor 630 and the conductor 660c each extend in the Y direction and are arranged to overlap each other in a top view. The conductors 660a, 660b, and 670c each extend in the X direction and are arranged to overlap each other in a top view. The conductors 670a and 670b are each arranged so as not to extend in either the X direction or the Y direction.

[0104] In this manner, the semiconductor device 120 can include the transistors 600a, 600b, and 600c, and conductors functioning as wirings, without significantly increasing the area occupied by the semiconductor device 120 when viewed from above.

[0105] [Transistor 600] Next, the structures of transistors 600a, 600b, and 600c will be described. Note that in the following description, transistors 600a, 600b, and 600c will be described as transistor 600, focusing on common features. That is, in transistor 600a, the insulator 640a, the conductor 660a, the oxide 650a, the insulator 672a, and a part of the conductor 670a (here, referring to the region of the conductor 670a in contact with the insulator 672a and the region in the vicinity thereof) correspond to the insulator 640, the conductor 660, the oxide 650, the insulator 672, and the conductor 670, respectively. Furthermore, in transistor 600b, a portion of conductor 670a (here referring to the region of conductor 670a in contact with oxide 650b and the region therearound), insulator 640b, conductor 660b, oxide 650b, insulator 672b, and a portion of conductor 670b (here referring to the region of conductor 670b in contact with insulator 672b and the region therearound) correspond to conductor 630, insulator 640, conductor 660, oxide 650, insulator 672, and conductor 670, respectively. Furthermore, in transistor 600c, a portion of conductor 670b (here referring to the region of conductor 670b in contact with oxide 650c and the region in its vicinity), insulator 640c, conductor 660c, oxide 650c, insulator 672c, and conductor 670c correspond to conductor 630, insulator 640, conductor 660, oxide 650, insulator 672, and conductor 670, respectively.

[0106] The transistor 600 includes a conductor 630, an insulator 640, a conductor 660 on the insulator 640, an oxide 650, an insulator 672 on the oxide 650, and a conductor 670 on the insulator 672. The oxide 650 functions as a semiconductor film including a channel formation region, the conductor 670 functions as a gate electrode, the insulator 672 functions as a gate insulating film, the conductor 630 functions as one of a source electrode and a drain electrode, and the conductor 660 functions as the other of the source electrode and the drain electrode.

[0107] In the transistor 600, a metal oxide functioning as an oxide semiconductor is used for the oxide 650 including the channel formation region.

[0108] The metal oxide preferably contains at least one of indium and zinc. Furthermore, for example, it is preferable to have indium, M (wherein M is one or more elements selected from gallium, aluminum, yttrium, tin, silicon, boron, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt), and zinc. It is particularly preferable that M is one or more elements selected from gallium, aluminum, yttrium, and tin.

[0109] In particular, as the metal oxide, it is preferable to use an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also referred to as "IGZO"). Alternatively, an oxide containing indium (In), aluminum (Al), and zinc (Zn) (also referred to as "IAZO") may be used. Alternatively, an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) (also referred to as "IAGZO") may be used. Alternatively, an oxide containing indium (In), tin (Sn), and zinc (Zn) (also referred to as "ITZO (registered trademark)") may be used. Alternatively, an oxide containing indium (In), gallium (Ga), zinc (Zn), and tin (Sn) (also referred to as "IGZTO") may be used.

[0110] By increasing the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained in a metal oxide, a transistor using the metal oxide for a semiconductor layer including a channel formation region can have excellent characteristics such as a large on-state current, high field-effect mobility, and high frequency characteristics.

[0111] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of M. Examples of atomic ratios of metal elements in such In-M-Zn oxides include a composition in which In:M:Zn=1:1:1 or thereabouts, a composition in which In:M:Zn=1:1:1.2 or thereabouts, a composition in which In:M:Zn=2:1:3 or thereabouts, a composition in which In:M:Zn=3:1:2 or thereabouts, a composition in which In:M:Zn=4:2:3 or thereabouts, a composition in which In:M:Zn=4:2:4.1 or thereabouts, a composition in which In:M:Zn=5:1:3 or thereabouts, a composition in which In:M:Zn=5:1:6 or thereabouts, a composition in which In:M:Zn=5:1:7 or thereabouts, a composition in which In:M:Zn=5:1:8 or thereabouts, a composition in which In:M:Zn=6:1:6 or thereabouts, and a composition in which In:M:Zn=5:2:5 or thereabouts. Furthermore, the atomic ratio of In in the In-M-Zn oxide may be smaller than the atomic ratio of M. Examples of atomic ratios of metal elements in such In-M-Zn oxides include a composition of In:M:Zn=1:3:2 or a composition thereabout, or a composition of In:M:Zn=1:3:4 or a composition thereabout. Note that a composition thereabout includes a range of plus or minus 30% of the desired atomic ratio.

[0112] For example, when describing a composition having an atomic ratio of In:Ga:Zn=4:2:3 or thereabout, this includes a case where, when In is taken as 4, Ga is 1 or more and 3 or less, and Zn is 2 or more and 4 or less. Furthermore, when describing a composition having an atomic ratio of In:Ga:Zn=5:1:6 or thereabout, this includes a case where, when In is taken as 5, Ga is more than 0.1 and 2 or less, and Zn is 5 or more and 7 or less. Furthermore, when describing a composition having an atomic ratio of In:Ga:Zn=1:1:1 or thereabout, this includes a case where, when In is taken as 1, Ga is more than 0.1 and 2 or less, and Zn is more than 0.1 and 2 or less.

[0113] Furthermore, when metal oxides are used in a stacked structure, for example, a three-layer stacked structure can be used in which a first layer is a metal oxide having an atomic ratio of metal elements of In:Ga:Zn = 1:1:1, a second layer is a metal oxide having an atomic ratio of metal elements of In:Zn = 4:1, and a third layer is a metal oxide having an atomic ratio of metal elements of In:Ga:Zn = 1:1:1. It is preferable that the band gaps of the metal oxides in the first and third layers are larger than the band gap of the metal oxide in the second layer. This configuration allows the metal oxide in the second layer to serve as the main current path, resulting in a so-called buried channel structure.

[0114] The composition of metal oxides can be analyzed by, for example, secondary ion mass spectrometry (SIMS), energy dispersive X-ray spectrometry (EDX), X-ray photoelectron spectrometry (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Spectrometry) or the like can be used. Alternatively, a combination of these techniques may be used for analysis. Note that for elements with low content, the actual content and the content obtained by analysis may differ due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0115] In one embodiment of the present invention, in the semiconductor device 120, for example, the proportion of indium atoms in the oxide 650a of the transistor 600a may be higher than the proportion of indium atoms in the oxide 650b of the transistor 600b and the proportion of indium atoms in the oxide 650c of the transistor 600c. This can increase the on-state current of the transistor 600a and improve the data read speed, for example. Furthermore, for example, the proportion of indium atoms in the oxide 650c of the transistor 600c may be higher than the proportion of indium atoms in the oxide 650b of the transistor 600b. This can increase the on-state current of the transistor 600c and improve the data write speed, for example.

[0116] The metal oxide can be formed by sputtering or atomic layer deposition (ALD). When the metal oxide is formed by sputtering, the composition of the formed metal oxide may differ from the composition of the sputtering target. In particular, the zinc content in the formed metal oxide may decrease to about 50% compared to the sputtering target.

[0117] The oxide semiconductor preferably has crystallinity. Examples of the crystalline oxide semiconductor include a c-axis aligned crystalline oxide semiconductor (CAAC-OS), a nanocrystalline oxide semiconductor (nc-OS), a polycrystalline oxide semiconductor, and a single-crystalline oxide semiconductor. As the oxide semiconductor, it is preferable to use a CAAC-OS or an nc-OS, and it is particularly preferable to use a CAAC-OS.

[0118] The CAAC-OS preferably has multiple layered crystalline regions, each with its c-axis oriented in the normal direction to the surface where it is formed. For example, the oxide semiconductor preferably has layered crystals parallel to the surface where it is formed. With this structure, the layered crystals of the oxide semiconductor are formed parallel to the channel length direction of the transistor, which allows the on-state current of the transistor to be increased.

[0119] In one embodiment of the present invention, in a method for forming an oxide semiconductor, a CAAC-OS, which is an oxide semiconductor with high crystallinity, can be used as a nucleus or a seed to increase the crystallinity of oxide semiconductors formed above and below the CAAC-OS. This can increase the crystallinity of the entire oxide semiconductor. In other words, oxide semiconductors formed above and below the CAAC-OS can be grown by solid-phase growth using the CAAC-OS as a nucleus or a seed, thereby forming an oxide semiconductor with high crystallinity. An oxide semiconductor formed by such a film formation method can be called an axial growth CAAC (AG CAAC).

[0120] By increasing the crystallinity of an oxide semiconductor, a transistor including the oxide semiconductor in a semiconductor layer including a channel formation region can have excellent characteristics (for example, a transistor with high on-state current, a transistor with high field-effect mobility, a transistor with a small S value, a transistor with high frequency characteristics (also referred to as f characteristics), and a highly reliable transistor).

[0121] The crystallinity of an oxide semiconductor can be analyzed by, for example, an X-ray diffraction (XRD) pattern, a transmission electron microscope (TEM) image, or an electron diffraction (ED) pattern. Alternatively, a combination of these methods may be used for analysis.

[0122] In one embodiment of the present invention, in the semiconductor device 120, for example, the crystallinity of the oxide 650a in the transistor 600a may be higher than that of the oxide 650b in the transistor 600b and that of the oxide 650c in the transistor 600c. This can increase the on-state current of the transistor 600a and improve the data read speed, for example. Furthermore, for example, the crystallinity of the oxide 650c in the transistor 600c may be higher than that of the oxide 650b in the transistor 600b. This can increase the on-state current of the transistor 600c and improve the data write speed, for example.

[0123] As shown in Figures 4B and 4C, an opening 648 is provided in the insulator 640 and the conductor 660, reaching the conductor 630. At least a portion of the oxide 650 is disposed in the opening 648. The oxide 650 has a region in contact with the upper surface of the conductor 630 in the opening 648, a region in contact with the side surface of the conductor 660 in the opening 648, and a region in contact with at least a portion of the upper surface of the conductor 660. The insulator 672 is disposed so that at least a portion of it is located in the opening 648. The conductor 670 is disposed so that at least a portion of it is located in the opening 648. As shown in Figures 4B and 4C, the conductor 670 is preferably disposed so as to fill the opening 648.

[0124] The conductor 630 may have a structure in which tantalum nitride is stacked on titanium nitride, for example. In this case, the titanium nitride may be in contact with the insulator below the conductor 630, and the tantalum nitride may be in contact with the oxide 650. With such a structure, excessive oxidation of the conductor 630 by the oxide 650 can be suppressed. Furthermore, when an oxide insulator is used as the insulator below the conductor 630, excessive oxidation of the conductor 630 can be suppressed by the oxide insulator. Note that the conductor 630 may have a structure in which tungsten is stacked on titanium nitride, for example.

[0125] Furthermore, since the conductor 630 has a region in contact with the oxide 650, it is preferable to use a conductive material containing oxygen. With such a structure, the conductor 630 can maintain its conductivity even if it absorbs oxygen. Furthermore, even when a material containing oxygen is used for the insulator below the conductor 630, the conductivity of the conductor 630 can be maintained.

[0126] Furthermore, as the conductor 630, for example, indium tin oxide (also referred to as ITO), silicon-added indium tin oxide (also referred to as ITSO), or indium zinc oxide (also referred to as IZO (registered trademark)) can be used in a single layer or in a stacked layer.

[0127] The oxide 650 has a region in contact with the side surface of the conductor 660 in the opening 648 and a region in contact with part of the top surface of the conductor 660. In this way, the oxide 650 contacts not only the side surface but also the top surface of the conductor 660, thereby increasing the area in which the oxide 650 and the conductor 660 contact each other.

[0128] 4C shows a structure in which the side edge of the oxide 650 is located inside the side edge of the conductor 660. Note that one embodiment of the present invention is not limited to this. For example, a structure in which the side edge of the oxide 650 and the side edge of the conductor 660 coincide with each other in at least one of the X direction and the Y direction may be used. Alternatively, a structure in which the side edge of the oxide 650 is located outside the side edge of the conductor 660 may be used.

[0129] The side surface of the opening 648 (which may also be referred to as the side surface of the opening 648 in the insulator 640) is preferably perpendicular to the upper surface of the conductor 630. In other words, the insulator 640 can be said to have the opening 648 extending in a direction perpendicular to the upper surface of the conductor 630. In this case, the opening 648 has a cylindrical shape.

[0130] Although this embodiment describes an example in which the opening 648 has a circular shape when viewed from above, one embodiment of the present invention is not limited to this. For example, the opening 648 may have a substantially circular shape such as an ellipse, a polygonal shape such as a square, or a polygonal shape such as a square with rounded corners when viewed from above. In this case, the maximum width of the opening 648 can be calculated appropriately according to the shape of the topmost part of the opening 648 when viewed from above.

[0131] For example, if opening 648 is rectangular in top view, the maximum width of opening 648 may be the length of the diagonal of the rectangle. Alternatively, for example, if opening 648 is approximately circular such as an ellipse, polygonal, or polygonal with rounded corners in top view, the maximum width of opening 648 may be the maximum width of the shape of opening 648 in top view.

[0132] The portions of the oxide 650, the insulator 672, and the conductor 670 that are disposed in the opening 648 are provided to reflect the shape of the opening 648. Thus, the oxide 650 is provided along the opening 648, the insulator 672 is provided to cover the oxide 650, and the conductor 670 is provided to fill the recess in the insulator 672 that reflects the shape of the opening 648.

[0133] That is, a part of the semiconductor film (corresponding to the oxide 650) including the channel formation region of the transistor 600 is provided along the side surface of the opening 648. That is, the part is provided in a direction perpendicular to the top surface of the conductor 630. In other words, the channel length direction of the transistor 600 has a component perpendicular to the top surface of the conductor 630.

[0134] Here, an insulator that contains excess oxygen and releases oxygen by heating is preferably used as the insulator 672. In this way, oxygen can be effectively supplied from the insulator 672 to the channel formation region of the oxide 650.

[0135] The insulator 672 may be, for example, a material that can be used for the insulator 522, the insulator 524, or the insulator 545 described later. For example, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, or silicon oxide having vacancies can be used. In particular, silicon oxide or silicon oxynitride is preferable in terms of its thermal stability. It is also preferable to use an insulator in which the concentrations of impurities such as hydrogen and water are reduced.

[0136] Furthermore, it is preferable to use a single layer or a stacked layer of a conductive material for each of the conductors 630, 660, and 670. For example, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion.

[0137] The conductor 630, the conductor 660, and the conductor 670 may each be made of a material that can be used for the conductor 503, the conductor 560, or the conductor 542a and the conductor 542b, which will be described later. For example, titanium nitride or tantalum nitride can be used. Furthermore, in terms of, for example, conductivity and heat resistance, it is preferable to use a stack of tungsten.

[0138] Furthermore, since the insulator 640 functions as an interlayer film, it is preferable to use a material with a low dielectric constant. By using a material with a low dielectric constant as an interlayer film, the parasitic capacitance generated between wirings can be reduced. Furthermore, an insulator containing a material with a low dielectric constant can be used in a single layer or a stacked layer.

[0139] For example, a material that can be used for the insulator 516 described later may be used as the insulator 640. For example, silicon oxide or silicon oxynitride is preferably used because of its thermal stability.

[0140] An insulator having a barrier property against oxygen, hydrogen, and the like is preferably used for each of the insulator 620 and the insulator 678. For example, an insulator having a barrier property that prevents impurities such as hydrogen from diffusing into the region where the transistor 600 is provided from outside the region where the transistor 600 is provided is preferably used.

[0141] For example, the material that can be used for the insulator 514 described later can be used for the insulator 620 and the insulator 678. For example, a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide is preferably used because it has a barrier property against hydrogen.

[0142] 4B and 4C , the opening 648 is provided so that the side surface of the opening 648 is perpendicular to the top surface of the conductor 630; however, one embodiment of the present invention is not limited to this. For example, the side surface of the opening 648 may have a tapered shape.

[0143] In this specification and the like, a tapered shape refers to a shape in which at least a portion of a side surface of a structure is inclined with respect to the substrate surface. The angle between the inclined side surface and the substrate surface is referred to as a taper angle. In particular, in this specification and the like, a tapered shape having a taper angle greater than 0° and less than 90° is sometimes referred to as a forward taper shape, and a tapered shape having a taper angle greater than 90° and less than 180° is sometimes referred to as a reverse taper shape.

[0144] 4B and 4C show the oxide 650 as a single layer, one embodiment of the present invention is not limited to this. The oxide 650 may have a stacked structure of multiple oxide layers with different chemical compositions.

[0145] Fig. 5A is an enlarged view of oxide 650 and its vicinity in Fig. 4B, Fig. 5B is a cross-sectional view in the XY plane of the portion indicated by the dashed dotted line A5-A6 in Fig. 5A.

[0146] As shown in FIG. 5A, the oxide 650 includes a region 650i and regions 650na and 650nb that are provided to sandwich the region 650i.

[0147] Region 650na is a region of oxide 650 that contacts conductor 630. At least a portion of region 650na functions as one of the source and drain regions of transistor 600. Region 650nb is a region of oxide 650 that contacts conductor 660. At least a portion of region 650nb functions as the other of the source and drain regions of transistor 600. As shown in FIG. 5B , conductor 660 contacts the entire periphery of oxide 650. Thus, the other of the source and drain regions of transistor 600 can be formed along the entire periphery of a portion of oxide 650 that is formed in the same layer as conductor 660.

[0148] The region 650i is a region between the regions 650na and 650nb of the oxide 650. At least a part of the region 650i functions as a channel formation region of the transistor 600. That is, the channel formation region of the transistor 600 is located in a region of the oxide 650 between the conductor 630 and the conductor 660. It can also be said that the channel formation region of the transistor 600 is located in a region of the oxide 650 that is in contact with the insulator 640 or in a region in the vicinity of the insulator 640.

[0149] The channel length of the transistor 600 is the distance between the source region and the drain region. In other words, the channel length of the transistor 600 can be said to be determined by the thickness of the insulator 640 on the conductor 630. In FIG. 5A , the channel length L of the transistor 600 is indicated by a dashed double-headed arrow. In a cross-sectional view, the channel length L is the distance between the edge of the region where the oxide 650 and the conductor 630 contact each other and the edge of the region where the oxide 650 and the conductor 660 contact each other. In other words, the channel length L corresponds to the length of the side of the insulator 640 on the opening 648 side in a cross-sectional view.

[0150] In a planar transistor, the channel length is set by the exposure limit of photolithography, whereas in one embodiment of the present invention, the channel length can be set by the film thickness of the insulator 640. Therefore, the channel length of the transistor 600 can be made into an extremely fine structure that is equal to or less than the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 1 nm or more, or 5 nm or more). This increases the on-state current of the transistor 600, thereby improving its frequency characteristics.

[0151] Furthermore, as described above, the channel formation region, the source region, and the drain region can be formed in the opening 648. This allows the area occupied by the transistor 600 to be reduced compared to a planar transistor in which the channel formation region, the source region, and the drain region are provided separately on the XY plane.

[0152] Furthermore, in the XY plane including the channel formation region of the oxide 650, the oxide 650, the insulator 672, and the conductor 670 are arranged concentrically, as in FIG. 5B . Therefore, the side surface of the conductor 670 located at the center faces the side surface of the oxide 650 via the insulator 672. That is, in a top view, the entire periphery of the oxide 650 forms the channel formation region. In this case, for example, the channel width of the transistor 600 is determined by the periphery length of the oxide 650. That is, the channel width of the transistor 600 can be determined by the maximum width of the opening 648 (or the maximum diameter if the opening 648 is circular in a top view). In FIGS. 5A and 5B , the maximum width D of the opening 648 is indicated by a double-headed, dashed arrow. In FIG. 5B , the channel width W of the transistor 600 is indicated by a double-headed, dashed arrow. Increasing the maximum width D of the opening 648 increases the channel width per unit area, thereby increasing the on-state current.

[0153] When the opening 648 is formed using photolithography, the maximum width D of the opening 648 is set by the exposure limit of photolithography. The maximum width D of the opening 648 is also set by the film thickness of each of the oxide 650, the insulator 672, and the conductor 670 provided in the opening 648. The maximum width D of the opening 648 is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and is preferably 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. When the opening 648 is circular in top view, the maximum width D of the opening 648 corresponds to the diameter of the opening 648, and the channel width W can be calculated as "D × π."

[0154] The channel length L of the transistor 600 of one embodiment of the present invention is preferably smaller than at least the channel width W of the transistor 600. The channel length L of the transistor 600 of one embodiment of the present invention is 0.1 to 0.99 times, preferably 0.5 to 0.8 times, the channel width W of the transistor 600. With such a structure, a transistor with favorable electrical characteristics and high reliability can be realized.

[0155] Furthermore, by forming the opening 648 so as to have a circular shape in top view, the oxide 650, the insulator 672, and the conductor 670 are arranged concentrically. This makes the distance between the conductor 670 and the oxide 650 uniform, allowing the gate electric field of the oxide 650 to be applied uniformly.

[0156] Note that the transistor 600 illustrated in FIGS. 4A to 4C is an example and is not limited to this configuration.

[0157] [Variation 1] In the semiconductor device 120, the channel lengths of the transistors 600a, 600b, and 600c can be changed by changing the thicknesses of the insulators 640a, 640b, and 640c.

[0158] 6A and 6B are cross-sectional views illustrating a semiconductor device 120A, which is a variation of the semiconductor device 120. The semiconductor device 120A differs from the semiconductor device 120 in that the channel lengths of the transistors 600a, 600b, and 600c are different from each other.

[0159] In the semiconductor device 120A, for example, the channel length La of the transistor 600a is smaller than the channel length Lb of the transistor 600b and the channel length Lc of the transistor 600c. The channel length Lc is also smaller than the channel length Lb. In other words, the channel length Lb is larger than the channel length La and the channel length Lc. The channel length Lc is also larger than the channel length La.

[0160] In the transistor 600a, the on-state current can be increased by reducing the channel length La. Therefore, the data read speed can be improved in the semiconductor device 120A. Furthermore, in the transistor 600c, the on-state current can be increased by reducing the channel length Lc. Therefore, the data write speed can be improved in the semiconductor device 120A.

[0161] In the semiconductor device 120A, the on-state current of the transistor 600a may be set to be larger than the on-state current of the transistor 600c because the data read speed is more likely to be a determining factor than the data write speed. Therefore, for example, the channel length La of the transistor 600a is set to be smaller than the channel length Lc of the transistor 600c.

[0162] 7A and 7B are cross-sectional views illustrating a semiconductor device 120B, which is a modification of the semiconductor device 120. The semiconductor device 120B differs from the semiconductor device 120 in that the conductor 670b extends beyond the end of the oxide 650.

[0163] With this configuration, a capacitance can be provided between the conductor 670b and the conductor 660b as a pair of electrodes, that is, the capacitance between the conductor 670b corresponding to the wiring NL11 and the conductor 660b corresponding to the wiring WBL can be increased.

[0164] That is, as described above, in a bootstrap circuit including the gate capacitance of the transistor 600c corresponding to the transistor M11 and the gate capacitance of the transistor 600b corresponding to the transistor M12, the potential of the conductor 670b corresponding to the wiring NL11 can be increased. Therefore, for example, even if VDD is reduced, the transistor 600b can be sufficiently turned on, thereby reducing power consumption.

[0165] <Layout Example of Semiconductor Device> Here, an example of a layout in which the above-described semiconductor devices 120 are arranged in a matrix will be described.

[0166] 8A and 8B are each a top view illustrating an example of a layout of a semiconductor device of one embodiment of the present invention.

[0167] 8A and 8B, nine semiconductor devices 120 are arranged in a matrix of 3 rows and 3 columns. Here, the semiconductor device 120 arranged in the first row and first column is shown as semiconductor device 120[1,1], the semiconductor device 120 arranged in the first row and third column is shown as semiconductor device 120[1,3], the semiconductor device 120 arranged in the third row and first column is shown as semiconductor device 120[3,1], and the semiconductor device 120 arranged in the third row and third column is shown as semiconductor device 120[3,3].

[0168] In addition, oxide 650a, oxide 650b, and oxide 650c of semiconductor device 120[1,1] are collectively referred to as oxide 650[1,1], oxide 650a, oxide 650b, and oxide 650c of semiconductor device 120[1,3] are collectively referred to as oxide 650[1,3], oxide 650a, oxide 650b, and oxide 650c of semiconductor device 120[3,1] are collectively referred to as oxide 650[3,1], and oxide 650a, oxide 650b, and oxide 650c of semiconductor device 120[3,3] are collectively referred to as oxide 650[3,3].

[0169] In addition, openings 648a, 648b, and 648c of semiconductor device 120[1,1] are collectively referred to as opening 648[1,1], openings 648a, 648b, and 648c of semiconductor device 120[1,3] are collectively referred to as opening 648[1,3], openings 648a, 648b, and 648c of semiconductor device 120[3,1] are collectively referred to as opening 648[3,1], and openings 648a, 648b, and 648c of semiconductor device 120[3,3] are collectively referred to as opening 648[3,3].

[0170] The three semiconductor devices 120 arranged in the first row are electrically connected to the conductors 630[1] and 660c[1] extending in the row direction (Y direction). The three semiconductor devices 120 arranged in the second row are electrically connected to the conductors 630[2] and 660c[2] extending in the row direction (Y direction). The three semiconductor devices 120 arranged in the third row are electrically connected to the conductors 630[3] and 660c[3] extending in the row direction (Y direction).

[0171] The three semiconductor devices 120 arranged in the first row are electrically connected to the conductors 660a[1] and 660b[1] extending in the column direction (X direction). The three semiconductor devices 120 arranged in the second row are electrically connected to the conductors 660a[2] and 660b[2] extending in the column direction (X direction). The three semiconductor devices 120 arranged in the third row are electrically connected to the conductors 660a[3] and 660b[3] extending in the column direction (X direction).

[0172] 8A, the three semiconductor devices 120 arranged in the first row are electrically connected to conductors 670c[1] extending in the row direction (X direction). The three semiconductor devices 120 arranged in the second row are electrically connected to conductors 670c[2] extending in the row direction (X direction). The three semiconductor devices 120 arranged in the third row are electrically connected to conductors 670c[3] extending in the row direction (X direction).

[0173] That is, the direction in which the conductors 670c[1] to 670c[3] extend is parallel to the direction in which the conductors 660a[1] to 660a[3] extend, parallel to the direction in which the conductors 660b[1] to 660b[3] extend, and perpendicular to the direction in which the conductors 630[1] to 630[3] extend and perpendicular to the direction in which the conductors 660c[1] to 660c[3] extend.

[0174] Furthermore, when viewed from above, conductor 670c[1], conductor 660a[1], and conductor 660b[1] have regions where they overlap with each other, conductor 670c[2], conductor 660a[2], and conductor 660b[2] have regions where they overlap with each other, and conductor 670c[3], conductor 660a[3], and conductor 660b[3] have regions where they overlap with each other. In addition, when viewed from above, the ends of conductor 670c[1], conductor 660a[1], and conductor 660b[1] do not have to be aligned, the ends of conductor 670c[2], conductor 660a[2], and conductor 660b[2] do not have to be aligned, and the ends of conductor 670c[3], conductor 660a[3], and conductor 660b[3] do not have to be aligned.

[0175] In addition, when viewed from above, the conductor 630[1] and the conductor 660c[1] have an overlapping region, the conductor 630[2] and the conductor 660c[2] have an overlapping region, and the conductor 630[3] and the conductor 660c[3] have an overlapping region. Note that, when viewed from above, the ends of the conductor 630[1] and the conductor 660c[1] do not have to be aligned, the ends of the conductor 630[2] and the conductor 660c[2] do not have to be aligned, and the ends of the conductor 630[3] and the conductor 660c[3] do not have to be aligned.

[0176] 8B, the three semiconductor devices 120 arranged in the first row are electrically connected to a conductor 670c[1] extending in the row direction (Y direction). The three semiconductor devices 120 arranged in the second row are electrically connected to a conductor 670c[2] extending in the row direction (Y direction). The three semiconductor devices 120 arranged in the third row are electrically connected to a conductor 670c[3] extending in the row direction (Y direction).

[0177] That is, the direction in which conductors 670c[1] to 670c[3] extend is parallel to the direction in which conductors 630[1] to 630[3] extend, parallel to the direction in which conductors 660c[1] to 660c[3] extend, perpendicular to the direction in which conductors 660a[1] to 660a[3] extend, and perpendicular to the direction in which conductors 660b[1] to 660b[3] extend.

[0178] Furthermore, when viewed from above, the conductor 670c[1], the conductor 630[1], and the conductor 660c[1] have overlapping regions, the conductor 670c[2], the conductor 630[2], and the conductor 660c[2] have overlapping regions, and the conductor 670c[3], the conductor 630[3], and the conductor 660c[3] have overlapping regions. Note that when viewed from above, the ends of the conductors 670c[1], the conductor 630[1], and the conductor 660c[1] do not have to be aligned, the ends of the conductors 670c[2], the conductor 630[2], and the conductor 660c[2] do not have to be aligned, and the ends of the conductors 670c[2], the conductor 630[3], and the conductor 660c[3] do not have to be aligned.

[0179] In addition, when viewed from above, the conductors 660a[1] and 660b[1] have overlapping regions, the conductors 660a[2] and 660b[2] have overlapping regions, and the conductors 660a[3] and 660b[3] have overlapping regions. Note that, when viewed from above, the ends of the conductors 660a[1] and 660b[1] do not have to be aligned, the ends of the conductors 660a[2] and 660b[2] do not have to be aligned, and the ends of the conductors 660a[3] and 660b[3] do not have to be aligned.

[0180] 8A, the overlapping area between the wirings BSL and WWL and the overlapping area between the wirings BSL and RWL can be reduced compared to the layout example shown in FIG. 8B. That is, the parasitic capacitance of the wirings WWL and RWL can be reduced. Therefore, for example, the data write speed and read speed can be improved.

[0181] In addition, in the layout example shown in FIG. 8B, the wiring BSL extends in the same direction as the wiring WWL and the wiring RWL. Therefore, for example, when a signal is applied to the wiring BSL, such a layout example may be adopted.

[0182] Although an example in which nine semiconductor devices 120 are arranged in a matrix of three rows and three columns has been shown here, the arrangement is not limited to this. The arrangement of the multiple semiconductor devices 120 may be two rows, four or more rows, or two columns, or four or more columns.

[0183] 9 is a circuit diagram illustrating a semiconductor device 100B, which is a modification of the semiconductor device 100. The semiconductor device 100B differs from the semiconductor device 100 in that the transistors M11, M12, and M13 each have a back gate.

[0184] The back gate of the transistor M11 is electrically connected to the wiring BGL1, the back gate of the transistor M12 is electrically connected to the wiring BGL2, and the back gate of the transistor M13 is electrically connected to the wiring BGL3.

[0185] Here, the threshold voltage of a transistor having a back gate shifts depending on the back gate voltage. For example, when the back gate voltage is higher than 0 V, the threshold voltage is lower (also referred to as a negative shift) than when the back gate voltage is 0 V. Also, when the back gate voltage is lower than 0 V, the threshold voltage is higher (also referred to as a positive shift) than when the back gate voltage is 0 V.

[0186] Therefore, the threshold voltages of the transistors M11, M12, and M13 can be changed by the potentials applied to the wirings BGL1, BGL2, and BGL3, respectively.

[0187] In one embodiment of the present invention, for example, the potentials applied to the wirings BGL1 and BGL3 may be higher than the potential applied to the wiring BGL2. Furthermore, for example, the potential applied to the wiring BGL3 may be higher than the potential applied to the wiring BGL1. In other words, for example, the potential applied to the wiring BGL2 may be lower than the potentials applied to the wirings BGL1 and BGL3. Furthermore, for example, the potential applied to the wiring BGL1 may be lower than the potential applied to the wiring BGL3.

[0188] By increasing the potential applied to the wiring BGL1, the threshold voltage of the transistor M11 is shifted in the negative direction, thereby improving the data writing speed. By decreasing the potential applied to the wiring BGL2, the threshold voltage of the transistor M12 is shifted in the positive direction, thereby enabling data to be stored for a long period of time. By increasing the potential applied to the wiring BGL3, the threshold voltage of the transistor M13 is shifted in the negative direction, thereby improving the data reading speed.

[0189] In the semiconductor device 100B, the threshold voltage of the transistor M13 may be set lower than the threshold voltage of the transistor M11 because the data read speed is more likely to be a determining factor than the data write speed. Therefore, for example, the potential applied to the wiring BGL3 is set higher than the potential applied to the wiring BGL1.

[0190] 10 is a cross-sectional view illustrating a structural example of a transistor having a back gate according to one embodiment of the present invention. The transistor 600B illustrated in FIG. 10 is a variation of the transistor 600. The transistor 600B has two gates (a gate and a back gate) corresponding to each other with a channel formation region therebetween.

[0191] The transistor 600B differs from the transistor 600 in that it includes a conductor 680 and an insulator 682. In the transistor 600B, the insulator 682 is provided between the insulator 640 and the oxide 650 on the side surface of the opening 648, and the conductor 680 is provided in part of the insulator 640 so as to surround the outer periphery of the oxide 650 with the insulator 682 interposed therebetween.

[0192] Here, the conductor 670 may function as a first gate (also simply referred to as a gate) electrode, and the conductor 680 may function as a second gate (also referred to as a back-gate) electrode. In this case, the insulator 672 functions as a first gate insulating film, and the insulator 682 functions as a second gate insulating film.

[0193] The transistor 600B also differs from the transistor 600 in that the conductor 630 has a recessed portion at a position overlapping with the opening 648. In the transistor 600B, part of the oxide 650 and part of the insulator 682 are provided in the recessed portion of the conductor 630. In this case, the bottom surface of the oxide 650 is located lower than the bottom surface of the insulator 682.

[0194] This structure can increase the area where the oxide 650 and the conductor 630 are in contact with each other, thereby reducing the contact resistance between the oxide 650 and the conductor 630.

[0195] Here, for example, a material that can be used for the conductor 670 may be used as the conductor 680. Furthermore, for example, a material that can be used for the insulator 672 may be used as the insulator 682.

[0196] <Structure Example 5 of Semiconductor Device> In one embodiment of the present invention, transistors having a structure different from that of vertical transistors such as the transistors 600 and 600B can be used in the semiconductor device 100 and the semiconductor device 110. For example, planar transistors can be used as the transistors M11, M12, and M13.

[0197] [Transistor 500] Here, a transistor 500 will be described as an example of a planar transistor that can be used for the semiconductor device 100, the semiconductor device 110, and the like of one embodiment of the present invention.

[0198] 11A is a top view of the transistor 500. FIG. 11B is a cross-sectional view of the portion indicated by the dashed dotted line A1-A2 in FIG. 11A and is also a cross-sectional view of the transistor 500 in the channel length direction (illustrated as the X direction). FIG. 11C is a cross-sectional view of the portion indicated by the dashed dotted line A3-A4 in FIG. 11A and is also a cross-sectional view of the transistor 500 in the channel width direction (illustrated as the Y direction). Note that some elements are omitted from the top view of FIG. 11A for clarity.

[0199] As shown in FIGS. 11B and 11C, an insulator 514 and an insulator 516 are stacked in this order on top of the insulator 512.

[0200] Any of the insulators 512, 514, and 516 is preferably an insulator that has barrier properties against oxygen, hydrogen, and the like.

[0201] The insulator 514 is preferably an insulator having a barrier property that prevents impurities such as hydrogen from diffusing from outside the region where the transistor 500 is provided to the region where the transistor 500 is provided. The insulator 514 can be, for example, a material similar to the insulator 324 described later.

[0202] As an insulator having a barrier property against hydrogen, it is preferable to use a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0203] In particular, aluminum oxide has a high barrier property against both oxygen and impurities such as hydrogen and water. Therefore, aluminum oxide can prevent impurities such as hydrogen and water from entering the transistor 500 during and after the manufacturing process of the transistor, and can suppress the release of oxygen from the oxide constituting the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0204] Parasitic capacitance between wirings can be reduced by using a material with a relatively low dielectric constant for the insulators 512 and 516. For the insulators 512 and 516, for example, a material similar to the insulator 326 described later can be used.

[0205] As shown in Figures 11B and 11C, the transistor 500 has a conductor 503 arranged so as to be embedded in the insulator 514 and the insulator 516, an insulator 522 arranged on the insulator 516 and the conductor 503, an insulator 524 arranged on the insulator 522, an oxide 530a arranged on the insulator 524, an oxide 530b arranged on the oxide 530a, conductors 542a and 542b arranged apart from each other on the oxide 530b, an insulator 580 arranged on the conductors 542a and 542b and having an opening formed therein overlapping with the conductors 542a and 542b, an insulator 545 arranged along the opening, and a conductor 560 arranged on the formation surface of the insulator 545.

[0206] Note that the oxide 530a and the oxide 530b may be collectively referred to as the oxide 530.

[0207] The oxide 530 functions as a semiconductor film including a channel formation region of the transistor 500 .

[0208] The conductor 503 is arranged to overlap the oxide 530 and the conductor 560 .

[0209] Here, the conductor 503 preferably includes a conductor 503a provided in contact with the insulators 514 and 516 and a conductor 503b provided so as to be embedded inside the conductor 503a. Furthermore, an insulator 544 is preferably disposed between the insulator 580 and the oxide 530a, the oxide 530b, the conductor 542a, and the conductor 542b. Furthermore, the conductor 560 preferably includes a conductor 560a provided inside the insulator 545 and a conductor 560b provided so as to be embedded inside the conductor 560a. Furthermore, an insulator 582 is preferably disposed over the insulator 580, the conductor 560, and the insulator 545.

[0210] 11B and 11C , the conductor 503 has a two-layer structure including the conductor 503a and the conductor 503b, but the conductor 503 is not limited to this structure. For example, the conductor 503 may have a single-layer structure or a three-layer structure.

[0211] Although the configuration in which the ends of the conductors 542a and 542b are aligned with the end of the oxide 530 is shown, the present invention is not limited to this. For example, the conductors 542a and 542b may extend beyond the end of the oxide 530.

[0212] Although the oxide 530 has a two-layer structure including the oxide 530a and the oxide 530b, the structure is not limited thereto. For example, the oxide 530 may have a single-layer structure or a three-layer structure or more.

[0213] Although the conductor 560 has a two-layer structure including the conductor 560a and the conductor 560b, the conductor 560 is not limited to this structure. For example, the conductor 560 may have a single-layer structure or a three-layer structure.

[0214] Here, in the transistor 500, the conductor 560 functions as a gate electrode, the insulator 545 functions as a gate insulating film, and the conductor 542a and the conductor 542b function as one and the other of a source electrode or a drain electrode, respectively.

[0215] As described above, the conductor 560 is formed so as to be embedded in an opening (sometimes referred to as an opening of the insulator 580) formed in a region of the insulator 580 between the conductors 542a and 542b. Therefore, the arrangement of the conductor 560, the conductors 542a, and the conductors 542b is selected in a self-aligned manner with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be arranged between the source electrode and the drain electrode in a self-aligned manner. With this configuration, the conductor 560 can be formed without providing a margin for alignment. Therefore, the area occupied by the transistor 500 can be reduced. This allows for miniaturization and high integration of semiconductor devices.

[0216] Furthermore, since the conductor 560 is formed in a self-aligned manner in the region between the conductor 542a and the conductor 542b, the conductor 560 does not have a region overlapping with the conductor 542a and the conductor 542b. This reduces the parasitic capacitance formed between the conductor 560 and the conductor 542a and the conductor 542b. This improves the switching speed of the transistor 500. This improves the frequency characteristics of the semiconductor device.

[0217] Furthermore, miniaturization of semiconductor devices requires shortening the gate length of the transistor 500, but at the same time, it is necessary to ensure that the conductivity of the conductor 560 does not decrease. If the thickness of the conductor 560 is increased for this purpose, the conductor 560 may have a shape with a high aspect ratio. Therefore, by providing the conductor 560 so that it is embedded in the opening of the insulator 580, the conductor 560 with a shape with a high aspect ratio can be formed without collapsing during the process.

[0218] Here, the conductor 560 may function as a first gate (also simply referred to as a gate) electrode, and the conductor 503 may function as a second gate (also referred to as a back-gate) electrode. In this case, the insulator 545 functions as a first gate insulating film, and the insulators 522 and 524 function as second gate insulating films.

[0219] As described above, the conductor 503 is arranged to overlap with the oxide 530 and the conductor 560. Therefore, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 are connected, and the channel formation region formed in the oxide 530 can be covered.

[0220] In this case, in the transistor 500, for example, the threshold voltage of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560. In particular, applying a negative potential to the conductor 503 increases the threshold voltage of the transistor 500, thereby enabling a reduction in off-state current. Therefore, for example, applying a negative potential to the conductor 503 can reduce the drain current (sometimes referred to as cutoff current) when the potential applied to the conductor 560 is 0 V.

[0221] In this specification and the like, a transistor structure in which the electric field of the gate electrode electrically surrounds the channel formation region is referred to as a surrounded channel (S-channel) structure. The S-channel structure disclosed in this specification and the like can also be said to have a structure different from a Fin structure and a planar structure. On the other hand, the S-channel structure disclosed in this specification and the like can also be regarded as a type of Fin structure or a type of planar structure. In this specification and the like, a Fin structure refers to a structure in which the gate electrode is disposed so as to surround at least two or more sides of the channel (specifically, two, three, or four sides, etc.). By employing the Fin structure and the S-channel structure, a transistor can be obtained that has improved resistance to the short channel effect. In other words, a transistor can be obtained that is less susceptible to the short channel effect.

[0222] By forming a transistor in the S-channel structure, the channel formation region can be electrically surrounded by the electric field of the gate electrode. Since the S-channel structure electrically surrounds the channel formation region with the electric field of the gate electrode, it can be said that the S-channel structure is substantially equivalent to a Gate All Around (GAA) structure or a Lateral Gate All Around (LGAA) structure. By forming a transistor in the S-channel, GAA, or LGAA structure, the channel formation region formed at or near the interface between the semiconductor film and the gate insulating film can be the entire bulk of the semiconductor film. Therefore, it is possible to increase the density of current flowing through the transistor, thereby improving the on-state current of the transistor or the field-effect mobility of the transistor.

[0223] As described above, the conductor 503 has the conductor 503a formed in contact with the insulators 514 and 516, and the conductor 503b formed further inside.

[0224] The conductor 503a is preferably made of a conductive material that has barrier properties against impurities such as hydrogen (e.g., at least one of hydrogen atoms and hydrogen molecules), water, and copper (has the function of suppressing the diffusion of the impurities; i.e., the impurities are less likely to permeate). Furthermore, the conductor 503a is preferably made of a conductive material that has barrier properties against oxygen (e.g., at least one of oxygen atoms and oxygen molecules) (has the function of suppressing the diffusion of oxygen; i.e., the impurities are less likely to permeate). In other words, the conductor 503a preferably has barrier properties against any one or all of the above impurities and oxygen.

[0225] In this way, the conductor 503a has a barrier property against oxygen, which can prevent the conductor 503b from being oxidized and reducing its conductivity, thereby allowing the conductor 503b to also function as a wiring.

[0226] In this case, it is preferable to use a conductive material with high conductivity as the conductor 503b, such as a conductive material containing tungsten, copper, or aluminum as its main component.

[0227] Here, it is preferable to use an insulator containing more oxygen than the amount of oxygen required for the stoichiometric composition as the insulator in contact with the oxide 530. The oxygen is easily released from the insulator by heating. Note that in this specification and elsewhere, oxygen released by heating may be referred to as "excess oxygen."

[0228] The insulator 524 is in contact with the oxide 530. Therefore, the insulator 524 preferably has a region containing excess oxygen (also referred to as an "excess oxygen region").

[0229] In this way, by providing an insulator containing excess oxygen in contact with the oxide 530, oxygen vacancies (V Ｏ This can reduce oxygen vacancy (also referred to as oxygen vacancy) and improve the reliability of the transistor 500.

[0230] In the oxide 530, a defect in which hydrogen enters an oxygen vacancy in the oxide 530 (hereinafter, V Ｏ H. ) may function as a donor and generate electrons as carriers. Furthermore, some of the hydrogen may bond with oxygen, which is bonded to a metal atom, to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics. Furthermore, hydrogen in an oxide semiconductor is easily moved by stress, such as heat or an electric field. Therefore, if an oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may be reduced. In one embodiment of the present invention, V in the oxide 530 Ｏ It is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic hydrogen.

[0231] In this way, V ＯTo obtain an oxide semiconductor in which H is sufficiently reduced, it is important to remove impurities such as hydrogen and water from the oxide semiconductor (also referred to as "dehydration" or "dehydrogenation treatment") and to supply oxygen to the oxide semiconductor to compensate for oxygen vacancies (also referred to as "oxygenation treatment"). Ｏ When an oxide semiconductor in which impurities such as H are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0232] When the insulator 524 has an excess oxygen region, the insulator 522 preferably has a barrier property against oxygen. The insulator 522 having a barrier property against oxygen can, for example, prevent oxygen contained in the oxide 530 from diffusing toward the insulator 516. Furthermore, for example, the conductor 503 can be prevented from reacting with oxygen contained in the insulator 524, the oxide 530, and the like.

[0233] Here, in a transistor using an oxide semiconductor for a semiconductor film, it is preferable that a channel formation region of the transistor has fewer oxygen vacancies or a lower impurity concentration (for example, the concentration of hydrogen, nitrogen, or a metal element) than a source region and a drain region. Ｏ H is formed and electrons that act as carriers may be generated, so V Ｏ It is also preferable that the amount of H is small. As described above, the channel formation region of the transistor is a high-resistance region with a low carrier concentration. Therefore, the channel formation region of the transistor can be said to be i-type (intrinsic) or substantially i-type.

[0234] In addition, the source and drain regions of the transistor have more oxygen vacancies than the channel formation region. Ｏ It is preferable that the source region and the drain region of the transistor have a high carrier concentration or a high impurity concentration. As described above, the source region and the drain region of the transistor are n-type regions with a high carrier concentration and low resistance compared to the channel formation region.

[0235] The band gap of the metal oxide used as the oxide semiconductor is preferably 2 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wide band gap as the oxide semiconductor, the off-state current of the transistor can be reduced.

[0236] The insulator 522 is preferably made of a high-dielectric-constant (high-k) material (a material with a high relative dielectric constant).

[0237] As transistors become more miniaturized and highly integrated, the thinner gate insulating film can cause problems such as gate leakage current. By using a high-k material as the insulator that functions as the gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0238] Examples of insulators that function as gate insulating films include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), and strontium titanate (SrTiO ３ ), or an insulator including barium strontium titanate (BST), is preferably used in a single layer or a laminated layer.

[0239] In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium, in terms of an insulator having barrier properties against oxygen, impurities, etc. As the insulator, it is preferable to use, for example, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate).

[0240] Furthermore, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. These insulators may be used after being nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on these insulators.

[0241] By forming the insulator 522 using such a material, the insulator 522 can function as an insulator that prevents oxygen from being released from the oxide 530 and prevents impurities such as hydrogen from being mixed into the oxide 530 from the periphery of the transistor 500.

[0242] 11B and 11C shows a structure in which two layers, the insulator 522 and the insulator 524, are stacked as the second gate insulating film; however, the present invention is not limited to this. For example, the second gate insulating film may have a single-layer structure or a stacked structure of three or more layers. In this case, the second gate insulating film may have a structure in which the same material is stacked, or a structure in which different materials are stacked.

[0243] In the transistor 500, a metal oxide functioning as an oxide semiconductor is used for the oxide 530 including the channel formation region. For example, the metal oxide that can be used for the oxide 650 described above may be used for the oxide 530. Note that as the oxide semiconductor, a metal oxide can be used as a single layer or a stacked layer.

[0244] In the oxide 530, the oxide 530a is provided below the oxide 530b, which makes it possible to suppress the diffusion of impurities from components formed below the oxide 530a into the oxide 530b.

[0245] The oxide 530 preferably has a configuration of multiple oxide layers with different atomic ratios of the metal atoms. Specifically, the atomic ratio of the element M among the constituent elements in the metal oxide used for the oxide 530a is preferably larger than the atomic ratio of the element M among the constituent elements in the metal oxide used for the oxide 530b. Furthermore, the atomic ratio of the element M to In in the metal oxide used for the oxide 530a is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 530b. Furthermore, the atomic ratio of In to M in the metal oxide used for the oxide 530b is preferably larger than the atomic ratio of In to M in the metal oxide used for the oxide 530a.

[0246] The oxide 530a preferably has a conduction band minimum energy higher than that of the oxide 530b, or in other words, the oxide 530a preferably has a lower electron affinity than that of the oxide 530b.

[0247] Here, the energy level of the conduction band minimum at the junction between the oxide 530a and the oxide 530b changes gradually. In other words, the energy level of the conduction band minimum at the junction between the oxide 530a and the oxide 530b changes continuously, or the junction has a continuous junction. To achieve this, the defect level density of the mixed layer formed at the interface between the oxide 530a and the oxide 530b may be reduced.

[0248] Specifically, when the oxide 530a and the oxide 530b have a common element (main component) other than oxygen, a mixed layer with a low density of defect states can be formed. For example, when the oxide 530b is an In—Ga—Zn oxide, the oxide 530a may be an In—Ga—Zn oxide, a Ga—Zn oxide, or gallium oxide.

[0249] In this case, the main carrier path is the oxide 530b. By configuring the oxide 530a as described above, the defect state density at the interface between the oxide 530a and the oxide 530b can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the on-state current of the transistor 500 can be increased.

[0250] A conductor 542a and a conductor 542b which function as a source electrode and a drain electrode are provided over the oxide 530b.

[0251] The conductors 542a and 542b can be made of, for example, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, or lanthanum, an alloy containing these metal elements, or an alloy combining these metal elements. In particular, conductive materials that are resistant to oxidation or that maintain conductivity even after absorbing oxygen are preferably used, such as tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel. Furthermore, metal nitride films such as tantalum nitride are preferably used because they have barrier properties against oxygen, hydrogen, and the like.

[0252] 11B and 11C show a structure in which the conductor 542a and the conductor 542b are single layers, but the present invention is not limited to this. For example, the conductor 542a and the conductor 542b may have a stacked structure of two or more layers.

[0253] The conductor 542a and the conductor 542b may be, for example, a structure in which a tantalum nitride film and a tungsten film are stacked, a structure in which a titanium film and an aluminum film are stacked, a structure in which an aluminum film is stacked on a tungsten film, a structure in which a copper film is stacked on a copper-magnesium-aluminum alloy film, a structure in which a copper film is stacked on a titanium film, or a structure in which a copper film is stacked on a tungsten film.

[0254] Alternatively, for example, a three-layer structure may be used in which an aluminum film or copper film is stacked on top of a titanium film or titanium nitride film, and a titanium film or titanium nitride film is further stacked on top of that, or a three-layer structure in which an aluminum film or copper film is stacked on top of a molybdenum film or molybdenum nitride film, and a molybdenum film or molybdenum nitride film is further stacked on top of that.

[0255] Note that the conductor 542a and the conductor 542b may be formed using a transparent conductive material containing, for example, indium oxide, tin oxide, or zinc oxide.

[0256] 11B , in the oxide 530, a region 543a may be formed as a low-resistance region at the interface with the conductor 542a and in its vicinity. In addition, in the oxide 530, a region 543b may be formed as a low-resistance region at the interface with the conductor 542b and in its vicinity. In this case, the region 543a functions as one of a source region and a drain region, and the region 543b functions as the other of the source region and the drain region. A channel formation region is formed in the region sandwiched between the regions 543a and 543b.

[0257] In this way, by providing the conductors 542a and 542b so as to be in contact with the oxide 530, the oxygen concentrations in the regions 543a and 543b may be reduced. Furthermore, a metal compound layer containing the metal contained in the conductors 542a and 542b and components of the oxide 530 may be formed in the regions 543a and 543b. In such a case, the carrier concentrations in the regions 543a and 543b increase, and the regions 543a and 543b become low-resistance regions.

[0258] The insulator 544 is provided to cover the conductors 542 a and 542 b and suppresses oxidation of the conductors 542 a and 542 b. In this case, the insulator 544 may be provided to cover the side surfaces of the oxide 530 and the insulator 524 and to be in contact with the insulator 522.

[0259] For example, a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, magnesium, etc. can be used as the insulator 544. In addition, for example, silicon nitride oxide, silicon nitride, etc. can also be used.

[0260] Alternatively, an insulator containing an oxide of one or both of aluminum and hafnium may be used. For example, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) may be used. In particular, it is preferable to use hafnium aluminate, for example, because it has high heat resistance and is less likely to crystallize during heat treatment in a later step.

[0261] Note that if the conductors 542a and 542b are made of a material that is resistant to oxidation or a material whose conductivity does not decrease significantly even when it absorbs oxygen, the insulator 544 does not necessarily have to be provided.

[0262] The insulator 544 can prevent impurities such as hydrogen and water contained in the insulator 580 from diffusing into the oxide 530b. The insulator 580 can also prevent excess oxygen from being contained in the conductor 542a and the conductor 542b from being oxidized.

[0263] It is preferable to use an insulator that contains excess oxygen and releases oxygen by heating, similar to the above-described insulator 524, as the insulator 545. In this way, oxygen can be effectively supplied from the insulator 545 to the channel formation region of the oxide 530b.

[0264] Specifically, for example, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having vacancies can be used as the insulator 545. In particular, silicon oxide or silicon oxynitride is preferably used in terms of its thermal stability.

[0265] As the insulator 545, an insulator in which the concentrations of impurities such as hydrogen and water are reduced is preferably used, similar to the insulator 524. Note that the thickness of the insulator 545 is preferably 1 nm to 20 nm.

[0266] Here, a metal oxide may be provided between the insulator 545 and the conductor 560 to efficiently supply excess oxygen contained in the insulator 545 to the oxide 530. The metal oxide preferably has a barrier property against oxygen. This suppresses the diffusion of excess oxygen from the insulator 545 to the conductor 560. This suppresses a decrease in the amount of excess oxygen supplied to the oxide 530. Furthermore, it is possible to suppress oxidation of the conductor 560 due to excess oxygen. For example, a material that can be used for the insulator 544 may be used as the metal oxide.

[0267] 11B and 11C illustrate a structure in which the insulator 545 is a single layer, but the present invention is not limited to this. For example, the insulator 545 functioning as the first gate insulating film may have a stacked structure of two or more layers, similar to the insulators 522 and 524 functioning as the second gate insulating films. For example, the insulator 545 may have a stacked structure of a high-k material and a thermally stable material. This allows the gate voltage during operation of the transistor 500 to be reduced while maintaining the physical film thickness of the insulator 545.

[0268] The conductor 560a of the conductor 560 may be, for example, hydrogen, water, nitrogen, or nitrogen oxide (e.g., N ２ O, NO, or NO ２ It is preferable to use a conductive material that has a barrier property against impurities such as copper and the like. It is also preferable to use a conductive material that has a barrier property against oxygen. When the conductor 560a has a barrier property against oxygen, it is possible to prevent the conductor 560b from being oxidized by oxygen contained in the insulator 545, which would reduce the electrical conductivity.

[0269] As the conductive material having a barrier property against oxygen, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used.

[0270] The conductor 560a can be made of an oxide semiconductor that can be used for the oxide 530. In this case, by forming the conductor 560b by a sputtering method, the electrical resistance of the conductor 560a can be reduced, making the conductor 560a a conductor. This can be called an oxide conductor (OC) electrode.

[0271] The conductor 560 can also function as a wiring. Therefore, it is preferable to use a conductive material with high conductivity as the conductor 560b, similar to the conductor 503b. For example, a conductive material containing tungsten, copper, or aluminum as its main component can be used.

[0272] The conductor 560b may be configured by laminating different materials, for example, by laminating titanium or titanium nitride and the above-mentioned conductive material.

[0273] The insulator 580 is provided over the conductor 542a and the conductor 542b with the insulator 544 interposed therebetween.

[0274] The insulator 580 preferably has an excess oxygen region.

[0275] The insulator 580 can be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having voids, or resin. Silicon oxide or silicon oxynitride is particularly preferred because of its thermal stability. Furthermore, silicon oxide or silicon oxide having voids is preferred because it allows for easy formation of an excess oxygen region in a later step.

[0276] By providing the insulator 580 having an excess oxygen region, oxygen is released by heating, and the oxygen in the insulator 580 can be efficiently supplied to the oxide 530. Note that the insulator 580 preferably has a reduced concentration of impurities such as hydrogen and water.

[0277] The insulator 582 is preferably provided in contact with the top surface of the insulator 580, the top surface of the conductor 560, and the top surface of the insulator 545. By forming the insulator 582 by a sputtering method, excess oxygen regions can be provided in the insulator 545 and the insulator 580. This allows oxygen to be supplied from the excess oxygen regions to the oxide 530.

[0278] The insulator 582 can be, for example, a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium.

[0279] In particular, aluminum oxide has a high barrier property against impurities such as hydrogen, and even a thin film with a thickness of 0.5 nm to 3.0 nm can suppress the diffusion of impurities such as hydrogen. Therefore, aluminum oxide formed by sputtering not only functions as an oxygen source but also as an insulator with barrier properties against impurities such as hydrogen.

[0280] An insulator 584 functioning as an interlayer film is preferably provided over the insulator 582. The insulator 584 preferably has a reduced concentration of impurities such as hydrogen and water, similar to the insulator 524, for example.

[0281] The conductor 540a and the conductor 540b are provided in openings formed in the insulator 584, the insulator 582, the insulator 580, and the insulator 544. In this case, the conductor 540a and the conductor 540b are provided opposite each other with the conductor 560 interposed therebetween.

[0282] After the transistor 500 is formed, an opening may be formed to surround the transistor 500, and an insulator with high barrier properties against hydrogen and water may be formed to cover the opening. By surrounding the transistor 500 with the insulator with high barrier properties, hydrogen and water can be prevented from entering from the outside. Alternatively, multiple transistors 500 may be collectively surrounded by an insulator with high barrier properties against hydrogen and water. When forming an opening to surround the transistor 500, for example, an opening reaching the insulator 522 or the insulator 514 may be formed, and the insulator with high barrier properties may be formed in contact with the insulator 522 or the insulator 514. This allows the manufacturing process of the transistor 500 to serve as part of the process. For example, a material similar to the insulator 522 or the insulator 514 may be used as the insulator with high barrier properties against hydrogen and water.

[0283] Note that the transistor 500 illustrated in FIGS. 11A to 11C is just an example and is not limited to this configuration.

[0284] <Structure Example of Memory Device> A memory device that can use the semiconductor device of one embodiment of the present invention will be described. At least a part of the semiconductor device 100, the semiconductor device 110, the semiconductor device 120, or the like described above can be used for the memory device.

[0285] 12 and 13 are block diagrams each illustrating an example of the configuration of the storage device 700. FIG.

[0286] The memory device 700 shown in each of FIGS. 12 and 13 includes a memory array 721 and a drive circuit 722 .

[0287] The memory array 721 includes a plurality of semiconductor devices 100. Each semiconductor device 100 functions as a memory cell. Note that the semiconductor device 100 may be appropriately replaced with the semiconductor device 110, the semiconductor device 120, or the like.

[0288] The plurality of semiconductor devices 100 are arranged in a matrix of M rows and N columns, where M is an integer of 1 or more, and N is an integer of 1 or more.

[0289] In addition, in each of Figures 12 and 13, as representative examples, semiconductor device 100[1,1] arranged in the first row and first column, semiconductor device 100[1,N] arranged in the first row and Nth column, semiconductor device 100[M,1] arranged in the Mth row and first column, and semiconductor device 100[M,N] arranged in the Mth row and Nth column are illustrated.

[0290] Figure 12 also illustrates wiring WWL[1], wiring RWL[1], and wiring BSL[1] electrically connected to N semiconductor devices 100 arranged in the first row, wiring WWL[M], wiring RWL[M], and wiring BSL[M] electrically connected to N semiconductor devices 100 arranged in the Mth row, wiring WBL[1] and wiring RBL[1] electrically connected to M semiconductor devices 100 arranged in the first column, and wiring WBL[N] and wiring RBL[N] electrically connected to M semiconductor devices 100 arranged in the Nth column.

[0291] Figure 13 also illustrates wiring WWL[1] and wiring RWL[1] electrically connected to N semiconductor devices 100 arranged in the first row, wiring WWL[M] and wiring RWL[M] electrically connected to N semiconductor devices 100 arranged in the Mth row, wiring WBL[1], wiring RBL[1], and wiring BSL[1] electrically connected to M semiconductor devices 100 arranged in the first column, and wiring WBL[N], wiring RBL[N], and wiring BSL[N] electrically connected to M semiconductor devices 100 arranged in the Nth column.

[0292] 12 corresponds to the layout example shown in Fig. 8A described above when the semiconductor device 120 is included instead of the semiconductor device 100. Also, the configuration example of the memory array 721 shown in Fig. 13 corresponds to the layout example shown in Fig. 8B described above when the semiconductor device 120 is included instead of the semiconductor device 100.

[0293] The drive circuit 722 includes a power switch 761, a power switch 762, and a peripheral circuit 771. The peripheral circuit 771 includes a peripheral circuit 781, a control circuit 772, and a voltage generation circuit 773.

[0294] In one embodiment of the present invention, for example, a Si transistor can be used as a transistor included in the driver circuit 722. Therefore, for example, a CMOS circuit (e.g., a circuit operating complementarily, a CMOS logic gate, or a CMOS logic circuit) formed by electrically connecting the gate of an n-channel Si transistor and the gate of a p-channel Si transistor can be used as the driver circuit 722.

[0295] Furthermore, for example, by using OS transistors as transistors included in the semiconductor device 100, the memory array 721 can be stacked on the driver circuit 722 that uses Si transistors. This allows the memory device 700 to be miniaturized. Furthermore, the wiring distance between the driver circuit 722 and the memory array 721 can be shortened. This allows the read speed and write speed of the memory device 700 to be improved.

[0296] Furthermore, although not shown, the memory device 700 may have a configuration in which the memory array 721 has a plurality of sense amplifiers arranged in a matrix, and a plurality of semiconductor devices 100 are stacked on the sense amplifiers. With such a configuration, the data stored in the memory array 721 can be read out in a massively parallel manner by simultaneously accessing the plurality of sense amplifiers.

[0297] For example, a signal is supplied to each of the terminal BW, terminal CE, terminal GW, terminal MCK, terminal WAKE, terminal ADDR, terminal WDA, terminal PON1, and terminal PON2 from outside the storage device 700. In addition, for example, a signal is output from the terminal RDA to outside the storage device 700.

[0298] For example, a clock signal is applied to terminal MCK. Furthermore, a control signal is applied to each of terminal BW, terminal CE, and terminal GW. A chip enable signal is applied to terminal CE. A global write enable signal is applied to terminal GW. A byte write enable signal is applied to terminal BW. An address signal is applied to terminal ADDR. Write data is applied to terminal WDA. Read data is applied to terminal RDA. A power gating control signal is applied to terminals PON1 and PON2. The signals applied to terminals PON1 and PON2 may be generated by, for example, control circuit 772.

[0299] The control circuit 772 has a function of controlling the operation of the memory device 700. The control circuit 772 has a function of performing a logical operation on signals provided to the terminals CE, GW, and BW, respectively, to determine an operation mode (e.g., a write operation or a read operation) of the memory device 700. The control circuit 772 also has a function of generating a signal that controls the peripheral circuit 781 so that the operation mode is executed.

[0300] The voltage generation circuit 773 has a function of generating an arbitrary potential for operating the driver circuit 722. For example, the voltage generation circuit 773 has a function of generating an arbitrary potential by inputting a clock signal provided to a terminal MCK in accordance with a signal provided to a terminal WAKE. For example, a signal that controls whether or not the clock signal provided to the terminal MCK is input to the voltage generation circuit 773 is provided to the terminal WAKE.

[0301] The peripheral circuit 781 has a function of writing and reading data to and from the semiconductor device 100. The peripheral circuit 781 has a function of generating various signals for controlling the operation of the semiconductor device 100, etc. The peripheral circuit 781 has a row decoder 782, a column decoder 784, a row driver 783, a column driver 785, a data driver 786, an input circuit 787, and an output circuit 788.

[0302] The row decoder 782 and the column decoder 784 have the function of decoding an address signal applied to the terminal ADDR. The row decoder 782 has the function of specifying a row to be accessed. The column decoder 784 has the function of specifying a column to be accessed. The row driver 783 has the function of selecting a row specified by the row decoder 782 and providing a desired signal to, for example, the corresponding semiconductor device 100. The column driver 785 has the function of selecting a column specified by the column decoder 784 and providing a desired signal to, for example, the corresponding semiconductor device 100.

[0303] The data driver 786 has a function of writing and reading data to and from the semiconductor device 100 selected by the row driver and the column driver. The input circuit 787 has a function of holding data provided to a terminal WDA from outside the memory device 700. The data (data Din) held in the input circuit 787 is written to the semiconductor device 100 via the data driver 786. The data stored in the semiconductor device 100 is read out to an output circuit 788 via the data driver 786. The output circuit 788 has a function of holding the read data (data Dout). It also has a function of outputting the held data from a terminal RDA to outside the memory device 700.

[0304] In the memory device 700 shown in FIG. 12, the row driver 783 has a function of applying a desired signal to the wirings WWL[1] to WWL[M] and the wirings RWL[1] to RWL[M] and a function of applying a desired potential to the wirings BSL[1] to BSL[M], and the column driver 785 and the data driver 786 have a function of exchanging data with the wirings WBL[1] to WBL[N] and the wirings RBL[1] to RBL[N].

[0305] In addition, in the memory device 700 shown in Figure 13, the row driver 783 has the function of applying desired signals to the wirings WWL[1] to WWL[M] and the wirings RWL[1] to RWL[M], and the column driver 785 and the data driver 786 have the function of exchanging data with the wirings WBL[1] to WBL[N] and the wirings RBL[1] to RBL[N] and the function of applying desired potentials to the wirings BSL[1] to BSL[M].

[0306] The power switch 761 has a function of controlling whether or not the potential applied to the terminal VMD is supplied to the peripheral circuit 771. The power switch 762 has a function of controlling whether or not the potential applied to the terminal VMH is supplied to the row driver 783. Here, for example, a high power supply potential (e.g., potential VDD) for operating the drive circuit 722 is applied to the terminal VMD, and a low power supply potential (e.g., potential VSS) is applied to the terminal VMS. Also, for example, a high power supply potential (e.g., a potential higher than potential VDD) for operating the semiconductor device 100 or the like is applied to the terminal VMH. The power switch 761 is controlled to a conductive state or a non-conductive state by a signal applied to the terminal PON1. The power switch 762 is controlled to a conductive state or a non-conductive state by a signal applied to the terminal PON2.

[0307] Note that the circuits and terminals of the driver circuit 722 may be omitted as appropriate. Other circuits and terminals may be added as appropriate.

[0308] 14A is a block diagram illustrating a configuration example of a memory device 740 according to one embodiment of the present invention. The memory device 740 includes a memory array 741 (MEM array), a sense amplifier array 742 (SA array), a write word line driver 743 (WWL driver), a read word line driver 744 (RWL driver), a sense amplifier driver 745 (SA driver), an input / output interface 746 (W / R IF), and a controller 747.

[0309] For example, a memory array 741 having a plurality of memory cells is stacked on a sense amplifier array 742 having a plurality of sense amplifiers. The memory cells correspond to the semiconductor device 100 described above, etc. The sense amplifiers have the function of reading and writing data from and to the memory cells. The sense amplifiers are electrically connected, for example, to the wirings WBL and RBL in the semiconductor device 100 functioning as memory cells. The write word line driver 743 and the read word line driver 744 correspond, for example, to the row decoder 782 and row driver 783 described above, etc. The write word line driver 743 is electrically connected, for example, to the wirings WWL in the semiconductor device 100 functioning as memory cells, and the read word line driver 744 is electrically connected, for example, to the wirings RWL in the semiconductor device 100 functioning as memory cells. The sense amplifier driver 745 corresponds to the column decoder 784, the column driver 785, and the data driver 786 described above, the input / output interface 746 corresponds to the input circuit 787 and the output circuit 788 described above, and the controller 747 corresponds to the control circuit 772 and the voltage generating circuit 773 described above. The controller 747 may have a function of generating a potential to be applied to the wiring BSL in the semiconductor device 100 having a function as a memory cell, for example.

[0310] FIG. 14B is a circuit diagram illustrating an example of the configuration of a sense circuit 750 that can be applied to the sense amplifiers included in the sense amplifier array 742.

[0311] The sense circuit 750 includes an amplifier circuit 751, a precharge circuit 752, a precharge circuit 753, and a switch circuit 754. The amplifier circuit 751, the precharge circuit 752, the precharge circuit 753, and the switch circuit 754 are electrically connected to the wirings GBL and GBLB, respectively. The switch circuit 754 is electrically connected to the wirings DBL and DBLB.

[0312] The sense circuit 750 has a function of reading and writing data from and to the memory cells of the memory array 741 .

[0313] The amplifier circuit 751 has a function of applying a predetermined potential to each of the wirings SAP and SAN, thereby outputting a potential corresponding to one of the binary data to the wiring GBL and outputting a potential corresponding to the other of the binary data to the wiring GBLB.

[0314] Specifically, the amplifier circuit 751 includes a transistor M751a, a transistor M751b, a transistor M751c, and a transistor M751d. One of the source and the drain of the transistor M751a is electrically connected to the wiring GBL. One of the source and the drain of the transistor M751b is electrically connected to the wiring GBL. One of the source and the drain of the transistor M751c is electrically connected to the wiring GBLB. One of the source and the drain of the transistor M751d is electrically connected to the wiring GBLB. The other of the source and the drain of the transistor M751a and the other of the source and the drain of the transistor M751c are electrically connected to the wiring SAN. The other of the source and the drain of the transistor M751b and the other of the source and the drain of the transistor M751d are electrically connected to the wiring SAP. The gates of the transistors M751a and M751b are electrically connected to the wiring GBLB. The gates of the transistors M751c and M751d are electrically connected to the wiring GBL. The transistors M751a and M751c are n-channel transistors. The transistors M751b and M751d are p-channel transistors. In other words, the amplifier circuit 751 can be said to have an inverter loop formed by an inverter of the transistors M751a and M751b and an inverter of the transistors M751c and M751d.

[0315] The precharge circuit 752 has a function of precharging the wiring GBL and the wiring GBLB to a potential applied to the wiring VPRE in response to a signal applied to the wiring EQB.

[0316] Specifically, the precharge circuit 752 includes a transistor M752a, a transistor M752b, and a transistor M752c. One of the source and the drain of the transistor M752a is electrically connected to the wiring GBL. One of the source and the drain of the transistor M752b is electrically connected to the wiring GBLB. The other of the source and the drain of the transistor M752a and the other of the source and the drain of the transistor M752b are electrically connected to the wiring VPRE. One of the source and the drain of the transistor M752c is electrically connected to the wiring GBL. The other of the source and the drain of the transistor M752c is electrically connected to the wiring GBLB. The gates of the transistors M752a, M752b, and M752c are electrically connected to the wiring EQB. The transistors M752a, M752b, and M752c are p-channel transistors.

[0317] The precharge circuit 753 has a function of precharging the wiring GBL and the wiring GBLB to a potential applied to the wiring VPRE in response to a signal applied to the wiring EQ.

[0318] Specifically, the precharge circuit 753 includes a transistor M753a, a transistor M753b, and a transistor M753c. One of the source and the drain of the transistor M753a is electrically connected to the wiring GBL. One of the source and the drain of the transistor M753b is electrically connected to the wiring GBLB. The other of the source and the drain of the transistor M753a and the other of the source and the drain of the transistor M753b are electrically connected to the wiring VPRE. One of the source and the drain of the transistor M753c is electrically connected to the wiring GBL. The other of the source and the drain of the transistor M753c is electrically connected to the wiring GBLB. The gates of the transistors M753a, M753b, and M753c are electrically connected to the wiring EQ. The transistors M753a, M753b, and M753c are n-channel transistors.

[0319] The switch circuit 754 has a function of bringing the pair of wirings GBL and GBLB and the pair of wirings DBL and DBLB into a conductive state or a non-conductive state in response to a signal applied to the wiring CSEL.

[0320] Specifically, the switch circuit 754 includes a transistor M754a and a transistor M754b. One of the source and the drain of the transistor M754a is electrically connected to the wiring GBL. The other of the source and the drain of the transistor M754a is electrically connected to the wiring DBL. One of the source and the drain of the transistor M754b is electrically connected to the wiring GBLB. The other of the source and the drain of the transistor M754b is electrically connected to the wiring DBLB. The gates of the transistors M754a and M754b are electrically connected to the wiring CSEL. The transistors M754a and M754b are n-channel transistors.

[0321] Here, the wiring GBL is electrically connected to, for example, the wiring WBL and the wiring RBL in the semiconductor device 100 that functions as a memory cell. At this time, a switch circuit may be provided between the wiring GBL and the wiring WBL and the wiring RBL so that a potential is applied from the wiring GBL to the wiring WBL when writing data and a potential is applied from the wiring RBL to the wiring GBL when reading data. The same applies to the wiring GBLB.

[0322] The wirings SAP, SAN, VPRE, EQ, EQB, and CSEL are electrically connected to the sense amplifier driver 745. The wirings DBL and DBLB are electrically connected to the input / output interface 746.

[0323] Stacked Structure Example 1 FIG. 15 is a cross-sectional view illustrating a configuration example of a memory device 700 in which a memory array 721 using OS transistors is stacked over a driver circuit 722 using Si transistors.

[0324] 15 illustrates a transistor 550 provided over a substrate 311 and a semiconductor device 120 including a transistor 600a, a transistor 600b, and a transistor 600c provided over the transistor 550. Note that the cross-sectional view in the channel length direction (illustrated as the X direction) of the transistor 550 is illustrated here. Five semiconductor devices 120 are illustrated as an example. Each semiconductor device 120 functions as a memory cell.

[0325] As shown in Figure 15, the transistor 550 is provided over a substrate 311 and has a conductor 316 that functions as a gate electrode, an insulator 315 that functions as a gate insulating film, a semiconductor region 313 that functions as a channel formation region, a low-resistance region 314a that functions as one of the source region and the drain region, and a low-resistance region 314b that functions as the other of the source region and the drain region.

[0326] Note that the transistor 550 may be either a p-channel type or an n-channel type. For example, by electrically connecting the gate of the n-channel transistor 550 and the gate of the p-channel transistor 550, a CMOS circuit (e.g., a circuit that operates complementarily, a CMOS logic gate, or a CMOS logic circuit) can be configured.

[0327] Note that the transistor 550 can have a so-called Fin structure in which, for example, the top surface and the side surfaces in the channel width direction of a semiconductor region 313 made of a part of the substrate 311 are covered with a conductor 316 via an insulator 315. This increases the effective channel width, thereby improving the on-state characteristics of the transistor 550. Furthermore, the contribution of the electric field of the gate electrode can be increased, thereby improving the off-state characteristics of the transistor 550.

[0328] The transistor 550 preferably includes a semiconductor such as a silicon-based semiconductor, and preferably includes single crystal silicon, in the region where the channel of the semiconductor region 313 is formed, the region nearby the region, the low-resistance region 314a that serves as one of the source and drain regions, and the low-resistance region 314b that serves as the other of the source and drain regions. Alternatively, the transistor 550 may be formed of a material containing, for example, germanium, silicon germanium, gallium arsenide, or gallium aluminum arsenide. Alternatively, the transistor 550 may be configured using silicon whose effective mass is controlled by applying stress to the crystal lattice to change the lattice spacing. Alternatively, the transistor 550 may be a high electron mobility transistor (HEMT) using, for example, gallium arsenide, gallium aluminum arsenide, or the like.

[0329] The low resistance region 314a and the low resistance region 314b contain, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0330] For example, a semiconductor material such as silicon containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron, can be used as the conductor 316. Alternatively, for example, a conductive material such as a metal material, an alloy material, or a metal oxide material can be used.

[0331] Note that the work function is determined by the material of a conductor; therefore, the threshold voltage of a transistor can be adjusted by selecting the material of the conductor.

[0332] It is preferable to use a material such as titanium nitride or tantalum nitride as the conductor 316. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum in a laminated state. In particular, in terms of heat resistance, it is preferable to use a tungsten in a laminated state.

[0333] An insulator 320 , an insulator 322 , an insulator 324 , and an insulator 326 are stacked in this order to cover the transistor 550 .

[0334] It is preferable to use, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, or aluminum nitride as the insulators 320, 322, 324, and 326. In particular, it is preferable to use silicon oxide or silicon oxynitride because of their thermal stability.

[0335] In this specification, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen, aluminum oxynitride refers to a material whose composition contains more oxygen than nitrogen, and aluminum nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0336] The insulator 322 may function as a planarizing film that planarizes steps caused by the transistor 550 or the like provided thereunder. For example, the top surface of the insulator 322 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to improve the planarity.

[0337] As the insulator 324, it is preferable to use an insulator having barrier properties that prevent impurities such as hydrogen from diffusing from the substrate 311 or the transistor 550 to the region where the transistor 600 (transistor 600a, transistor 600b, and transistor 600c) is provided.

[0338] As an insulator having a barrier property against hydrogen, for example, silicon nitride formed by a CVD method can be used. Alternatively, for example, a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide can be used.

[0339] Here, when hydrogen diffuses into a semiconductor element including an oxide semiconductor, such as the transistor 600, the characteristics of the semiconductor element may deteriorate. Therefore, an insulator that suppresses hydrogen diffusion is preferably used between the transistor 600 and the transistor 550. Specifically, the insulator that suppresses hydrogen diffusion is an insulator that releases a small amount of hydrogen.

[0340] The insulator 326 preferably has a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. Furthermore, for example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced.

[0341] Conductors (such as conductors 328 and 330) are embedded in insulators 320, 322, 324, and 326.

[0342] The conductor 328 and the conductor 330 function as plugs or wiring.

[0343] In this specification and the like, a conductor that functions as a plug or wiring may have multiple components collectively assigned the same reference symbol. The wiring and the plug may be integrated. That is, a portion of the conductor may function as a wiring and a portion of the conductor may function as a plug.

[0344] Each plug or wiring (e.g., conductor 328 and conductor 330) can be made of a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material, in a single layer or in a stacked layer.

[0345] In particular, it is preferable to use a high-melting-point material that has both heat resistance and conductivity for each plug or wiring. Examples of such materials include tungsten and molybdenum. It is also preferable to use a low-resistance conductive material that can reduce wiring resistance for each plug or wiring. Examples of such materials include aluminum and copper.

[0346] A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in Fig. 15, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. Furthermore, a conductor 356 is embedded in the insulator 350, the insulator 352, and the insulator 354.

[0347] The conductor 356 functions as a plug or a wiring. For example, the same material as the conductors 328 and 330 can be used as the conductor 356. In particular, it is preferable to use a conductor that has a barrier property against hydrogen.

[0348] The insulators 350, 352, and 354 can be formed using materials similar to those of the insulators 324, 322, and 326. In particular, it is preferable to use an insulator that has a barrier property against hydrogen.

[0349] Here, a conductor having a barrier property against hydrogen is formed in the opening of the insulator 350 having a barrier property against hydrogen. With this structure, the transistor 550 and the transistor 600 can be separated by the conductor having a barrier property against hydrogen. Therefore, diffusion of hydrogen from the transistor 550 to the transistor 600 can be suppressed.

[0350] For example, tantalum nitride may be used as a conductor having a barrier property against hydrogen. Alternatively, a stack of tantalum nitride and highly conductive tungsten may be used. By using a stack of tantalum nitride and tungsten as the conductor, the conductor can suppress the diffusion of hydrogen while maintaining the conductivity of the wiring.

[0351] That is, by forming the conductor 356 as a stack of tantalum nitride and tungsten, it is possible to suppress diffusion of hydrogen from the transistor 550 while maintaining the conductivity of the wiring. In this case, it is preferable that the tantalum nitride layer of the conductor 356 having a barrier property against hydrogen be in contact with the insulator 350 having a barrier property against hydrogen.

[0352] Although not shown, the transistor 550 is electrically connected to the transistor 600 via the conductor 328, the conductor 330, the conductor 356, and the like.

[0353] Although the wiring layer including the conductor 356 has been described here, the present invention is not limited to this. The wiring layer including the conductor 356 may not be provided, or two or more wiring layers similar to the wiring layer including the conductor 356 may be provided.

[0354] Note that the transistor 550 shown in FIG. 15 is just an example and is not limited to this configuration.

[0355] [Substrate] Examples of substrates that can be used for providing the semiconductor device of one embodiment of the present invention, the memory device including the semiconductor device, and the like include a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, a metal substrate (e.g., a stainless steel substrate, a substrate including stainless steel foil, a tungsten substrate, or a substrate including tungsten foil), a semiconductor substrate (e.g., a single-crystal semiconductor substrate, a polycrystalline semiconductor substrate, or a compound semiconductor substrate), or an SOI (Silicon on Insulator) substrate. A heat-resistant plastic substrate may also be used as the substrate. Examples of glass substrates include barium borosilicate glass, aluminosilicate glass, aluminoborosilicate glass, and soda-lime glass. Alternatively, for example, crystallized glass can be used as the glass substrate.

[0356] In addition, the substrate can be, for example, a flexible substrate, a laminated film, paper containing a fibrous material, or a base film. Examples of flexible substrates, laminated films, or base films include plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), or polytetrafluoroethylene (PTFE). Other examples include synthetic resins such as acrylic. Other examples include polypropylene, polyester, polyvinyl fluoride, or polyvinyl chloride. Other examples include polyamide, polyimide, aramid resin, epoxy resin, inorganic vapor deposition film, or paper. In particular, by manufacturing transistors using, for example, a semiconductor substrate, a single-crystal substrate, or an SOI substrate, it is possible to manufacture transistors with small size, high current capacity, and little variation in characteristics, size, or shape. Constructing a circuit using such transistors can reduce the power consumption of the circuit or increase the circuit integration.

[0357] Alternatively, a flexible substrate may be used as the substrate, and one or more of, for example, a transistor, a resistor, and a capacitor may be formed directly on the flexible substrate. Alternatively, a release layer may be provided between the substrate and one or more of, for example, a transistor, a resistor, and a capacitor. The release layer can be used to separate a semiconductor device, after a part or all of the semiconductor device is completed thereon, from the substrate and transfer the device to another substrate. In this case, for example, one or more of the transistor, the resistor, and the capacitor can be transferred to a substrate with poor heat resistance or a flexible substrate. Note that the release layer may be, for example, a laminated structure of an inorganic film of a tungsten film and a silicon oxide film, a structure in which an organic resin film such as polyimide is formed on a substrate, or a silicon film containing hydrogen.

[0358] That is, a semiconductor device may be formed on a certain substrate and then transferred to another substrate. Examples of substrates onto which a semiconductor device may be transferred include, in addition to the substrates on which the above-described transistors can be formed, paper substrates, cellophane substrates, aramid film substrates, polyimide film substrates, stone substrates, wood substrates, cloth substrates (including, for example, natural fibers (silk, cotton, or hemp), synthetic fibers (nylon, polyurethane, or polyester), or recycled fibers (acetate, cupra, rayon, or recycled polyester)), leather substrates, and rubber substrates. By using these substrates, it is possible to manufacture a flexible semiconductor device or a semiconductor device that is not easily broken. It is also possible to impart heat resistance to the semiconductor device. It is also possible to reduce the weight or thickness of the semiconductor device.

[0359] By providing a semiconductor device over a flexible substrate, an increase in weight can be suppressed and a semiconductor device that is less likely to be damaged can be provided.

[0360] Stacked Structure Example 2 FIG. 16 is a cross-sectional view illustrating a configuration example in which semiconductor devices 120 functioning as memory cells are stacked in a memory array 721 of a memory device 700. In FIG.

[0361] 16 illustrates a semiconductor device 120_1 and a semiconductor device 120_2 provided on the semiconductor device 120_1. Note that, although an example in which two semiconductor devices 120 are stacked is shown here, three or more semiconductor devices 120 may be stacked.

[0362] In this way, by stacking the semiconductor devices 120 each having a function as a memory cell, it is possible to improve the recording density of the memory device.

[0363] Note that the semiconductor device according to one embodiment of the present invention is not limited to the semiconductor device described in this embodiment. At least part of the configuration examples, operation examples, and corresponding drawings described in this embodiment can be appropriately combined with other configuration examples, operation examples, drawings, and embodiments described in this specification.

[0364] In this embodiment, a transistor including an oxide semiconductor in a channel formation region (OS transistor) will be described. Note that the description of the OS transistor will be briefly compared with a transistor including silicon in a channel formation region (also referred to as a Si transistor).

[0365] [OS Transistor] An OS transistor is preferably formed using an oxide semiconductor with a low carrier concentration. For example, the carrier concentration of a channel formation region of an oxide semiconductor is preferably 1×10 １８ cm −３ Below 1 × 10, preferably １７ cm −３ less than 1×10 １６ cm −３ less than 1×10 １３ cm −３ less than 1×10 １０ cm −３ is less than 1×10 −９ cm −３That is all. Note that when the carrier concentration in an oxide semiconductor is reduced, the density of defect states in the oxide semiconductor may be reduced by reducing the impurity concentration in the oxide semiconductor. In this specification and the like, an oxide semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may also be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0366] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor may have a low density of trap states due to a low density of defect states. Furthermore, charges trapped in the trap states of the oxide semiconductor take a long time to disappear and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0367] Therefore, reducing the impurity concentration in the oxide semiconductor is effective for stabilizing the electrical characteristics of a transistor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen and nitrogen. Note that the impurity in the oxide semiconductor refers to, for example, any element other than the main component constituting the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0368] Furthermore, when impurities or oxygen vacancies exist in a channel formation region of an oxide semiconductor, the electrical characteristics of an OS transistor are likely to fluctuate, and reliability may be reduced. Ｏ H) in the channel formation region, generating electrons that serve as carriers. ＯWhen H is formed, the donor concentration in the channel formation region may increase. As a result, the threshold voltage of an OS transistor may vary as the donor concentration in the channel formation region increases. Therefore, if an OS transistor has oxygen vacancies in the channel formation region of an oxide semiconductor, the OS transistor is likely to have normally-on characteristics (a drain current flows when the gate voltage is 0 V). Therefore, in the channel formation region of an oxide semiconductor, impurities, oxygen vacancies, and V Ｏ It is preferable that H is reduced as much as possible.

[0369] The band gap of the oxide semiconductor is preferably larger than that of silicon (typically 1.1 eV), preferably 2 eV or more, more preferably 2.5 eV or more, and further preferably 3.0 eV or more. By using an oxide semiconductor having a band gap larger than that of silicon, the off-state current (also referred to as Ioff) of the transistor can be reduced.

[0370] Furthermore, in Si transistors, a short channel effect (SCE) occurs as the transistors are miniaturized. This makes miniaturization of Si transistors difficult. One of the factors that causes the short channel effect is the small band gap of silicon. On the other hand, an OS transistor uses an oxide semiconductor, which is a semiconductor material with a wide band gap, and therefore the short channel effect can be suppressed. In other words, an OS transistor is a transistor that does not have the short channel effect or has an extremely small short channel effect.

[0371] The short-channel effect is a deterioration in electrical characteristics that becomes apparent as transistors are miniaturized (channel lengths are reduced). Specific examples of the short-channel effect include a decrease in threshold voltage, an increase in subthreshold swing (sometimes referred to as S value), and an increase in leakage current. Here, the S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude while the drain voltage is kept constant in the subthreshold region.

[0372] Furthermore, the characteristic length is widely used as an index of resistance to the short channel effect. The characteristic length is an index of how easily the potential in the channel formation region bends. The smaller the characteristic length, the steeper the potential rises, and therefore the more resistant it is to the short channel effect.

[0373] An OS transistor is an accumulation-mode transistor, while a Si transistor is an inversion-mode transistor. Therefore, compared with a Si transistor, an OS transistor has a smaller characteristic length between a source region and a channel formation region and a smaller characteristic length between a drain region and a channel formation region. Therefore, an OS transistor is more resistant to the short-channel effect than a Si transistor. That is, when a transistor with a short channel length is to be manufactured, an OS transistor is more suitable than a Si transistor.

[0374] Even when the carrier concentration of the oxide semiconductor is reduced to the point where the channel formation region becomes i-type or substantially i-type, the conduction band minimum of the channel formation region in a short-channel transistor is lowered due to the conduction-band-lowering (CBL) effect, and therefore the energy difference between the conduction band minimums of the source or drain region and the channel formation region can be reduced to 0.1 eV or more and 0.2 eV or less. − The source and drain regions are n-type regions. ＋ The region of type n ＋ / n − / n ＋ an accumulation-type junction-less transistor structure, or ＋ / n − / n ＋ It can also be regarded as an accumulation type non-junction transistor structure.

[0375] The above structure enables an OS transistor to have good electrical characteristics even when miniaturized or highly integrated. For example, an OS transistor can have good electrical characteristics even when the gate length is 20 nm or less, 15 nm or less, 10 nm or less, 7 nm or less, or 6 nm or less and 1 nm or more, 3 nm or more, or 5 nm or more. On the other hand, a Si transistor may have difficulty achieving a gate length of 20 nm or less or 15 nm or less due to the short-channel effect. Therefore, an OS transistor can be used as a transistor with a shorter channel length than a Si transistor. Note that the gate length refers to the length of a gate electrode in a direction in which carriers move inside a channel formation region during transistor operation and refers to the width of the bottom surface of the gate electrode in a top view of the transistor.

[0376] Furthermore, miniaturization of an OS transistor can improve the high-frequency characteristics of the transistor. Specifically, the cutoff frequency of the transistor can be improved. When the gate length of an OS transistor is within the above range, the cutoff frequency of the transistor can be set to, for example, 50 GHz or higher, preferably 100 GHz or higher, and further preferably 150 GHz or higher at room temperature.

[0377] As described above, an OS transistor has excellent advantages over a Si transistor in that it has a smaller off-state current and can be manufactured as a transistor with a short channel length.

[0378] The configuration, structure, method, or the like described in this embodiment can be used in appropriate combination with the configuration, structure, method, or the like described in other embodiments.

[0379] Embodiment 3 In this embodiment, an application example of a memory device according to one embodiment of the present invention will be described.

[0380] <Example of Hierarchical Structure of Storage Devices> Generally, computers and the like use various storage devices depending on the application. FIG. 17 shows various storage devices by hierarchy. The higher the storage device, the faster the operating speed is required, while the lower the storage device, the larger the storage capacity and recording density are required. FIG. 17 shows, from the top layer to the bottom, a register, a cache memory, a main memory, and storage. The cache memory may also include, from top to bottom, a primary cache (L1), a secondary cache (L2), and a tertiary cache (L3). While an example having up to a tertiary cache is shown here, a lower-level cache memory may also be included. The lowest-level cache memory may also be called an LLC (Last Level Cache) or an FLC (Final Level Cache). For example, a storage class memory may be included between the main memory and the storage.

[0381] Registers integrated into arithmetic processing units (also called processors) such as CPUs (Central Processing Units) and GPUs (Graphics Processing Units) are used to temporarily store the results of calculations performed by cores. They also have the function of storing setting information for the arithmetic processing units. As a result, they are frequently accessed by the arithmetic processing units. Therefore, registers are required to operate at high speeds.

[0382] For example, a static random access memory (SRAM) is used as the cache memory. The cache memory has the function of duplicating and storing a portion of the data stored in the main memory. By storing a copy of frequently used data, the speed of accessing the data can be increased. The cache memory is required to have a faster operating speed than the main memory.

[0383] The main memory may be, for example, a dynamic random access memory (DRAM). The main memory has a function of storing programs and data read from storage. The main memory is required to have a larger storage capacity and a higher recording density than cache memory.

[0384] Storage has the function of storing data that requires long-term storage and various programs used by processing units. Therefore, storage requires large storage capacity and high recording density. For example, a hard disk drive (HDD) or a solid state drive (SSD) located on top of an HDD can be used as the storage. For example, a large-capacity, non-volatile storage device such as a NAND flash memory (e.g., 3D NAND) can be used as the SSD.

[0385] The storage device according to one aspect of the present invention is excellent in that it has a high operating speed, is capable of retaining data for a long period of time, has high rewrite endurance, and is capable of low-voltage operation. The storage device according to one aspect of the present invention is suitable as a storage device located in an area (OSmem) that includes a hierarchy where a cache memory is located, a hierarchy where a main memory is located, and a hierarchy where a storage is located.

[0386] That is, for example, it is preferable to replace a DRAM used in a main memory with a storage device according to one embodiment of the present invention. Here, since DRAM requires a refresh operation and is a destructive readout storage device, it consumes more power than other storage devices. Therefore, by not using DRAM, it is possible to reduce power consumption. It is also preferable to replace, for example, a portion of an SRAM used in a cache memory and a portion of a 3D NAND used in storage with a storage device according to one embodiment of the present invention.

[0387] One embodiment of the present invention can be configured without using a DRAM, which has conventionally been used as a main memory or the like. In this case, a storage device according to one embodiment of the present invention can be used in place of the DRAM. With such a configuration, power consumption can be dramatically reduced (for example, by one hundredth or one thousandth or less). Therefore, by deploying information processing devices including computers, servers, and the like having such a configuration throughout the world, global warming can be suppressed.

[0388] <Configuration Example of Memory Cell> A memory device according to one embodiment of the present invention is a memory device (also referred to as an OS memory) using an oxide semiconductor. The memory device includes a memory cell using an OS transistor. In addition to the semiconductor device 100 described in Embodiment 1, the memory cell can also have the following structure.

[0389] The memory cell 950a shown in FIG. 18A includes a transistor M911 and a capacitor C911. One of the source and the drain of the transistor M911 is electrically connected to one terminal of the capacitor C911. The other of the source and the drain of the transistor M911 is electrically connected to a wiring BL that functions as a bit line. The gate of the transistor M911 is electrically connected to a wiring WL that functions as a word line. The other terminal of the capacitor C911 is electrically connected to a wiring CL. Note that the wiring that electrically connects the one of the source and the drain of the transistor M911 and one terminal of the capacitor C911 may be referred to as a wiring MN in the following description.

[0390] The memory cell 950a can store binary data by associating the amount of charge stored in the capacitor C911, i.e., the amount of charge held in the wiring MN, with "1" or "0." Note that, for example, ternary or more levels of data may be stored. Furthermore, when writing data, the memory cell 950a controls the conduction state of the transistor M911 to apply a potential corresponding to the data from the wiring BL to the wiring MN, thereby holding a charge corresponding to the potential. Furthermore, when reading data, the memory cell 950a controls the conduction state of the transistor M911 to extract the charge held in the wiring MN to the wiring BL.

[0391] Note that when data is read from the memory cell 950a, the charge held in the wiring MN is extracted to the wiring BL, and the potential of the wiring MN changes. That is, when data is read from the memory cell 950a, the stored data is destroyed. That is, when data is read from the memory cell 950a, destructive reading occurs. Therefore, after data is read from the memory cell 950a, data needs to be written back (refreshed).

[0392] In one embodiment of the present invention, for example, an n-channel OS transistor can be used as the transistor M911.

[0393] Note that the memory cell 950a shown in FIG. 18A is a dynamic random access memory (DRAM) memory cell. In particular, a structure using an OS transistor as the transistor M911 may be referred to as a DOSRAM (registered trademark). Since the DOSRAM uses an OS transistor with extremely low off-state current, it can store data for a long period of time. Furthermore, it can store multilevel data or analog data. Furthermore, since once-written data can be stored for a long period of time, the frequency of data refresh can be reduced. Furthermore, since the electrostatic capacitance of the cell capacitance (capacitance C911) can be reduced, the cell size can be reduced. Therefore, by using a DOSRAM, it is possible to reduce the power consumption and improve the recording density of a semiconductor device or a memory device.

[0394] The memory cell 950b shown in FIG. 18B is a modification of the memory cell 950a shown in FIG. 18A, and differs in that it does not have the capacitance C911.

[0395] 18B, charge can be stored in the parasitic capacitance (the capacitance between the gate and either the source or the drain of the transistor M911) indicated by the dashed line, etc. By adopting such a configuration, for example, the cell size can be reduced, and the recording density of the semiconductor device and the memory device can be improved.

[0396] The memory cell 950c shown in FIG. 18C includes a transistor M921, a transistor M922, and a capacitor C921. One of the source and drain of the transistor M921 is electrically connected to the gate of the transistor M922 and one terminal of the capacitor C921. The other of the source and drain of the transistor M921 is electrically connected to a wiring WBL that functions as a write bit line. The gate of the transistor M921 is electrically connected to a wiring WWL that functions as a write word line. One of the source and drain of the transistor M922 is electrically connected to a wiring RBL that functions as a read bit line. The other of the source and drain of the transistor M922 is electrically connected to a wiring PL. The other terminal of the capacitor C921 is electrically connected to a wiring RWL that functions as a read word line. Note that a wiring that electrically connects one of the source and the drain of the transistor M921, the gate of the transistor M922, and one terminal of the capacitor C921 to each other may be referred to as a wiring MN.

[0397] The memory cell 950c can store binary data by associating the amount of charge stored in the capacitor C921, i.e., the amount of charge held in the wiring MN, with "1" or "0." Note that, for example, ternary or more levels of data may be stored. Furthermore, when writing data, the memory cell 950c controls the conduction state of the transistor M921 to apply a potential corresponding to the data from the wiring WBL to the wiring MN, thereby holding a charge corresponding to the potential. Furthermore, when reading data, the memory cell 950c can output a potential corresponding to the data to the wiring RBL by turning the transistor M922 on or off depending on the potential of the wiring MN.

[0398] In one embodiment of the present invention, for example, an n-channel OS transistor can be used as the transistor M921, and for example, an n-channel transistor (such as an OS transistor or a Si transistor) can be used as the transistor M922.

[0399] The memory cell 950c shown in FIG. 18C is a gain cell type memory cell. In particular, a configuration using an OS transistor as the transistor M921 may be referred to as NOSRAM (registered trademark). NOSRAM can store data for a long period of time because it uses an OS transistor with extremely low off-state current. It can also store multilevel data or analog data. Furthermore, because the writing transistor (transistor M921) and the reading transistor (transistor M922) are different, data reading is nondestructive. Therefore, it can be used, for example, as a nonvolatile memory.

[0400] 18D is a modification of the memory cell 950c shown in FIG. 18C, and differs in that it does not have a capacitor C921. Also, it differs in that the other of the source and the drain of the transistor M922 is electrically connected to the wiring RWL.

[0401] 18D, charge can be stored in a parasitic capacitance added to the wiring MN. By adopting such a configuration, for example, the cell size can be reduced, and the recording density of the semiconductor device and the memory device can be improved.

[0402] The memory cell 950e shown in Figure 18E is a modified example of the memory cell 950c shown in Figure 18C, and differs in that the other of the source and the drain of the transistor M921 is electrically connected to the wiring BL, and one of the source and the drain of the transistor M922 is electrically connected to the wiring BL.

[0403] 18E, the wiring BL can function as both a write bit line and a read bit line. With this configuration, for example, the cell size can be reduced, and the storage density of the semiconductor device and the memory device can be improved.

[0404] 18F is a modification of the memory cell 950c shown in Fig. 18C, and differs in that it has a transistor M922p instead of the transistor M922. The transistor M922p can be, for example, a p-channel Si transistor.

[0405] 18F uses a p-channel transistor to read data, which may simplify the configuration and operation of the sense amplifier, etc. By using such a configuration, for example, the layout area of ​​the driver circuit can be reduced, thereby enabling miniaturization of the semiconductor device and memory device.

[0406] 18B , and further includes a transistor M923. One of the source and the drain of the transistor M922 is electrically connected to one of the source and the drain of the transistor M923, the other of the source and the drain of the transistor M922 is electrically connected to a wiring PL, the other of the source and the drain of the transistor M923 is electrically connected to a wiring RBL, and the gate of the transistor M923 is electrically connected to a wiring RWL. The transistor M923 can be, for example, an n-channel transistor (e.g., an OS transistor or a Si transistor).

[0407] 18G, the parasitic capacitance between the wiring MN and the wiring RBL can be reduced. With such a configuration, for example, it is possible to suppress the introduction of noise into the wiring MN via the gate capacitance of the transistor M922, thereby improving the reliability of the semiconductor device and the memory device.

[0408] 18H includes transistors M931, M932, M933, M934, capacitors C931, C932, inverters X931, and X932. One of the source or drain of transistor M931 is electrically connected to one of the source or drain of transistor M933, the input terminal of inverter X931, and the output terminal of inverter X932. One of the source or drain of transistor M932 is electrically connected to one of the source or drain of transistor M934, the output terminal of inverter X931, and the input terminal of inverter X932. The other of the source or drain of transistor M933 is electrically connected to one terminal of capacitor C931. The other of the source or drain of transistor M934 is electrically connected to one terminal of capacitor C932. The other of the source and drain of the transistor M931 is electrically connected to a wiring BL that functions as one of a pair of bit lines. The other of the source and drain of the transistor M932 is electrically connected to a wiring BLB that functions as the other of the pair of bit lines. The gates of the transistors M931 and M932 are electrically connected to a wiring WL that functions as a word line. The gates of the transistors M933 and M934 are electrically connected to a wiring BRL. The other terminal of the capacitor C931 and the other terminal of the capacitor C932 are electrically connected to a wiring CL.

[0409] The memory cell 950h can store binary data of "1" or "0" in an inverter loop formed by an inverter X931 and an inverter X932. When writing data, the memory cell 950h can apply potentials corresponding to the data to the inverter loop from the wiring BL and the wiring BLB by controlling the conduction states of the transistors M931 and M932. When reading data, the memory cell 950h can extract potentials corresponding to the data stored in the inverter loop from the wiring BL and the wiring BLB by controlling the conduction states of the transistors M931 and M932.

[0410] Furthermore, by controlling the conduction states of transistors M933 and M934, memory cell 950h can apply a potential corresponding to the data stored in the inverter loop to one terminal of capacitor C931 and one terminal of capacitor C932, respectively, and can hold a charge corresponding to the potential. In other words, data can be backed up. Furthermore, by controlling the conduction states of transistors M933 and M934, memory cell 950h can extract the charge held in one terminal of capacitor C931 and one terminal of capacitor C932, respectively, to the inverter loop. In other words, data can be recovered.

[0411] In one embodiment of the present invention, for example, n-channel OS transistors can be used as the transistors M931, M932, M933, and M934. Furthermore, inverter circuits available in a standard circuit library can be used as the inverters X931 and X932. That is, for example, n-channel and p-channel Si transistors can be used as the transistors included in the inverters X931 and X932.

[0412] Note that the memory cell 950h shown in FIG. 18H is a memory cell of a back-up capable static random access memory (SRAM). In particular, a configuration in which OS transistors are used for the transistors M931, M932, M933, and M934 may be referred to as an OS-SRAM (Oxide Semiconductor-SRAM).

[0413] Note that one embodiment of the present invention is not limited to the memory cells 950a to 950h, and memory cells having structures each of which can be appropriately combined can be used.

[0414] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification and the like.

[0415] In this embodiment, electronic components, electronic devices, mainframes, space equipment, and data centers (also referred to as data centers (DCs)) that can use the semiconductor device described in the above embodiment will be described. The electronic components, electronic devices, mainframes, space equipment, and data centers that use the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0416] [Electronic Component] FIG. 19A is a perspective view of an electronic component 5700 and a substrate (mounting substrate 5704) on which the electronic component 5700 is mounted. The electronic component 5700 shown in FIG. 19A has a semiconductor device 5710 in a mold 5711. FIG. 19A omits some details to show the interior of the electronic component 5700. The electronic component 5700 has lands 5712 on the outside of the mold 5711. The lands 5712 are electrically connected to electrode pads 5713. The electrode pads 5713 are electrically connected to the semiconductor device 5710 by wires 5714. The electronic component 5700 is mounted on, for example, a printed circuit board 5702. A plurality of such electronic components are combined and electrically connected on the printed circuit board 5702 to complete the mounting substrate 5704.

[0417] The semiconductor device 5710 also includes a drive circuit layer 5715 and a memory layer 5716. The memory layer 5716 has a configuration in which multiple memory cell arrays are stacked. The stacked configuration of the drive circuit layer 5715 and the memory layer 5716 can be a monolithically stacked configuration. In a monolithically stacked configuration, the layers can be connected without using, for example, through-electrode technology such as a TSV (Through Silicon Via) or bonding technology such as Cu-Cu direct bonding. By monolithically stacking the drive circuit layer 5715 and the memory layer 5716, for example, a so-called on-chip memory configuration can be achieved in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster.

[0418] Furthermore, by configuring an on-chip memory, it is possible to reduce the size of connection wiring, etc., compared to technologies that use through electrodes such as TSVs, and therefore it is also possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0419] It is also preferable that the memory cell arrays included in the memory layer 5716 are formed using OS transistors and the memory cell arrays are monolithically stacked. By monolithically stacking the memory cell arrays, it is possible to improve either or both of the memory bandwidth and the memory access latency. Note that the bandwidth is the amount of data transferred per unit time. Also, the access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 5716, it is more difficult to achieve a monolithically stacked structure than when OS transistors are used. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithically stacked structure.

[0420] That is, OS transistors have an excellent effect of enabling a wider memory bandwidth than Si transistors.

[0421] The semiconductor device 5710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and cutting it into dices during the semiconductor chip manufacturing process. Examples of semiconductor materials that can be used for the die include silicon, silicon carbide, and gallium nitride. For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0422] 19B is a perspective view of an electronic component 5730. The electronic component 5730 is an example of a SiP (System in Package) or an MCM (Multi Chip Module). The electronic component 5730 has an interposer 5731 provided on a package substrate 5732 (printed circuit board), and a semiconductor device 5735 and a plurality of semiconductor devices 5710 provided on the interposer 5731.

[0423] In the electronic component 5730, the semiconductor device 5710 can be used as a storage device such as a high bandwidth memory (HBM), and the semiconductor device 5735 can be used as an integrated circuit (e.g., an arithmetic unit, a control unit, or a signal processing unit) such as a central processing unit (CPU), a graphics processing unit (GPU), or a field programmable gate array (FPGA).

[0424] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used for the package substrate 5732. For example, a silicon interposer or a resin interposer can be used for the interposer 5731.

[0425] The interposer 5731 has a plurality of wirings and functions to electrically connect a plurality of integrated circuits having different terminal pitches via the plurality of wirings. The plurality of wirings are provided in a single layer or multiple layers. The interposer 5731 also functions to electrically connect the integrated circuits provided on the interposer 5731 to electrodes provided on the package substrate 5732. For these reasons, the interposer 5731 is sometimes referred to as a "rewiring substrate" or "intermediate substrate." The interposer 5731 may also be provided with through electrodes, which may be used to electrically connect the integrated circuits to the package substrate 5732. When a silicon interposer is used for the interposer 5731, TSVs may also be used as the through electrodes.

[0426] It is preferable to use a silicon interposer as the interposer 5731. A silicon interposer does not require an active element, and therefore can be manufactured at lower cost than an integrated circuit. Furthermore, since the wiring of a silicon interposer can be formed using a semiconductor process, it is easy to form fine wiring that is difficult to form with a resin interposer.

[0427] To achieve a wide memory bandwidth, an HBM needs to connect many wires. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0428] Furthermore, for example, SiP or MCM using a silicon interposer is less likely to suffer from a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer. Furthermore, since the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is less likely to occur. In particular, it is preferable to use a silicon interposer for a 2.5D package (2.5-dimensional packaging) in which multiple integrated circuits are arranged side by side on an interposer.

[0429] On the other hand, for example, when electrically connecting multiple integrated circuits with different terminal pitches using a silicon interposer, a TSV, or the like, a space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 5730, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings necessary to achieve a wide memory bandwidth. Therefore, as described above, a monolithically stacked configuration using OS transistors is preferable. Also, a composite structure may be used in which a memory cell array stacked using TSVs and a monolithically stacked memory cell array are combined.

[0430] The substrate on which the electronic component 5730 is mounted may be provided with a heat sink (heat dissipation plate) overlapping the electronic component 5730. When a heat sink is provided, it is preferable that the height of the integrated circuit provided on the interposer 5731 be the same. For example, it is preferable that the height of the electronic component 5730 be the same as that of the semiconductor device 5710 and the semiconductor device 5735.

[0431] In order to mount the electronic component 5730 on another substrate, the package substrate 5732 may have electrodes 5733 on its bottom. FIG. 19B shows an example in which the electrodes 5733 are formed with solder balls. By providing solder balls in a matrix on the bottom of the package substrate 5732, the electronic component 5730 can be mounted using a ball grid array (BGA) method. The electrodes 5733 may also be formed with conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 5732, the electronic component 5730 can be mounted using a pin grid array (PGA) method.

[0432] The electronic component 5730 can be mounted on other substrates using various mounting methods, not limited to BGA or PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), or a quad flat non-leaded package (QFN).

[0433] [Electronic Device] FIG. 20A is a perspective view of an electronic device 6500. The electronic device 6500 shown in FIG. 20A is a portable information terminal that can be used as a smartphone. The electronic device 6500 includes, for example, a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and a control device 6509. Note that the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a memory device. The semiconductor device of one embodiment of the present invention can be applied to the display portion 6502 or the control device 6509, for example. The use of the semiconductor device of one embodiment of the present invention for the control device 6509 is preferable because power consumption can be reduced.

[0434] FIG. 20B is a perspective view of an electronic device 6600. The electronic device 6600 shown in FIG. 20B is an information terminal that can be used as a laptop personal computer. The electronic device 6600 includes, for example, a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display portion 6615, and a control device 6616. Note that the control device 6616 includes, for example, one or more selected from a CPU, a GPU, and a memory device. The semiconductor device of one embodiment of the present invention can be applied to, for example, the control device 6509 or the control device 6616. The use of the semiconductor device of one embodiment of the present invention for the control device 6616 is preferable because power consumption can be reduced.

[0435] [Mainframe] Fig. 20C is a perspective view of a mainframe 5600. The mainframe 5600 shown in Fig. 20C has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe 5600 may also be called a supercomputer.

[0436] Fig. 20D is a perspective view illustrating an example configuration of a computer 5620. In Fig. 20D, the computer 5620 has a motherboard 5630. The motherboard 5630 has a plurality of slots 5631 and a plurality of connection terminals (not shown). A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, each of which is connected to the motherboard 5630.

[0437] A PC card 5621 shown in Figure 20E is an example of a processing board equipped with, for example, a CPU, a GPU, and a storage device. The PC card 5621 has a board 5622. The board 5622 also has a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Note that although Figure 20E illustrates semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628, the following description of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 can be referred to for information regarding these semiconductor devices.

[0438] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe (Peripheral Component Interconnect Express).

[0439] Each of the connection terminals 5623, 5624, and 5625 can be, for example, an interface for supplying power or inputting signals to the PC card 5621. Furthermore, each of the connection terminals 5623, 5624, and 5625 can be, for example, an interface for outputting signals calculated by the PC card 5621. Examples of standards for each of the connection terminals 5623, 5624, and 5625 include Universal Serial Bus (USB), Serial ATA (SATA), and Small Computer System Interface (SCSI). Furthermore, when a video signal is output from each of the connection terminals 5623, 5624, and 5625, examples of the respective standards include High-Definition Multimedia Interface (HDMI (registered trademark)).

[0440] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0441] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 5730 described above can be used as the semiconductor device 5627.

[0442] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5628 include a memory device. For example, the electronic component 5700 described above can be used as the semiconductor device 5628.

[0443] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations necessary for learning and inference in artificial intelligence, for example.

[0444] [Space Equipment] The semiconductor device of one embodiment of the present invention can be used in space equipment such as equipment that processes and stores information, for example.

[0445] The semiconductor device of one embodiment of the present invention can include an OS transistor. The OS transistor exhibits small changes in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and is therefore suitable for use in an environment where radiation may be incident. For example, the OS transistor is suitable for use in outer space.

[0446] Fig. 21A shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Fig. 21A also shows a planet 6804 in outer space. Although outer space refers to an altitude of 100 km or higher, the outer space described in this specification may also include the thermosphere, mesosphere, and stratosphere.

[0447] 21A , a battery management system (also referred to as a BMS) or a battery control circuit may be provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it consumes low power and has high reliability even in space.

[0448] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0449] The solar panel 6802 generates the power necessary for the operation of the satellite 6800 when irradiated with sunlight. However, for example, in a situation where the solar panel 6802 is not irradiated with sunlight or where the amount of sunlight irradiating the solar panel 6802 is small, the solar panel 6802 generates less power. Therefore, the satellite 6800 may not generate the power necessary for its operation. In order to operate the satellite 6800 even in a situation where the power generated by the solar panel 6802 is small, the satellite 6800 may be provided with a secondary battery 6805. The solar panel 6802 may also be called a solar cell module.

[0450] The satellite 6800 can generate a signal. The signal is transmitted via the antenna 6803. Furthermore, for example, a receiver installed on the ground or another satellite can receive the signal. For example, the receiver can measure the position of the receiver by receiving the signal transmitted by the satellite 6800. As described above, the satellite 6800 can constitute a satellite positioning system.

[0451] The control device 6807 has a function of controlling the satellite 6800. The control device 6807 is configured using, for example, one or more devices selected from a CPU, a GPU, and a storage device. Note that the control device 6807 is preferably a semiconductor device including an OS transistor, which is one embodiment of the present invention. The OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. That is, the OS transistor is preferable because it has high reliability even in an environment where radiation may be incident.

[0452] That is, an OS transistor has an excellent effect of being more radiation resistant than a Si transistor.

[0453] The artificial satellite 6800 may also be configured to include a sensor. For example, the artificial satellite 6800 may be configured to include a visible light sensor, thereby enabling it to have the function of detecting sunlight reflected from an object on the ground. The artificial satellite 6800 may also be configured to include a thermal infrared sensor, thereby enabling it to have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 may function as, for example, an earth observation satellite.

[0454] Although an artificial satellite is given as an example of space equipment in this embodiment, the present invention is not limited thereto. The semiconductor device of one embodiment of the present invention can be used in space equipment such as a spaceship, a space capsule, or a space probe, for example.

[0455] [Data Center] The semiconductor device according to one embodiment of the present invention can be used in a storage system applied to a data center, for example. The data center is required to perform long-term management of data, for example, by ensuring the immutability of data. Managing long-term data requires, for example, the installation of storage and servers for storing huge amounts of data, the securing of a stable power source for retaining the data, or the securing of cooling equipment required for retaining the data. Therefore, for example, the data center building needs to be enlarged.

[0456] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the semiconductor device that stores data. Therefore, for example, it is possible to reduce the size of the storage system, the size of the power supply for storing data, and the scale of the cooling equipment. Therefore, it is possible to reduce the space required for the data center.

[0457] Furthermore, the semiconductor device of one embodiment of the present invention has low power consumption, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and peripheral modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0458] Fig. 21B shows a storage system applicable to a data center. The storage system 7000 shown in Fig. 21B has a plurality of servers 7001sb as hosts 7001 (illustrated as Host Computers). It also has a plurality of storage devices 7003md as storage 7003 (illustrated as Storage). The host 7001 and storage 7003 are connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).

[0459] The host 7001 corresponds to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0460] Although the storage 7003 uses flash memory to reduce the data access speed, i.e., the time required to write or read data, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 7003, a storage system typically provides cache memory within the storage to reduce the time required to write or read data.

[0461] The above-mentioned cache memory is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.

[0462] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refreshing the cache memory can be reduced and the power consumption of the cache memory can be reduced.Furthermore, by using a stacked memory cell array, the cache memory can be miniaturized.

[0463] Note that the semiconductor device of one embodiment of the present invention can be applied to any one or more of electronic components, electronic devices, mainframe computers, space equipment, and data centers to reduce power consumption. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can contribute to the reduction of carbon dioxide (CO ２ Furthermore, the semiconductor device of one embodiment of the present invention consumes low power and is therefore effective as a countermeasure against global warming.

[0464] The configuration, structure, method, or the like described in this embodiment can be used in appropriate combination with the configuration, structure, method, or the like described in other embodiments.

[0465] Example 1 In this example, a circuit simulation was performed on a semiconductor device of one embodiment of the present invention, and the results of confirming the operation will be described.

[0466] The circuit simulation was performed using a circuit simulator "SmartSpice" from Silvaco, Inc. Using the circuit simulator, the semiconductor device 100 shown in Fig. 1A was operated as shown in the timing chart of Fig. 2 .

[0467] 22A and 22B are graphs showing the results of a circuit simulation for writing and reading data of "1." Figures 23A and 23B are graphs showing the results of a circuit simulation for writing and reading data of "0."

[0468] 22A and 23A plot the potentials applied to the wirings WWL, WBL, and RWL, respectively. 22B and 23B plot the changes in the potentials of the wirings NL11, NL12, and RBL, respectively. Although not shown, a constant potential of 1.8 V was applied to the wiring BSL.

[0469] For comparison, Figure 22B plots the results of a circuit simulation for a case in which the semiconductor device 100 does not have a bootstrap circuit, i.e., does not have the transistor M11, and the gate of the transistor M12 is electrically connected to the wiring WWL, with the symbols for the wiring NL12 (2T) and the wiring RBL (2T) assigned.

[0470] 22A and 22B , it was confirmed that, by including a bootstrap circuit in the semiconductor device 100, when writing data "1," the potential of the wiring NL11 rises and the potential of the wiring NL12 becomes higher than that of the wiring NL12(2T). As a result, it was confirmed that, when reading data "1," the potential of the wiring RBL changes faster than the potential of the wiring RBL(2T). This means that the data read speed can be increased.

[0471] 23A and 23B , when writing or reading data "0," the potential of the wiring NL12 becomes 0 V, and therefore a sufficient gate voltage is applied to the transistor M12 compared to when writing or reading data "1." Therefore, it was confirmed that writing and reading were performed correctly even when writing or reading data "0."

[0472] This example shows that the use of a semiconductor device of one embodiment of the present invention in a memory device can increase the operating speed of the memory device.

[0473] (Additional Notes Regarding the Description of the Present Specification, etc.) The following additional notes will be given regarding the above-described embodiments and the explanation of each configuration in the embodiments.

[0474] In this specification, when it is stated that X and Y are connected, it is understood that the following cases are disclosed in this specification: when X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are directly connected. Therefore, it is not limited to a specific connection relationship, for example, a connection relationship shown in a figure or text, and it is understood that connection relationships other than those shown in a figure or text are also disclosed in a figure or text. X and Y are each an object (e.g., a device, an element, a circuit, wiring, an electrode, a terminal, a conductive film, or a layer, etc.).

[0475] X and Y being electrically connected means that when an object having some kind of electrical action exists between X and Y, it enables the exchange of electrical signals between X and Y. As an example of when X and Y are electrically connected, one or more elements (for example, a switch, a transistor, a capacitance element, an inductor, a resistance element, a diode, a display device, a light-emitting device, or a load) that enable the electrical connection between X and Y can be connected between X and Y.

[0476] As an example of a case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, a logic circuit (for example, an inverter, a NAND circuit, or a NOR circuit), a signal conversion circuit (for example, a digital-to-analog conversion circuit, an analog-to-digital conversion circuit, or a gamma correction circuit), a potential level conversion circuit (for example, a power supply circuit (for example, a step-up circuit or a step-down circuit), or a level shifter circuit that changes the potential level of a signal), a voltage source, a current source, a switching circuit, an amplifier circuit (for example, a circuit that can increase the signal amplitude or current amount, an operational amplifier, a differential amplifier circuit, a source follower circuit, or a buffer circuit), a signal generation circuit, a memory circuit, or a control circuit) can be connected between X and Y. As an example, even if another circuit is sandwiched between X and Y, X and Y are considered to be functionally connected if a signal output from X is transmitted to Y.

[0477] It should be noted that when it is explicitly stated that X and Y are electrically connected, this includes the case where X and Y are electrically connected (i.e., the case where X and Y are connected with another element or another circuit sandwiched between them) and the case where X and Y are directly connected (i.e., the case where X and Y are connected without another element or another circuit sandwiched between them).

[0478] Furthermore, for example, it can be expressed as follows: "X, Y, the source of the transistor (sometimes referred to as one of the first terminal and the second terminal in this specification, etc.), and the drain of the transistor (sometimes referred to as the other of the first terminal and the second terminal in this specification, etc.) are electrically connected to each other, and are electrically connected in the order of X, the source of the transistor, the drain of the transistor, and Y." Alternatively, it can be expressed as follows: "The source of the transistor is electrically connected to X, the drain of the transistor is electrically connected to Y, and X, the source of the transistor, the drain of the transistor, and Y are electrically connected in this order." Alternatively, it can be expressed as follows: "X is electrically connected to Y through the source and drain of the transistor, and X, the source of the transistor, the drain of the transistor, and Y are provided in this connection order." By using expressions similar to these examples to define the order of connections in a circuit configuration, it is possible to distinguish between the source and drain of a transistor and determine the technical scope. Note that these expressions are merely examples, and the present invention is not limited to these expressions. Here, X and Y are each an object (for example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, or a layer).

[0479] Note that even when independent components are shown electrically connected to each other in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has the functions of both the wiring and the electrode. Therefore, the term "electrically connected" in this specification also includes such cases where one conductive film has the functions of multiple components.

[0480] Furthermore, in this specification, the term "resistive element" may refer to, for example, a circuit element or wiring having a resistance value higher than 0 Ω. Therefore, in this specification, the term "resistive element" includes, for example, wiring having a resistance value, a transistor in which current flows from drain to source, a diode, or a coil. Therefore, the term "resistive element" may be replaced with, for example, terms such as "resistance," "load," or "region having a resistance value." Conversely, the terms "resistance," "load," or "region having a resistance value" may be replaced with, for example, terms such as "resistive element." The resistance value may be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. Furthermore, for example, the resistance value may be, for example, 1 Ω or more and 1×10 ９ It may be set to Ω or less.

[0481] When a wiring is used as a resistor, the resistance value of the resistor may be determined by the length of the wiring. Alternatively, the resistor may use a conductor having a different resistivity from the conductor used as the wiring. Alternatively, when a semiconductor is used as a resistor, the resistance value of the resistor may be determined by doping impurities into the semiconductor.

[0482] Furthermore, in this specification, the term "capacitive element" can refer to, for example, a circuit element having a capacitance value higher than 0 F, a region of wiring having a capacitance value higher than 0 F, a parasitic capacitance, or a gate capacitance of a transistor. Therefore, in this specification, the term "capacitive element" is not limited to a circuit element including a pair of electrodes and a dielectric between the electrodes. The term "capacitive element" also includes, for example, a parasitic capacitance occurring between wirings, or a gate capacitance occurring between one of the source or drain of a transistor and the gate. Furthermore, terms such as "capacitive element," "parasitic capacitance," or "gate capacitance" can be replaced with terms such as "capacitance." Conversely, the term "capacitance" can be replaced with terms such as "capacitive element," "parasitic capacitance," or "gate capacitance." Furthermore, the term "pair of electrodes" in a "capacitive element" can be replaced with, for example, a "pair of conductors," a "pair of conductive regions," or a "pair of regions." The capacitance value can be, for example, 0.05 fF or more and 10 pF or less. Alternatively, it may be set to, for example, 1 pF or more and 10 μF or less.

[0483] In this specification and the like, a transistor has three terminals called a gate (also referred to as a gate terminal, a gate region, or a gate electrode), a source (also referred to as a source terminal, a source region, or a source electrode), and a drain (also referred to as a drain terminal, a drain region, or a drain electrode). A transistor also has a region where a channel is formed between the drain and the source (also referred to as a channel formation region). A transistor can pass a current between the source and the drain through the channel formation region. The channel formation region is a region through which a current mainly flows. A gate is a control terminal between the source and the drain that controls the amount of current flowing in the channel formation region. The two terminals that function as a source or a drain are input / output terminals of the transistor.

[0484] Note that one of the two input / output terminals serves as a source and the other as a drain depending on the conductivity type of the transistor (n-channel or p-channel) and the level of the potential applied to the three terminals of the transistor. Furthermore, for example, when the direction of current changes during circuit operation, the function as a source and the function as a drain may be interchanged. For this reason, the terms "source" and "drain" are interchangeable in this specification. Furthermore, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) or "the other of the source or drain" (or second electrode or second terminal) are used.

[0485] Depending on the structure, a transistor may have a back gate in addition to the three terminals described above. In this case, in this specification, one of the gate or the back gate of the transistor may be referred to as a first gate, and the other of the gate or the back gate of the transistor may be referred to as a second gate. Furthermore, for the same transistor, the terms "gate" and "back gate" may be interchangeable. Furthermore, when a transistor has three or more gates, in this specification, each gate may be referred to as, for example, a first gate, a second gate, or a third gate.

[0486] In this specification, a transistor having a multi-gate structure with two or more gate electrodes can be used. A multi-gate transistor has channel formation regions connected in series, resulting in a structure in which multiple transistors are connected in series. Therefore, a multi-gate transistor can reduce off-state current and improve the transistor's breakdown voltage (improved reliability). Furthermore, when a multi-gate transistor operates in the saturation region, even if the voltage between the drain and source changes, the current between the drain and source does not change significantly, resulting in a voltage-current characteristic with a flat slope. A transistor having a voltage-current characteristic with a flat slope can realize an ideal current source circuit or an active load with a very high resistance value. As a result, a transistor having a voltage-current characteristic with a flat slope can realize, for example, a differential circuit or a current mirror circuit with good characteristics.

[0487] Furthermore, in this specification, when a single circuit element is illustrated on a circuit diagram, the circuit element may include multiple circuit elements. For example, when a single resistor is illustrated on a circuit diagram, the resistor includes two or more resistors electrically connected in series. For example, when a single capacitor is illustrated on a circuit diagram, the capacitor includes two or more capacitors electrically connected in parallel. For example, when a single transistor is illustrated on a circuit diagram, the transistor includes two or more transistors electrically connected in series, with the gates of the respective transistors electrically connected to each other. Similarly, when a single switch is illustrated on a circuit diagram, the switch includes two or more transistors, with the two or more transistors electrically connected in series or parallel, and with the gates of the respective transistors electrically connected to each other.

[0488] Furthermore, in this specification and the like, a "node" can be rephrased as a "terminal," "wiring," "electrode," "conductive layer," "conductor," or "impurity region," depending on, for example, the circuit configuration or the device structure. Furthermore, for example, a "terminal" or "wiring" can be rephrased as a "node."

[0489] Furthermore, in this specification, "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative. In other words, a change in the reference potential will change, for example, the potential applied to wiring, the potential applied to a circuit, or the potential output from a circuit.

[0490] Furthermore, in this specification and the like, the terms "high-level potential (also referred to as "high-level potential," "H potential," or "H")" and "low-level potential (also referred to as "low-level potential," "L potential," or "L")" do not refer to any particular potential. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials provided by both wirings do not have to be equal to each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials provided by both wirings do not have to be equal to each other.

[0491] Furthermore, in this specification, "electric current" refers to the phenomenon of charge transfer (electrical conduction). For example, the statement "electrical conduction of positively charged bodies is occurring" can be rephrased as "electrical conduction of negatively charged bodies is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "electric current" refers to the phenomenon of charge transfer (electrical conduction) associated with the movement of carriers. Examples of carriers include electrons, holes, anions, cations, and complex ions. Note that carriers vary depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, vacuum, etc.). Furthermore, the "direction of current" in, for example, wiring, is the direction in which positive carriers move and is expressed as a positive current amount. In other words, the direction in which negative carriers move is opposite to the direction of current and is expressed as a negative current amount. Therefore, in this specification and the like, unless otherwise specified regarding the positive or negative sign of a current (or the direction of the current), for example, a statement such as "current flows from element A to element B" can be rephrased as "current flows from element B to element A," etc. Furthermore, for example, a statement such as "current is input to element A" can be rephrased as "current is output from element A," etc.

[0492] Furthermore, in this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be referred to as "second" in another embodiment or in the claims. Furthermore, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0493] Furthermore, in this specification, terms indicating arrangement, such as "above," "below," "upward," or "belowward," may be used for convenience in describing the positional relationship between components with reference to drawings. Furthermore, the positional relationship between components changes as appropriate depending on the orientation in which each component is depicted. Therefore, terms indicating arrangement described in this specification are not limited to these terms and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing by 180 degrees. Furthermore, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the left (or right) surface of a conductor" by rotating the orientation of the drawing by 90 degrees.

[0494] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not necessarily mean that electrode B is formed on insulating layer A in direct contact with it, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0495] Furthermore, in this specification, terms such as "row" or "column" may be used to describe components arranged in a matrix and their positional relationships. Furthermore, the positional relationships between components change as appropriate depending on the direction in which each component is depicted. Therefore, terms such as "row" or "column" used in this specification are not limited to these terms and can be rephrased appropriately depending on the situation. For example, the expression "row direction" can be rephrased as "column direction" by rotating the orientation of the drawing by 90 degrees.

[0496] Furthermore, in this specification and the like, for example, terms such as "overlap" do not limit the state of the stacking order of components, etc. For example, the expression "electrode B overlapping insulating layer A" is not limited to the state in which electrode B is formed on insulating layer A. The expression "electrode B overlapping insulating layer A" does not exclude, for example, the state in which electrode B is formed under insulating layer A, or the state in which electrode B is formed on the right (or left) side of insulating layer A.

[0497] Furthermore, in this specification and the like, the terms "adjacent" or "close to" do not limit components to being in direct contact with each other. For example, the expression "electrode B adjacent to insulating layer A" does not necessarily mean that insulating layer A and electrode B are formed in direct contact with each other, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0498] Furthermore, in this specification and the like, terms such as "film" or "layer" may be interchangeable depending on the situation. For example, the term "conductive layer" may be interchangeable with the term "conductive film." For example, the term "insulating film" may be interchangeable with the term "insulating layer." Furthermore, terms such as "film" or "layer" may be interchangeable with other terms depending on the situation without using those terms. For example, the term "conductive layer" or "conductive film" may be interchangeable with the term "conductor." Furthermore, the term "conductor" may be interchangeable with the term "conductive layer" or "conductive film." For example, the term "insulating layer" or "insulating film" may be interchangeable with the term "insulator." Furthermore, the term "insulator" may be interchangeable with the term "insulating layer" or "insulating film."

[0499] Furthermore, in this specification and the like, terms such as "electrode," "wiring," or "terminal" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" or "wiring" include, for example, cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes, for example, cases where multiple "electrodes," "wirings," or "terminals" are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal." Furthermore, for example, a "terminal" can be part of a "wiring" or "electrode." Furthermore, for example, terms such as "electrode," "wiring," or "terminal" may be replaced with terms such as "region."

[0500] Furthermore, in this specification and the like, terms such as "wiring," "signal line," or "power line" may be interchangeable depending on the situation. For example, the term "wiring" may be changed to the term "signal line." For example, the term "wiring" may be changed to the term "power line." The reverse is also true, for example, terms such as "signal line" or "power line" may be changed to the term "wiring." The term "power line" may be changed to the term "signal line." The reverse is also true, for example, terms such as "signal line" may be changed to the term "power line." The term "potential" applied to wiring may be changed to the term "signal" depending on the situation. The reverse is also true, for example, terms such as "signal" may be changed to the term "potential."

[0501] In addition, in this specification, a "switch" has multiple terminals and has the function of switching (selecting) conduction or non-conduction between the terminals. For example, if a switch has two terminals and both terminals are conductive, the switch is said to be in a "conductive state" or "on state." Also, if both terminals are non-conductive, the switch is said to be in a "non-conductive state" or "off state." Note that switching the switch to either the conductive state or the non-conductive state, or maintaining either the conductive state or the non-conductive state, may be referred to as "controlling the conduction state."

[0502] In other words, a switch is a device that has the function of controlling whether or not a current flows. Alternatively, a switch is a device that has the function of selecting and switching a path through which a current flows. For example, an electrical switch or a mechanical switch can be used as the switch. In other words, the switch is not limited to a specific type.

[0503] There are types of switches that are normally in a non-conductive state but can be made conductive by controlling the conductive state, and these switches are sometimes called "contact A." There are also types of switches that are normally in a conductive state but can be made non-conductive by controlling the conductive state, and these switches are sometimes called "contact B."

[0504] Examples of electrical switches include transistors (e.g., bipolar transistors or MOS transistors), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, or diode-connected transistors), and logic circuits that combine these. Note that when a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0505] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. Such a switch has an electrode that can be mechanically moved, and the movement of the electrode selects a conductive state or a non-conductive state.

[0506] In this specification, the "channel length" of a transistor may refer to, for example, the distance between the source and drain in a region where the semiconductor (or the portion in the semiconductor through which current flows when the transistor is on) and the gate overlap, or the distance between the source and drain in a region where a channel is formed.

[0507] In addition, in this specification, the "channel width" of a transistor may refer to, for example, the length of the portion where the source and drain face each other in a region where the semiconductor (or the portion where current flows in the semiconductor when the transistor is on) and the gate overlap, or the length of the portion where the source and drain face each other in a region where a channel is formed.

[0508] In this specification and the like, terms such as "substrate," "wafer," or "die" do not limit the functionality of these components. For example, terms such as "substrate," "wafer," or "die" may be interchangeable depending on the situation.

[0509] In this specification, "parallel" does not necessarily mean strictly parallel. Therefore, the term "parallel" can be appropriately interchangeable with terms such as "approximately parallel," "generally parallel," or "substantially parallel." "Parallel," "generally parallel," "generally parallel," or "substantially parallel" can include, for example, a state in which two lines or planes are arranged at an angle of -5° or more and 5° or less. Alternatively, they can include a state in which two lines or planes are arranged at an angle of -10° or more and 10° or less. Alternatively, they can include a state in which two lines or planes are arranged at an angle of -30° or more and 30° or less. Therefore, "parallel" can mean, for example, "parallel or roughly parallel." Furthermore, "perpendicular" does not necessarily mean strictly perpendicular. Therefore, the term "perpendicular" can be appropriately interchangeable with terms such as "generally perpendicular," "generally perpendicular," or "substantially perpendicular." "Perpendicular," "generally perpendicular," "generally perpendicular," or "substantially perpendicular" can include, for example, a state in which two lines or planes are arranged at an angle of 85° or more and 95° or less. Alternatively, it may include a state in which two straight lines or planes are arranged at an angle of 80° or more and 100° or less. Alternatively, it may include a state in which two straight lines or planes are arranged at an angle of 60° or more and 120° or less. Therefore, "perpendicular" may mean, for example, "perpendicular or approximately perpendicular."

[0510] In this specification, "equal heights" refers to the same height from a reference surface (e.g., a flat surface such as a substrate surface) in a cross-sectional view. For example, in a semiconductor device manufacturing process, a planarization process may expose the surface of a single layer or multiple layers. In this case, the surfaces to be planarized have the same height from the reference surface. However, depending on the processing equipment, processing method, or material of the processed surface during the planarization process, the heights of multiple layers may not be strictly equal. In this specification, "equal heights" is also used. For example, when there are two layers (here, a first layer and a second layer) with different heights relative to a reference surface, the difference between the height of the top surface of the first layer and the height of the top surface of the second layer is 20 nm or less. Therefore, "equal heights" may mean, for example, "equal heights or approximately equal heights."

[0511] In this specification, "edges coincide" means that, when viewed from above, at least a portion of the contours of stacked layers overlap. For example, this includes cases in which, in a semiconductor device manufacturing process, upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the contour of the upper layer may be located inside the contour of the lower layer, or the contour of the upper layer may be located outside the contour of the lower layer. In this specification, this case is also referred to as "edges coincide." Therefore, "edges coincide" can mean, for example, "edges coincide or approximately coincide."

[0512] In this specification, for example, when referring to counting values ​​and measurement values, or to things, methods, events, etc. that can be converted into counting values ​​or measurement values, terms such as "identical," "same," "equal," "simultaneous," "match," or "uniform" (including synonyms thereof) include an error of plus or minus 20% unless otherwise specified. Thus, for example, "identical" may mean "identical or approximately identical," "same" may mean "same or approximately the same," "equal" may mean "equal or approximately equal," "simultaneous" may mean "simultaneous or approximately simultaneous," "match" may mean "match or approximately match," and "uniform" may mean "uniform or approximately uniform."

[0513] In this specification and the like, the term "impurity" in a semiconductor refers to, for example, a substance other than the main component constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % is an impurity. The presence of impurities in a semiconductor may, for example, increase the defect state density of the semiconductor, decrease the carrier mobility, or decrease the crystallinity. When the semiconductor is an oxide semiconductor, examples of impurities that change the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main component of the oxide semiconductor. In particular, examples of impurities include hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. For example, the inclusion of impurities in an oxide semiconductor may cause oxygen vacancies in the oxide semiconductor.

[0514] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into, for example, oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (also referred to as oxide semiconductors or simply as OSs). For example, when a metal oxide is used as a semiconductor including a channel formation region of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, when a metal oxide is used as a material capable of forming a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, the term "OS transistor" can be rephrased as a transistor including a metal oxide or an oxide semiconductor.

[0515] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0516] In addition, in drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification, the "X direction" refers to the direction along the X axis, and the forward direction and the reverse direction may not be distinguished unless explicitly stated. The same applies to the "Y direction" and the "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other. In this specification, one of the X direction, Y direction, and Z direction may be referred to as the "first direction" or "first direction." The other may be referred to as the "second direction" or "second direction." The remaining one may be referred to as the "third direction" or "third direction."

[0517] 100: semiconductor device, M11: transistor, M12: transistor, M13: transistor, WWL: wiring, RWL: wiring, WBL: wiring, RBL: wiring, BSL: wiring, NL11: wiring, NL12: wiring, 110: semiconductor device, 190a: layer, 190b: layer, 190c: layer, 120: semiconductor device, 620: insulator, 600: transistor, 630: conductor, 640: insulator, 648: opening, 650: oxide, 650i: region, 650na: region, 650nb: region, 660: conductor, 670: conductor, 672: insulator, 600a: transistor, 64 0a: insulator, 648a: opening, 650a: oxide, 660a: conductor, 670a: conductor, 672a: insulator, 600b: transistor, 640b: insulator, 648b: opening, 650b: oxide, 660b: conductor, 670b: conductor, 672b: insulator, 600c: transistor, 640c: insulator, 648c: opening, 650c: oxide, 660c: conductor, 670c: conductor, 672c: insulator, 678: insulator, 120A: semiconductor device, 120B: semiconductor device, 100B: semiconductor device, BGL1: wiring, BGL2: wiring, BGL3: wiring, 600 B: transistor, 680: conductor, 682: insulator, 500: transistor, 503: conductor, 503a: conductor, 503b: conductor, 512: insulator, 514: insulator, 516: insulator, 522: insulator, 524: insulator, 530: oxide, 530a: oxide, 530b: oxide, 540a: conductor, 540b: conductor, 542a: conductor, 542b: conductor, 543a: region, 543b: region, 544: insulator, 545: insulator, 560: conductor, 560a: conductor, 560b: conductor, 580: insulator, 582: insulator, 584: insulator, 700 : memory device, 721: memory array, 722: driver circuit, 761: power switch, 762: power switch, 771: peripheral circuit, 772: control circuit, 773: voltage generation circuit, 781: peripheral circuit, 782: row decoder, 783: row driver, 784: column decoder, 785: column driver, 786: data driver, 787: input circuit, 788: output circuit, BW: terminal, CE: terminal, GW: terminal, MCK: terminal, WAKE: terminal, ADDR: terminal, RDA: terminal, WDA: terminal, PON1: terminal, PON2: terminal, VMD: terminal, VMS: terminal, VMH: terminal,740: memory device, 741: memory array, 742: sense amplifier array, 743: write word line driver, 744: read word line driver, 745: sense amplifier driver, 746: input / output interface, 747: controller, 750: sense circuit, 751: amplifier circuit, 752: precharge circuit, 753: precharge circuit, 754: switch circuit, M751a: transistor, M751b: transistor, M751c: transistor, M751d: transistor, M752a: transistor, M752b: transistor, M752c: transistor, M753a: transistor , M753b: transistor, M753c: transistor, M754a: transistor, M754b: transistor, GBL: wiring, GBLB: wiring, SAP: wiring, SAN: wiring, VPRE: wiring, EQ: wiring, EQB: wiring, CSEL: wiring, DBL: wiring, DBLB: wiring, 550: transistor, 311: substrate, 313: semiconductor region, 314a: low resistance region, 314b: low resistance region, 315: insulator, 316: conductor, 320: insulator, 322: insulator, 324: insulator, 326: insulator, 328: conductor, 330: conductor, 350: insulator, 352: insulator, 354: insulator, 356: conductor,

Claims

A first transistor, a second transistor, and a third transistor, one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor; one of the source and the drain of the second transistor is electrically connected to the gate of the third transistor; a gate of the first transistor is electrically connected to a first wiring to which a constant potential is applied; the other of the source and the drain of the first transistor is electrically connected to a second wiring; the other of the source and the drain of the second transistor is electrically connected to a third wiring; one of a source and a drain of the third transistor is electrically connected to a fourth wiring; the other of the source and the drain of the third transistor is electrically connected to a fifth wiring; Semiconductor device. 　 A first transistor, a second transistor, and a third transistor, the first transistor is located in an upper layer of the second transistor, the second transistor is located in an upper layer of the third transistor, the first transistor, the second transistor, and the third transistor have overlapping regions; one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor; one of the source and the drain of the second transistor is electrically connected to the gate of the third transistor; a gate of the first transistor is electrically connected to a first wiring; the other of the source and the drain of the first transistor is electrically connected to a second wiring; the other of the source and the drain of the second transistor is electrically connected to a third wiring; one of a source and a drain of the third transistor is electrically connected to a fourth wiring; the other of the source and the drain of the third transistor is electrically connected to a fifth wiring; Semiconductor device. 　 a first transistor, a second transistor, a third transistor, a first conductor, a second conductor, a third conductor, a fourth conductor, a fifth conductor, a sixth conductor, and a seventh conductor; the first conductor and the second conductor are located above the third conductor, the third conductor and the fourth conductor are located above the fifth conductor, the fifth conductor and the sixth conductor are located above the seventh conductor, the first conductor has a region above the second conductor that functions as a first wiring, and a region below the second conductor that functions as a gate electrode of the first transistor, the third conductor has a region above the fourth conductor that functions as one of a source electrode or a drain electrode of the first transistor, and a region below the fourth conductor that functions as a gate electrode of the second transistor, the fifth conductor has a region above the sixth conductor that functions as one of a source electrode or a drain electrode of the second transistor, and a region below the second conductor that functions as a gate electrode of the third transistor, the second conductor has a region that functions as the other of the source electrode and the drain electrode of the first transistor, and a region that functions as a second wiring; the fourth conductor has a region that functions as the other of the source electrode and the drain electrode of the second transistor and a region that functions as a third wiring; the seventh conductor has a region that functions as one of a source electrode or a drain electrode of the third transistor and a region that functions as a fourth wiring; the sixth conductor has a region that functions as the other of the source electrode and the drain electrode of the third transistor and a region that functions as a fifth wiring, the first conductor, the second conductor, the third conductor, the fourth conductor, the fifth conductor, the sixth conductor, and the seventh conductor have regions that overlap each other in a top view, A channel length direction of each of the first transistor, the second transistor, and the third transistor is a depth direction in a top view. Semiconductor device. 　 In any one of claims 1 to 3, a channel formation region of the second transistor includes an oxide semiconductor; Semiconductor device. In claim 4, a channel formation region of the third transistor includes an oxide semiconductor; a crystallinity of an oxide semiconductor included in a channel formation region of the third transistor is higher than a crystallinity of an oxide semiconductor included in a channel formation region of the second transistor; Semiconductor device. 　 In any one of claims 1 to 3, a channel length of each of the first transistor and the third transistor is smaller than a channel length of the second transistor; Semiconductor device. 　 In any one of claims 1 to 3, each of the first transistor, the second transistor, and the third transistor has a back gate; a potential applied to a back gate of each of the first transistor and the third transistor is greater than a potential applied to a back gate of the second transistor; Semiconductor device. 　 In any one of claims 1 to 3, The direction in which the first wiring extends is perpendicular to the direction in which the second wiring and the fourth wiring extend, and is parallel to the direction in which the third wiring and the fifth wiring extend. Semiconductor device.

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