Galvanic isolation device and manufacturing method thereof

Abstract

The purpose of one embodiment of the present invention is to provide a galvanic isolation device comprising: a first semiconductor die and a second semiconductor die disposed to be spaced apart from each other; and a galvanic isolator disposed between the first semiconductor die and the second semiconductor die and disposed to be spaced apart from the first semiconductor die and the second semiconductor die.

Description

Galvanic separation element and method for manufacturing the same

[0001] The present invention relates to a galvanic separation element and a method for manufacturing the same.

[0002] Galvanic isolators can be used to transmit and receive signals between circuits with different reference potentials. A galvanic isolator can be defined as a device that blocks current flow between circuits with different reference potentials while enabling signal transmission. Demand for galvanic isolators is increasing across various applications, and this demand may necessitate the use of galvanic isolators that offer high efficiency and high reliability.

[0003] Galvanic isolation refers to the electrical and physical separation between the transmitter and receiver of a signal.

[0004] A galvanic separator may be referred to as a device comprising a galvanic separator and a semiconductor die.

[0005] Conventionally, galvanic separation elements are implemented using a silicon process, and when designing a galvanic separation element using this silicon process, there is a limitation that only certain processes can be used.

[0006] Recently, research on galvanic separation devices without process limitations has been continuously conducted.

[0007] One embodiment of the present invention provides a galvanic separation element without process limitations during design.

[0008] One embodiment of the present invention provides a galvanic isolation device including a galvanic isolator disposed between a first semiconductor die and a second semiconductor die and spaced apart from the first semiconductor die and the second semiconductor die.

[0009] One embodiment of the present invention provides a galvanic separation element including a galvanic separator formed by a post-process.

[0010] One embodiment of the present invention for achieving the above-described technical task is to provide a galvanic isolation element including a first semiconductor die and a second semiconductor die that are arranged to be spaced apart from each other, and a galvanic isolator that is arranged between the first semiconductor die and the second semiconductor die and is spatially spaced from the first semiconductor die and the second semiconductor die, wherein the galvanic isolator is electrically connected to the first semiconductor die and the second semiconductor die by a first bonding wire and a second bonding wire, respectively.

[0011] The galvanic separator may include a first capacitor and a second capacitor that are spaced apart from each other, and the first capacitor and the second capacitor may each include a first capacitor electrode and a second capacitor electrode, and may further include a first dielectric layer disposed between the first capacitor electrode and the second capacitor electrode of the first capacitor and a second dielectric layer disposed between the first capacitor electrode and the second capacitor electrode of the second capacitor.

[0012] The first dielectric layer may be disposed spaced apart from the first semiconductor die and the second semiconductor die, and the second dielectric layer may be disposed spaced apart from the first semiconductor die and the second semiconductor die.

[0013] A first terminal connected to the first semiconductor die through a third bonding wire; and a second terminal connected to the second semiconductor die through a fourth bonding wire, wherein a voltage applied to the second terminal is greater than a voltage applied to the first terminal, and the first terminal and the second terminal may be made of the same material as the galvanic separator and formed by the same process.

[0014] It may further include a molding portion surrounding each of the first semiconductor die, the second semiconductor die, and the galvanic separator.

[0015] The first capacitor electrode and the second capacitor electrode of the first capacitor overlap at least partially in a plane, the first capacitor electrode and the second capacitor electrode of the second capacitor overlap at least partially in a plane, the first capacitor electrode of the first capacitor and the first capacitor electrode of the second capacitor have a first protrusion, the first protrusion is connected to the second semiconductor die via the second bonding wire, the second capacitor electrode of the first capacitor and the second capacitor electrode of the second capacitor have a second protrusion, the second protrusion is connected to the first semiconductor die via the first bonding wire, and the first protrusion and the second protrusion may not overlap each other in a plane.

[0016] The first capacitor further includes a first dielectric layer disposed between the first capacitor electrode and the second capacitor electrode of the first capacitor, and a second dielectric layer disposed between the first capacitor electrode and the second capacitor electrode of the second capacitor, wherein the first protrusion and the second protrusion may not overlap the first dielectric layer and the second dielectric layer in a planar view.

[0017] The galvanic separator may include a third capacitor and a fourth capacitor that are spaced apart from each other, and the third capacitor and the fourth capacitor may each include a first capacitor electrode and a second capacitor electrode, and the first capacitor electrode and the second capacitor electrode of the third capacitor may be disposed in the same layer, and the first capacitor electrode and the second capacitor electrode of the fourth capacitor may each include a plurality of protrusions spaced apart from each other, and the first capacitor electrode and the second capacitor electrode of the fourth capacitor may each include a plurality of protrusions spaced apart from each other.

[0018] A third dielectric layer disposed between the first capacitor electrode and the second capacitor electrode of the third capacitor and a fourth dielectric layer disposed between the first capacitor electrode and the second capacitor electrode of the fourth capacitor are included, and the third dielectric layer and the fourth dielectric layer may each have a zigzag shape.

[0019] Another embodiment of the present invention comprises the steps of forming a lead frame having an outer frame, a first lower electrode, a second lower electrode, a first upper electrode, and a second upper electrode extending from the outer frame, a step of forming a dielectric material layer between the first lower electrode and the first upper electrode and between the second lower electrode and the second upper electrode, a step of removing the dielectric material layer that is not disposed between the first lower electrode and the first upper electrode and between the second lower electrode and the second upper electrode in a planar manner to form a first capacitor and a second capacitor, a step of forming a first semiconductor die and a second semiconductor die spaced apart from each other within the outer frame, a step of connecting the first semiconductor die to the first capacitor and the second capacitor using a first bonding wire, and a step of connecting the second semiconductor die to the first capacitor and the second capacitor using a second bonding wire, a step of forming a molding part formed within the outer frame and surrounding the first semiconductor die, the second semiconductor die, the first capacitor, and the second capacitor, and a step of forming the outer portion of the lead frame. A method for manufacturing a galvanic isolation element may be provided, comprising a step of removing a frame, wherein the first capacitor and the second capacitor are disposed between the first semiconductor die and the second semiconductor die, and are disposed spaced apart from each other between the first semiconductor die and the second semiconductor die.

[0020] A galvanic separation device according to one embodiment of the present invention includes a galvanic separator disposed between a first semiconductor die and a second semiconductor die and spaced apart from the first semiconductor die and the second semiconductor die, so that there may be no process limitations in device design.

[0021] A galvanic separation element according to one embodiment of the present invention can form a galvanic separator through post processing.

[0022] In addition to the effects mentioned above, other features and advantages of the present invention are described below or may be clearly understood by those skilled in the art to which the present invention pertains from such description and explanation.

[0023] FIG. 1 is a plan view of a galvanic separation element according to one embodiment of the present invention.

[0024] Figure 2 is a cross-sectional view taken along line I-I' of Figure 1.

[0025] FIG. 3 is a cross-sectional view of a galvanic separation element according to another embodiment of the present invention.

[0026] Figures 4a to 4g are process diagrams showing a manufacturing process of a galvanic separation element according to one embodiment of the present invention.

[0027] FIGS. 5A to 5D are process diagrams showing a part of a manufacturing process of a galvanic separation element according to one embodiment of the present invention.

[0028] Figure 6 is a schematic diagram of a power element drive system including a galvanic isolation element.

[0029] The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below, along with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms. These embodiments are provided solely to ensure that the disclosure of the present invention is complete and to inform those skilled in the art of the scope of the invention.

[0030] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are merely illustrative, and the present invention is not limited to the details depicted in the drawings. Throughout the specification, identical components may be designated by identical reference numerals. Furthermore, in describing the present invention, if a detailed description of a related known technology is deemed to unnecessarily obscure the gist of the present invention, the detailed description will be omitted.

[0031] In this specification, when the words "include," "have," and "consist of" are used, other parts may be added, unless the expression "only" is used. When a component is expressed in the singular, the plural is included unless otherwise explicitly stated.

[0032] When interpreting a component, it is interpreted as including the error range even if there is no separate explicit description.

[0033] For example, when the positional relationship between two parts is described as ‘on top of’, ‘upper part of’, ‘lower part of’, ‘next to’, etc., one or more other parts may be located between the two parts unless the expression ‘right away’ or ‘directly’ is used.

[0034] Spatially relative terms such as "below," "beneath," "lower," "above," and "upper" can be used to easily describe the relationship between one element or component and other elements or components, as illustrated in the drawings. Spatially relative terms should be understood to include different orientations of the elements during use or operation in addition to the orientations depicted in the drawings. For example, if an element depicted in the drawings were flipped over, an element described as "below" or "beneath" another element could end up being placed "above" the other element. Thus, the exemplary term "below" can include both the above and below directions. Similarly, the exemplary term "above" or "above" can include both the above and below directions.

[0035] When describing a temporal relationship, for example, when the temporal relationship is described as 'after', 'following', 'next to', 'before', etc., it can also include cases where it is not continuous, as long as the expression 'immediately' or 'directly' is not used.

[0036] While terms like "first" and "second" are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, a "first" component referred to below may also be a "second" component within the technical scope of the present invention.

[0037] The term "at least one" should be understood to include all possible combinations of one or more associated items. For example, "at least one of the first, second, and third items" can mean any combination of items that can be represented by two or more of the first, second, and third items, as well as each of the first, second, and third items.

[0038] The features of each of the various embodiments of the present invention can be partially or wholly combined or combined with each other, and various technical connections and operations are possible, and each embodiment can be implemented independently of each other or implemented together in a related relationship.

[0039] In adding reference numerals to components of each drawing describing embodiments of the present invention, the same components may have the same numerals as much as possible even if they are shown in different drawings.

[0040] Fig. 1 is a plan view of a galvanic separation element (100) according to one embodiment of the present invention. Fig. 2 is a cross-sectional view taken along line I-I' of Fig. 1.

[0041] According to one embodiment of the present invention, a galvanic separation element (100) may include a first semiconductor die (110), a second semiconductor die (120), and a galvanic separator (130).

[0042] The galvanic separation element (100) can be included in electronic devices such as TVs, personal computers (PCs), and other means of transportation such as vehicles.

[0043] The first semiconductor die (110) and the second semiconductor die (120) may correspond to a transmitter and a receiver, respectively. In addition, the first semiconductor die (110) and the second semiconductor die (120) may correspond to semiconductor chips.

[0044] According to one embodiment of the present invention, a power semiconductor in a wafer state that has not been packaged may be referred to as a "semiconductor die." Power semiconductors can be broadly divided into switching elements and rectifier elements. The switching elements may be IGBTs (Insulated Gate Bipolar Transistors) or MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and the rectifier elements may be widely known diodes.

[0045] The first semiconductor die (110) and the second semiconductor die (120) may have different reference potentials, and the galvanic isolator (130) may transmit a signal containing information between the first semiconductor die (110) and the second semiconductor die (120).

[0046] Referring to FIGS. 1 and 2, the first semiconductor die (110) and the second semiconductor die (120) are arranged spaced apart from each other.

[0047] Referring to FIGS. 1 and 2, a galvanic separator (130) is disposed between a first semiconductor die (110) and a second semiconductor die (120), and is disposed spatially separated from the first semiconductor die (110) and the second semiconductor die (120). For example, the first semiconductor die (110) and the galvanic separator (130) are disposed spaced apart from each other except for being connected by a first bonding wire (151). In addition, the second semiconductor die (120) and the galvanic separator (130) are disposed spaced apart from each other except for being connected by a second bonding wire (152).

[0048] According to one embodiment of the present invention, the galvanic separator (130) may include a first capacitor (131) and a second capacitor (132).

[0049] FIG. 1 illustrates a first capacitor (131) and a second capacitor (132) being placed between a first semiconductor die (110) and a second semiconductor die (120), respectively, and being placed spaced apart from the first semiconductor die (110) and the second semiconductor die (120).

[0050] According to one embodiment of the present invention, the first capacitor (131) and the second capacitor (132) each include a first capacitor electrode (131a, 132a) and a second capacitor electrode (131b, 132b).

[0051] For example, the first capacitor (131) may include a first capacitor electrode (131a) and a second capacitor electrode (131b), and the second capacitor (132) may include a first capacitor electrode (132a) and a second capacitor electrode (132b).

[0052] Referring to FIGS. 1 and 2, the first capacitor (131) includes a first capacitor electrode (131a) and a second capacitor electrode (131b) that is disposed on the first capacitor electrode (131a) and overlaps the first capacitor electrode (131a) in a planar manner. In addition, the second capacitor (132) includes a first capacitor electrode (132a) and a second capacitor electrode (132b) that is disposed on the first capacitor electrode (132a) and overlaps the first capacitor electrode (132a) in a planar manner.

[0053] According to one embodiment of the present invention, the first capacitor electrode (131a) of the first capacitor (131) and the first capacitor electrode (132a) of the second capacitor (132) may be made of the same material and formed by the same process.

[0054] Additionally, the second capacitor electrode (131b) of the first capacitor (131) and the second capacitor electrode (132b) of the second capacitor (132) may be made of the same material and formed by the same process.

[0055] A galvanic separation element (100) according to one embodiment of the present invention may include a first dielectric layer (131c) disposed between a first capacitor electrode (131a) and a second capacitor electrode (131b) of a first capacitor (131).

[0056] A galvanic separation element (100) according to one embodiment of the present invention may include a second dielectric layer (132c) disposed between a first capacitor electrode (132a) and a second capacitor electrode (132b) of a second capacitor (132).

[0057] FIG. 2 illustrates a first dielectric layer (131c) being disposed between the first capacitor electrode (131a) and the second capacitor electrode (131b) of the first capacitor (131). Although the second dielectric layer (132c) is not depicted in the drawing, like the first dielectric layer (131c), the second dielectric layer (132c) may be disposed between the first capacitor electrode (132a) and the second capacitor electrode (132b) of the second capacitor (132).

[0058] According to one embodiment of the present invention, the first dielectric layer (131c) is disposed spaced apart from the first semiconductor die (110) and the second semiconductor die (120), and the second dielectric layer (132c) is disposed spaced apart from the first semiconductor die (110) and the second semiconductor die (120).

[0059] FIG. 2 illustrates a first dielectric layer (131c) being placed spaced apart from the first semiconductor die (110) and the second semiconductor die (120).

[0060] According to one embodiment of the present invention, the first semiconductor die (110) and the first capacitor (131) and the second capacitor (132) are each connected by a first bonding wire (151). For example, FIG. 2 illustrates a state in which the first semiconductor die (110) is connected to the second capacitor electrode (131b) of the first capacitor (131) by a first bonding wire (151).

[0061] The second semiconductor die (120) and the first capacitor (131) and the second capacitor (132) are each connected by a second bonding wire (152). For example, FIG. 2 illustrates a state in which the second semiconductor die (120) is connected to the first capacitor electrode (131a) of the first capacitor (131) by a second bonding wire (152).

[0062] A galvanic separation element (100) according to one embodiment of the present invention may further include a first terminal (141) and a second terminal (142) that are spaced apart from each other.

[0063] Referring to FIG. 1, the first terminal (141) can be connected to the first semiconductor die (110) via the third bonding wire (153), and the second terminal (142) can be connected to the second semiconductor die (120) via the fourth bonding wire (154).

[0064] At this time, a low voltage may be applied to the first terminal (141), and a high voltage may be applied to the second terminal (142). However, one embodiment of the present invention is not limited thereto.

[0065] According to one embodiment of the present invention, the voltage applied to the second terminal (142) may be greater than the voltage applied to the first terminal (141).

[0066] According to one embodiment of the present invention, the first terminal (141) and the second terminal (142) can be made of the same material as the galvanic separator (130) and formed by the same process. Therefore, no separate process is required to form the first terminal (141) and the second terminal (142).

[0067] A galvanic separation element (100) according to one embodiment of the present invention may further include a molding portion (160).

[0068] Referring to FIGS. 1 and 2, the molding portion (160) can surround each of the first semiconductor die (110), the second semiconductor die (120), and the galvanic separator (130).

[0069] For example, the molding portion (160) may surround the upper surface, lower surface, and side surfaces of the first semiconductor die (110) and the second semiconductor die (120), respectively. For example, the molding portion (160) may surround the upper surface, lower surface, and side surfaces of the first capacitor (131) and the second capacitor (132), respectively.

[0070] According to one embodiment of the present invention, the first capacitor electrode (131a) of the first capacitor (131) and the first capacitor electrode (132a) of the second capacitor (132) may each include a first protrusion (131am, 132am), and the second capacitor electrode (131b) of the first capacitor (131) and the second capacitor electrode (132b) of the second capacitor (132) may each include a second protrusion (131bm, 132bm).

[0071] Referring to FIGS. 1 and 2, the first protrusion (131am) of the first capacitor electrode (131a) protrudes toward the second semiconductor die (120), and the second protrusion (131bm) of the second capacitor electrode (131b) protrudes toward the first semiconductor die (110).

[0072] Referring to FIGS. 1 and 2, the first protrusions (131am, 132am) of the first capacitor electrodes (131a, 132a) are each connected to the second semiconductor die (120) through the second bonding wire (152), and the second protrusions (131bm, 132bm) of the second capacitor electrodes (131b, 132b) are each connected to the first semiconductor die (110) through the first bonding wire (151).

[0073] For example, the first protrusion (131am) and the second protrusion (131bm) of the first capacitor (131) may not overlap each other in a plane, and the first protrusion (132am) and the second protrusion (132bm) of the second capacitor (132) may not overlap each other in a plane.

[0074] For example, the first protrusion (131am) and the second protrusion (131bm) of the first capacitor (131) may not overlap with the first dielectric layer (131c), and the first protrusion (132am) and the second protrusion (132bm) of the second capacitor (132) may not overlap with the second dielectric layer (132c).

[0075] According to one embodiment of the present invention, the first capacitor electrode (131a) and the second capacitor electrode (131b) of the first capacitor (131) of the galvanic separation element (100) may be formed during the process of forming the lead frame (140). In addition, the first capacitor electrode (132a) and the second capacitor electrode (132b) of the second capacitor (132) may also be formed during the process of forming the lead frame (140) (see FIGS. 4a to 4g).

[0076] Typically, when forming a capacitor between different semiconductor dies, the capacitor can be placed on either layer of the semiconductor dies. In such cases, a separate semiconductor process may be required to form the capacitor. In other words, a semiconductor process may be required to form the capacitor, in addition to the semiconductor process used to form the semiconductor dies. Furthermore, there are limitations to the use of specific processes when forming a galvanic separator.

[0077] However, according to the present invention, if the first capacitor (131) and the second capacitor (132) of the galvanic separation element (100) are formed by the same process using the same material as the lead frame (140), the galvanic separation element (100) having the first capacitor (131) and the second capacitor (132) can be manufactured by post-processing without a separate process.

[0078] As a result, there is no limitation on the process for manufacturing the galvanic separation element (100) according to the present invention, and a process more suitable for the product characteristics can be freely selected.

[0079] FIG. 3 is a cross-sectional view of a galvanic separation element (200) according to another embodiment of the present invention.

[0080] The galvanic separation element (200) illustrated in FIG. 3 may have the same structure as the galvanic separation element (100) illustrated in FIGS. 1 and 2, except for the galvanic separator (130).

[0081] According to one embodiment of the present invention, the galvanic separation element (200) may include a third capacitor (133) and a fourth capacitor (134) that are spaced apart from each other.

[0082] FIG. 3 illustrates that the third capacitor (133) and the fourth capacitor (134) are respectively placed between the first semiconductor die (110) and the second semiconductor die (120), and are placed apart from the first semiconductor die (110) and the second semiconductor die (120).

[0083] According to one embodiment of the present invention, the third capacitor (133) and the fourth capacitor (134) each include a first capacitor electrode (133a, 134a) and a second capacitor electrode (133b, 134b).

[0084] For example, the third capacitor (133) may include a first capacitor electrode (133a) and a second capacitor electrode (133b), and the fourth capacitor (134) may include a first capacitor electrode (134a) and a second capacitor electrode (134b).

[0085] Referring to FIG. 3, the third capacitor (133) includes a first capacitor electrode (133a) and a second capacitor electrode (133b) arranged on the same layer. In addition, the fourth capacitor (134) includes a first capacitor electrode (134a) and a second capacitor electrode (134b) arranged on the same layer.

[0086] For example, the first capacitor electrode (133a) and the second capacitor electrode (133b) of the third capacitor (133) do not overlap each other in a plane. In addition, the first capacitor electrode (134a) and the second capacitor electrode (134b) of the fourth capacitor (134) do not overlap each other in a plane.

[0087] According to one embodiment of the present invention, the third capacitor (133) and the fourth capacitor (134) may be made of the same material and formed by the same process.

[0088] A galvanic separation element (200) according to one embodiment of the present invention may include a third dielectric layer (133c) disposed between a first capacitor electrode (133a) and a second capacitor electrode (133b) of a third capacitor (133). For example, the third dielectric layer (133c) may have a zigzag shape between the first capacitor electrode (133a) and the second capacitor electrode (133b).

[0089] A galvanic separation element (200) according to one embodiment of the present invention may include a fourth dielectric layer (134c) disposed between a first capacitor electrode (134a) and a second capacitor electrode (134b) of a fourth capacitor (134). For example, the fourth dielectric layer (134c) may have a zigzag shape between the first capacitor electrode (134a) and the second capacitor electrode (134b).

[0090] According to one embodiment of the present invention, the third dielectric layer (133c) is disposed spaced apart from the first semiconductor die (110) and the second semiconductor die (120), and the fourth dielectric layer (134c) is disposed spaced apart from the first semiconductor die (110) and the second semiconductor die (120).

[0091] FIG. 3 illustrates a third dielectric layer (133c) being arranged spaced apart from the first semiconductor die (110) and the second semiconductor die (120). FIG. 3 also illustrates a fourth dielectric layer (134c) being arranged spaced apart from the first semiconductor die (110) and the second semiconductor die (120).

[0092] According to one embodiment of the present invention, the first capacitor electrode (133a) and the second capacitor electrode (133b) of the third capacitor (133) each include a plurality of protrusions (133am, 133bm) that are spaced apart from each other. For example, the first capacitor electrode (133a) of the third capacitor (133) includes a plurality of protrusions (133am) that are spaced apart from each other. In addition, the second capacitor electrode (133b) of the third capacitor (133) includes a plurality of protrusions (133bm) that are spaced apart from each other.

[0093] According to one embodiment of the present invention, the first capacitor electrode (134a) and the second capacitor electrode (134b) of the fourth capacitor (134) each include a plurality of protrusions (134am, 134bm) that are spaced apart from each other. For example, the first capacitor electrode (134a) of the fourth capacitor (134) includes a plurality of protrusions (134am) that are spaced apart from each other. In addition, the second capacitor electrode (134b) of the fourth capacitor (134) includes a plurality of protrusions (134bm) that are spaced apart from each other.

[0094] For example, the plurality of protrusions (133am, 133bm) of the first capacitor electrode (133a) and the second capacitor electrode (133b) may be arranged parallel to the first direction. At this time, the first direction means a direction parallel to a straight line connecting the first semiconductor die (110) and the second semiconductor die (120) at the shortest distance. In addition, the plurality of protrusions (134am, 134bm) of the first capacitor electrode (134a) and the second capacitor electrode (134b) may be arranged parallel to the first direction.

[0095] Additionally, the plurality of protrusions (133am) of the first capacitor electrode (133a) are arranged alternately with the plurality of protrusions (133bm) of the second capacitor electrode (133b). The plurality of protrusions (134am) of the first capacitor electrode (134a) are arranged alternately with the plurality of protrusions (134bm) of the second capacitor electrode (134b).

[0096] Figures 4a to 4g are process diagrams showing a manufacturing process of a galvanic separation element according to one embodiment of the present invention.

[0097] The plan views of the galvanic separation elements illustrated in FIGS. 4a to 4g correspond to the plan views of the galvanic separation elements (100) illustrated in FIG. 1.

[0098] A method for manufacturing a galvanic separation element according to one embodiment of the present invention comprises the steps of forming a lead frame (140) having an outer frame (143), a first lower electrode (144a), a second lower electrode (145a), a first upper electrode (144b) and a second upper electrode (145b) extending from the outer frame (143), a step of forming a dielectric material layer (131m) between the first lower electrode (144a) and the first upper electrode (144b) and between the second lower electrode (145a) and the second upper electrode (145b), a step of removing the dielectric material layer (131m) that is not disposed between the first lower electrode (144a) and the first upper electrode (144b) and between the second lower electrode (145a) and the second upper electrode (145b) in a planar manner to form a first capacitor (131) and a second capacitor (132), and a step of forming a first capacitor (131) and a second capacitor (132) spaced apart from each other within the outer frame (143). The method may include a step of forming a first semiconductor die (110) and a second semiconductor die (120) to be placed, a step of connecting the first semiconductor die (110) to a first capacitor (131) and a second capacitor (132) using a first bonding wire (151), and a step of connecting the second semiconductor die (120) to the first capacitor (131) and the second capacitor (132) using a second bonding wire (152), a step of forming a molding part (160) formed within an external frame (143) and surrounding the first semiconductor die (110), the second semiconductor die (120), the first capacitor (131), and the second capacitor (132), and a step of removing the external frame (143) of the lead frame (140).

[0099] Referring to FIG. 4a, a lead frame (140) having an outer frame (143), a first lower electrode (144a) extending from the outer frame (143), a second lower electrode (145a), a first upper electrode (144b), and a second upper electrode (145b) can be formed.

[0100] Although not shown in the drawing, the lead frame (140) may be placed on a metal plate (not shown).

[0101] Referring to FIG. 4A, the lead frame (140) includes a first terminal (141) and a second terminal (142) spaced apart from each other, an outer frame (143) disposed at the outermost edge, a first lower electrode (144a) and a first upper electrode (144b) extending from one side of the outer frame (143), and a second lower electrode (145a) and a second upper electrode (145b) extending from the other side of the outer frame (143). For example, the first upper electrode (144b) may be disposed on the first lower electrode (144a) and may overlap with the first lower electrode (144a). For example, the second upper electrode (145b) may be disposed on the second lower electrode (145a) and may overlap with the second lower electrode (145a).

[0102] Referring to FIG. 4b, a dielectric material layer (131m) can be formed between the first lower electrode (144a) and the first upper electrode (144b) and between the second lower electrode (145a) and the second upper electrode (145b).

[0103] The dielectric material layer (131m) may be disposed not only between the first lower electrode (144a) and the first upper electrode (144b) and between the second lower electrode (145a) and the second upper electrode (145b), but also over the entire area within the outer frame (143). However, one embodiment of the present invention is not limited thereto, and the dielectric material layer (131m) may be disposed only between the first lower electrode (144a) and the first upper electrode (144b) and between the second lower electrode (145a) and the second upper electrode (145b).

[0104] Referring to FIG. 4c, the dielectric material layer (131m) that is not disposed between the first lower electrode (144a) and the first upper electrode (144b) and between the second lower electrode (145a) and the second upper electrode (145b) on a plane may be removed to form the first capacitor (131) and the second capacitor (132). By the process of FIG. 4c, the first capacitor (131) may include the first capacitor electrode (131a) and the second capacitor electrode (131b), and the second capacitor (132) may include the first capacitor electrode (132a) and the second capacitor electrode (132b). In addition, by the process of FIG. 4c, the first dielectric (not shown) can be placed between the first capacitor electrode (131a) and the second capacitor electrode (131b), and the second dielectric (not shown) can be placed between the first capacitor electrode (132a) and the second capacitor electrode (132b) (see FIG. 2).

[0105] The first lower electrode (144a), the first upper electrode (144b), the second lower electrode (145a), and the second upper electrode (145b) illustrated in FIG. 4b may correspond to the first capacitor electrode (131a), the second capacitor electrode (131b), the first capacitor electrode (132a), and the second capacitor electrode (132b) illustrated in FIG. 4c, respectively.

[0106] Referring to FIG. 4d, a first semiconductor die (110) and a second semiconductor die (120) can be formed to be spaced apart from each other within an external frame (143).

[0107] The first semiconductor die (110) and the second semiconductor die (120) may be spaced apart from each other with the first capacitor (131) and the second capacitor (132) interposed therebetween. At this time, the first semiconductor die (110) and the second semiconductor die (120) may be placed on a metal plate (not shown).

[0108] Referring to FIG. 4e, the first semiconductor die (110) can be connected to the first capacitor (131) and the second capacitor (132) using the first bonding wire (151), and the second semiconductor die (120) can be connected to the first capacitor (131) and the second capacitor (132) using the second bonding wire (152).

[0109] Specifically, FIG. 4e illustrates a first semiconductor die (110) being connected to a second capacitor electrode (131b, 132b) through a first bonding wire (151), and a second semiconductor die (120) being connected to a first capacitor electrode (131a, 132a) through a second bonding wire (152). In addition, the first semiconductor die (110) is connected to a first terminal (141) through a third bonding wire (153), and the second semiconductor die (120) is connected to a second terminal (142) through a fourth bonding wire (154).

[0110] Referring to FIG. 4f, a molding portion (160) can be formed within an outer frame (143) and surrounding a first semiconductor die (110), a second semiconductor die (120), a first capacitor (131), and a second capacitor (132).

[0111] The molding portion (160) may surround the upper surface, lower surface, and side surfaces of the first semiconductor die (110) and the second semiconductor die (120), respectively. For example, the molding portion (160) may surround the upper surface, lower surface, and side surfaces of the first capacitor (131) and the second capacitor (132), respectively.

[0112] Referring to FIG. 4g, the outer frame (143) of the lead frame (140) can be removed.

[0113] Even when the outer frame (143) is removed, the first capacitor (131), the second capacitor (132), the first terminal (141) and the second terminal (142) are not removed.

[0114] FIGS. 5A to 5D are process diagrams showing a part of a manufacturing process of a galvanic separation element according to one embodiment of the present invention.

[0115] Specifically, the manufacturing process of the galvanic separation element illustrated in FIGS. 5a to 5d is another example of the manufacturing process of the galvanic separation element illustrated in FIGS. 4a to 4c.

[0116] A method for manufacturing a galvanic separation element according to another embodiment of the present invention comprises the steps of forming a lead frame (140) having an outer frame (143), a first lower electrode (144a) and a second lower electrode (145a) extending from the outer frame (143), a step of forming a dielectric material layer (131m) on the first lower electrode (144a) and the second lower electrode (145a), a step of forming a first upper electrode (144b) and a second upper electrode (145b) connected to the outer frame (143) on the dielectric material layer (131m), a step of removing the dielectric material layer (131m) that is not disposed between the first lower electrode (144a) and the first upper electrode (144b) and between the second lower electrode (145a) and the second upper electrode (145b) in a plane, thereby forming a first capacitor (131) and a second capacitor (132), and a step of forming a first capacitor (131) and a second capacitor (132) spaced apart from each other within the outer frame (143). The method may include a step of forming a first semiconductor die (110) and a second semiconductor die (120) to be placed, a step of connecting the first semiconductor die (110) to the first capacitor (131) and the second capacitor (132) using a first bonding wire (151), and a step of connecting the second semiconductor die (120) to the first capacitor (131) and the second capacitor (132) using a second bonding wire (152), a step of forming a molding part (160) formed within an external frame (143) and surrounding the first semiconductor die (110), the second semiconductor die (120), the first capacitor (131) and the second capacitor (132), and a step of removing the external frame (143) of the lead frame (140).

[0117] Referring to FIG. 5a, a lead frame (140) having an outer frame (143), a first lower electrode (144a) extending from the outer frame (143), and a second lower electrode (145a) can be formed.

[0118] Referring to FIG. 5b, a dielectric material layer (131m) can be formed on the first lower electrode (144a) and the second lower electrode (145a).

[0119] The dielectric material layer (131m) may be disposed not only on the first lower electrode (144a) and the second lower electrode (145a), but may also be disposed over the entire area within the outer frame (143). However, one embodiment of the present invention is not limited thereto, and the dielectric material layer (131m) may be disposed only in the area overlapping the first lower electrode (144a) and the area overlapping the second lower electrode (145a).

[0120] Referring to FIG. 5c, a first upper electrode (144b) and a second upper electrode (145b) connected to an external frame (143) may be formed on a dielectric material layer (131m). For example, the first upper electrode (144b) may be disposed on the first lower electrode (144a) and overlap with the first lower electrode (144a). In addition, the second upper electrode (145b) may be disposed on the second lower electrode (145a) and overlap with the second lower electrode (145a).

[0121] Referring to FIG. 5d, the dielectric material layer (131m) that is not disposed between the first lower electrode (144a) and the first upper electrode (144b) and between the second lower electrode (145a) and the second upper electrode (145b) on a plane may be removed to form a first capacitor (131) and a second capacitor (132). By the process of FIG. 5d, the first capacitor (131) may include a first capacitor electrode (131a) and a second capacitor electrode (131b), and the second capacitor (132) may include a first capacitor electrode (132a) and a second capacitor electrode (132b). In addition, by the process of FIG. 5d, the first dielectric (not shown) can be placed between the first capacitor electrode (131a) and the second capacitor electrode (131b), and the second dielectric (not shown) can be placed between the first capacitor electrode (132a) and the second capacitor electrode (132b) (see FIG. 2).

[0122] Description of the process steps after the process of FIG. 5d is omitted as it is the same as the description of the process illustrated in FIGS. 4d to 4g.

[0123] Figure 6 is a schematic diagram of a power element driving system (10) including a galvanic separation element (100).

[0124] Although FIG. 6 illustrates a power element drive system (10) including the galvanic separation element (100) illustrated in FIGS. 1 and 2, the embodiment of the present invention is not limited thereto, and the power element drive system (10) may also include the galvanic separation element (200) illustrated in FIG. 3.

[0125] Referring to FIG. 6, the power element driving system (10) includes a galvanic isolation element (100), a microcontroller unit (MCU) (300), and a power element (400). The microcontroller unit (300) can transmit a PWM signal (301) to the galvanic isolation element (100) to control the power element (400). At this time, the PWM signal refers to a pulse width modulation (PWM) signal. In addition, in order to confirm whether the power element (400) is operating properly through transmission of the PWM signal (301), a monitoring signal (not shown) for monitoring various sensed signals is transmitted from the galvanic isolation element (100).

[0126] Referring to FIG. 6, the galvanic separation element (100) includes a first semiconductor die (110), a second semiconductor die (120), and a galvanic separator (130). At this time, the first semiconductor die (110) may correspond to a low voltage section, and the second semiconductor die (120) may correspond to a high voltage section.

[0127] The first semiconductor die (110) can receive a PWM signal (301) from a microcontroller unit (300) and output a low-voltage PWM signal (not shown) to a galvanic separator (130).

[0128] The galvanic separator (130) can generate a high-voltage PWM signal (not shown) by boosting a low-voltage PWM signal (not shown) to a high voltage while insulating the first semiconductor die (110) and the second semiconductor die (120) and provide the high-voltage PWM signal (not shown) to the second semiconductor die (120).

[0129] The second semiconductor die (120) can receive a high voltage PWM signal and generate an output signal (302) to provide to the power device (400).

[0130] The present invention described above is not limited to the aforementioned embodiments and the attached drawings, and it will be apparent to those skilled in the art that various substitutions, modifications, and changes are possible without departing from the technical scope of the present invention. Therefore, the scope of the present invention is indicated by the following claims, and all changes or modified forms derived from the meaning, scope, and equivalent concepts of the claims should be interpreted as being included within the scope of the present invention.

Claims

1. A first semiconductor die and a second semiconductor die are arranged spaced apart from each other; and A galvanic separator is disposed between the first semiconductor die and the second semiconductor die, and is disposed spatially spaced from the first semiconductor die and the second semiconductor die. The galvanic separator is a galvanic separator element electrically connected to the first semiconductor die and the second semiconductor die by a first bonding wire and a second bonding wire, respectively.

2. In paragraph 1, The galvanic separator comprises a first capacitor and a second capacitor which are spaced apart from each other, The first capacitor and the second capacitor each include a first capacitor electrode and a second capacitor electrode, A first dielectric layer disposed between the first capacitor electrode and the second capacitor electrode of the first capacitor; and A galvanic separation element further comprising a second dielectric layer disposed between the first capacitor electrode and the second capacitor electrode of the second capacitor.

3. In paragraph 2, A galvanic isolation element, wherein the first dielectric layer is disposed spaced apart from the first semiconductor die and the second semiconductor die, and the second dielectric layer is disposed spaced apart from the first semiconductor die and the second semiconductor die.

4. In paragraph 1, A first terminal connected to the first semiconductor die through a third bonding wire; and A second terminal connected to the second semiconductor die through a fourth bonding wire is included, The voltage applied to the second terminal is greater than the voltage applied to the first terminal, A galvanic separator element wherein the first terminal and the second terminal are made of the same material as the galvanic separator and formed by the same process.

5. In paragraph 1, A galvanic separation element further comprising a molding portion surrounding each of the first semiconductor die, the second semiconductor die, and the galvanic separator.

6. In paragraph 2, The first capacitor electrode and the second capacitor electrode of the first capacitor overlap at least partially in a plane, The first capacitor electrode and the second capacitor electrode of the second capacitor overlap at least partially in a plane, The first capacitor electrode of the first capacitor and the first capacitor electrode of the second capacitor have a first protrusion, and the first protrusion is connected to the second semiconductor die via the second bonding wire, The second capacitor electrode of the first capacitor and the second capacitor electrode of the second capacitor have a second protrusion, and the second protrusion is connected to the first semiconductor die via the first bonding wire, A galvanic separation element in which the first protrusion and the second protrusion do not overlap each other on a plane.

7. In paragraph 6, A first dielectric layer disposed between the first capacitor electrode and the second capacitor electrode of the first capacitor; and Further comprising a second dielectric layer disposed between the first capacitor electrode and the second capacitor electrode of the second capacitor, A galvanic separation element in which the first protrusion and the second protrusion do not overlap with the first dielectric layer and the second dielectric layer on a plane.

8. In paragraph 1, The galvanic separator includes a third capacitor and a fourth capacitor which are spaced apart from each other, The third capacitor and the fourth capacitor each include a first capacitor electrode and a second capacitor electrode, The first capacitor electrode and the second capacitor electrode of the third capacitor are arranged on the same layer, The first capacitor electrode and the second capacitor electrode of the fourth capacitor are arranged on the same layer, The first capacitor electrode and the second capacitor electrode of the third capacitor each include a plurality of protrusions spaced apart from each other, A galvanic separation element, wherein the first capacitor electrode and the second capacitor electrode of the fourth capacitor each include a plurality of protrusions spaced apart from each other.

9. In paragraph 8, A third dielectric layer disposed between the first capacitor electrode and the second capacitor electrode of the third capacitor; and A fourth dielectric layer is disposed between the first capacitor electrode and the second capacitor electrode of the fourth capacitor, A galvanic separation element, wherein the third dielectric layer and the fourth dielectric layer each have a zigzag shape.

10. A step of forming a lead frame having an outer frame, a first lower electrode, a second lower electrode, a first upper electrode, and a second upper electrode extending from the outer frame; A step of forming a dielectric material layer between the first lower electrode and the first upper electrode and between the second lower electrode and the second upper electrode; A step of forming a first capacitor and a second capacitor by removing the dielectric material layer that is not disposed between the first lower electrode and the first upper electrode and between the second lower electrode and the second upper electrode on a plane; A step of forming a first semiconductor die and a second semiconductor die spaced apart from each other within the outer frame; A step of connecting the first semiconductor die to the first capacitor and the second capacitor using a first bonding wire, and connecting the second semiconductor die to the first capacitor and the second capacitor using a second bonding wire; A step of forming a molding part formed within the outer frame and surrounding the first semiconductor die, the second semiconductor die, the first capacitor, and the second capacitor; and A step of removing the outer frame of the lead frame is included, A method for manufacturing a galvanic isolation element, wherein the first capacitor and the second capacitor are disposed between the first semiconductor die and the second semiconductor die, and are disposed spaced apart from each other between the first semiconductor die and the second semiconductor die.

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