Photodiode and manufacturing method therefor, and electronic element

Abstract

Provided in the embodiments of the present application is a photodiode. The photodiode comprises: a first dielectric layer having a first conductive type; a photogenerated minority carrier collecting area, which is stacked on the first dielectric layer, wherein the photogenerated minority carrier collecting area has a second conductive type and has a preset pattern area; and a first pinning layer, which covers the photogenerated minority carrier collecting area, wherein the first pinning layer has the first conductive type.

Description

Photodiode and manufacturing method thereof, and electronic component

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 2023110361823, filed on August 16, 2023, entitled “Photodiode, method for manufacturing the same, and electronic component”, Chinese patent application No. 2023110433821, filed on August 17, 2023, entitled “Photodiode, method for manufacturing the same, and electronic component”, Chinese patent application No. 2023118464029, filed on December 28, 2023, entitled “Photodiode, method for manufacturing the same, and electronic component”, and Chinese patent application No. 2023118464226, filed on December 28, 2023, the entirety of which is hereby incorporated by reference. Technical Field

[0003] The present application relates to the field of semiconductor technology, and in particular to a photodiode and a manufacturing method thereof, and an electronic component. Background Art

[0004] Image sensors often use photodiodes to convert photoelectric signals. During operation, photodiodes may generate dark current, which can affect the desired electrical signal. This dark current is affected by various factors, including the junction area, depletion region width, surface and interface states, and the defect density of the semiconductor material.

[0005] To reduce dark current, some technologies employ a fully depleted diode structure. However, this structure places special demands on the parameters of semiconductor epitaxial materials. This requires specialized adjustment or customization of the semiconductor epitaxial material doping concentration, which incurs high process R&D costs for manufacturers. Furthermore, the resulting dark current level may not meet actual device specifications.

[0006] Prior art often uses pinning structures to suppress dark current and reduce parasitic junction capacitance. However, with the development of image sensors, some photodiodes with very large photosensitive areas can no longer meet the ultra-low dark current requirements of pinning structures alone. While dark current can be suppressed by reducing the width of the depletion region, this will affect the device's quantum efficiency and responsivity.

[0007] Therefore, it is currently difficult to reduce dark current while ensuring the photon quantum efficiency.

[0008] Summary of the Invention

[0009] According to some embodiments, a photodiode, a method for manufacturing the same, and an electronic component are provided.

[0010] An embodiment of the present application provides a photodiode, which includes: a first dielectric layer having a first conductivity type; a photogenerated minority carrier collection region stacked on the first dielectric layer, the photogenerated minority carrier collection region having a second conductivity type, and the photogenerated minority carrier collection region having a preset pattern area; and a first pinning layer covering the photogenerated minority carrier collection region, the first pinning layer having the first conductivity type.

[0011] In some embodiments, the photodiode also includes a collection conductive region stacked on the first dielectric layer; the first dielectric layer has a first region, a second region and a third region, the first region and the third region are separated by the second region, the photogenerated minority carrier collection region is located in the second region, the collection conductive region is located in the first region, and the collection conductive region is connected to the photogenerated minority carrier collection region.

[0012] In some embodiments, the photodiode further includes a first electrode, a second electrode, a first anti-reflection film and a first passivation layer; the first electrode contacts the collecting conductive region, and the second electrode is electrically connected to the first dielectric layer in the third region; the first anti-reflection film is located on the side of the first electrode facing away from the first dielectric layer, and the first passivation layer is located on the side of the first anti-reflection film facing away from the first dielectric layer.

[0013] In some embodiments, the photodiode further includes a second antireflection film and a second passivation layer. The second antireflection film is located on the side of the first dielectric layer facing away from the photogenerated minority carrier collection region, and the second passivation layer is located on the side of the second antireflection film facing away from the first dielectric layer.

[0014] In some embodiments, the preset pattern area includes at least one mesh area, and the ratio of the total area of ​​all mesh areas to the peripheral contour area of ​​the photogenerated minority carrier collection region is in a range of 3% to 80%.

[0015] In some embodiments, the photodiode further includes: a buried layer located between the first dielectric layer and the photogenerated minority carrier collection region along the first direction, the buried layer having a second doping type, and a doping concentration of the buried layer greater than a doping concentration of the photogenerated minority carrier collection region.

[0016] A method for manufacturing a photodiode includes: forming a photominority carrier collection region stacked on a first dielectric layer, wherein the first dielectric layer has a first conductivity type, the photominority carrier collection region has a second conductivity type, and the photominority carrier collection region has a preset pattern area; and forming a first pinning layer covering the photominority carrier collection region, the first pinning layer having the first conductivity type.

[0017] In some embodiments, the method further includes: forming a collection conductive region stacked on the first dielectric layer, the first dielectric layer having a first region, a second region and a third region, the first region and the third region being separated by the second region, the photogenerated minority carrier collection region being located in the second region, the collection conductive region being located in the first region, and the collection conductive region being connected to the photogenerated minority carrier collection region.

[0018] In some embodiments, the method further includes: forming a first electrode contacting the collecting conductive region, forming a second electrode electrically connected to the first dielectric layer in the third region; forming a first anti-reflection film located on the side of the first electrode facing away from the first dielectric layer; and forming a first passivation layer located on the side of the first anti-reflection film facing away from the first dielectric layer.

[0019] In some embodiments, the method further includes: forming a first dielectric layer stacked on the substrate through an epitaxial process; removing the substrate; forming a second anti-reflection film on the side of the first dielectric layer facing away from the photogenerated minority carrier collection region; and forming a second passivation layer on the side of the second anti-reflection film facing away from the first dielectric layer.

[0020] An electronic component is also provided, comprising: a photodiode as described in any one of the above items; and a circuit electrically connected to the photogenerated minority carrier collection region and to the first dielectric layer.

[0021] A photodiode is also provided, which includes: a first dielectric layer having a first conductivity type; a photogenerated minority carrier collection region stacked on the first dielectric layer, the photogenerated minority carrier collection region having a second conductivity type, and the photogenerated minority carrier collection region having a preset pattern area; and a pinning structure, which includes at least a first pinning layer covering the photogenerated minority carrier collection region and a second pinning layer extending into the preset pattern area, and the pinning structure has the first conductivity type.

[0022] In some embodiments, the first dielectric layer includes a first region, a second region, and a third region, wherein the first region and the third region are separated by the second region; and the photogenerated minority carrier collection region is located in the second region.

[0023] In some embodiments, the photodiode further includes a collecting conductive region, a second dielectric layer, a first electrode, and a second electrode; the collecting conductive region is located in the first region, the collecting conductive region is parallel to the photogenerated minority carrier collection region and is connected to the photogenerated minority carrier collection region; the second dielectric layer is located in the third region, the second dielectric layer is parallel to the photogenerated minority carrier collection region, and the second dielectric layer is connected to the first dielectric layer; the first electrode contacts the collecting conductive region; and the second electrode contacts the second dielectric layer.

[0024] In some embodiments, the photodiode further includes a first antireflection film and a first passivation layer. The first antireflection film is located on a side of the first electrode facing away from the first dielectric layer. The first passivation layer is located on a side of the first antireflection film facing away from the first electrode.

[0025] In some embodiments, the photodiode further includes a second antireflection film and a second passivation layer. The second antireflection film is located on the side of the first dielectric layer facing away from the photogenerated minority carrier collection region, and the second passivation layer is located on the side of the second antireflection film facing away from the first dielectric layer.

[0026] In some embodiments, the preset pattern area includes at least one mesh area, and the ratio of the total area of ​​all mesh areas to the peripheral contour area of ​​the photogenerated minority carrier collection region is in a range of 3% to 80%.

[0027] In some embodiments, the photodiode further includes: a buried layer located between the first dielectric layer and the photogenerated minority carrier collection region along the first direction, the buried layer having a second doping type, and a doping concentration of the buried layer greater than a doping concentration of the photogenerated minority carrier collection region.

[0028] A method for manufacturing a photodiode, the method comprising: forming a photo-minority carrier collection region stacked on a first dielectric layer, the first dielectric layer having a first conductivity type, and the photo-minority carrier collection region having a second conductivity type; and forming a pinning structure, the pinning structure comprising at least a first pinning layer covering the photo-minority carrier collection region and a second pinning layer extending into a preset pattern area of ​​the photo-minority carrier collection region, the pinning structure having the first conductivity type.

[0029] In some embodiments, the method further includes: epitaxially forming a first dielectric layer, the first dielectric layer having a first region, a second region and a third region, the first region and the third region being separated by the second region; and forming a photogenerated minority carrier collection region located in the second region, forming a second dielectric layer located in the third region and forming a collection conductive region located in the first region through an epitaxial process and a doping process; wherein the step of forming the pinning structure includes: etching to form a groove penetrating the photogenerated minority carrier collection region; and performing a second ion implantation process to form a first pinning layer, a second pinning layer and a third pinning layer located on the bottom wall of the trench.

[0030] In some embodiments, the method further includes: forming a first electrode electrically connected to the photogenerated minority carrier collection region, forming a second electrode electrically connected to the first dielectric layer; forming a first anti-reflection film located on the side of the first electrode facing away from the first dielectric layer; and forming a first passivation layer located on the side of the first anti-reflection film facing away from the first dielectric layer.

[0031] In some embodiments, a first dielectric layer is stacked on a substrate, and a photogenerated minority carrier collection region is located on a side of the first dielectric layer facing away from the substrate; the method further includes: removing the substrate; forming a second anti-reflection film, the second anti-reflection film being located along the stacking direction on a side of the first dielectric layer facing away from the photogenerated minority carrier collection region; and forming a second passivation layer located on a side of the second anti-reflection film facing away from the first dielectric layer.

[0032] An electronic component is also provided, comprising: the photodiode of any one of the aforementioned items; and a circuit electrically connected to the photogenerated minority carrier collection region and to the first dielectric layer.

[0033] A photodiode includes: a first dielectric layer having a first doping type; a second dielectric layer having a second doping type and extending into the first dielectric layer along a first direction; and a pinning layer extending into the second dielectric layer along the first direction, wherein the pinning layer has the first doping type and the doping concentration of the pinning layer is greater than the doping concentration of the first dielectric layer, and the pinning layer includes a pinning region body and at least one mesh channel corresponding to the second dielectric layer.

[0034] In some embodiments, at least one mesh channel is arranged in an array in a plane perpendicular to the first direction. Along a second direction perpendicular to the first direction, the spacing between two adjacent mesh channels is greater than the size of the mesh channel along the second direction.

[0035] In some embodiments, the ratio of the area of ​​all mesh channels in the vertical plane in the first direction to the area of ​​the pinning region body ranges from 1% to 40%, and the doping concentration of the pinning layer is greater than the doping concentration of the second dielectric layer.

[0036] In some embodiments, the ratio of the area of ​​all mesh channels in the vertical plane in the first direction to the area of ​​the pinning region body ranges from 2.5% to 10%.

[0037] In some embodiments, the photodiode further includes a first contact region, a second contact region, an insulating layer, a first electrode and a second electrode; the first contact region extends into the first dielectric layer along the first direction, the first contact region has a first doping type and a doping concentration greater than the doping concentration of the first dielectric layer; the second contact region extends into the second dielectric layer along the first direction, the second contact region has a second doping type and a doping concentration greater than the doping concentration of the second dielectric layer; the pinning layer includes an electrode window, and the second contact region is located in the electrode window; along a second direction perpendicular to the first direction, the pinning layer protrudes from the second dielectric layer and is electrically connected to the first dielectric layer; the insulating layer is located on the side of the pinning layer facing away from the first dielectric layer along the first direction; the first electrode penetrates the insulating layer along the first direction and is electrically in contact with the first contact region, so as to be electrically connected to the first dielectric layer; the second electrode penetrates the insulating layer along the first direction and is electrically in contact with the second contact region, so as to be electrically connected to the second dielectric layer.

[0038] In some embodiments, the photodiode further includes a first antireflection film, a first passivation layer and a substrate. The first antireflection film and the first passivation layer are stacked in sequence on the side of the insulating layer facing away from the pinning layer. The substrate is located on the side of the first dielectric layer facing away from the pinning layer along the first direction.

[0039] In some embodiments, the photodiode further includes a passivation film, a second antireflection film, and a second passivation layer, which are sequentially stacked on a side of the first dielectric layer facing away from the pinning layer along the first direction.

[0040] In some embodiments, the photodiode further includes a buried layer located between the first dielectric layer and the second dielectric layer along the first direction, the buried layer having the second doping type, and a doping concentration of the buried layer greater than a doping concentration of the second dielectric layer.

[0041] An electronic component is also provided, comprising: a circuit; and the photodiode of any one of the aforementioned items, electrically connected to the circuit.

[0042] A method for manufacturing a photodiode is also provided, the method comprising: forming a first dielectric layer, the first dielectric layer having a first doping type; forming a second dielectric layer extending into the first dielectric layer along a first direction, the second dielectric layer having a second doping type; and forming a pinning layer extending into the second dielectric layer along the first direction, the pinning layer having the first doping type and a doping concentration greater than a doping concentration of the first dielectric layer, the pinning layer comprising a pinning region body and at least one mesh channel corresponding to the second dielectric layer.

[0043] In some embodiments, the doping concentration of the pinned layer is greater than the doping concentration of the second dielectric layer.

[0044] In some embodiments, the step of forming the first dielectric layer includes: providing a substrate, and forming the first dielectric layer on one side of the substrate; the method further includes: removing the substrate; forming an antireflection film on a side of the first dielectric layer facing away from the pinning layer along the first direction; and forming a passivation layer on a side of the antireflection film facing away from the first dielectric layer along the first direction.

[0045] A photodiode includes: a first dielectric layer having a first doping type; a second dielectric layer having a second doping type and extending into the first dielectric layer along a first direction; a pinning structure extending into the second dielectric layer along the first direction, the projection of the pinning structure along the first direction covering a portion of the second dielectric layer, the pinning structure having the first doping type; and a buried layer located between the first dielectric layer and the second dielectric layer along the first direction, the buried layer having the second doping type, and the doping concentration of the buried layer being greater than the doping concentration of the second dielectric layer.

[0046] In some embodiments, the first doping type is one of electron doping and hole doping, and the second doping type is the other of electron doping and hole doping.

[0047] In some embodiments, a projection of the pinned layer along a first direction covers a portion of the buried layer, and the pinned layer protrudes from the second dielectric layer along a second direction perpendicular to the first direction. The doping concentration of the pinned layer is greater than the doping concentration of the first dielectric layer, and the doping concentration of the pinned layer is greater than the doping concentration of the second dielectric layer.

[0048] In some embodiments, the doping concentration of the buried layer is less than the doping concentration of the pinned layer.

[0049] In some embodiments, the photodiode further comprises:

[0050] an insulating layer located on a side of the pinning structure facing away from the second dielectric layer along the first direction,

[0051] The first electrode penetrates the insulating layer and is electrically connected to the second dielectric layer.

[0052] a second electrode penetrating the insulating layer and electrically connected to the first dielectric layer; and a pinning structure electrically connected to the first dielectric layer;

[0053] a first contact region extending into the first dielectric layer and electrically contacting the second electrode, wherein the doping concentration of the first contact region is greater than the doping concentration of the first dielectric layer; and

[0054] The second contact region extends into the second dielectric layer and is in electrical contact with the first electrode. The doping concentration of the second contact region is greater than the doping concentration of the second dielectric layer.

[0055] In some embodiments, the photodiode further includes a substrate, the substrate is located on a side of the first dielectric layer facing away from the second dielectric layer along the first direction, and the substrate has a first doping type.

[0056] In some embodiments, the photodiode further includes a first anti-reflection film and a first passivation layer, and the first anti-reflection film and the first passivation layer are sequentially stacked on a side of the insulating layer facing away from the pinning layer along the first direction.

[0057] In some embodiments, the photodiode further includes a passivation film, a second antireflection film, and a second passivation layer, which are sequentially stacked on a side of the first dielectric layer facing away from the second dielectric layer along the first direction.

[0058] An electronic component is also provided, comprising: a circuit; and the photodiode of any one of the aforementioned items, electrically connected to the circuit.

[0059] A method for manufacturing a photodiode is also provided, the method comprising: forming a first dielectric layer having a first doping type; forming a buried layer extending into the first dielectric layer along a first direction, the buried layer having a second doping type; forming a second dielectric layer extending into the first dielectric layer along the first direction, the second dielectric layer being located on a side of the buried layer facing away from the first dielectric layer along the first direction, the second dielectric layer having the second doping type and a doping concentration less than that of the buried layer; and forming a pinning layer extending into the second dielectric layer along the first direction, the projection of the pinning layer covering a portion of the second dielectric layer, the pinning layer having the first doping type.

[0060] The details of one or more embodiments of the present application are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the present application will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, without paying any creative work, they can also obtain drawings of other embodiments based on these drawings.

[0062] FIG1 is a flow chart of a method for manufacturing a photodiode according to an embodiment;

[0063] FIG2 is a schematic diagram of a photodiode according to an embodiment;

[0064] FIG3 is a cross-sectional view along line AA in FIG2 ;

[0065] FIG4 is a graph showing the relationship between the performance of a typical photodiode and mesh parameters according to various embodiments;

[0066] 5A-5F show the shapes of various preset pattern areas;

[0067] FIG6 is a schematic diagram of a photodiode according to another embodiment;

[0068] Figure 7 is a cross-sectional view along line BB in Figure 6;

[0069] FIG8 is a cross-sectional view of a photodiode according to another embodiment;

[0070] FIG9 is a structural block diagram of an electronic component according to an embodiment;

[0071] FIG10 is a flow chart of a method for manufacturing a photodiode according to an embodiment;

[0072] FIG11 is a schematic diagram of a photodiode according to another embodiment;

[0073] FIG12 is a cross-sectional view along line AA in FIG11;

[0074] FIG13 is a cross-sectional view of a photodiode according to another embodiment;

[0075] FIG14 is a graph showing the relationship between the performance of a photodiode and mesh parameters according to various embodiments;

[0076] FIG15 is a schematic diagram of a photodiode according to another embodiment;

[0077] FIG16 is a cross-sectional view along line BB in FIG15;

[0078] FIG17 is a block diagram of a structure of an electronic component according to an embodiment;

[0079] FIG18 is a schematic diagram of a front-illuminated photodiode according to an embodiment;

[0080] FIG19 is a schematic diagram of a back-illuminated photodiode according to an embodiment;

[0081] FIG20 is a schematic diagram of a front-illuminated photodiode according to another embodiment;

[0082] FIG21 is a block diagram of a structure of an electronic component according to an embodiment;

[0083] FIG22 is a flow chart of a method for manufacturing a photodiode according to an embodiment;

[0084] FIG23 is a schematic diagram of a front-illuminated photodiode according to an embodiment;

[0085] FIG24 is a schematic diagram of a back-illuminated photodiode according to an embodiment;

[0086] FIG25 is a block diagram of a structure of an electronic component according to an embodiment;

[0087] FIG. 26 is a flow chart of a method for manufacturing a photodiode according to an embodiment. DETAILED DESCRIPTION

[0088] To make the above-mentioned objects, features, and advantages of the present application more clearly understood, the specific embodiments of the present application are described in detail below with reference to the accompanying drawings. The following description sets forth many specific details to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways than those described herein, and those skilled in the art can make similar improvements without violating the scope of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0089] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "perpendicular", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0090] In this application, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0091] In addition, the terms "first", "second", "third", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. For example, the first conductivity type may also be referred to as the second conductivity type, and the second conductivity type may also be referred to as the first conductivity type. In the description of this application, "multiple" means at least two, for example, two, three, etc., unless otherwise clearly and specifically defined.

[0092] In this application, unless otherwise clearly specified and limited, the terms "connected", "connect", etc. should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integrated connection; it can be a flexible connection, or a rigid connection along at least one direction; it can be a mechanical connection, or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, or directly connected with the presence of an intermediate medium, or it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. The terms "install", "set", "fix", etc. can be broadly understood as connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0093] As used herein, the terms "layer" and "region" refer to a portion of a material that includes an area with a certain thickness. A layer can extend horizontally, vertically and / or along a tapered surface. A layer can be an area of ​​a uniform or non-uniform continuous structure, and its thickness perpendicular to the extension direction may not be greater than the thickness of the continuous structure. A layer can include multiple layers, which can be stacked layers or discretely extended layers. The shapes of the various regions and layers in the drawings and their relative sizes and positional relationships are only exemplary and may deviate from the actual shapes due to manufacturing tolerances or technical limitations, and the design can be adjusted according to actual needs.

[0094] Referring to FIG. 1 , FIG. 1 illustrates a method for manufacturing a photodiode according to one embodiment. Referring to FIG. 2 and FIG. 6 , this method 1000 can manufacture both front-illuminated and back-illuminated photodiodes 100. The method 1000 for manufacturing a photodiode according to an embodiment of the present application is described in detail below in conjunction with FIG. 2 through FIG. 7 .

[0095] As shown in FIG. 2 and FIG. 3 , in some embodiments, a method 1000 for manufacturing a photodiode includes the following steps.

[0096] In some embodiments, the method 1000 includes the step of forming a dielectric layer 2. Specifically, the step of forming the dielectric layer 2 includes: step S101, providing a substrate 1, and forming a first dielectric layer 21 on the substrate 1; and step S102, forming a second dielectric layer 22 stacked on the first dielectric layer 21.

[0097] The dielectric layer 2 stacked on the substrate 1 can be formed by an epitaxial process. For example, the first dielectric layer 21 and the second dielectric layer 22 can be formed in a one-step deposition process.

[0098] Substrate 1 is made of a semiconductor material, which may include at least one of silicon carbide, silicon, silicon germanium, germanium, and Group III-V compounds such as gallium nitride and gallium arsenide. Substrate 1 has a first conductivity type, which may be a hole-type conductivity type. For example, substrate 1 has a p++ doping type. Dielectric layer 2 may be made of a semiconductor material. Dielectric layer 2 has the first conductivity type, and its doping concentration is lower than that of substrate 1. For example, dielectric layer 2 has a p-type doping type.

[0099] The structure shown in Figure 2 can be part of a photodiode 100. As shown in Figure 2, the stacking direction of the dielectric layer 2 and substrate 1 is approximately parallel to the Z-axis. The dielectric layer 2 has a first region α, a second region β, and a third region γ along the XY plane. Specifically, the first dielectric layer 21 has a first region α, a second region β, and a third region γ. The first region α and the third region γ may be separated by the second region β. The second dielectric layer 22 is located in the second region β. The dielectric layer 2 also includes a third dielectric layer 23 stacked on the first dielectric layer 21 and located in the third region γ. The third dielectric layer 23 can be formed simultaneously with the second dielectric layer 22.

[0100] The method 1000 for manufacturing a photodiode further includes the step of forming a collection layer. Specifically, the step of forming the collection layer includes step S103: forming a photo-generated minority carrier collection region 31. In some embodiments, after forming the dielectric layer 2, an ion implantation process can be used to form the photo-generated minority carrier collection region 31 extending into the dielectric layer 2 (or forming a structure stacked on the first dielectric layer 21). In the embodiments of the present application, the structure formed in each step can serve as a prefabricated structure for subsequent steps. For example, the prefabricated dielectric layer formed before the ion implantation process is the prefabricated dielectric layer, and the dielectric layer 2 shown in FIG. 2 is obtained after the ion implantation process.

[0101] The photogenerated minority carrier collection region 31 has a second conductivity type. The second conductivity type is different from the first conductivity type, for example, the second conductivity type is an electron conductivity type. Exemplarily, the photogenerated minority carrier collection region 31 has an n-type doping type.

[0102] The photogenerated minority carrier collection region 31 has a preset pattern area. In the present embodiment, as shown in FIG2 , the preset pattern area includes at least one mesh area 30. In the present embodiment, there are multiple mesh areas 30, each mesh area 30 is roughly square, and multiple mesh areas 30 are arranged in a matrix. The mesh area 30 can be formed using a mask during the ion implantation process. The main body of the photogenerated minority carrier collection region 31 is connected as one, and the multiple mesh areas 30 can be basically evenly distributed in the photogenerated minority carrier collection region 31 in the XY plane. Exemplarily, the photogenerated minority carrier collection region 31 and the mesh area 30 are both located in the second region β.

[0103] In other embodiments, after forming the first dielectric layer 21, a prefabricated second dielectric layer can be formed using an in-situ doping process. This prefabricated second dielectric layer is then subjected to compensatory doping to obtain a photogenerated minority carrier collection region 31 based on the prefabricated second dielectric layer and a second dielectric layer 22 obtained through this compensatory doping. By way of example, this step also yields a collection conductive region 32 based on the prefabricated second dielectric layer, as well as a first dielectric region located within the third region γ. The first dielectric region may include a third dielectric layer 23 and a fourth dielectric layer 24.

[0104] In some embodiments, the step of forming the collection layer further includes: forming a collection conductive region 32. This sub-step can be performed simultaneously with step S103. The collection conductive region 32 is located in the first region α, and can be integrated with the photogenerated minority carrier collection region 31. Referring to Figure 2, the collection conductive region 32, the photogenerated minority carrier collection region 31, the second dielectric layer 22 and the third dielectric layer 23 are arranged in parallel and are all stacked on the first dielectric layer 21. The second dielectric layer 22 is filled in the mesh area 30 of the photogenerated minority carrier collection region 31. The collection layer and the dielectric layer 2 can realize an n-on-p type optoelectronic semiconductor structure.

[0105] In some existing technologies, discrete point-shaped photoelectron collection regions are used. Although this can also reduce dark current, the photon quantum efficiency will be significantly affected.

[0106] In some embodiments, the method 1000 for manufacturing a photodiode further includes the step of forming a pinning structure 4. Exemplarily, the step of forming the pinning structure 4 includes step S104: forming a first pinning layer 41. In some embodiments, a pinning cover 42 and a pinning protrusion 43 may also be formed simultaneously. The first pinning layer 41 has a first conductivity type. Exemplarily, the first pinning layer 41 has a p++ type doping type. The first pinning layer 41 keeps the boundary of the depletion region 20 of the underlying photoelectric semiconductor structure away from the surface passivation interface region, thereby suppressing the influence of interface states and fixed charges on the performance of the photodiode 100. In addition, the heavy doping concentration of the first pinning layer 41 causes the underlying photogenerated minority carrier collection region 31 to be fully depleted, that is, the width of the depletion region 20 of the photodiode 100 is pinned, thereby effectively clamping the dark current.

[0107] In some embodiments, in step S104, a first pinning layer 41 covering the photogenerated minority carrier collection region 31 may be formed by ion implantation, thereby extending the pinning structure 4 into the dielectric layer 2. The dielectric layer 2 may include a fourth dielectric layer 24 located in the third region γ and parallel to the pinning structure 4.

[0108] The first pinning layer 41 is located in the second region β, and the portion where the collection layer overlaps with the pinning structure 4 can be referred to as the junction region. The outer contour of the second region β can correspond to the outer contour of the junction region; the inner contour of the second region β, i.e., the outer contour of the first region α, can correspond to the inner contour of the junction region. The pinning cover 42 is located in the mesh region 30 and can cover the second dielectric layer 22. The mesh region 30 can also be referred to as the non-junction region. The pinning protrusion 43 protrudes from the photogenerated minority carrier collection region 31 and can extend into the third region γ. The pinning cover 42 and the pinning protrusion 43 help prevent the depletion region 20 from extending to the top surface of the dielectric layer 2.

[0109] In some embodiments, the method 1000 for manufacturing a photodiode further includes the step of forming a contact region. Specifically, the step of forming the contact region includes: forming a first contact region 51. The first contact region 51 is located in the first region α and may extend into the collecting conductive region 32. The first contact region 51 may be spaced apart from the pinning structure 4. Specifically, the two are separated by the collecting conductive region 32. The first contact region 51 may have an n++ type doping type, whose doping concentration is greater than the doping concentration of the collecting conductive region 32, and whose conductive performance is better than the conductive performance of the collecting conductive region 32, so that the first contact region 51 can be used to form an ohmic contact with a metal electrode. The step of forming the contact region further includes: forming a second contact region 52. The second contact region 52 is located in the third region γ and may be connected to the dielectric layer 2 or extend into the fourth dielectric layer 24. The second contact region 52 may be directly connected to the pinning structure 4 or separated from the pinning structure 4. The second contact region 52 may have a p++ type doping type, whose doping concentration is greater than that of the dielectric layer 2 and whose conductivity is better than that of the dielectric layer 2 . Therefore, the second contact region 52 can be used to form a good ohmic contact with the metal electrode.

[0110] In some embodiments, the method 1000 for manufacturing a photodiode further includes the step of forming an electrode structure 6. Specifically, the step of forming the electrode structure 6 includes: first forming an insulating layer (not shown), which is light-transmissive; then performing step S105: forming a first electrode 61; and finally forming a second electrode 62. Specifically, the first electrode 61 is formed to contact the collecting conductive region 32; the second electrode 62 is formed to be located in the third region γ and electrically connected to the first dielectric layer 21; the second electrode 62 can contact the dielectric layer 2. Exemplarily, the first electrode 61 is in ohmic contact with the first contact region 51; the second electrode 62 is in ohmic contact with the second contact region 52. The second electrode 62 can function as an anode, while the first electrode 61 functions as a cathode.

[0111] When a reverse bias voltage exceeding the pinning threshold voltage is applied between the first electrode 61 and the second electrode 62, the photogenerated minority carrier collection region 31 is fully depleted, achieving a localized pinning effect that clamps the dark current. The mesh region 30 is free of depletion regions 20, reducing the effective junction area and further reducing dark current. In areas not covered by the heavily p++-doped pinning structure 4, such as the first region α, the n-type doped collection conductive region 32 remains undepleted, widening the depletion region 20. However, this area is minimal and does not affect the overall dark current level of the photodiode 100.

[0112] In some embodiments, the method 1000 for manufacturing a photodiode further includes: forming a first antireflection film 7 located on the side of the first electrode 61 facing away from the first dielectric layer 21; and forming a first passivation layer 8 located on the side of the first antireflection film 7 facing away from the first dielectric layer 21. The first antireflection film 7 is used to reduce the reflectivity of photons in a specific wavelength band, and the material can be SiO2, Al2O3, HfO2, or Ta2O5. The first passivation layer 8 can be the final passivation layer on the surface, which can be a dense single-layer passivation material layer or a multi-layer passivation material. The materials of the first passivation layer 8 include SiO2, SiON, SiO2 / SiN x etc. At least one.

[0113] The method 1000 for manufacturing a photodiode provided in the above embodiment is easy to implement, wherein a photogenerated minority carrier collection region 31 having a mesh region 30 is formed. The manufactured photodiode 100 can achieve: significantly reducing dark current while minimizing the loss of photoquantum efficiency.

[0114] Compared to existing photodiodes, which have a complete photoelectron collection region but no mesh region, the photodiode manufactured using the method provided in the above embodiment has a dark current reduced by more than 40% while the quantum efficiency is only reduced by about 5%.

[0115] In some embodiments, the area of ​​the entire mesh region 30 is configured to account for 20% to 50% of the outer peripheral area of ​​the photogenerated minority carrier collection region 31. The outer peripheral area of ​​the photogenerated minority carrier collection region 31 is equivalent to the sum of the areas of the second region β and the first region α. ​​By way of example, when the entire mesh region 30 accounts for 20% of the outer peripheral area of ​​the photogenerated minority carrier collection region 31, the dark current is reduced by 45%, and the quantum efficiency in the visible light band is only reduced by approximately 5%. By way of example, when the entire mesh region 30 accounts for 40% of the outer peripheral area of ​​the photogenerated minority carrier collection region 31, the dark current is reduced by more than 70%, and the quantum efficiency in the visible light band is only reduced by approximately 8%.

[0116] Refer to Figure 4, which shows the relationship between the performance of multiple photodiodes and mesh parameters, where the mesh parameters select the mesh duty cycle. Dark current and responsivity data were measured for six embodiments of this application. In the photodiode of the first embodiment, the mesh duty cycle (the ratio of the mesh area to the outer contour area of ​​the photogenerated minority carrier collection region) was 5%; in the photodiode of the second embodiment, the mesh duty cycle was 10%; in the photodiode of the third embodiment, the mesh duty cycle was 20%; in the photodiode of the fourth embodiment, the mesh duty cycle was 40%; in the photodiode of the fifth embodiment, the mesh duty cycle was 60%; and in the photodiode of the sixth embodiment, the mesh duty cycle was 80%. According to the photodiodes of these embodiments, by increasing the mesh duty cycle, dark current is significantly reduced while responsivity remains relatively stable. Responsivity is proportional to quantum efficiency and is an external manifestation of quantum efficiency. Therefore, it can be seen that the quantum efficiency decreases less. For example, in the photodiodes provided by the above embodiments, the mesh duty cycle can be set within the range of 3% to 80%. To ensure responsiveness, the duty cycle can be set within a range of 3% to 60%, such as 10% or 50%. Optionally, the duty cycle can be set within a range of 20% to 40%.

[0117] The preset pattern region shown in FIG2 includes at least one square mesh region 30. In other embodiments, when viewed from the direction in which the dielectric layer 2 and the substrate 1 are stacked (i.e., along a direction parallel to the Z axis), the preset pattern region may also include at least one circular mesh region 30 (see FIG5A ), at least one vertical stripe-shaped mesh region 30 (see FIG5B ), at least one horizontal stripe-shaped mesh region 30 (see FIG5C ), at least one mesh region 30 consisting of at least one short strip and at least one long strip (see FIG5D ), at least one L-shaped mesh region 30 (see FIG5E ), or at least one ╋-shaped mesh region 30 (see FIG5F ), or a combination of the above mesh regions 30. The multiple mesh regions 30 are substantially uniformly distributed in the photogenerated minority carrier collection region 31 within the XY plane. The cross-sectional areas of different mesh regions 30 may also vary.

[0118] 6 and 7 , a method 1000 for manufacturing a photodiode provided in an embodiment of the present application may be used to manufacture a back-illuminated photodiode 100 .

[0119] In some embodiments, after forming the electrode structure 6 , the substrate 1 may be removed. For example, the dielectric layer 2 may be thinned, for example, until the first dielectric layer 21 has a desired thickness, thereby ensuring the integrity of the depletion region 20 .

[0120] The method 1000 further includes forming a second antireflection film 9 on the side of the first dielectric layer 21 facing away from the photogenerated minority carrier collection region 31, and forming a second passivation layer 10 on the side of the second antireflection film 9 facing away from the first dielectric layer 21. The film structure of the second antireflection film 9 can be designed and manufactured according to the requirements of the back-illuminated photodiode 100. The characteristics of the second passivation layer 10 can be referred to the first passivation layer 8 described above and will not be further described.

[0121] For example, the first passivation layer 8 may still be provided on the side of the electrode structure 6 facing away from the dielectric layer 2 .

[0122] 2 and 6 , an embodiment of the present application provides a photodiode 100 . The photodiode 100 can be manufactured using the method of the aforementioned embodiment. The photodiode 100 may include a first dielectric layer 21 , a photogenerated minority carrier collection region 31 , and a first pinning layer 41 .

[0123] The first dielectric layer 21 has a first conductivity type, and the photogenerated minority carrier collection region 31 has a second conductivity type. The first conductivity type is one of a hole type and an electron type, and the second conductivity type is the other of a hole type and an electron type. The photogenerated minority carrier collection region 31 is stacked on the first dielectric layer 21 along the Z-axis direction, and the photogenerated minority carrier collection region 31 has a preset pattern area. In this embodiment, the preset pattern area may be a mesh area 30. Exemplarily, the mesh area 30 may be filled with the second dielectric layer 22. The conductivity type of the second dielectric layer 22 is different from the conductivity type of the photogenerated minority carrier collection region 31. The first pinning layer 41 covers the photogenerated minority carrier collection region 31, and the first pinning layer 41 has the first conductivity type.

[0124] Exemplarily, there are multiple mesh regions 30. The multiple mesh regions 30 can be arranged in an array. The ratio of the total area of ​​all mesh regions 30 to the outer peripheral contour area of ​​the photogenerated minority carrier collection region 31 is in a range of 3% to 80%, for example, 10%, 20%, 40%, or 60%.

[0125] Exemplarily, the first dielectric layer 21 includes a first region α, a second region β, and a third region γ. The first region α and the third region γ are separated by the second region β, and the photogenerated minority carrier collection region 31 is located in the second region β. The photodiode 100 also includes a collection conductive region 32 stacked on the first dielectric layer 21. The collection conductive region 32 is located in the first region α and is integrally connected to the photogenerated minority carrier collection region 31, also achieving electrical conductivity.

[0126] The photodiode 100 further includes a first electrode 61 and a second electrode 62. The first electrode 61 may be located in the first region α and contact the collecting conductive region 32 to achieve electrical conduction. The second electrode 62 may be located in the third region γ and may be indirectly electrically connected to the first dielectric layer 21.

[0127] In the front-illuminated photodiode 100, the photodiode 100 further includes a first antireflection film 7 and a first passivation layer 8. The first antireflection film 7 is located on the side of the first electrode 61 facing away from the first dielectric layer 21. The first antireflection film 7 is used to increase the transmittance of light at the photogenerated minority carrier collection region 31. The first passivation layer 8 is located on the side of the first antireflection film 7 facing away from the first dielectric layer 21.

[0128] In a back-illuminated photodiode 100, the photodiode 100 further includes a second antireflection film 9 and a second passivation layer 10. The second antireflection film 9 is located on the side of the first dielectric layer 21 facing away from the photogenerated minority carrier collection region 31. The second antireflection film 9 can be used to increase the transmittance of light in the second region β. The second passivation layer 10 is located on the side of the second antireflection film 9 facing away from the first dielectric layer 21.

[0129] The photodiode 100 has a low dark current and a high quantum efficiency, and can achieve a performance balance between dark current and quantum efficiency.

[0130] Referring to Figure 8, in one embodiment, the photodiode 100 further includes a buried layer 330. The buried layer 330 is located between the first dielectric layer 21 and the photogenerated minority carrier collection region 31 along the first direction. The buried layer 330 may be attached to the photogenerated minority carrier collection region 31. The buried layer 330 may include a portion located in the second region β. For example, the thickness of the buried layer 330 may be less than the thickness of the photogenerated minority carrier collection region 31, and the thickness of the portion of the buried layer 330 located in the second region β may be less than the thickness of the portion of the photogenerated minority carrier collection region 31 located in the second region β. In other embodiments, the thickness of the buried layer 330 may also be equal to or greater than the thickness of the photogenerated minority carrier collection region 31.

[0131] In some embodiments, along the X-axis, the buried layer 330 has a size comparable to the width of the photogenerated minority carrier collection region 31 and the edges thereof are aligned, so that the projection of the pinning structure 4 along the Y-axis may cover a portion of the buried layer 330 .

[0132] Both the buried layer 330 and the photogenerated minority carrier collection region 31 may have a second doping type, and the doping concentration of the buried layer 330 is greater than the doping concentration of the photogenerated minority carrier collection region 31. The second doping type is one of N-type doping and P-type doping, or one of electron-type doping and hole-type doping. The second doping type is different from the first doping type. In other words, the conductivity type of the buried layer 330 is opposite to that of the first dielectric layer 21.

[0133] The photogenerated minority carrier collection region 31, the buried layer 330, and the first dielectric layer 21 can be used to form a photodetection structure, which can achieve the effect of a photodetection diode. The pinning structure 4, the photogenerated minority carrier collection region 31, and the buried layer 330 can be used to form a pinning structure, which can achieve the effect of a pinned diode. The circuit structure of the pinned diode and the photodetection diode can be a parallel structure. For example, the doping concentration of the buried layer 330 is less than the doping concentration of the pinning structure 4. The two have different doping types, but the performance of the pinned diode can be adjusted by limiting the relationship between the doping concentration values.

[0134] 9 , an embodiment of the present application further provides an electronic component 300 , which includes a photodiode 100 and a circuit 200 .

[0135] The structure of the photodiode 100 can refer to any of the above embodiments and will not be described in detail here. The circuit 200 is electrically connected to the photogenerated minority carrier collection region 31 and the first dielectric layer 21. For example, the circuit 200 is electrically connected to the first electrode 61 and the second electrode 62.

[0136] The circuit performance of the electronic component 300 is stable, and the photodiode 100 thereof can reduce dark current while ensuring a high quantum efficiency level.

[0137] 10 , which shows a flow chart of a method 1000 for manufacturing a photodiode according to an embodiment of the present invention. The method 1000 can be used to manufacture the photodiode 100. The method 1000 includes the following steps.

[0138] Step S101: Forming a first dielectric layer 21. The first dielectric layer 21 has a first conductivity type, which can be either a hole-type conductivity type or an electron-type conductivity type. In this embodiment, the first conductivity type is a hole-type conductivity type. For example, the first dielectric layer 21 has a p-type doping type. Hereinafter, the structure obtained in each step may be referred to as a prefabricated structure for the subsequent step, which can then be processed and adjusted in subsequent steps.

[0139] Step S102: forming a second dielectric layer 22. The second dielectric layer 22 may be an integral structure with the first dielectric layer 21. The second dielectric layer 22 has a first conductivity type.

[0140] Step S103: Forming a photogenerated minority carrier collection region 31 stacked on the first dielectric layer 21. The photogenerated minority carrier collection region 31 has a second conductivity type that is different from the first conductivity type. For example, the photogenerated minority carrier collection region has an n-type doping type. Exemplarily, the photogenerated minority carrier collection region 31 can be formed based on a portion of the prefabricated second dielectric layer structure.

[0141] In other embodiments, after forming the prefabricated photogenerated minority carrier collection region, the second dielectric layer 22 can be formed based on a portion of the prefabricated photogenerated minority carrier collection region. The photogenerated minority carrier collection region 31 and the second dielectric layer 22 are arranged side by side on the first dielectric layer 21.

[0142] Step S104: forming a pinning structure 4. Specifically, the pinning structure 4 includes a first pinning layer 41 covering the photogenerated minority carrier collection region 31 and a second pinning layer 42 extending into the mesh region 30 of the photogenerated minority carrier collection region 31. The pinning structure 4 has a first conductivity type, and illustratively, the pinning structure 4 has a p++ doping type.

[0143] The method 1000 for fabricating a photodiode provided in the above embodiment is easy to implement. A photogenerated minority carrier collection region having a mesh region is formed, and a pinning structure is used to clamp dark current and isolate surface states. The fabricated photodiode can achieve significant reductions in dark current while minimizing loss in photon quantum efficiency.

[0144] The method 1000 for manufacturing a photodiode disclosed in the present disclosure is described in detail below with reference to FIG. 11 to FIG. 15 .

[0145] FIG11 illustrates a photodiode 100 according to an embodiment of the present disclosure. In some embodiments, step S101 includes providing a substrate 1 and forming a first dielectric layer 21 stacked on substrate 1. Step S102 includes forming a second dielectric layer 22 stacked on the first dielectric layer 21. The dielectric layer 2 stacked on substrate 1 can be formed by an epitaxial process. For example, the first dielectric layer 21 and the second dielectric layer 22 can be formed in a single deposition process.

[0146] Substrate 1 is made of a semiconductor material, which may include at least one of silicon carbide, silicon, silicon germanium, germanium, and Group III-V compounds such as gallium nitride and gallium arsenide. Substrate 1 has a first conductivity type, which may be a hole-type conductivity type. For example, substrate 1 has a p++ doping type. Dielectric layer 2 is made of a semiconductor material. Dielectric layer 2 has the first conductivity type, and its doping concentration is lower than that of substrate 1.

[0147] As shown in Figure 11, the stacking direction of the dielectric layer 2 and substrate 1 is parallel to the Z-axis. The dielectric layer 2 has a first region α, a second region β, and a third region γ along the XY plane. Specifically, the first dielectric layer 21 has a first region α, a second region β, and a third region γ. The first region α and the third region γ may be separated by the second region β. The structure shown in Figure 11 can be part of a photodiode 100. The second dielectric layer 22 is located in the third region γ. The dielectric layer 2 also includes a third dielectric layer 23 stacked on the second dielectric layer 22 and located in the third region γ. The third dielectric layer 23 can be formed in a single deposition process with the second dielectric layer 22.

[0148] Method 1000 for manufacturing a photodiode further includes forming a collection layer. Specifically, the collection layer formation step includes: step S103, forming a photogenerated minority carrier collection region 31; and forming a collection conductive region 32. The photogenerated minority carrier collection region 31 has the second conductivity type. Exemplarily, the photogenerated minority carrier collection region 31 has an n-type doping type.

[0149] In some embodiments, a dielectric layer 2 may be formed, and then a first ion implantation process may be performed to form a photogenerated minority carrier collection region 31 extending into the dielectric layer 2. In this embodiment, the aforementioned doping process is achieved through the first ion implantation process. In this embodiment, the structure formed in each step may serve as a prefabricated structure for subsequent steps. For example, a first prefabricated dielectric layer may be formed before the first ion implantation process, and a second prefabricated dielectric layer may be obtained after the first ion implantation process. This second prefabricated dielectric layer may then be further modified when forming the pinning structure 4.

[0150] Specifically, after epitaxially forming the first dielectric layer 21, epitaxially forming a prefabricated second dielectric layer stacked on the first dielectric layer 21 is continued. A first ion implantation process is then used to form the photogenerated minority carrier collection region 31 based on the prefabricated second dielectric layer. The doping concentration distribution of the photogenerated minority carrier collection region 31 formed by the first ion implantation process achieves a peak function distribution. This ensures a uniform and stable structure of the dielectric layer 2, and the formation process of the photogenerated minority carrier collection region 31 is controllable.

[0151] In other embodiments, after forming the first dielectric layer 21, an in-situ doping process can be used to form a prefabricated doping layer (also referred to as a prefabricated photogenerated minority carrier collection region) stacked on the first dielectric layer 21, and then the portion of the prefabricated doping layer located in the third region γ is subjected to compensation doping to obtain a photogenerated minority carrier collection region 31 based on the prefabricated doping layer and a second dielectric layer 22 obtained by the compensation doping. In this embodiment, the aforementioned doping process is achieved through an in-situ doping process or an in-situ epitaxial doping process. The doping concentration distribution of the photogenerated minority carrier collection region 31 by the in-situ epitaxial doping process is uniform. Exemplarily, the portion of the prefabricated doping layer located in the first region α is the collection conductive region 32. The in-situ doping structure of the photogenerated minority carrier collection region 31 is balanced and stable.

[0152] Referring to Figure 12, the photogenerated minority carrier collection region 31 is located in the second region β. The collection conductive region 32 is located in the first region α and can be integrated with the photogenerated minority carrier collection region 31. The photogenerated minority carrier collection region 31 can surround the collection conductive region 32. The collection layer and the dielectric layer 2 can realize an n-on-p type optoelectronic semiconductor structure. The outer contour of the photogenerated minority carrier collection region 31 is the outer contour of the collection layer, and the outer contour area of ​​the photogenerated minority carrier collection region 31 includes the area of ​​the collection conductive region 32.

[0153] In some embodiments, the step of forming the pinning structure 4 includes: etching to form a groove 40; and then forming the pinning structure 4 through a second ion implantation process. This step obtains the pinning structure 4 and defines a preset pattern area. In other words, in the XY plane, the boundary between the pinning structure 4 and the photogenerated minority carrier collection region 31 defines a preset pattern area. In this embodiment, the preset pattern area includes at least one mesh area 30. The photogenerated minority carrier collection region 31 is an integrated structure, and each part is interconnected. In some prior arts, although the use of discrete point-shaped photoelectron collection regions can also reduce dark current, the shrinkage of the depletion region will cause a decrease in the photoquantum efficiency and response speed, that is, the photoquantum efficiency of the diode will be significantly affected.

[0154] The pinning structure 4 includes a first pinning layer 41 and a second pinning layer 42, both of which can be formed simultaneously by a second ion implantation process. The first pinning layer 41 covers the photogenerated minority carrier collection region 31, and the two are stacked along the Z-axis direction. The second pinning layer 42 extends into the mesh region 30. The second pinning layer 42 is located on the sidewalls of the groove 40. The outer contour pattern of the second pinning layer 42 along the XY plane defines the mesh region 30. Exemplarily, the second ion implantation process also forms a third pinning layer 43 located on the bottom wall of the groove 40.

[0155] Pinning structure 4 leaves a window in first region α. ​​The window in pinning structure 4 defines the boundary of first region α and thereby separates photogenerated minority carrier collection region 31 from collection conductive region 32. Pinning structure 4 has a first conductivity type. The heavily doped pinning structure 4 isolates photogenerated minority carrier collection region 31 from surface etching damage, preventing the negative effects of interface states and fixed charges on dark current, and further suppressing dark current.

[0156] The pinning structure 4 may further include a third pinning layer 43 and a pinning protrusion 44. The third pinning layer 43 is located at the bottom wall of the trench 40 and may extend into the first dielectric layer 21. The pinning protrusion 44 protrudes from the photogenerated minority carrier collection region 31 along the extension direction of the photogenerated minority carrier collection region 31, that is, along the XY plane. The pinning protrusion 44 is stacked on the second dielectric layer 22 to prevent the outer contour of the photogenerated minority carrier collection region 31 from being too close to the surface of the semiconductor structure.

[0157] Exemplarily, the step of forming the pinning structure 4 includes: etching to form at least one groove 40 that passes through the photogenerated minority carrier collection region 31, which helps to ensure that the pinning structure 4 passes through the photogenerated minority carrier collection region 31. Optionally, similar to the aforementioned mesh area 30, the cross-sectional shape of the groove 40 can also be at least one of a circle (see FIG5A), a vertical bar (see FIG5B), a horizontal bar (see FIG5C), two short bars plus one long bar (see FIG5D), an "L" shape (see FIG5E), or a "╋" shape (see FIG5F), or a combination thereof. The extension direction of the groove 40 can be parallel to the Z-axis direction or can be inclined relative to the Z-axis direction. The cross-sectional shape of the groove 40 along the extension direction can be cylindrical or a trapezoid with a larger notch. The cross-sectional areas of different grooves 40 can also be different.

[0158] In some embodiments, the perimeter of the etched trench 40 may be spaced apart from the pre-existing photo-generated minority carrier collection region 31. After the pinning structure 4 is formed, since the depth of the pinning structure 4 along the Z-axis is less than this space, it can be connected to the photo-generated minority carrier collection region 31. In other embodiments, the sidewalls of the trench 40 may also expose the pre-fabricated photo-generated minority carrier collection region 31, and then compensatory doping may be performed to obtain the pinning structure 4, with at least a portion of the pinning structure 4 extending into the pre-fabricated photo-generated minority carrier collection region 31 by a certain dimension.

[0159] In other embodiments, during the step of etching to form the trench 40, the trench 40 penetrates the portion of the prefabricated doped layer in the second region β. A second ion implantation process is then performed to form the first pinning layer 41 and the second pinning layer 42. The formation of the pinning structure 4 also provides the photogenerated minority carrier collection region 31.

[0160] Referring to Figure 11 , the dielectric layer 2, the collection layer, and the pinning structure 4 interact to form a depletion region 20 in the semiconductor structure. The first pinning layer 41 distances the boundary of the depletion region 20 below it from the surface passivation interface region, thereby suppressing the effects of interface states and fixed charges on the performance of the photodiode 100. The high doping concentration of the pinning structure 4 fully depletes the photogenerated minority carrier collection region 31, effectively pinning the width of the depletion region 20 of the photodiode 100 and thus effectively suppressing dark current.

[0161] The first pinned layer 41 is located in the second region β. The portion where the collecting layer overlaps with the first pinned layer 41 can be referred to as the junction region. The outer contour of the second region β can correspond to the outer contour of the junction region; the inner contour of the second region β (i.e., the outer contour of the first region α) can correspond to the inner contour of the junction region. The mesh region 30 can also be referred to as the non-junction region. The third pinned layer 43 and the pinning protrusion 44 help prevent the depletion region 20 from extending to the surface of the dielectric layer 2.

[0162] In some embodiments, method 1000 for manufacturing a photodiode further includes the step of forming a contact region. Specifically, the step of forming the contact region includes forming a first contact region 51. The first contact region 51 is located in the first region α and may extend into the collecting conductive region 32. The first contact region 51 and the pinning structure 4 may be separated by the collecting conductive region 32. The first contact region 51 may have an n++ doping type, a doping concentration greater than that of the collecting conductive region 32, and a better conductivity than that of the collecting conductive region 32. The step of forming the contact region further includes forming a second contact region 52. The second contact region 52 is located in the third region γ and may be connected to the dielectric layer 2 or extend into the third dielectric layer 23. The second contact region 52 may be directly connected to the pinning structure 4 or spaced apart. The second contact region 52 may have a p++ doping type, a doping concentration greater than that of the dielectric layer 2, and a better conductivity than that of the dielectric layer 2.

[0163] In some embodiments, the method 1000 for manufacturing a photodiode includes the step of forming an electrode structure 6. Specifically, the step of forming the electrode structure 6 includes: forming an insulating layer (not shown). The insulating layer is light-transmissive and can fill the trench 40. The step of forming the electrode structure 6 also includes S105: forming a first electrode 61 and forming a second electrode 62. Exemplarily, a first electrode 61 is formed to contact the collecting conductive region 32; a second electrode 62 is formed in the third region γ to be electrically connected to the first dielectric layer 21, and the second electrode 62 can contact the dielectric layer 2. Exemplarily, the first electrode 61 is in ohmic contact with the first contact region 51; the second electrode 62 is in ohmic contact with the second contact region 52. The second electrode 62 can serve as an anode, while the first electrode 61 serves as a cathode.

[0164] When a reverse bias voltage exceeding the pinning threshold voltage is applied between the first electrode 61 and the second electrode 62, the photogenerated minority carrier collection region 31 is fully depleted, achieving a local pinning effect that can clamp the dark current. The absence of the depletion region 20 in the mesh region 30 reduces the effective junction area and further reduces the dark current. In areas not covered by the heavily p++ doped pinning structure 4, such as the first region α, the n-type doped collection conductive region 32 is not depleted, and the depletion region 20 widens. However, this area is very small and does not affect the overall dark current level of the photodiode 100.

[0165] In some embodiments, the method 1000 for manufacturing a photodiode further includes: forming a first antireflection film 7 located on the side of the first electrode 61 facing away from the first dielectric layer 21; and forming a first passivation layer 8 located on the side of the first antireflection film 7 facing away from the first dielectric layer 21. The first antireflection film 7 is used to reduce the reflectivity of photons in a specific wavelength band, and the material can be SiO2, Al2O3, HfO2, or Ta2O5. The first passivation layer 8 can be the final passivation layer on the surface, which can be a dense single-layer passivation material layer or a multi-layer passivation material. The materials of the first passivation layer 8 include SiO2, SiON, SiO2 / SiN x etc. At least one.

[0166] The above-mentioned method 1000 for manufacturing a photodiode is easy to implement, wherein a photominority carrier collection region 31 having a mesh region 30 is formed, and a first pinning layer 41 covering the photominority carrier collection region 31 and a second pinning layer 42 extending into the photominority carrier collection region 31 along the stacking direction are formed. The manufactured photodiode 100 can achieve: significantly reducing dark current while minimizing the loss of photoquantum efficiency.

[0167] Compared to existing photodiodes, which have a complete photoelectron collection region but no mesh region, the photodiode 100 manufactured using the method provided in the present disclosure can reduce dark current by more than 70%, while reducing quantum efficiency by only about 7%.

[0168] In some embodiments, the area of ​​the entire mesh region 30 accounts for 3% to 80% of the outer peripheral area of ​​the photogenerated minority carrier collection region 31. The outer peripheral area of ​​the photogenerated minority carrier collection region 31 is equivalent to the sum of the areas of the second region β and the first region α. ​​For example, when the entire mesh region 30 accounts for 20% of the outer peripheral area of ​​the photogenerated minority carrier collection region 31, the dark current is reduced by 45%, and the quantum efficiency in the visible light band is only reduced by approximately 5%. For example, when the entire mesh region 30 accounts for 40% of the outer peripheral area of ​​the photogenerated minority carrier collection region 31, the dark current is reduced by more than 70%, and the quantum efficiency in the visible light band is only reduced by approximately 7%.

[0169] Referring to Figure 13, in one embodiment, the photodiode 100 further includes a buried layer 330. The buried layer 330 is located between the first dielectric layer 21 and the photogenerated minority carrier collection region 31 along the first direction. The buried layer 330 may be attached to the photogenerated minority carrier collection region 31. The buried layer 330 may include a portion located in the second region β. For example, the thickness of the buried layer 330 may be less than the thickness of the photogenerated minority carrier collection region 31, and the thickness of the portion of the buried layer 330 located in the second region β may be less than the thickness of the portion of the photogenerated minority carrier collection region 31 located in the second region β. In other embodiments, the thickness of the buried layer 330 may also be equal to or greater than the thickness of the photogenerated minority carrier collection region 31.

[0170] In some embodiments, along the X-axis, the buried layer 330 has a size comparable to the width of the photogenerated minority carrier collection region 31 and the edges thereof are aligned, so that the projection of the pinning structure 4 along the Y-axis may cover a portion of the buried layer 330 .

[0171] Both the buried layer 330 and the photogenerated minority carrier collection region 31 may have a second doping type, and the doping concentration of the buried layer 330 is greater than the doping concentration of the photogenerated minority carrier collection region 31. The second doping type is one of N-type doping and P-type doping, or one of electron-type doping and hole-type doping. The second doping type is different from the first doping type. In other words, the conductivity type of the buried layer 330 is opposite to that of the first dielectric layer 21.

[0172] The photogenerated minority carrier collection region 31, the buried layer 330, and the first dielectric layer 21 can be used to form a photodetection structure, which can achieve the effect of a photodetection diode. The pinning structure 4, the photogenerated minority carrier collection region 31, and the buried layer 330 can be used to form a pinning structure, which can achieve the effect of a pinned diode. The circuit structure of the pinned diode and the photodetection diode can be a parallel structure. For example, the doping concentration of the buried layer 330 is less than the doping concentration of the pinning structure 4. The two have different doping types, but the performance of the pinned diode can be adjusted by limiting the relationship between the doping concentration values.

[0173] Refer to Figure 14, which shows the relationship between the performance of multiple photodiodes and mesh parameters, where the mesh parameters select the mesh duty cycle. Dark current data and internal quantum efficiency data were measured for six embodiments of the present disclosure. In the photodiode of the first embodiment, the mesh duty cycle (the ratio of the mesh area to the outer contour area of ​​the photogenerated minority carrier collection region) was 5%; in the photodiode of the second embodiment, the mesh duty cycle was 10%; in the photodiode of the third embodiment, the mesh duty cycle was 20%; in the photodiode of the fourth embodiment, the mesh duty cycle was 40%; in the photodiode of the fifth embodiment, the mesh duty cycle was 60%; and in the photodiode of the sixth embodiment, the mesh duty cycle was 80%. According to the photodiodes of these embodiments, by increasing the mesh duty cycle, dark current is significantly reduced while the internal quantum efficiency remains relatively stable. For example, in the photodiodes provided by the above embodiments, the mesh duty cycle can be set within a range of 3% to 80%. To ensure responsiveness, it can be set within a range of 10% to 60%. Optionally, the mesh duty cycle may be set within a range of 20% to 40%.

[0174] 15 and 16 , a method 1000 for manufacturing a photodiode provided in one embodiment may be used to manufacture a back-illuminated photodiode 100 .

[0175] In some embodiments, after forming the electrode structure 6 , the substrate 1 may be removed. For example, the dielectric layer 2 may be thinned, for example, until the first dielectric layer 21 has a desired thickness, for example, to ensure that the depletion region 20 is intact.

[0176] The method 1000 further includes forming a second antireflection film 9 on the side of the first dielectric layer 21 facing away from the photogenerated minority carrier collection region 31, and forming a second passivation layer 10 on the side of the second antireflection film 9 facing away from the first dielectric layer 21. The film structure of the second antireflection film 9 can be designed and manufactured according to the requirements of the back-illuminated photodiode 100. The characteristics of the second passivation layer 10 can be referred to the first passivation layer 8 described above and will not be further described.

[0177] For example, the first passivation layer 8 may still be provided on the side of the electrode structure 6 facing away from the dielectric layer 2 .

[0178] 11 and 15 , an embodiment of the present disclosure provides a photodiode 100 . The photodiode 100 can be manufactured using the method of the aforementioned embodiment. The photodiode 100 may include a first dielectric layer 21 , a photogenerated minority carrier collection region 31 , and a pinning structure 4 .

[0179] The first dielectric layer 21 has a first conductivity type, and the photogenerated minority carrier collection region 31 has a second conductivity type. The first conductivity type is one of a hole type and an electron type, and the second conductivity type is the other of the hole type and the electron type. The photogenerated minority carrier collection region 31 is stacked on the first dielectric layer 21 along the Z-axis direction and has a mesh region 30. The pinning structure 4 includes a first pinning layer 41 covering the photogenerated minority carrier collection region 31 and a second pinning layer 42 extending into the mesh region 30. The pinning structure 4 has the first conductivity type.

[0180] For example, there are multiple mesh regions 30. The multiple mesh regions 30 can be arranged in an array. The ratio of the total area of ​​all mesh regions 30 to the outer contour area of ​​the photogenerated minority carrier collection region 31 is in the range of 20% to 50%.

[0181] Illustratively, the first dielectric layer 21 includes a first region α, a second region β, and a third region γ. The first region α and the third region γ are separated by the second region β, and the photogenerated minority carrier collection region 31 is located in the second region β. The photodiode 100 also includes a collection conductive region 32 stacked on the first dielectric layer 21. The collection conductive region 32 is located in the first region α and is integrally connected to the photogenerated minority carrier collection region 31, also achieving electrical conductivity.

[0182] The photodiode 100 further includes a first electrode 61 and a second electrode 62. The first electrode 61 may be located in the first region α and contact the collecting conductive region 32 to achieve electrical conduction. The second electrode 62 may be located in the third region γ and may be indirectly electrically connected to the first dielectric layer 21. The second electrode 62 contacts the second dielectric layer 22.

[0183] In the front-illuminated photodiode 100, the photodiode 100 further includes a first antireflection film 7 and a first passivation layer 8. The first antireflection film 7 is located on the side of the first electrode 61 facing away from the first dielectric layer 21 and is used to increase the transmittance of light in the photogenerated minority carrier collection region 31. The first passivation layer 8 is located on the side of the first antireflection film 7 facing away from the first dielectric layer 21.

[0184] In the back-illuminated photodiode 100, the photodiode 100 further includes a second antireflection film 9 and a second passivation layer 10. The second antireflection film 9 is located on the side of the first dielectric layer 21 facing away from the photogenerated minority carrier collection region 31 and can be used to increase the transmittance of light in the second region β. The second passivation layer 10 is located on the side of the second antireflection film 9 facing away from the first dielectric layer 21.

[0185] The photodiode 100 provided in this embodiment has a low dark current and a high quantum efficiency, and can achieve a performance balance between dark current and quantum efficiency.

[0186] 17 , an embodiment of the present application further provides an electronic component 300 , which includes a photodiode 100 and a circuit 200 .

[0187] The structure of the photodiode 100 can refer to any of the above embodiments and will not be described in detail here. The circuit 200 is electrically connected to the photogenerated minority carrier collection region 31 and the first dielectric layer 21. For example, the circuit 200 is electrically connected to the first electrode 61 and the second electrode 62.

[0188] The electronic component 300 has stable circuit performance and good photoelectric conversion efficiency.

[0189] Referring to FIG. 18 , FIG. 18 illustrates a photodiode 100 according to one embodiment. This photodiode 100 may be a front-illuminated photodiode. Photodiode 100 includes a first dielectric layer 21, a second dielectric layer 22, and a pinning structure 4 stacked sequentially along the Z-axis. For example, the Z-axis in FIG. 18 may be a first direction.

[0190] The photodiode 100 can be a one-piece structure. For example, its upper surface in FIG18 can be referred to as the front surface, and its lower surface can be referred to as the back surface. It should be understood that the designations of front and back are for convenience and do not necessarily limit or imply the posture of the photodiode 100 during manufacture or use. The photodiode 100 can have a first region A, a second region B, and a third region C in the XY plane. The first dielectric layer 21, the second dielectric layer 22, and the pinning structure 4 are stacked at least in the first region A.

[0191] The first dielectric layer 21 may have a first doping type. The first doping type is one of N-type doping and P-type doping, or one of electron doping and hole doping. In this embodiment, the first doping type is hole doping. The second dielectric layer 22 may have a second doping type, which is different from the first doping type. In other words, the conductivity type of the second dielectric layer 22 is opposite to that of the first dielectric layer 21.

[0192] In the first region A and the third region C, the first dielectric layer 21 and the second dielectric layer 22 can be stacked along the Z-axis, forming a pn junction to form a photodetection structure and realize the function of a photodetection diode. For example, overall, the second dielectric layer 22 extends into the first dielectric layer 21, and the upper surface of the first dielectric layer 21 in the second region B can be coplanar with the upper surface of the second dielectric layer 22.

[0193] The pinning structure 4 has a first doping type. Exemplarily, the doping concentration of the pinning structure 4 is greater than the doping concentration of the first dielectric layer 21. The doping concentration herein may refer to an effective doping concentration. The pinning structure 4 and the second dielectric layer 22 may constitute a pinning structure, which may function as a pinned diode. Exemplarily, the doping concentration of the pinning structure 4 is greater than the doping concentration of the second dielectric layer 22 to ensure that the pinning structure 4 pins the second dielectric layer 22. The pinning diode and the photodetection diode may be connected in parallel.

[0194] As shown in FIG18 , the pinning structure 4 includes a pinning region body 431 and at least one mesh channel 432 corresponding to the second dielectric layer 22. The pinning structure 4 extends into the second dielectric layer 22 along a first direction. For example, the pinning region body 431 extends into the second dielectric layer 22 and is stacked with and electrically connected to the first portion 221 of the second dielectric layer 22. The mesh channel 432 is configured to accommodate the second portion 222 of the second dielectric layer 22. The upper surface of the second portion 222 can be coplanar with the upper surface of the pinning region body 431.

[0195] As shown in FIG18 , according to the above-described photodiode 100, a depletion region 20 can be formed by integrating a photodetector diode and a local pinning diode. Due to the high doping concentration of the pinning region body 431, the boundary of the depletion region 20 is located away from the front surface of the pinning structure 4, thereby suppressing the impact of interface states and surface recombination on the performance of the photodiode 100. The portion of the first portion 221 of the second dielectric layer 22 corresponding to the pinning region body 431 can be fully depleted, while the depletion region 20 barely extends into the second portion 222. The portion of the first portion 221 corresponding to the mesh channel 432 can form an island-like region. This island-like region is surrounded by the depletion region 20 in a plane perpendicular to the Z-axis. Within the first dielectric layer 21, the portion corresponding to the mesh channel 432 can achieve a wider depletion region width, namely, the boundary of the depletion region 20 corresponding to the mesh channel 432 is more prominent than the boundary corresponding to the pinning region body 431. The increased width of the depletion region 20 enhances the local quantum efficiency of the photodiode 100.

[0196] The above-mentioned photodiode 100 achieves an improvement in quantum efficiency while the dark current does not increase significantly.

[0197] Alternatively, the material of the photodiode 100 may include at least one of silicon carbide, silicon, silicon germanium, germanium, group III-V compounds such as indium arsenide and gallium arsenide, and group II-VI compounds.

[0198] Illustratively, the pinning structure 4 includes a plurality of mesh channels 432. The plurality of mesh channels 432 are distributed in a plane perpendicular to the Z-axis, for example, discretely distributed. The pinning region body 431 can be a one-piece structure or comprise a partial structure. The mesh channels 432 can be arranged based on the shape and overall extent of the second dielectric layer 22 and the shape and overall extent of the pinning structure 4.

[0199] Optionally, the plurality of mesh channels 432 are arranged in an array in a plane perpendicular to the Z-axis direction (i.e., the XY plane). As shown in FIG18 , the plurality of mesh channels 432 can form a rectangular array, i.e., some mesh channels 432 can be arranged in rows along the X-axis direction, and other mesh channels 432 can be arranged in columns along the Y-axis direction. Along any arrangement direction, the distance between any two adjacent mesh channels 432 can be the same or different. In other embodiments, the distribution of the plurality of mesh channels 432 can also be other methods, such as a honeycomb arrangement. The photodiode 100 can achieve higher quantum efficiency and have balanced and stable electrical properties.

[0200] Exemplarily, the mesh channel 432 may have a rectangular outline in the XY plane. The length direction of the side of the rectangular outline may be along the X-axis direction or the Y-axis direction. The cross-sectional areas of different mesh channels 432 may be different. In other embodiments, the mesh channel 432 may have a non-concave shape that can be realized by any semiconductor process. In addition, in other embodiments, similar to the aforementioned mesh area 30, the cross-sectional shape of the mesh channel 432 may also be at least one of a circle (see FIG. 5A ), a vertical bar shape (see FIG. 5B ), a horizontal bar shape (see FIG. 5C ), two short bars plus one long bar shape (see FIG. 5D ), an “L” shape (see FIG. 5E ), or a “╋” shape (see FIG. 5F ), or a combination thereof.

[0201] Illustratively, along a second direction perpendicular to the first direction, for example, along the X-axis direction perpendicular to the Z-axis direction, the pinning structure 4 protrudes from the second dielectric layer 22 and extends into the first dielectric layer 21. The pinning structure 4 can be electrically connected to the first dielectric layer 21. The mesh channel 432 corresponds to the second dielectric layer 22. Illustratively, within a plane perpendicular to the Z-axis direction, a gap is left between the mesh channel 432 and the boundary of the second dielectric layer 22 to ensure that the island region is located in the second dielectric layer 22.

[0202] Optionally, along a second direction perpendicular to the first direction, the spacing between two adjacent mesh channels 432 may be greater than the size of the mesh channels 432 along the second direction, but the present invention is not limited thereto. In other embodiments, the plurality of mesh channels 432 may include adjacent mesh channels 432, and the spacing between two adjacent mesh channels 432 may be less than or equal to the size of the mesh channels 432 along the second direction. By controlling the size of the pinning region body 431, the dark current clamping effect can be enhanced.

[0203] Illustratively, the ratio of the area of ​​all mesh channels 432 in a plane perpendicular to the first direction to the area of ​​the pinning region body 431 ranges from 1% to 40%. Exemplarily, this ratio can range from 2.5% to 10%, for example, approximately 3%, 5%, or 8%. In other embodiments, the ratio of the projected area of ​​all mesh channels 432 in a plane perpendicular to the first direction to the projected area of ​​the second dielectric layer 22 can range from 2.5% to 10%. Alternatively, the area ratio of a single mesh channel 432 to the second dielectric layer 22 can range from 1% to 2.5%, for example; however, other smaller or larger values ​​are also possible.

[0204] As shown in FIG18 , the photodiode 100 further includes an interconnect layer 60. The interconnect layer 60 is located on the side of the pinning structure 4 facing away from the second dielectric layer 22 along the Z-axis. The interconnect layer 60 may be a multilayer structure. For example, the interconnect layer 60 may include an insulating layer 90, a first electrode 61, and a second electrode 62. The insulating layer 90 may be made of an insulating material, while the first electrode 61 and the second electrode 62 may be made of a metal. The first electrode 61 and the second electrode 62 may each include a conductive pattern extending in a plane perpendicular to the Z-axis and a conductive channel extending along the Z-axis. The conductive pattern may be electrically connected to a plurality of conductive channels, which may be used to make ohmic contacts with the semiconductor structure.

[0205] The first electrode 61 can be electrically connected to the portion of the first dielectric layer 21 located in the second region B. The first electrode 61 can be electrically connected to the pinning structure 4 through the first dielectric layer 21. The second electrode 62 is electrically connected to the second dielectric layer 22. For example, the pinning structure 4 includes an electrode window 433, which can be located in the third region C. The second dielectric layer 22 includes a third portion 223 located within the electrode window 433. The second electrode 62 can be electrically connected to the electrode window 433. The electrode window 433 can be located at the center of the pinning structure 4, or at a location corresponding to the center of the second dielectric layer 22. The mesh channel 432 and the electrode window 433 are separated by the pinning region body 431.

[0206] Illustratively, the photodiode 100 further includes a first contact region 51 and a second contact region 52. The first contact region 51 extends into the first dielectric layer 21 along the Z-axis direction. The first contact region 51 has a first doping type and a doping concentration greater than that of the first dielectric layer 21. In other words, the first contact region 51 may be heavily doped. The second contact region 52 extends into the second dielectric layer 22 along the Z-axis direction. The second contact region 52 has a second doping type and a doping concentration greater than that of the second dielectric layer 22. In other words, the second contact region 52 may be heavily doped. The second contact region 52 is located within the electrode window 433.

[0207] The first electrode 61 may penetrate the insulating layer 90 along a first direction. The first electrode 61 may be in ohmic contact with the first contact region 51 to be electrically connected to the first dielectric layer 21. The second electrode 62 may penetrate the insulating layer 90 along a first direction. The second electrode 62 may be in ohmic contact with the second contact region 52 to be electrically connected to the second dielectric layer 22. A reverse bias voltage exceeding the pinning threshold voltage may be applied to the semiconductor structure via the first electrode 61 and the second electrode 62 to form the depletion region 20.

[0208] As shown in FIG18 , the photodiode 100 further includes a substrate 1. The substrate 1 is located on the side of the first dielectric layer 21 facing away from the pinning structure 4 along the Z-axis. The substrate 1 may have a first doping type, and its doping concentration may be greater than that of the first dielectric layer 21. The photodiode 100 can generate an electrical signal in response to light incident from the front. Due to the provision of the mesh channels 432, the depletion region 20 is locally widened, thereby enhancing the local quantum efficiency. Consequently, the photodiode 100 exhibits high quantum efficiency and low dark current.

[0209] Illustratively, the first dielectric layer 21 has p-type doping, the second dielectric layer 22 has n-type doping, and the pinning structure 4 has p++-type doping. Illustratively, the first contact region 51 has p++-type doping, the second contact region has n++-type doping, and the substrate 1 may have p+-type doping. The photodiode 100 of this embodiment has an np structure, the first electrode 61 may be an anode electrode, and the second electrode 62 may be a cathode electrode. In other embodiments, the photodiode 100 may also be formed as a pn structure.

[0210] For example, the photodiode 100 further includes a first antireflection film (not shown) and a first passivation layer (not shown). For a front-illuminated photodiode 100, the first antireflection film and the first passivation layer can be stacked sequentially on the interconnect layer 60, i.e., on the side of the interconnect layer 60 facing away from the pinning structure 4. The first antireflection film helps improve light transmittance, and the first passivation layer can be used to protect the functional layers underneath.

[0211] As shown in Figure 19, Figure 19 shows a photodiode 100 according to another embodiment, which is a back-incident type. In some embodiments, compared to the front-incident type photodiode 100 shown in Figure 18, the photodiode 100 shown in Figure 19 can omit the substrate 1, and the first dielectric layer 21 can be thinner.

[0212] Passivation layers may be provided on both the front and back surfaces of the photodiode 100. Exemplarily, the photodiode 100 further includes a second passivation layer 10. The second passivation layer 10 is located on the side of the first dielectric layer 21 facing away from the pinning structure 4 along the Z-axis. The photodiode 100 may generate an electrical signal in response to light passing through the second passivation layer 10. Exemplarily, the photodiode 100 further includes a second antireflection film (not shown), which may be located between the second passivation layer 10 and the first dielectric layer 21.

[0213] Exemplarily, the photodiode 100 further includes a passivation film (not shown). The passivation film, the second antireflection film, and the second passivation layer 10 may be stacked sequentially in a direction away from the first dielectric layer 21 and away from the second dielectric layer 22. A shallow interface heavily P+ doped region may be included between the passivation film and the first dielectric layer 21. The passivation film is a SiO2 / Al2O3 composite passivation film system that can introduce fixed negative charges. This prevents the depletion region of the pn junction from contacting the passivation interface, thereby reducing the impact of interface states on the dark current performance of the photodiode 100.

[0214] 20 , which shows a photodiode 100 according to another embodiment, the photodiode 100 further includes a buried layer 330 .

[0215] The buried layer 330 is located between the first dielectric layer 21 and the second dielectric layer 22 along the first direction. The buried layer 330 may be attached to the second dielectric layer 22. The buried layer 330 may include a portion located in the second region B and may also include a portion located in the first region A. For example, the thickness of the buried layer 330 may be less than the thickness of the second dielectric layer 22, and the thickness of the portion of the buried layer 330 located in the second region B may be less than the thickness of the portion of the second dielectric layer 22 located in the second region B. For example, the thickness of the buried layer 330 may also be equal to or thicker than the thickness of the second dielectric layer 22.

[0216] In some embodiments, along the X-axis, the buried layer 330 has a size comparable to the width of the second dielectric layer 22 and its edges are aligned, so that the projection of the pinning structure 4 along the Y-axis can cover a portion of the buried layer 330 .

[0217] Both the buried layer 330 and the second dielectric layer 22 may have a second doping type, and the doping concentration of the buried layer 330 is greater than the doping concentration of the second dielectric layer 22. The second doping type is one of N-type doping and P-type doping, or one of electron doping and hole doping. The second doping type is different from the first doping type. In other words, the conductivity type of the buried layer 330 is opposite to that of the first dielectric layer 21. Exemplarily, the doping concentration of the second dielectric layer 22 is at a low level, similar to that of an intrinsic semiconductor.

[0218] The second dielectric layer 22, the buried layer 330, and the first dielectric layer 21 can be used to form a photodetection structure, which can realize the function of a photodetection diode. The pinning structure 4, the second dielectric layer 22, and the buried layer 330 can be used to form a pinning structure, which can realize the function of a pinning diode. The circuit structure of the pinning diode and the photodetection diode can be a parallel structure. For example, the doping concentration of the buried layer 330 is lower than the doping concentration of the pinning structure 4. The two have different doping types, but the performance of the pinning diode can be adjusted by limiting the relationship between the doping concentration values.

[0219] Referring to FIG. 21 , one embodiment further provides an electronic component 300, which may include: a circuit 200 and a photodiode 100. The photodiode 100 may be the photodiode 100 provided in the aforementioned embodiment, and is electrically connected to the circuit 200. For example, the first electrode 61 and the second electrode 62 may be electrically connected to the circuit 200, respectively. The electronic component 300 may realize a photoelectric effect. For example, the photodiode 100 generates a photocurrent signal based on a light signal, and the circuit 200 may collect the photocurrent signal and then perform processing such as integration, amplification, and analog-to-digital conversion on the photocurrent signal. The electronic component 300 may realize a digitized electrical signal output of the light signal.

[0220] 22 , an embodiment further provides a method 1000 for manufacturing a photodiode. The method 1000 may include the following steps S101 to S103 .

[0221] Step S101: Form a first dielectric layer. The first dielectric layer has a first doping type. For example, the first dielectric layer can be formed by epitaxial growth on a substrate followed by ion implantation. In other embodiments, the first dielectric layer can be epitaxially grown on a substrate and in-situ doped. The first dielectric layer can be formed by layering.

[0222] Step S102: Forming a second dielectric layer. In some embodiments, the second dielectric layer having the second doping type can be formed by ion implantation. The second dielectric layer extends into the first dielectric layer along the Z-axis. It should be understood that the term "extend" herein refers to an overall trend and does not exclude situations such as tilted implantation.

[0223] Step S103, forming a pinning layer. A pinning layer extending into the second dielectric layer along the first direction can be formed by an ion implantation process. The pinning layer includes a pinning region body and a mesh channel corresponding to the second dielectric layer, and illustratively, also includes an electrode window. The pinning region body and the mesh channel can be formed simultaneously by an implantation process; they can also be formed using other semiconductor processes. The above method 1000 can form a pinning layer having the aforementioned composite function with fewer steps. The pinning layer has a first doping type and a doping concentration greater than the doping concentration of the first dielectric layer. Exemplarily, the doping concentration of the pinning layer is greater than the doping concentration of the first dielectric layer.

[0224] The above-described method for manufacturing a photodiode can form a photodiode that can improve quantum efficiency while maintaining a clamped dark current, is easy to perform, and has a high cost-effectiveness.

[0225] In other embodiments, a thinner prefabricated first dielectric layer may be formed first; then a prefabricated second dielectric layer stacked thereon may be formed; and then a portion of the prefabricated second dielectric layer may be compensatory doped so that the portion has a first doping type and forms an integral first dielectric layer with the prefabricated first dielectric layer, and a second dielectric layer extending into the first dielectric layer is obtained based on the prefabricated second dielectric layer.

[0226] Exemplarily, the step of forming the first dielectric layer includes providing a substrate and forming the first dielectric layer on one side of the substrate. The substrate allows for good epitaxial growth. This method is easy to implement and can form a semiconductor structure and photodiode device with stable structure and good performance.

[0227] Exemplarily, method 1000 for manufacturing a photodiode further includes: forming a first contact region; forming a second contact region; and forming an interconnect layer. Method 1000 may also include forming a first antireflection film system. The first antireflection film system is located on the interconnect layer and may include at least one stacked film layer for increasing light transmittance. A first passivation layer may also be formed on the first antireflection film system.

[0228] In other embodiments, the method 1000 for manufacturing a photodiode further includes: step S104, removing the substrate; illustratively, forming a passivation film; forming an antireflection film located along the first direction on a side of the first dielectric layer facing away from the pinning layer, which may be referred to as a second antireflection film system; and step S105, forming a passivation layer located along the first direction on a side of the antireflection film facing away from the first dielectric layer, which may be referred to as a second passivation layer. This method can be used to manufacture back-illuminated photodiodes.

[0229] For example, after removing the substrate, the first dielectric layer can be ground, polished, and subjected to an anti-reflection treatment. It is understood that the first dielectric layer before the grinding step can be referred to as a prefabricated first dielectric layer, and the photodiode provided by the present invention can also be further processed in subsequent processes. The structure formed in the previous process can be referred to as a prefabricated structure in subsequent processes.

[0230] Referring to FIG. 23 , FIG. 23 illustrates a photodiode 100 according to one embodiment. The photodiode 100 may be a front-illuminated photodiode. The photodiode 100 may have a first region A, a second region B, and a third region C arranged in parallel. The three regions may be arranged sequentially along the X-axis direction (i.e., the second direction) in the figure. The photodiode 100 may be a one-piece structure. For example, its upper end face in the figure may be referred to as the front face, and its lower end face may be referred to as the back face. It will be understood that the terms front face and back face are for convenience only and do not necessarily limit or imply the posture of the photodiode 100 during manufacture or use.

[0231] The photodiode 100 may include a first dielectric layer 21 and a second dielectric layer 22. In the first region A and the second region B, the first dielectric layer 21 and the second dielectric layer 22 may be stacked along the Y-axis direction (i.e., the first direction) in the figure, and the two layers are used to form a photodetection structure to achieve a photoelectric effect. For example, overall, the second dielectric layer 22 extends into the first dielectric layer 21, and the upper surface of the portion of the first dielectric layer 21 in the third region C may be coplanar with the upper surface of the second dielectric layer 22.

[0232] In one embodiment, the photodiode 100 further includes a pinning structure 4 and a buried layer 330 .

[0233] The pinning structure 4 extends into the second dielectric layer 22 along the first direction. The projection of the pinning structure 4 along the first direction covers a portion of the second dielectric layer 22, exposing another portion of the second dielectric layer 22. For example, in the second region B, a portion of the pinning structure 4 overlaps a portion of the second dielectric layer 22; the upper surface of the portion of the second dielectric layer 22 in the first region A may be coplanar with the upper surface of the pinning structure 4.

[0234] Both the pinning structure 4 and the first dielectric layer 21 may have a first doping type. The first doping type is one of N-type doping and P-type doping, or one of electron doping and hole doping. Exemplarily, the doping concentration of the pinning structure 4 is greater than the doping concentration of the first dielectric layer 21, which may be referred to as an effective doping concentration. Exemplarily, the doping concentration of the pinning structure 4 is greater than the doping concentration of the second dielectric layer 22.

[0235] The buried layer 330 is located between the first dielectric layer 21 and the second dielectric layer 22 along the first direction. The buried layer 330 may be attached to the second dielectric layer 22. As shown in FIG23 , the buried layer 330 may include a portion located in the second region B and may also include a portion located in the first region A. For example, the thickness of the buried layer 330 may be less than the thickness of the second dielectric layer 22, and the thickness of the portion of the buried layer 330 located in the second region B may be less than the thickness of the portion of the second dielectric layer 22 located in the second region B. For example, the thickness of the buried layer 330 may also be equal to or thicker than the thickness of the second dielectric layer 22.

[0236] In some embodiments, along the X-axis, the buried layer 330 has a size comparable to the width of the second dielectric layer 22 and its edges are aligned, so that the projection of the pinning structure 4 along the Y-axis can cover a portion of the buried layer 330 .

[0237] Both the buried layer 330 and the second dielectric layer 22 may have a second doping type, and the doping concentration of the buried layer 330 is greater than the doping concentration of the second dielectric layer 22. The second doping type is one of N-type doping and P-type doping, or one of electron doping and hole doping. The second doping type is different from the first doping type. In other words, the conductivity type of the buried layer 330 is opposite to that of the first dielectric layer 21. Exemplarily, the doping concentration of the second dielectric layer 22 is at a low level, similar to that of an intrinsic semiconductor.

[0238] The second dielectric layer 22, the buried layer 330, and the first dielectric layer 21 can be used to form a photodetection structure, which can realize the function of a photodetection diode. The pinning structure 4, the second dielectric layer 22, and the buried layer 330 can be used to form a pinning structure, which can realize the function of a pinning diode. The circuit structure of the pinning diode and the photodetection diode can be a parallel structure. For example, the doping concentration of the buried layer 330 is lower than the doping concentration of the pinning structure 4. The two have different doping types, but the performance of the pinning diode can be adjusted by limiting the relationship between the doping concentration values.

[0239] In some embodiments, the photodiode 100 further includes a first electrode 61 (i.e., a collecting electrode) and a second electrode 62 (i.e., a common electrode). The first electrode 61 can be electrically connected to the second dielectric layer 22. For example, the first electrode 61 can be electrically connected to the portion of the second dielectric layer 22 located in the first region A. The second electrode 62 can be electrically connected to the first dielectric layer 21. For example, the second electrode 62 can be electrically connected to the portion of the first dielectric layer 21 located in the third region C. For example, the pinning structure 4 is electrically connected to the first dielectric layer 21. The pinning structure 4 can protrude from the second dielectric layer 22 along the X-axis and be electrically connected to the first dielectric layer 21. The pinning structure 4 can share the second electrode 62 with the first dielectric layer 21.

[0240] As shown in FIG. 23 , the photodiode 100 provided according to the above embodiment can form a depletion region 20 by integrating a photodetection diode and a local pinning diode.

[0241] When the reverse bias voltage between the first electrode 61 and the second electrode 62 reaches the pinning threshold voltage, the second dielectric layer 22 and the buried layer 330 in the pinned diode or in the second region B are fully depleted. Along the Y-axis, the size of the depletion region 20 corresponding to the pinned diode is determined by the doping concentration of the pinning structure 4 and the doping concentration of the buried layer 330, and has a weak functional relationship with the reverse bias voltage. Due to the high doping concentration of the pinning structure 4, the boundary of the depletion region 20 is far away from the front of the pinning structure 4, thereby suppressing the impact of interface states and surface recombination on the performance of the photodiode 100. Therefore, the dark current of the photodetection diode is clamped by the pinning diode and does not change significantly with changes in the bias voltage, and the dark current is controlled.

[0242] The doping concentration of the second dielectric layer 22 is low, nearly equal to the intrinsic concentration. Therefore, the portion corresponding to the pinned structure 4 is susceptible to full depletion under reverse bias voltage. The depth of the PN junction can be increased by increasing the thickness of the second dielectric layer 22. For example, the doping concentration of the buried layer 330 can be at least an order of magnitude higher than that of the second dielectric layer 22, allowing the boundary of the depletion region 20 in the first dielectric layer 21 to be further away from the front surface of the pinned structure 4. The depletion region 20 of the photodiode 100 has a large span along the Y-axis, which reduces the travel distance of photogenerated carriers, suppresses the effects of bulk recombination, and improves the photon quantum efficiency and responsivity of the photodetector diode.

[0243] Alternatively, the material of the photodiode 100 may include at least one of silicon carbide, silicon, silicon germanium, germanium, group III-V compounds such as indium arsenide and gallium arsenide, and group II-VI compounds.

[0244] As shown in FIG23 , the photodiode 100 may further include a first contact region 51 and a second contact region 52. The first contact region 51 extends into the first dielectric layer 21 and electrically contacts the second electrode 62. The doping concentration of the first contact region 51 is greater than that of the first dielectric layer 21. The second contact region 52 extends into the second dielectric layer 22 and electrically contacts the first electrode 61. The doping concentration of the second contact region 52 is greater than that of the second dielectric layer 22. For example, the first contact region 51 and the second contact region 52 may form an ohmic contact. For example, the first contact region 51 may be spaced apart from the pinning structure 4. The second contact region 52 may be spaced apart from the pinning structure 4 along the X-axis.

[0245] For example, the first dielectric layer 21 has p-type doping, the buried layer 330 has n-type doping, the second dielectric layer 22 has n-type doping that can be close to the intrinsic doping level, and the pinning structure 4 can have p+ type doping. The first contact region 51 can then have p+ type doping, and the second contact region 52 can have n+ type doping. The second electrode 62 can be an anode electrode, and the first electrode 61 can be a cathode electrode.

[0246] Optionally, for a front-illuminated photodiode, the photodiode 100 further includes an insulating layer 90. The insulating layer 90 is located on the side of the pinning structure 4 facing away from the second dielectric layer 22 along the first direction, i.e., the light-entering side. The first electrode 61 penetrates the insulating layer 90 and is electrically connected to the second dielectric layer 22. The second electrode 62 penetrates the insulating layer 90 and is electrically connected to the first dielectric layer 21.

[0247] Illustratively, the photodiode 100 further includes a first antireflection film (not shown) and a first passivation layer (not shown). Illustratively, the first antireflection film may be located on a side of the insulating layer 90 facing away from the pinning structure 4 along the first direction to increase light transmittance. The first passivation layer may be located on a side of the first antireflection film facing away from the insulating layer 90 along the first direction to protect functional layers such as the first antireflection film.

[0248] Exemplarily, the photodiode 100 further includes a substrate 1. The substrate 1 is located on a side of the first dielectric layer 21 facing away from the second dielectric layer 22 along the first direction. The substrate 1 has a first doping type, which may be the same as the doping type of the first dielectric layer 21, for example, p+ type doping.

[0249] In other embodiments, the first dielectric layer 21 has n-type doping, the buried layer 330 has p-type doping, the second dielectric layer 22 has p-type doping that may be close to the intrinsic doping level, and the pinning structure 4 may have n+ type doping. In this case, the first contact region 51 may have n+ type doping, the second contact region 52 may have p+ type doping, and the substrate 1 may have n+ type doping.

[0250] As shown in FIG. 24 , in some embodiments, the photodiode 100 may be a back-illuminated photodiode.

[0251] Illustratively, the photodiode 100 further includes a second antireflection film (not shown) and a second passivation layer 10. The second antireflection film and the second passivation layer 10 are sequentially stacked on a side of the first dielectric layer 21 facing away from the second dielectric layer 22 along the first direction. The second antireflection film can increase light transmittance, and the second passivation layer 10 is used to protect functional layers such as the first dielectric layer 21.

[0252] Exemplarily, the photodiode 100 further includes a passivation film (not shown). This passivation film may be stacked between the aforementioned second antireflection film and the first dielectric layer 21. A shallow interface heavily P+ doped region may be included between the passivation film and the first dielectric layer 21. The passivation film is a SiO2 / Al2O3 composite passivation film system that can introduce fixed negative charges. This prevents the depletion region of the pn junction from contacting the passivation interface, thereby reducing the impact of interface states on the dark current performance of the photodiode 100.

[0253] In some embodiments, the first dielectric layer 21 has p-type doping, the buried layer 330 has n-type doping, and the doping types of the remaining portions are not described in detail. In other embodiments, the first dielectric layer 21 has n-type doping, the buried layer 330 has p-type doping, and the doping types of the remaining portions are not described in detail.

[0254] 25 , one embodiment further provides an electronic component 300, which may include a circuit 200 and a photodiode 100. The photodiode 100 may be the photodiode 100 provided in any of the aforementioned embodiments, and is electrically connected to the circuit 200. For example, the first electrode 61 and the second electrode 62 may be electrically connected to the circuit 200, respectively. The electronic component 300 may implement a photoelectric effect. For example, the photodiode 100 generates a photocurrent signal based on a light signal, and the circuit 200 may collect the photocurrent signal and then perform processing such as integration, amplification, and analog-to-digital conversion on the photocurrent signal. The electronic component 300 may output a digitized electrical signal as the light signal.

[0255] 26 shows a method 100 for manufacturing a photodiode according to an embodiment. In some embodiments, the method 1000 may include the following steps S101 to S104.

[0256] Step S101: Forming a first dielectric layer. The first dielectric layer has a first doping type. Exemplarily, the first dielectric layer can be formed by epitaxial growth on a substrate followed by ion implantation. In other embodiments, the first dielectric layer can be epitaxially grown on a substrate and in-situ doped. The first dielectric layer can be formed in layers. Exemplarily, a first layer located below a buried layer along the Y-axis, a second layer flush with the buried layer, and a third layer flush with the second dielectric layer can be formed in sequence. The multiple sub-steps of the step of forming the first dielectric layer can be discontinuous.

[0257] Step S102: Forming a buried layer. In some embodiments, selective implantation can be performed after forming the second layer of the first dielectric layer to form the buried layer. In other embodiments, an in-situ doped buried layer can be formed, and then dopant compensation can be performed in the third region C to form the second layer of the first dielectric layer.

[0258] Step S103: Forming a second dielectric layer. Exemplarily, the third layer of the first dielectric layer can be epitaxially grown, and then the second dielectric layer can be formed by ion implantation. The doping concentration of the second dielectric layer is lower than that of the buried layer, and can approximate an intrinsic implantation region. Exemplarily, the second dielectric layer can be epitaxially grown and in-situ doped, and then the third layer of the first dielectric layer can be formed by dopant compensation in the third region C.

[0259] Step S104: forming a pinning layer extending into the second dielectric layer. For example, the pinning layer may be formed by an ion implantation process.

[0260] Illustratively, the method 1000 further includes forming a first contact region and a second contact region by an ion implantation process, and then forming a common electrode that is in ohmic contact with the first contact region, and further forming a contact electrode that is in ohmic contact with the second contact region.

[0261] For example, to manufacture a back-illuminated photodiode, the substrate may be removed, and then the first dielectric layer may be ground, polished, and subjected to an anti-reflection treatment. It is understood that the first dielectric layer before the grinding step may be referred to as a prefabricated first dielectric layer, and the photodiode provided by the embodiments of the present invention may also be further processed in subsequent processes. Optionally, an anti-reflection film may be formed on the side of the insulating layer facing away from the pinning layer, and then a first passivation layer may be formed on the side of the anti-reflection film facing away from the insulating layer. For example, an anti-reflection film may be formed on the side of the first dielectric layer facing away from the second dielectric layer; and a second passivation layer may be formed on the side of the anti-reflection film facing away from the first dielectric layer.

[0262] The technical features of the embodiments disclosed above can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0263] In the embodiments disclosed above, unless otherwise expressly specified and limited, the order of execution of the steps is not limited. For example, the steps may be executed in parallel or in a different order. The substeps of each step may also be executed in an interleaved manner. The various forms of the above-mentioned processes may be used, and steps may be reordered, added, or deleted. As long as the desired results of the technical solutions provided in this application can be achieved, this document does not impose any restrictions.

[0264] The embodiments disclosed above only represent several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be understood as limiting the scope of patent protection for the invention. It should be pointed out that a person of ordinary skill in the art can make several variations and improvements without departing from the concept of the present invention, and these all fall within the scope of patent protection claimed by the present invention. Therefore, the scope of patent protection for the present invention shall be based on the appended claims.

Claims

1. A photodiode, comprising: A first dielectric layer (21) having a first conductivity type; A photogenerated minority carrier collection region (31) stacked on the first dielectric layer (21), the photogenerated minority carrier collection region (31) having a second conductivity type, and the photogenerated minority carrier collection region (31) having a preset pattern region; as well as A first pinning layer (41) covers the photogenerated minority carrier collection region (31), and the first pinning layer (41) has the first conductivity type.

2. The photodiode according to claim 1, further comprising a collecting conductive region (32) stacked on the first dielectric layer (21); The first dielectric layer (21) comprises a first region (α), a second region (β) and a third region (γ); the first region (α) and the third region (γ) are separated by the second region (β); the photogenerated minority carrier collection region (31) is located in the second region (β); the collection conductive region (32) is located in the first region (α); and the collection conductive region (32) is connected to the photogenerated minority carrier collection region (31).

3. The photodiode according to claim 2, further comprising: A first electrode (61) in contact with the collecting conductive area (32); A second electrode (62) electrically connected to the first dielectric layer (21) in the third region (γ); A first antireflection film (7) located on a side of the first electrode (61) facing away from the first dielectric layer (21); and The first passivation layer (8) is located on a side of the first anti-reflection film (7) facing away from the first dielectric layer (21).

4. The photodiode according to claim 1, further comprising: A second anti-reflection film (9) is located on a side of the first dielectric layer (21) facing away from the photogenerated minority carrier collection region (31); and The second passivation layer (10) is located on a side of the second anti-reflection film (9) facing away from the first dielectric layer (21).

5. The photodiode according to claim 1, wherein the preset pattern area includes at least one mesh area (30), and the ratio of the total area of ​​all the mesh areas (30) to the peripheral contour area of ​​the photogenerated minority carrier collection area (31) is in the range of 3% to 80%.

6. The photodiode according to claim 1, further comprising: A buried layer (330) is located between the first dielectric layer (21) and the photogenerated minority carrier collection region (31) along the first direction, the buried layer (330) has a second doping type, and the doping concentration of the buried layer (330) is greater than the doping concentration of the photogenerated minority carrier collection region (31).

7. A method for manufacturing a photodiode according to any one of claims 1 to 6, comprising: Forming a photogenerated minority carrier collection region (31) stacked on a first dielectric layer (21), wherein the first dielectric layer (21) has a first conductivity type, the photogenerated minority carrier collection region (31) has a second conductivity type, and the photogenerated minority carrier collection region (31) has a preset pattern region; as well as A first pinning layer (41) is formed covering the photogenerated minority carrier collection region (31), wherein the first pinning layer (41) has the first conductivity type.

8. The method according to claim 7, further comprising: A collecting conductive region (32) is formed and stacked on a first dielectric layer (21); the first dielectric layer (21) comprises a first region (α), a second region (β) and a third region (γ); the first region (α) and the third region (γ) are separated by the second region (β); the photogenerated minority carrier collecting region (31) is located at the second region (β); the collecting conductive region (32) is located at the first region (α); and the collecting conductive region (32) is connected to the photogenerated minority carrier collecting region (31).

9. The method according to claim 8, further comprising: forming a first electrode (61) in contact with the collecting conductive region (32), and forming a second electrode (62) in the third region (γ) electrically connected to the first dielectric layer (21); forming a first antireflection film (7) located on the side of the first electrode (61) facing away from the first dielectric layer (21); and A first passivation layer (8) is formed on the side of the first antireflection film (7) facing away from the first dielectric layer (21).

10. The method according to claim 7, further comprising: Forming the first dielectric layer (21) stacked on the substrate (1) by an epitaxial process; removing the substrate (1); forming a second anti-reflection film (9) located on the side of the first dielectric layer (21) facing away from the photogenerated minority carrier collection region (31); and A second passivation layer (10) is formed on the side of the second antireflection film (9) facing away from the first dielectric layer (21).

11. A photodiode, comprising: A first dielectric layer (21) having a first conductivity type; A photogenerated minority carrier collection region (31) stacked on the first dielectric layer (21), the photogenerated minority carrier collection region (31) having a second conductivity type, and the photogenerated minority carrier collection region (31) having a preset pattern region; as well as The pinning structure (4) comprises at least a first pinning layer (41) covering the photogenerated minority carrier collection region (31) and a second pinning layer (42) extending into the preset pattern region, and the pinning structure (4) has the first conductivity type.

12. The photodiode according to claim 11, wherein the first dielectric layer (21) comprises a first region (α), a second region (β) and a third region (γ), the first region (α) and the third region (γ) are separated by the second region (β); the photogenerated minority carrier collection region (31) is located in the second region (β); the photodiode further comprises: A collecting conductive region (32) is located in the first region (α), and the collecting conductive region (32) is parallel to the photogenerated minority carrier collecting region (31) and connected to the photogenerated minority carrier collecting region (31); A second dielectric layer (22) is located in the third region (γ), the second dielectric layer (22) is parallel to the photogenerated minority carrier collection region (31), and the second dielectric layer (22) is connected to the first dielectric layer (21); A first electrode (61) in contact with the collecting conductive area (32); and The second electrode (62) contacts the second dielectric layer (22).

13. The photodiode according to claim 12, further comprising a first antireflection film (7) and a first passivation layer (8), wherein the first antireflection film (7) is located on a side of the first electrode (61) facing away from the first dielectric layer (21), and the first passivation layer (8) is located on a side of the first antireflection film (7) facing away from the first electrode (61).

14. The photodiode according to claim 11, further comprising a second anti-reflection film (9) and a second passivation layer (10), wherein the second anti-reflection film (9) is located on a side of the first dielectric layer (21) facing away from the photogenerated minority carrier collection region (31), and the second passivation layer (10) is located on a side of the second anti-reflection film (9) facing away from the first dielectric layer (21).

15. The photodiode according to claim 11, wherein the preset pattern area includes at least one mesh area (30), and the ratio of the total area of ​​all the mesh areas (30) to the peripheral contour area of ​​the photogenerated minority carrier collection area (31) is in the range of 3% to 80%.

16. The photodiode of claim 12, further comprising: A buried layer (330) is located between the first dielectric layer (21) and the photogenerated minority carrier collection region (31) along the first direction, the buried layer (330) has a second doping type, and the doping concentration of the buried layer (330) is greater than the doping concentration of the photogenerated minority carrier collection region (31).

17. A method for manufacturing a photodiode according to any one of claims 11 to 16, comprising: forming a photogenerated minority carrier collection region (31) stacked on a first dielectric layer (21), wherein the first dielectric layer (21) has a first conductivity type, and the photogenerated minority carrier collection region (31) has a second conductivity type; and A pinning structure (4) is formed, wherein the pinning structure (4) comprises at least a first pinning layer (41) covering the photogenerated minority carrier collection region (31) and a second pinning layer (42) extending into a preset pattern region of the photogenerated minority carrier collection region (31), and the pinning structure (4) has the first conductivity type.

18. The method according to claim 17, further comprising: The first dielectric layer (21) is formed by epitaxial growth, wherein the first dielectric layer (21) has a first region (α), a second region (β) and a third region (γ), wherein the first region (α) and the third region (γ) are separated by the second region (β); and the photogenerated minority carrier collection region (31) located in the second region (β) is formed by epitaxial growth and doping processes, a second dielectric layer (22) located in the third region (γ) is formed, and a collection conductive region (32) located in the first region (α) is formed; The forming of the pinning structure (4) comprises: etching to form a groove (40) penetrating the photogenerated minority carrier collection region (31); and performing a second ion implantation process to form the first pinning layer (41), the second pinning layer (42), and a third pinning layer (43) located at the bottom wall of the groove (40).

19. The method according to claim 17 or 18, further comprising: forming a first electrode (61) electrically connected to the photogenerated minority carrier collection region (31), and forming a second electrode (62) electrically connected to the first dielectric layer (21); forming a first antireflection film (7) located on the side of the first electrode (61) facing away from the first dielectric layer (21); and A first passivation layer (8) is formed on the side of the first antireflection film (7) facing away from the first dielectric layer (21).

20. The method according to claim 17 or 18, wherein the first dielectric layer (21) is stacked on a substrate (1), and the photogenerated minority carrier collection region (31) is located on a side of the first dielectric layer (21) facing away from the substrate (1); The method further comprises: removing the substrate (1); forming a second anti-reflection film (9), wherein the second anti-reflection film (9) is located on a side of the first dielectric layer (21) facing away from the photogenerated minority carrier collection region (31) along the stacking direction; and A second passivation layer (10) is formed on the side of the second antireflection film (9) facing away from the first dielectric layer (21).

21. A photodiode, comprising: A first dielectric layer (21) having a first doping type; A second dielectric layer (22) having a second doping type and extending into the first dielectric layer (21) along a first direction; as well as A pinning structure (4) extends along the first direction into the second dielectric layer (22), the pinning structure (4) has the first doping type and the doping concentration of the pinning structure (4) is greater than the doping concentration of the first dielectric layer (21), and the pinning structure (4) comprises a pinning region body (431) and at least one mesh channel (432) corresponding to the second dielectric layer (22).

22. The photodiode according to claim 21, wherein the at least one mesh channel (432) is arranged in an array in a plane perpendicular to the first direction; and along a second direction perpendicular to the first direction, the spacing between two adjacent mesh channels (432) is greater than the size of the mesh channel (432) along the second direction.

23. The photodiode according to claim 21, wherein the ratio of the area of ​​all the mesh channels (432) in the vertical plane of the first direction to the area of ​​the pinning region body (431) ranges from 1% to 40%; and The doping concentration of the pinning structure (4) is greater than the doping concentration of the second dielectric layer (22).

24. The photodiode according to claim 23, wherein the ratio of the area of ​​all the mesh channels (432) in the vertical plane of the first direction to the area of ​​the pinning region body (431) ranges from 2.5% to 10%.

25. The photodiode according to any one of claims 21 to 24, further comprising: A first contact region (51) extending along the first direction into the first dielectric layer (21), the first contact region (51) having the first doping type and a doping concentration greater than a doping concentration of the first dielectric layer (21); a second contact region (52) extending into the second dielectric layer (22) along the first direction, the second contact region (52) having the second doping type and a doping concentration greater than the doping concentration of the second dielectric layer (22); the pinning structure (4) comprising an electrode window (433), the second contact region (52) being located within the electrode window (433); along a second direction perpendicular to the first direction, the pinning structure (4) protrudes from the second dielectric layer (22) and is electrically connected to the first dielectric layer (21); An insulating layer (90) located on a side of the pinning structure (4) facing away from the first dielectric layer (21) along the first direction; A first electrode (7) passes through the insulating layer (90) along the first direction and is in electrical contact with the first contact area (51) so as to be electrically connected to the first dielectric layer (21); and A second electrode (8) penetrates the insulating layer (90) along the first direction and electrically contacts the second contact area (52). The second dielectric layer (22) is in electrical contact with the second dielectric layer (22).

26. The photodiode according to claim 25, further comprising a first anti-reflection film, a first passivation layer and a substrate (1), wherein the first anti-reflection film and the first passivation layer are stacked in sequence on a side of the insulating layer (90) facing away from the pinning structure (4), and the substrate (1) is located on a side of the first dielectric layer (21) facing away from the pinning structure (4) along the first direction.

27. The photodiode according to claim 25, further comprising a passivation film, a second anti-reflection film and a second passivation layer (10), wherein the passivation film, the second anti-reflection film and the second passivation layer (10) are stacked in sequence on a side of the first dielectric layer (21) facing away from the pinning structure (4) along the first direction.

28. The photodiode of claim 21, further comprising: A buried layer (330) is located between the first dielectric layer (21) and the second dielectric layer (22) along the first direction, the buried layer (330) has the second doping type, and the doping concentration of the buried layer (330) is greater than the doping concentration of the second dielectric layer (22).

29. A method for manufacturing a photodiode according to any one of claims 21 to 28, comprising: forming a first dielectric layer (21), wherein the first dielectric layer (21) has a first doping type; forming a second dielectric layer (22) extending into the first dielectric layer (21) along a first direction, wherein the second dielectric layer (22) has a second doping type; as well as A pinning structure (4) is formed extending along the first direction into the second dielectric layer (22), wherein the pinning structure (4) has the first doping type and the doping concentration of the pinning structure (4) is greater than the doping concentration of the first dielectric layer (21), and the pinning structure (4) comprises a pinning region body (431) and at least one mesh channel (432) corresponding to the second dielectric layer (22).

30. The method according to claim 29, wherein forming the first dielectric layer (21) comprises: Provide substrate (1) forming the first dielectric layer (21) on one side of the substrate (1); The method further comprises: removing the substrate (1); forming an antireflection film located along the first direction on a side of the first dielectric layer (21) facing away from the pinning structure (4); and forming a passivation layer located along the first direction on a side of the antireflection film facing away from the first dielectric layer (21).

31. A photodiode, comprising: A first dielectric layer (21) having a first doping type; A second dielectric layer (22) having a second doping type and extending into the first dielectric layer (21) along a first direction; A pinning structure (4) extending along the first direction into the second dielectric layer (22), a projection of the pinning structure (4) along the first direction covering a portion of the second dielectric layer (22), and the pinning structure (4) having the first doping type; as well as A buried layer (330) is located between the first dielectric layer (21) and the second dielectric layer (22) along the first direction, the buried layer (330) has the second doping type, and the doping concentration of the buried layer (330) is greater than the doping concentration of the second dielectric layer (22).

32. The photodiode of claim 31, wherein the first doping type is one of electron doping and hole doping, and the second doping type is the other of electron doping and hole doping.

33. The photodiode according to claim 31, wherein the projection of the pinning structure (4) along the first direction covers a portion of the buried layer (330); the pinning structure (4) protrudes from the second dielectric layer (22) along a second direction perpendicular to the first direction; the doping concentration of the pinning structure (4) is greater than the doping concentration of the first dielectric layer (21), and the doping concentration of the pinning structure (4) is greater than the doping concentration of the second dielectric layer (22).

34. The photodiode of claim 33, wherein the doping concentration of the buried layer (330) is less than the doping concentration of the pinning structure (4).

35. The photodiode according to any one of claims 31 to 34, further comprising: An insulating layer (90) is located on the pinning structure (4) along the first direction facing away from the second dielectric layer (22). On one side, a first electrode (61) penetrating the insulating layer (90) and electrically connected to the second dielectric layer (22), A second electrode (62) passes through the insulating layer (90) and is electrically connected to the first dielectric layer (21); the pinning structure (4) is electrically connected to the first dielectric layer (21); A first contact region (51) extending into the first dielectric layer (21) and electrically contacting the second electrode (62), wherein the doping concentration of the first contact region (51) is greater than the doping concentration of the first dielectric layer (21); and The second contact region (52) extends into the second dielectric layer (22) and is in electrical contact with the first electrode (61); the doping concentration of the second contact region (52) is greater than the doping concentration of the second dielectric layer (22).

36. The photodiode according to claim 35, further comprising a substrate (1), wherein the substrate (1) is located on a side of the first dielectric layer (21) facing away from the second dielectric layer (22) along the first direction, and the substrate (1) has the first doping type.

37. The photodiode according to claim 35, further comprising a first anti-reflection film and a first passivation layer, wherein the first anti-reflection film and the first passivation layer are sequentially stacked on a side of the insulating layer (90) facing away from the pinning structure (4) along the first direction.

38. The photodiode according to claim 35, further comprising a passivation film, a second anti-reflection film and a second passivation layer (10), wherein the passivation film, the second anti-reflection film and the second passivation layer (10) are stacked in sequence on a side of the first dielectric layer (21) facing away from the second dielectric layer (22) along the first direction.

39. An electronic component comprising: Circuit (200); and The photodiode (100) according to any one of claims 1 to 6, 11 to 16, 21 to 28, and 31 to 38, being electrically connected to the circuit (200).

40. A method for manufacturing a photodiode according to any one of claims 31 to 38, comprising: forming a first dielectric layer (21) having a first doping type; forming a buried layer (330) extending into the first dielectric layer (21) along a first direction, wherein the buried layer (330) has a second doping type; forming a second dielectric layer (22) extending into the first dielectric layer (21) along the first direction, the second dielectric layer (22) being located on a side of the buried layer (330) facing away from the first dielectric layer (21) along the first direction, the second dielectric layer (22) having the second doping type and a doping concentration of the second dielectric layer (22) being less than a doping concentration of the buried layer (330); as well as A pinning structure (4) is formed extending into the second dielectric layer (22) along the first direction, the projection of the pinning structure (4) covers a portion of the second dielectric layer (22), and the pinning structure (4) has the first doping type.

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