Array substrate, electronic paper display apparatus, and driving method therefor

Abstract

An array substrate (S1a), an electronic paper display apparatus (500), and a driving method therefor. The array substrate (S1a) is provided with a plurality of pixel regions (PR), and comprises: a base substrate (200), a plurality of pixel electrodes (11), and a barrier wall electrode (be1a, be2, be1b) structure. The plurality of pixel electrodes (11) are respectively located in the plurality of pixel regions (PR). The barrier wall electrode (be1a, be2, be1b) structure is located between adjacent pixel regions (PR). The plurality of pixel regions (PR) include a first pixel region (PR1) and a second pixel region (PR2) arranged along a first direction and adjacent to each other. The barrier wall electrode (be1a, be2, be1b) structure comprises a first barrier wall electrode, a second barrier wall electrode, and a third barrier wall electrode. At least some of the barrier wall electrodes (be1a, be2, be1b) are sequentially arranged between the first pixel region (PR1) and the second pixel region (PR2) in the first direction. The first barrier wall electrode and the second barrier wall electrode are configured to form a first electric field. The second barrier wall electrode and the third barrier wall electrode are configured to form a second electric field. The first electric field and the second electric field are in opposite directions and are configured to collectively form an electron barrier. The second barrier wall electrode is a common electrode of the first electric field and the second electric field.

Description

Array substrate, electronic paper display device and driving method thereof Technical Field

[0001] Embodiments of the present disclosure relate to an array substrate, an electronic paper display device, and a driving method thereof. Background Art

[0002] Compared to mainstream display technologies such as liquid crystal and OLED, existing electronic paper display technology has advantages such as low power consumption and strong eye protection, and is therefore widely used. The display principle of electronic paper display technology is to provide a vertical electric field through electrodes in the upper and lower substrates arranged in opposite directions. There are charged dispersed particles (for example, black particles and / or white particles) in the dispersant between the upper and lower substrates. By controlling the vertical electric field, the aggregation morphology of the charged particles is controlled, thereby controlling the display of the display device. However, in existing electronic paper display devices, the charged particles in the dispersant may crosstalk between adjacent pixel areas, thereby adversely affecting the display of the display device.

[0003] Summary of the Invention

[0004] According to at least one embodiment of the present disclosure, an array substrate is provided, comprising: a base substrate; and a plurality of pixel electrodes and a barrier electrode structure, disposed on one side of the base substrate, the plurality of pixel electrodes being respectively located in the plurality of pixel regions, and the barrier electrode structure being located between adjacent pixel regions, wherein the plurality of pixel regions include a first pixel region and a second pixel region arranged in a first direction parallel to a major surface of the base substrate and adjacent to each other, the plurality of pixel electrodes including a first pixel electrode and a second pixel electrode respectively located in the first pixel region and the second pixel region; the barrier electrode structure including a first barrier electrode, a second barrier electrode, and a third barrier electrode, wherein at least a portion of the first barrier electrode, at least a portion of the second barrier electrode, and at least a portion of the third barrier electrode are sequentially arranged in the first direction between the first pixel region and the second pixel region, the first barrier electrode and the second barrier electrode being configured to form a first electric field, and the second barrier electrode and the third barrier electrode being configured to form a second electric field, the first electric field and the second electric field being in opposite directions and configured to jointly form an electron barrier, wherein the second barrier electrode is a common electrode for the first and second electric fields.

[0005] In the array substrate provided according to at least one embodiment of the present disclosure, at least a portion of the first barrier wall electrode is located at the periphery of the first pixel region and surrounds the first pixel region in a direction parallel to the main surface of the base substrate; at least a portion of the third barrier wall electrode is located at the periphery of the second pixel region and surrounds the second pixel region in a direction parallel to the main surface of the base substrate.

[0006] In the array substrate provided according to at least one embodiment of the present disclosure, the second barrier wall electrode surrounds the first barrier wall electrode and the third barrier wall electrode in a direction parallel to the main surface of the base substrate.

[0007] In the array substrate provided according to at least one embodiment of the present disclosure, the at least portion of the second blocking wall electrode is located between the first blocking wall electrode and the third blocking wall electrode in the first direction and has an opening, and the first blocking wall electrode and the third blocking wall electrode are electrically connected to each other via a connecting electrode passing through the opening.

[0008] In the array substrate provided according to at least one embodiment of the present disclosure, the plurality of pixel electrodes and the barrier electrode structure are arranged in the same layer and are spaced apart from each other.

[0009] In the array substrate provided according to at least one embodiment of the present disclosure, the blocking wall electrode structure is arranged on a side of the multiple pixel electrodes close to the base substrate, the orthographic projection of the first blocking wall electrode on the base substrate covers the first pixel area and extends beyond the edge of the orthographic projection of the first pixel area on the base substrate; or the orthographic projection of the third blocking wall electrode on the base substrate covers the second pixel area and extends beyond the edge of the orthographic projection of the second pixel area on the base substrate.

[0010] In the array substrate provided according to at least one embodiment of the present disclosure, each pixel electrode includes a plurality of pixel sub-electrodes, and the plurality of pixel sub-electrodes are spaced apart from each other and configured to be respectively connected to a plurality of data signal lines.

[0011] In the array substrate provided according to at least one embodiment of the present disclosure, one or more of the multiple data signal lines each include a data signal main line and a data signal auxiliary line connected to each other through a switching electrode, and the multiple data signal main lines are all located in an area outside the corresponding pixel area.

[0012] In the array substrate provided according to at least one embodiment of the present disclosure, gaps between the orthographic projections of the plurality of data signal main lines on the base substrate and the orthographic projections of the plurality of pixel sub-electrodes located in the same pixel area on the base substrate are offset.

[0013] In the array substrate provided according to at least one embodiment of the present disclosure, the plurality of pixel sub-electrodes include a plurality of strip electrodes, the plurality of strip electrodes are arranged along the first direction and extend along the second direction, and the first direction and the second direction intersect each other.

[0014] In the array substrate provided according to at least one embodiment of the present disclosure, the multiple pixel sub-electrodes include a first pixel sub-electrode and a second pixel sub-electrode, and the second pixel sub-electrode surrounds the first pixel sub-electrode in a direction parallel to the main surface of the base substrate.

[0015] In the array substrate provided according to at least one embodiment of the present disclosure, the barrier electrode structure is also reused as a reflective electrode.

[0016] According to at least one embodiment of the present disclosure, the array substrate provided further includes a plurality of transistors and a plurality of capacitors, each transistor including a gate, a source and a drain, each capacitor including at least a first plate and a second plate, the pixel sub-electrode of each pixel electrode is electrically connected to one of the source and the drain of the corresponding transistor, and is electrically connected to one of the first plate and the second plate of the corresponding capacitor, and the array substrate includes: a first conductive layer, a first insulating layer, a second conductive layer and a second insulating layer, which are sequentially arranged on one side of the base substrate, the gate and the first plate are located in the first conductive layer, the source, the drain and the second plate are located in the second conductive layer; and a first electrode layer, which is located on a side of the second insulating layer away from the base substrate, wherein the plurality of pixel electrodes are arranged in the first electrode layer, the second insulating layer has a first via, and the pixel sub-electrode is connected to the source or drain of the corresponding transistor through the first via.

[0017] In the array substrate provided according to at least one embodiment of the present disclosure, the second conductive layer has an opening; the second insulating layer and the first insulating layer have a second via hole, and the second via hole passes through the opening of the second conductive layer and is separated from the second conductive layer; and the pixel sub-electrode is electrically connected to the first plate of the capacitor through the second via hole.

[0018] In the array substrate provided according to at least one embodiment of the present disclosure, the capacitor also includes a third plate, and the pixel sub-electrode is reused as the third plate of the capacitor, and the capacitor includes a double-layer capacitor formed between the second plate and the first plate and between the second plate and the third plate.

[0019] In the array substrate provided according to at least one embodiment of the present disclosure, the second electrode plate is configured to receive a common voltage signal and multiplexed into a signal shielding structure.

[0020] In the array substrate provided according to at least one embodiment of the present disclosure, the blocking wall electrode structure is located in the first electrode layer, the second insulating layer further includes a third via hole, and the first blocking wall electrode and the third blocking wall electrode are respectively connected to the second plate of the corresponding capacitor through the third via hole.

[0021] The array substrate provided according to at least one embodiment of the present disclosure further includes: a second electrode layer, located on the side of the first electrode layer close to the base substrate, and located between the first electrode layer and the second insulating layer; and an organic layer, located between the first electrode layer and the second electrode layer, wherein the retaining wall electrode structure is located in the second electrode layer and is reused as a reflective electrode.

[0022] In the array substrate provided according to at least one embodiment of the present disclosure, the first via hole extends from the organic layer into the second insulating layer, and the second electrode layer has an opening, the first via hole passes through the opening and is spaced apart from the second electrode layer, so that the pixel sub-electrode passes through the opening to be connected to the source or drain of the corresponding transistor.

[0023] In the array substrate provided according to at least one embodiment of the present disclosure, the orthographic projections of the first blocking wall electrode and the third blocking wall electrode on the base substrate overlap with the orthographic projections of the first pixel electrode and the second pixel electrode on the base substrate, respectively, and the first blocking wall electrode and the third blocking wall electrode each have the opening.

[0024] In the array substrate provided according to at least one embodiment of the present disclosure, there are third vias in the first insulating layer and the second insulating layer, and the second conductive layer has an opening, the third via passes through the opening and is separated from the second conductive layer; and the first blocking wall electrode and the third blocking wall electrode are respectively electrically connected to the first plate of the corresponding capacitor through the third via.

[0025] In the array substrate provided according to at least one embodiment of the present disclosure, the first barrier wall electrode and the third barrier wall electrode are also respectively used as third plates of corresponding capacitors, and the capacitors each include a double-layer capacitor formed between the second plate and the first plate and between the second plate and the third plate.

[0026] In the array substrate provided according to at least one embodiment of the present disclosure, the orthographic projection of the first electrode layer on the base substrate overlaps with the orthographic projection of the second electrode layer on the base substrate, and the orthographic projection of the second electrode layer also covers the orthographic projection of the gap area between multiple pixel sub-electrodes in each pixel area on the base substrate.

[0027] In the array substrate provided according to at least one embodiment of the present disclosure, each pixel electrode includes a first pixel sub-electrode, a second pixel sub-electrode and a third pixel sub-electrode arranged along the first direction; in each pixel area, a plurality of transistors include a first transistor, a second transistor and a third transistor, which are respectively connected to the first pixel sub-electrode, the second pixel sub-electrode and the third pixel sub-electrode; wherein the first transistor and the second transistor are arranged along the first direction, the third transistor is located on one side of the first transistor and the third transistor in the second direction, and at least a part of the positive projection of the third transistor on the reference plane extending along the first direction is located between the positive projections of the first transistor and the second transistor on the reference plane, and the first direction and the second direction intersect.

[0028] In the array substrate provided according to at least one embodiment of the present disclosure, the multiple pixel regions are arranged into multiple pixel rows along the first direction and into multiple pixel columns along the second direction; in the first pixel region and the third pixel region located in the same pixel column and adjacent rows, the multiple transistors of the first pixel region and the multiple transistors of the third pixel region are symmetrically arranged.

[0029] In the array substrate provided according to at least one embodiment of the present disclosure, there is a first distance between the first transistor in the first pixel area and the first transistor in the third pixel area; there is a second distance between the second transistor in the first pixel area and the second transistor in the third pixel area; there is a third distance between the third transistor in the first pixel area and the third transistor in the third pixel area; the first distance, the second distance, and the third distance are all distances in the second direction; the first distance and the second distance are the same, and the third distance is different from the first distance and the second distance.

[0030] At least one embodiment of the present disclosure provides an electronic paper display device, comprising any of the above-mentioned array substrates.

[0031] In the electronic paper display device provided according to at least one embodiment of the present disclosure, the array substrate serves as a first substrate, and the electronic paper display device further includes: a second substrate having a common electrode and arranged opposite to the first substrate; and a dispersant layer located between the first substrate and the second substrate and including charged particles located in the plurality of pixel regions.

[0032] In the electronic paper display device provided according to at least one embodiment of the present disclosure, the charged particles include at least one of a first charged particle and a second charged particle, the first charged particle has a first electrical property, the second charged particle has a second electrical property, and the first electrical property and the second electrical property are opposite.

[0033] In the electronic paper display device provided according to at least one embodiment of the present disclosure, no physical barrier walls are included between adjacent pixel areas.

[0034] The electronic paper display device provided according to at least one embodiment of the present disclosure further includes a physical retaining wall, which is arranged between the first substrate and the second substrate in a direction perpendicular to the main surface of the base substrate, and is arranged between adjacent pixel areas in a direction parallel to the main surface of the base substrate.

[0035] In the electronic paper display device provided according to at least one embodiment of the present disclosure, the physical barrier wall overlaps with one or more barrier wall electrodes in the barrier wall electrode structure in a direction perpendicular to the main surface of the base substrate.

[0036] At least one embodiment of the present disclosure provides a driving method for an electronic paper display device, comprising: applying a first voltage, a second voltage, and a third voltage to the first barrier wall electrode, the second barrier wall electrode, and the third barrier wall electrode, respectively, wherein the first voltage is less than the second voltage, and the third voltage is less than the second voltage, so that the electron barrier formed by the barrier electrode structure between the adjacent first pixel region and the second pixel region includes two electric fields with opposite electric field directions and away from each other; or the first voltage is greater than the second voltage, and the third voltage is greater than the second voltage, so that the electron barrier formed by the barrier electrode structure between the adjacent first pixel region and the second pixel region includes two electric fields with opposite electric field directions and facing each other.

[0037] In the driving method of the electronic paper display device provided according to at least one embodiment of the present disclosure, the first voltage and the third voltage are the same.

[0038] At least one embodiment of the present disclosure provides an array substrate, comprising a plurality of pixel regions arranged in an array, wherein the plurality of pixel regions are arranged into a plurality of pixel rows along a first direction and into a plurality of pixel columns along a second direction, wherein the first direction and the second direction intersect, and the array substrate comprises: a base substrate; a plurality of pixel electrodes and a barrier wall electrode structure, which are arranged on one side of the base substrate, wherein the plurality of pixel electrodes are respectively located in the plurality of pixel regions, and the barrier wall electrode structure is located between adjacent pixel regions; wherein the barrier wall electrode structure comprises a plurality of first barrier wall electrodes and a second barrier wall electrode, wherein the plurality of first barrier wall electrodes are arranged in a one-to-one correspondence with the plurality of pixel regions, wherein at least a portion of each first barrier wall electrode surrounds a corresponding pixel region in a direction parallel to a main surface of the base substrate, and each first barrier wall electrode is surrounded by the second barrier wall electrode in a direction parallel to the main surface of the base substrate.

[0039] In the array substrate provided according to at least one embodiment of the present disclosure, the plurality of first barrier wall electrodes are configured to receive a first voltage signal, and the second barrier wall electrodes are configured to receive a second voltage signal, and the first voltage signal and the second voltage signal are different.

[0040] In the array substrate provided according to at least one embodiment of the present disclosure, the multiple first blocking wall electrodes are arranged into multiple rows along the first direction; the second blocking wall electrode has an opening in the portion between each two adjacent first blocking wall electrodes in the same row; the blocking wall electrode structure also includes a connecting electrode, which passes through the opening, so that the multiple first blocking wall electrodes in the same row are electrically connected to each other through the connecting electrode.

[0041] In the array substrate provided according to at least one embodiment of the present disclosure, the second barrier wall electrode is in a grid shape and defines a plurality of grid areas; a pixel area and the first barrier wall electrode surrounding the pixel area are provided in each grid area.

[0042] In the array substrate provided according to at least one embodiment of the present disclosure, each of the plurality of first barrier wall electrodes is ring-shaped or planar-shaped.

[0043] In the array substrate provided according to at least one embodiment of the present disclosure, each pixel electrode includes a plurality of pixel sub-electrodes, and the plurality of pixel sub-electrodes are respectively connected to a plurality of data signal lines; each data signal line includes at least a data signal main line, and one or more of the plurality of data signal lines each further includes a transfer electrode and a data signal auxiliary line, and the data signal auxiliary line is electrically connected to the data signal main line through the transfer electrode; the plurality of data signal main lines extend along the second direction and are located on opposite sides of the pixel area in the first direction, the data signal auxiliary lines and the transfer electrodes are located between adjacent data signal main lines in the first direction, and are located between the pixel area and the second blocking wall electrode in the second direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0045] FIG1 shows a schematic cross-sectional view of an electronic paper display device.

[0046] 2A to 2D respectively illustrate schematic cross-sectional views of electronic paper display devices according to some embodiments of the present disclosure.

[0047] FIG3A illustrates a schematic plan view of a plurality of pixel regions and a barrier electrode structure in a first substrate of an electronic paper display device according to some embodiments of the present disclosure.

[0048] FIG3B shows a schematic plan view of a pixel region and its surrounding barrier electrode structure in the first substrate of an electronic paper display device according to some embodiments of the present disclosure.

[0049] 3C and 3D are schematic plan views showing a barrier electrode structure between two adjacent pixel regions generating an electron barrier.

[0050] FIG3E schematically shows a plan view of a first substrate of an electronic paper display device in which a barrier electrode is connected to a signal line through a via hole.

[0051] FIG4 shows a schematic cross-sectional view of an array substrate according to some embodiments of the present disclosure.

[0052] 5 to 10B are schematic plan layout diagrams of various layers in the array substrate shown in FIG. 4 according to some embodiments of the present disclosure.

[0053] FIG11 shows a schematic cross-sectional view of an array substrate according to some other embodiments of the present disclosure.

[0054] 12 to 18B are schematic plan layout diagrams of various layers in the array substrate shown in FIG. 11 according to some embodiments of the present disclosure.

[0055] FIG19 shows a schematic cross-sectional view of an array substrate according to further embodiments of the present disclosure.

[0056] 20 to 25B are schematic plan layout diagrams of various layers in the array substrate shown in FIG. 19 according to some embodiments of the present disclosure.

[0057] FIG. 26 shows a schematic cross-sectional view of an array substrate according to yet other embodiments of the present disclosure.

[0058] 27 to 32B are schematic plan layout diagrams of various layers in the array substrate shown in FIG. 26 according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0059] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0060] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0061] FIG1 shows a schematic cross-sectional view of a display device.

[0062] Referring to Figure 1, the display device 50 is an electronic ink screen and includes a first substrate 12, a second substrate 22, a sealant 30, a pixel retaining wall 31, and a dispersant layer 45. The first substrate 12 and the second substrate 22 are arranged relative to each other, and the sealant 30 and the pixel retaining wall 31 are arranged between the first substrate 12 and the second substrate 22. The sealant 30 surrounds the edge of the display device, thereby defining the space where the dispersant layer 45 is located together with the first substrate 12 and the second substrate 22. The pixel retaining wall 31 separates the first substrate 12 and the second substrate 22 into multiple chambers to define multiple pixel areas. That is, each chamber corresponds to a pixel area.

[0063] The first substrate 12 includes a substrate 10 and a plurality of pixel electrodes 11, and the plurality of pixel electrodes 11 are arranged on one side of the substrate 10 close to the second substrate 22. The second substrate 22 includes a substrate 20 and a common electrode 21, and the common electrode 21 is arranged on one side of the substrate 20 close to the first substrate 12. In each pixel area, the pixel electrode 11 and the common electrode 21 are arranged relative to each other and are configured to generate an electric field in a vertical direction (i.e., a direction perpendicular to the main surface of the substrate). In some embodiments, the dispersant layer 45 includes a dispersant 40 and a plurality of charged particles 41 and a plurality of charged particles 42. The charged particles 41 and 42 are dispersed in the dispersant 40 and have opposite electrical properties to each other. For example, the charged particles 41 are white particles and are negatively charged, and the charged particles 42 are black particles and are positively charged.

[0064] In each pixel area, by applying appropriate voltages to the pixel electrode 11 and the common electrode 21, an upward or downward electric field is generated between the two electrodes. The dotted arrows in Figure 1 schematically illustrate the electric field lines of the electric field in each pixel. The charged particles 41 and 42 move under the action of the electric field, for example, each moving toward or away from one side of the common electrode. The display side of the display device 50 is, for example, the side where the second substrate 22 is located. For example, when the pixel electrode 11 and the common electrode 21 generate an upward electric field, the black charged particles move upward and are distributed on the upper visual field side of the figure, and the pixel area presents a black display; when the pixel electrode 11 and the common electrode 21 generate a downward electric field, the white charged particles move upward and are distributed on the upper visual field side of the figure, and the pixel area presents a white display. In addition, grayscale display can be achieved by controlling the degree of aggregation of black and white particles at the bottom and top of the pixel area; the more black particles at the top, the lower the brightness, and the more white particles at the top, the higher the brightness.

[0065] The pixel barrier 31 is provided between adjacent pixel regions to separate the dispersants and charged particles in the plurality of pixel regions from each other. The pixel barrier 31 comprises an insulating material and may also be referred to as an insulating barrier or a physical barrier. In some embodiments, a plurality of pixel barriers 31 may be formed on the first substrate 12 by a patterning process, and then the first substrate 12 and the second substrate 22 are aligned. However, in the process of forming the pixel barrier 31, due to limitations in process precision, it may be difficult to ensure the height uniformity of the formed pixel barrier 31 in different regions, which may result in the charged particles in the dispersant layer being able to crosstalk between adjacent pixel regions. For example, as shown in FIG1 , the height of a portion of the pixel barrier 31 is relatively low, so that there is a gap between the portion of the pixel barrier 31 and the first substrate 22, so that the charged particles may crosstalk between adjacent pixel regions through the gap.

[0066] The embodiments of the present disclosure provide an array substrate, an electronic paper display device including the same, and a driving method thereof. By setting a barrier electrode structure in the array substrate, and the barrier electrode structure being configured to form an electron barrier including two opposite electric fields, crosstalk between adjacent pixels of charged particles in the dispersant layer can be effectively prevented, thereby improving the display quality of the display device.

[0067] For example, an array substrate has a plurality of pixel areas arranged in an array, and includes: a base substrate and a plurality of pixel electrodes and a barrier electrode structure arranged on one side of the base substrate, the plurality of pixel electrodes are respectively located in the plurality of pixel areas, and the barrier electrode structure is located between adjacent pixel areas, wherein the plurality of pixel areas include a first pixel area and a second pixel area adjacent to each other in a first direction parallel to the main surface of the base substrate, and the plurality of pixel electrodes include a first pixel electrode and a second pixel electrode respectively located in the first pixel area and the second pixel area; the barrier electrode structure includes a first barrier electrode, a second barrier electrode and a third barrier electrode, and at least a portion of the first barrier electrode, at least a portion of the second barrier electrode and at least a portion of the third barrier electrode are arranged sequentially between the first pixel area and the second pixel area in the first direction, the first barrier electrode and the second barrier electrode are configured to form a first electric field, the second barrier electrode and the third barrier electrode are configured to form a second electric field, the first electric field and the second electric field are in opposite directions, and are configured to jointly form an electron barrier wall, wherein the second barrier electrode is a common electrode for the first electric field and the second electric field.

[0068] For example, a method for driving an electronic paper display device includes: applying a first voltage, a second voltage, and a third voltage to a first barrier electrode, a second barrier electrode, and a third barrier electrode, respectively, wherein the first voltage is less than the second voltage, and the third voltage is less than the second voltage, so that an electron barrier formed by the barrier electrode structure between adjacent first and second pixel regions includes two electric fields with opposite electric field directions and away from each other; or the first voltage is greater than the second voltage, and the third voltage is greater than the second voltage, so that an electron barrier formed by the barrier electrode structure between adjacent first and second pixel regions includes two electric fields with opposite electric field directions and facing each other. The electron barrier formed by the two electric fields can prevent crosstalk between the first and second pixel regions by charged particles.

[0069] Figures 2A to 2D are schematic cross-sectional views of electronic paper display devices according to some embodiments of the present disclosure. Figure 3A is a schematic plan view of a first substrate of an electronic paper display device according to some embodiments of the present disclosure.

[0070] Referring to Figures 2A and 3A, in some embodiments, an electronic paper display device 500 includes pixel regions PR and barrier wall regions BR. The barrier wall regions BR may be located outside the pixel regions PR and between adjacent pixel regions PR. For example, the electronic paper display device 500 includes a first substrate S1, a second substrate S2, and a dispersant layer DL. The first and second substrates S1 and S2 are disposed opposite each other, with the dispersant layer DL sandwiched between them. The first substrate S1 may include a base substrate 100 and a pixel electrode and barrier wall electrode structure disposed on a side of the base substrate 100 proximate to the second substrate S2. The second substrate S2 may include a base substrate 200 and a common electrode 201 disposed on a side of the base substrate 200 proximate to the first substrate S1. In some embodiments, the dispersant layer DL may include a dispersant 300 and charged particles distributed within the dispersant 300. For example, the charged particles may include at least one of a first charged particle and a second charged particle, the first charged particle having a first charge characteristic and the second charged particle having a second charge characteristic, the first charge characteristic and the second charge characteristic being opposite. For example, the dispersant 300 may include a plurality of charged particles 301 and a plurality of charged particles 302. The charged particles 301 and 302 are different in color and have opposite electrical properties; for example, the charged particles 301 are black particles and are positively charged, while the charged particles 302 are white particles and are negatively charged.

[0071] In some embodiments, a plurality of pixel regions PR are arranged in an array along a direction parallel to the main surface of the base substrate 100 (e.g., directions D1 and D2), and a barrier wall region BR may surround each pixel region PR in a direction parallel to the base substrate 100 (e.g., a horizontal direction including directions D1 and D2); that is, a barrier wall region BR is provided between every two adjacent pixel regions PR in the arrangement direction of the plurality of pixel regions PR. Direction D1 and direction D2 intersect with each other, for example, are perpendicular to each other. For the sake of simplicity of the diagram, FIG2A shows only one pixel region PR and barrier wall regions BR located on both sides of the pixel region in direction D1. The ellipsis in FIG2A located in the side areas of the barrier wall region BR indicates that other pixel regions and barrier wall regions may also be provided in these areas. It should be understood that the number of pixel regions shown in FIG2A and FIG3A is for illustrative purposes only, and the present disclosure is not limited thereto.

[0072] In each pixel region PR, the common electrode 201 and the pixel electrode pe are opposite to each other in a direction perpendicular to the main surface of the substrate 100 (for example, direction D3), and the pixel electrode pe may include a plurality of pixel sub-electrodes separated from each other, for example, pixel sub-electrodes spe1 and spe2. The plurality of pixel sub-electrodes spe1 and spe2 may be configured to receive the same or different data signals to be applied with the same or different voltages. The common electrode 201 may be configured to receive a common voltage (Vcom) signal, and an electric field along the direction D3 (i.e., a vertical electric field) may be generated between the common electrode 201 and each pixel sub-electrode. In some examples, different pixel sub-electrodes spe1 and spe2 located in the same pixel region PR may receive different voltage signals, thereby generating an electric field between different pixel sub-electrodes, the direction of the electric field being parallel to the main surface of the substrate, for example, the same as direction D1, and may be referred to as a horizontal electric field. It should be understood that in this article, the directions D1, D2, and D3 identified each include two opposite directions. For example, direction D1 includes the rightward and leftward directions in the figure, direction D3 includes the upward and downward directions in the figure, and direction D2 includes the direction toward or away from the paper in Figure 2A.

[0073] In some embodiments, within a pixel region, the multiple electric fields generated by the common electrode and multiple pixel sub-electrodes may collectively constitute a combined electric field. By controlling the voltage signals applied to the multiple pixel sub-electrodes, the direction and intensity of the electric field within the pixel region are controlled, thereby controlling the aggregation morphology of the charged particles and, in turn, controlling the display state of the pixel region. By splitting the pixel electrode within the pixel region into multiple, separated pixel sub-electrodes, and connecting the multiple pixel sub-electrodes to multiple different data signal lines so that each pixel sub-electrode can be individually controlled, the diversity of the charged particle aggregation morphology within the pixel region can be increased, and this facilitates precise control of the charged particle aggregation morphology, thereby enhancing the diversity and accuracy of the display of the display device.

[0074] With reference to Figures 2A and 3A, in some embodiments, in the barrier wall region between each two adjacent pixel regions, the barrier wall electrode structure includes three barrier wall electrodes, for example, a first barrier wall electrode, a second barrier wall electrode, and a third barrier wall electrode. The first barrier wall electrode, the second barrier wall electrode, and the third barrier wall electrode are sequentially arranged along the arrangement direction of the two adjacent pixel regions. For example, a plurality of pixel regions include a first pixel region PR1 and a second pixel region PR2 that are arranged in a direction D1 or D2 and are adjacent to each other, and the barrier wall electrode structure includes barrier wall electrodes be1a, be2, and be1b. The barrier wall electrodes be1a, be2, and be1b may be referred to as the first barrier wall electrode, the second barrier wall electrode, and the third barrier wall electrode, respectively. At least a portion of the barrier wall electrodes be1a, at least a portion of the barrier wall electrodes be2, and at least a portion of the barrier wall electrodes be1b are located between the first pixel region PR1 and the second pixel region PR2, and are sequentially arranged along the arrangement direction of the two adjacent pixel regions (for example, direction D1 or D2), and are spaced apart from each other, and are configured to generate an electron barrier wall comprising two electric fields in opposite directions between the two adjacent pixel regions. The arrows in FIG2A schematically illustrate the electric field formed by the multiple barrier wall electrodes in the barrier wall region. FIG3C and FIG3D schematically illustrate two reverse electric fields generated by three barrier wall electrodes between two adjacent pixel regions.

[0075] Referring to Figures 2A, 3A, 3C, and 3D, in the barrier wall region BR between each two adjacent pixel regions, at least portions of each of the three barrier electrodes be1a, be2, and be1b may be arranged along the arrangement direction of the two adjacent pixel regions (e.g., direction D1 or D2) and spaced apart from each other. That is, barrier electrodes be1a and be1b are arranged on opposite sides of barrier electrode be2 in the arrangement direction of the two adjacent pixel regions. Barrier electrode be2 is configured to receive a different voltage signal than barrier electrodes be1a and be1b, and barrier electrodes be1a and be1b may be configured to receive the same or different voltage signals. For example, barrier electrodes be1a, be2, and be1b may be configured to receive a first voltage ΔV1, a second voltage ΔV2, and a third voltage ΔV3, respectively; the second voltage ΔV2 is different from the first voltage ΔV1 and the third voltage ΔV3, and the first voltage ΔV1 and the third voltage ΔV3 may be the same or different. For example, in some examples, the first voltage ΔV1 and the third voltage ΔV3 may both be less than the second voltage ΔV2 or both be greater than the second voltage ΔV2, and the first voltage ΔV1 and the third voltage ΔV3 may be the same as each other.

[0076] For example, as shown in Figures 2A and 3C, the second voltage ΔV2 can be greater than the first voltage ΔV1 and greater than the third voltage ΔV3, and the first voltage ΔV1 and the third voltage ΔV3 can be substantially the same. Thus, the electron barrier formed by the barrier electrode structure between two adjacent pixel regions includes two electric fields with opposite directions and facing away from each other. For example, an electric field can be generated between barrier electrode be1a and barrier electrode be2, with a direction from barrier electrode be2 toward barrier electrode be1a; and an electric field can be generated between barrier electrode be1b and barrier electrode be2, with a direction from barrier electrode be2 toward barrier electrode be1b. In this example, the electric fields generated by barrier electrodes be1a and be2 can prevent positively charged particles in pixel region PR1 from approaching or entering barrier region BR and then crossing barrier region BR to reach pixel region PR2. They can also prevent negatively charged particles in pixel region PR2 from approaching or entering barrier region BR and then crossing barrier region BR to reach pixel region PR1. The electric field generated by the barrier electrodes be1b and be2 can prevent negatively charged particles in the pixel region PR1 from approaching or crossing the barrier region BR to cross into the pixel region PR2, and can also prevent positively charged particles in the pixel region PR2 from approaching or crossing the barrier region BR to cross into the pixel region PR1. However, the present disclosure is not limited thereto.

[0077] For example, as shown in Figures 2A and 3D, the second voltage ΔV2 can be less than the first voltage ΔV1 and the third voltage ΔV3, and the first voltage ΔV1 and the third voltage ΔV3 can be substantially equal. Thus, the electron barrier formed by the barrier electrode structure between two adjacent pixel regions includes two electric fields with opposite directions and facing each other. For example, an electric field can be generated between barrier electrode be1a and barrier electrode be2, with a direction from barrier electrode be1a to barrier electrode be2; and an electric field can be generated between barrier electrode be1b and barrier electrode be2, with a direction from barrier electrode be1b to barrier electrode be2. In this example, the electric field generated by barrier electrodes be1a and be2 can prevent negatively charged particles in pixel region PR1 from approaching or entering barrier region BR and then crossing barrier region BR to reach pixel region PR2. Furthermore, the electric field can prevent positively charged particles in pixel region PR2 from approaching or entering barrier region BR and then crossing barrier region BR to reach pixel region PR1. The electric field generated by the barrier electrodes be1b and be2 can prevent positively charged particles in the pixel area PR1 from approaching or crossing the barrier area BR to cross to the pixel area PR2, and can prevent negatively charged particles in the pixel area PR2 from approaching or crossing the barrier area BR to cross to the pixel area PR1.

[0078] In the embodiment of the present disclosure, since the multiple barrier electrodes provided in the barrier region between adjacent pixel regions generate an electron barrier comprising two reverse electric fields, regardless of whether the charged particles in the pixel region are positively charged and / or negatively charged, the electron barrier can effectively prevent the charged particles in each pixel region from approaching the barrier region or crossing the barrier region to crosstalk to other adjacent pixel regions. Specifically, charged particles 301 having a first electrical property (e.g., positive charge) can be prevented from approaching the barrier region or crossing the barrier region to crosstalk to other pixel regions by one of the two reverse electric fields, and charged particles 302 having a second electrical property (e.g., negative charge) can be prevented from approaching the barrier region or crossing the barrier region to crosstalk to other pixel regions by the other of the two reverse electric fields.

[0079] It should be noted that the directions of the electric field lines in FIG. 2A and FIG. 3C and FIG. 3D are shown as being completely opposite and identical to the arrangement direction of the adjacent pixel regions, but this is for illustrative purposes only and the present disclosure is not limited thereto. In some embodiments, in the barrier region BR, the plurality of barrier electrodes and the common electrode 201 of the second substrate S1 are also opposite to each other in a direction perpendicular to the main surface of the base substrate 100; in addition to generating an electric field in the horizontal direction (i.e., parallel to the main surface of the base substrate) by applying a voltage signal to the corresponding barrier electrodes, an electric field in the vertical direction (i.e., perpendicular to the main surface of the base substrate) can also be generated between one or more of the barrier electrodes and the common electrode 201. The horizontal electric field and the vertical electric field generate a combined electric field, and at least one component of the direction of the combined electric field can be the same as the arrangement direction of the adjacent pixel regions. For example, the direction of the combined electric field (first electric field) generated by the barrier electrode be1a, the barrier electrode be2 and the common electrode 201 can be diagonally upward or downward, and have a component horizontally to the left or horizontally to the right (left and right here are the directions shown in the figure); the direction of the combined electric field (second electric field) generated by the barrier electrode be1b, the barrier electrode be2 and the common electrode 201 can be diagonally upward or downward, and have a component to the right or to the left; that is, at least one component of the first electric field direction (for example, a component in a direction parallel to the main surface of the substrate) and at least one component of the second electric field direction (for example, a component in a direction parallel to the main surface of the substrate) are opposite to each other. Therefore, in this article, two reverse electric fields include two electric fields with completely opposite directions (for example, the case shown in the figure), and also include the case where at least one component of the two electric field directions (for example, a component parallel to the main surface of the substrate) is opposite to each other. In various embodiments of the present disclosure, at least one component of the first electric field direction and at least one component of the second electric field direction included in the electron blocking wall between every two adjacent pixel regions are opposite to each other and are the same as the arrangement direction of the two adjacent pixel regions.

[0080] It should be understood that the above embodiment is illustrated by taking the pixel region as an example in which two charged particles of opposite electrical properties are simultaneously included, but the present disclosure is not limited to this. In alternative embodiments, the pixel region may also include charged particles of only one electrical property; for example, the pixel region may only include negatively charged white particles, and a corresponding black light-absorbing layer is provided in the first substrate. In this case, the electron retaining wall shown in Figures 3C and 3D may also be used, and the electron retaining wall shown in Figure 3D may be preferred; or the pixel region may only include positively charged black particles, and a corresponding reflective layer is provided in the first substrate. In this case, the electron retaining wall shown in Figures 3C and 3D may also be used, and the electron retaining wall shown in Figure 3C may be preferred.

[0081] 2A and 3A , in some embodiments, a plurality of pixel regions PR are arranged in an array along a direction parallel to the main surface of the substrate 100 , for example, arranged in multiple rows along direction D1 and in multiple columns along direction D2 . It should be noted that FIG. 3A only briefly illustrates the outline of the pixel region PR and does not specifically illustrate the multiple pixel sub-electrodes located in the pixel region. For example, each pixel region PR is surrounded by a barrier electrode be1 in a direction parallel to the main surface of the substrate (which direction includes the arrangement direction of the pixel regions), and each barrier electrode be1 is surrounded by a barrier electrode be2 in a direction parallel to the main surface of the substrate (which direction includes the arrangement direction of the pixel regions). This allows a barrier electrode be2 to be provided between any two adjacent pixel regions, as well as barrier electrodes be1 located on opposite sides of the barrier electrode be2 in the arrangement direction of the two adjacent pixel regions. This allows the barrier electrode structure to generate an electron barrier consisting of two opposite electric fields between any two adjacent pixel regions.

[0082] Multiple barrier electrodes be1 may be provided in a one-to-one correspondence with multiple pixel regions PR, and the multiple barrier electrodes be1 are separated by barrier electrodes be2. With respect to two adjacent pixel regions (e.g., a first pixel region and a second pixel region adjacent in direction D1 or direction D2), the barrier electrode be1 surrounding the first pixel region and the barrier electrode be1 surrounding the second pixel region may serve as the barrier electrode be1a and the barrier electrode be1b in FIG. 2A and FIG. 3C , respectively, or vice versa. In some embodiments, the barrier electrode be2 may be referred to as the second barrier electrode, and the barrier electrode be1a and the barrier electrode be1b may be referred to as the first barrier electrode and the third barrier electrode, respectively, or vice versa; alternatively, all barrier electrodes be1 may be referred to as the first barrier electrode.

[0083] In some embodiments, the barrier electrode be1 may be in a grid shape and define a plurality of grid regions gr. The pixel regions PR and the barrier electrode be1 may be arranged in a one-to-one correspondence with the grid regions gr, so that a pixel region PR (i.e., a pixel electrode pe) and a barrier electrode be1 surrounding the pixel region PR are provided in each grid region gr. In this document, a grid region refers to a hollow region formed by the electrode portion of the grid-shaped barrier electrode. For example, the barrier electrode includes a plurality of electrode strips extending in a direction D1 and parallel to each other and a plurality of electrode strips extending in a direction D2 and parallel to each other. The plurality of electrode strips extending in the direction D1 and the plurality of electrode strips extending in the direction D2 intersect with each other to form a grid shape and define a plurality of grid regions gr. The plurality of electrode strips of the barrier electrode be2 may also be referred to as grid lines of the grid-shaped electrode. In other words, the barrier electrode be1 has a plurality of annular portions, the inner sidewall of each annular portion defining a grid region gr and surrounding the barrier electrode be1 and the pixel region PR located in the grid region gr.

[0084] FIG3B shows a schematic plan view of a pixel region and its surrounding barrier wall regions according to some other embodiments of the present disclosure.

[0085] Referring to FIG. 3B , in some embodiments, three ring-shaped barrier electrodes be1, be2, and be3 are disposed around the pixel region PR. The barrier electrodes be1, be2, and be3 are spaced apart from each other and their distances from the pixel region PR increase in sequence. For example, the pixel region PR is surrounded by the barrier electrode be1, the barrier electrode be1 is surrounded by the barrier electrode be2, and the barrier electrode be2 is surrounded by the barrier electrode be3.

[0086] In some embodiments, the structure shown in FIG3B is substantially equivalent to the structure shown in FIG3A . For example, taking the pixel region PR located at the center of FIG3A as an example, the barrier electrodes be1 and be2 directly surrounding the pixel region PR are equivalent to the barrier electrodes be1 and be2 shown in FIG3B . The barrier electrodes be1 surrounding the other adjacent pixel regions PR each have portions opposite to the barrier electrodes be2 , and together they form a similar ring-shaped barrier electrode; this similar ring-shaped barrier electrode is substantially equivalent to the barrier electrode be3 shown in FIG3B .

[0087] 3A to 3D , for each pixel region PR, three barrier electrodes are provided between the pixel region PR and each adjacent pixel region. The three barrier electrodes are configured to generate two electric fields with opposite electric field directions, thereby preventing crosstalk between charged particles in the pixel region and adjacent pixel regions.

[0088] In some embodiments, applying a voltage signal to each barrier electrode in the barrier electrode structure may include connecting the edge of the corresponding barrier electrode (e.g., the portion located at the edge of the display area) to a signal line provided in the same layer, so as to apply a voltage signal to the corresponding barrier electrode through the signal line; or may also include connecting the barrier electrode to a signal line located in a different layer through a via, so as to apply a corresponding voltage signal to the barrier electrode through the signal line and the via. For example, in the barrier structure shown in FIG3A , for the barrier electrode be2, the portion of the barrier electrode be2 located at the edge of the display area may be connected to a voltage signal line (not shown) to receive a corresponding voltage signal, while the barrier electrode be1 may be connected to a voltage signal line located in another layer through a via to receive a corresponding voltage signal. FIG3E schematically shows that the corresponding barrier electrode is connected to a signal line L located in a different layer through a via V, and the signal line L is configured to apply a voltage signal to the barrier electrode. It should be understood that the embodiments of the present disclosure do not limit the manner in which each barrier electrode receives a voltage signal, as long as the barrier electrode structure can receive a corresponding voltage signal to form an electron barrier.

[0089] In some embodiments, as shown in FIG2A , since the electron blocking wall formed by the blocking wall electrode structure can effectively block the crosstalk of charged particles between adjacent pixel areas, the physical blocking wall (or insulating blocking wall) can be omitted. That is, the display device 500 may not include a physical blocking wall disposed between the first substrate S1 and the second substrate S2 and located between adjacent pixel areas. For example, the dispersant 300 may also be located in the blocking wall area BR, that is, it may be located in an area that overlaps with the blocking wall electrode structure in a direction perpendicular to the main surface of the base substrate 100. Moreover, due to the electron blocking wall generated by the blocking wall electrode structure, the charged particles located in the pixel area PR generally do not crosstalk into the dispersant 300 located in the blocking wall area BR. Therefore, the crosstalk of charged particles can be effectively blocked only by the electron blocking wall formed by the blocking wall electrode structure. However, the present disclosure is not limited to this.

[0090] In other embodiments, in addition to the electronic barrier formed by the plurality of barrier electrodes, the barrier region BR may also include a physical barrier. The region where the physical barrier may overlap or not overlap with the region where the electronic barrier is located. For example, at least a portion of the physical barrier may be disposed in the region where the electronic barrier is located, and may overlap or not overlap with the barrier electrodes in a direction perpendicular to the major surface of the substrate; for example, the physical barrier may overlap with one or more barrier electrodes in the barrier electrode structure in a direction perpendicular to the major surface of the substrate.

[0091] Figures 2B and 2C are schematic cross-sectional views of display devices according to other embodiments of the present disclosure, illustrating examples of barrier regions including both physical and electronic barrier walls. In some embodiments, a physical barrier wall PW is further provided in barrier region BR. Physical barrier wall PW is provided between first substrate S1 and second substrate S2 in a direction perpendicular to the main surface of the substrate, and between adjacent pixel regions in a direction parallel to the main surface of the substrate.

[0092] 2B , in some embodiments, the physical barrier wall PW has a dimension (e.g., width, area, etc.) greater than that of a single barrier wall electrode in a direction parallel to the base substrate 100 (e.g., direction D1 and / or D2), and the physical barrier wall PW overlaps with multiple barrier wall electrodes in a direction D3 perpendicular to the base substrate 100. For example, the physical barrier wall PW may cover the sidewalls of the barrier wall electrodes be1a, be2, and be1b and their surfaces away from the base substrate 100, fill the gap between adjacent barrier wall electrodes, and extend toward the second substrate S2 until it approaches or contacts the common electrode 201.

[0093] 2C , in other embodiments, the physical barrier wall PW has a dimension (e.g., width, area, etc.) that is smaller or larger than a single barrier wall electrode in a direction parallel to the base substrate 100 (e.g., direction D1 and / or D2), and the physical barrier wall PW overlaps with a portion of the barrier wall electrode in a direction perpendicular to the base substrate 100. For example, the physical barrier wall PW may be located on the barrier wall electrode be1a, covering the sidewall of the barrier wall electrode be1a and its surface on the side away from the base substrate 100, and extending toward the second substrate S2 until it is close to or in contact with the common electrode 201. In this example, the physical barrier wall PW is disposed on the barrier wall electrode be1a near the pixel area. In other examples, the physical barrier wall PW may also be disposed on the barrier wall electrode be2 or be1b, or on any two of the three barrier wall electrodes, or in the gap between adjacent barrier wall electrodes.

[0094] In some embodiments, the physical barrier wall PW is located between the first substrate 100 and the second substrate 200 in a direction perpendicular to the main surface of the base substrate 100, and extends from the barrier region BR of the first substrate 100 (for example, on the barrier electrode) to the common electrode 201 close to or in contact with the second substrate S2. In the embodiment of the present disclosure, since an electronic barrier wall with two opposite electric fields is provided, charged particles in the pixel region PR can be prevented from approaching or crossing the barrier region. Therefore, even if the height of the physical barrier wall PW is uneven, charged particles in the pixel region can be prevented from crossing the barrier region and crosstalking to other pixel regions. Moreover, the barrier region uses an electronic barrier wall and a physical barrier wall to form a barrier structure, and the two can jointly block charged particles, thereby providing double protection and improving the ability of the barrier structure to prevent charged particles from crosstalking in adjacent pixel regions.

[0095] Figure 2D shows a schematic cross-sectional view of an electronic paper display device according to some other embodiments of the present disclosure. The solid arrows in Figure 2D schematically show the state where light is reflected after being irradiated by the display device, and the dotted arrows schematically show the direction of the electric field lines.

[0096] Referring to Figure 2D , in some embodiments, the electronic paper display device may further include a reflective electrode re. The reflective electrode re may be located lateral to the pixel electrode pe in a direction parallel to the main surface of the substrate 100, or may overlap with the pixel electrode pe in a direction perpendicular to the main surface of the substrate 100. The reflective electrode re may be located in the pixel region and / or the barrier region. The reflective electrode reflects light incident from the display side. For example, some light from the display side strikes the white particles and is reflected by them; some light passes through the white particles and strikes the reflective electrode and is reflected by it. This achieves secondary reflection, thereby enhancing the white state display of the pixel region. For example, in a pixel region, the multiple pixel sub-electrodes of the pixel electrode pe are spaced apart from each other. The reflective electrode re may be located lateral to the pixel sub-electrodes in a direction parallel to the main surface of the substrate 100, and may be located in the gaps between adjacent pixel sub-electrodes. For example, the reflective electrode re may be located between adjacent pixel electrodes in adjacent pixel regions. In some embodiments, the reflective electrode re and the pixel electrode pe may be disposed in different layers, and the reflective electrode re and the pixel electrode pe may overlap in a direction perpendicular to the main surface of the base substrate 100, but the present disclosure is not limited thereto. In other embodiments, the reflective electrode re and the pixel electrode pe may also be disposed in the same layer.

[0097] 2A to 2D , a packaging frame 80 is further disposed between the edges of the first substrate S1 and the second substrate S2 . The packaging frame 80 , the first substrate S1 , and the second substrate S2 together define a space where the dispersant layer DL is located.

[0098] FIG4 shows a schematic cross-sectional view of an array substrate according to some embodiments of the present disclosure, where the array substrate may be used as a first substrate in an electronic paper display device.

[0099] Referring to Figure 4, the array substrate S1a may include a plurality of pixel areas arranged in an array in the display area, a pixel electrode is provided in each pixel area, and the array substrate S1a includes a driving circuit connected to the pixel electrode. For example, in each pixel area, the pixel electrode may include a plurality of pixel sub-electrodes, and each pixel sub-electrode is connected to a corresponding driving circuit. The driving circuit may include one or more transistors and capacitors. Each transistor includes a gate, a gate insulating layer, an active layer, a source, and a drain, and each capacitor includes at least two electrode plates arranged opposite to each other, such as a first plate and a second plate, and the pixel sub-electrode of each pixel electrode is electrically connected to one of the source and drain of the corresponding transistor, and is electrically connected to the electrode plate (for example, the first plate or the second plate) of the corresponding capacitor.

[0100] It should be noted that in this article, "pixel area" refers to the effective display area, that is, the area in the electronic paper display device where charged particles are controlled by the pixel electrode and the common electrode, which area is roughly the area where the pixel electrode is located; the orthographic projection of the outer contour of the pixel area on the substrate may roughly coincide with the orthographic projection of the outer contour of the pixel electrode on the substrate; or the orthographic projection range of the pixel area is slightly larger than the said orthographic projection range of the pixel electrode, and the orthographic projection of the pixel electrode is within the orthographic projection range of the pixel area; in the case where the pixel electrode includes multiple pixel sub-electrodes, the pixel area includes the area where the multiple pixel sub-electrodes are located and the area where the gaps between the multiple pixel sub-electrodes are located, the outer contour of the pixel electrode is formed by connecting the outer contours of the multiple pixel sub-electrodes away from each other, and the orthographic projection of the pixel area on the main surface of the substrate roughly coincides with the orthographic projection of the multiple pixel sub-electrodes and the gaps between them on the main surface of the substrate.

[0101] For example, the array substrate S1a may include a base substrate 100, a transistor T, a capacitor C, a pixel electrode pe, and a barrier electrode structure be. The transistor T may include a gate GE, an active area AL, a source S, a drain D, and a gate insulating layer. The source S and drain D are interchangeable and may be collectively referred to as source / drain S / D. That is, the source S and drain D described in the figure may also be referred to as the drain D and source S, respectively. The capacitor C may include at least opposing electrode plates CE1 and CE2, and an inter-electrode insulating layer. In some embodiments, the electrode plates CE1 and CE2 may also be referred to as the first plate and the second plate, respectively.

[0102] For example, the array substrate S1a may include a conductive layer 101, an insulating layer 102, an active layer 103, a conductive layer 105, an insulating layer 106, an electrode layer 107, and a passivation layer 108, which are disposed on one side of a base substrate 100. The conductive layer 101, the insulating layer 102, the active layer 103, the conductive layer 105, the insulating layer 106, and the electrode layer 107 may be referred to as a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, and a first electrode layer, respectively. The conductive layer 101 is disposed on the base substrate 100 and may include a metal material such as copper, aluminum, molybdenum, or titanium. The insulating layer 102 is disposed on the base substrate 100 and covers the sidewalls of the conductive layer 101 and its surface away from the base substrate 100. The insulating layer 102 may include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. Active layer 103 and conductive layer 105 are located on the side of insulating layer 102 away from substrate 100, with conductive layer 105 partially covering a portion of the surface of active layer 103. Active layer 103 may include active materials such as low-temperature polysilicon or indium gallium zinc oxide (IGZO), while conductive layer 105 may include metal materials such as copper, aluminum, molybdenum, and titanium. Insulating layer 106 is disposed on insulating layer 102 and covers active layer 103 and conductive layer 105. Insulating layer 106 may include insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. Electrode layer 107 is located on the side of insulating layer 106 away from substrate 100. Electrode layer 107 may include a metal oxide such as indium tin oxide (ITO), or a metal oxide doped with a metal, such as a metal with reflective properties. For example, electrode layer 107 may include silver-doped indium tin oxide, but the present disclosure is not limited thereto. The passivation layer 108 is disposed on the insulating layer 106 and covers the sidewalls of the electrode layer 107 and the surface thereof away from the base substrate 100 . The passivation layer 108 includes, for example, an insulating material such as silicon nitride.

[0103] In some embodiments, the gate GE of the transistor T and one of the first and second plates of the capacitor C (e.g., the first plate CE1) are disposed in the same layer, for example, both disposed in the conductive layer 101. The active area AL of the transistor T is disposed in the active layer 103; the source and drain electrodes S / D of the transistor T may be disposed in the same layer as the other of the first and second plates of the capacitor C (e.g., the second plate CE2), for example, both disposed in the conductive layer 105. In each transistor T, the active layer 103 and the gate GE overlap in a direction perpendicular to the main surface of the substrate 100. A portion of the insulating layer 102 is located between the active layer 103 and the gate GE and serves as the gate insulation layer of the transistor T. The source electrode S and the drain electrode D respectively cover the sidewalls of the active layer 103 and the portion of its surface away from the substrate 100. In each capacitor C, the first and second plates CE1 and CE2 overlap in a direction perpendicular to the main surface of the substrate 100. A portion of the insulating layer 102 is located between the first and second plates CE1 and CE2 and serves as the inter-electrode insulation layer of the capacitor C.

[0104] In some embodiments, multiple pixel sub-electrodes spe of multiple pixel electrodes pe are arranged in the electrode layer 107; the blocking wall electrode structure be can be arranged in the same layer as the multiple pixel electrodes pe, for example, all are arranged in the electrode layer 107, and are spaced apart from each other. The blocking wall electrode structure be can also be reused as a reflective electrode re. That is, the pixel electrode pe, the blocking wall electrode structure be and the reflective electrode re can all be arranged in the same layer in the electrode layer 107. For the sake of simplicity of the diagram, only one pixel sub-electrode and the corresponding transistors, capacitors, blocking wall electrodes, etc. are shown in Figure 4. It should be understood that the other pixel sub-electrodes have similar cross-sectional structures. In this article, multiple components are "arranged in the same layer" means that the multiple components can be formed from the same material layer through the same patterning process.

[0105] In some embodiments, the pixel sub-electrode spe may extend through the insulating layer 106 to be electrically connected to one of the source and drain electrodes (e.g., the drain electrode D) of the transistor T, and may extend through the insulating layer 106, the conductive layer 105, and the insulating layer 102 to be electrically connected to the conductive layer 101, for example, to the first electrode plate CE1 located in the conductive layer 101. For example, a via v1 is provided in the insulating layer 106, and the pixel sub-electrode spe is electrically connected to the source electrode S or the drain electrode D (e.g., the drain electrode D) of the transistor T through the via v1; and a via v2 is provided in the insulating layers 106 and 102, and the pixel sub-electrode spe is electrically connected to the first electrode plate CE1 through the via v2. For example, the conductive layer 105 includes an opening 105o, and at least a portion of the opening 105o overlaps with the first electrode plate CE1 in a direction perpendicular to the main surface of the base substrate. The opening 105o may be located in or include the gap between the second electrode plate CE2 and the source / drain electrodes S / D. The via v2 passes through the opening 105o and is spaced apart from the conductive layer 105. That is, the via v2 extends from the surface of the insulating layer 106 away from the base substrate 100, through the insulating layer 106, through the opening 105o in the conductive layer 105, and then through the insulating layer 102 to expose a portion of the surface of the first electrode plate CE1, thereby electrically connecting the pixel sub-electrode SPE to the first electrode plate CE1 through the via v2. In other words, the portion of the pixel sub-electrode SPE located in the via v2 is located in the opening 105o in the conductive layer 105 and is spaced apart from the conductive layer 105.

[0106] In some embodiments, at least a portion of the pixel sub-electrode SPE may overlap with the second electrode plate CE2 in a direction perpendicular to the main surface of the substrate 100; that is, the orthographic projection of the pixel sub-electrode SPE on the substrate overlaps with the orthographic projection of the second electrode plate CE2 on the substrate. In other words, the pixel sub-electrode SPE is electrically connected to the first electrode plate CE1 of the capacitor CE1 and is disposed opposite the second electrode plate CE2. Therefore, the pixel sub-electrode SPE can also serve as the third electrode plate CE3 of the capacitor C, and the portion of the insulating layer 106 located between the second electrode plate CE2 and the pixel sub-electrode SPE can serve as an inter-electrode insulating layer. That is, the capacitor C includes the first electrode plate CE1, the second electrode plate CE2, the third electrode plate CE3, and the inter-electrode insulating layers 102 and 106. The second electrode plate CE2 is located between the first electrode plate CE1 and the third electrode plate CE3 in a direction perpendicular to the main surface of the substrate 100, and the first electrode plate CE1 and the third electrode plate CE3 are electrically connected to each other. In this way, the capacitor C includes double-layer capacitors formed between the first electrode plate CE1 and the second electrode plate CE2 and between the second electrode plate CE2 and the third electrode plate CE3, thereby increasing the capacitance area and improving the capacitance of the capacitor C.

[0107] In some embodiments, the second electrode plate CE2 can be configured to receive a common voltage (Vcom) signal, and the second electrode plate CE2 can also be multiplexed into a signal shielding structure to shield the signal of the layer below (eg, gate signal) from crosstalk to the pixel electrode pe.

[0108] In some embodiments, a portion of the barrier wall electrodes (e.g., the first barrier wall electrodes) in the barrier wall electrode structure bee can be electrically connected to the conductive layer 105 through the insulating layer 106 and configured to receive the Vcom signal. For example, the insulating layer 106 includes a via v3, and the portion of the barrier wall electrodes in the barrier wall electrode structure bee is electrically connected to the second electrode plate CE2 through the via v3 and configured to receive the Vcom signal. In some embodiments, the via v1, via v2, and via v3 can be referred to as the first via, the second via, and the third via, respectively.

[0109] Figures 5 to 9B show schematic planar layout diagrams of the various layers and / or multilayer stacks of the array substrate S1a shown in Figure 4 according to some embodiments of the present disclosure. For the sake of simplicity of the diagrams, Figures 5 to 9B only show the relevant layout diagrams of one pixel area and the surrounding barrier area. In some embodiments, in each pixel area, each pixel electrode includes a plurality of pixel sub-electrodes, each pixel sub-electrode is respectively connected to a corresponding transistor and capacitor, each transistor is respectively connected to a corresponding data signal line, and the data signal line is configured to apply a data signal to the corresponding pixel sub-electrode through the transistor. That is, the plurality of pixel sub-electrodes are respectively connected to a plurality of data signal lines. For example, the pixel sub-electrodes can be arranged in a one-to-one correspondence with the transistors, capacitors, and data signal lines. For example, in this example, in a single pixel area, the pixel electrode includes five pixel sub-electrodes, and accordingly, the array substrate includes five transistors, five capacitors, and five data signal lines arranged corresponding to the five pixel sub-electrodes. However, the present disclosure is not limited to this.

[0110] Figure 5 shows a schematic planar layout diagram of the conductive layer 101 in the array substrate S1a. The conductive layer 101 includes multiple gates GE, multiple electrode plates CE1, and also includes gate signal lines GL. The multiple gates GE can be arranged at intervals from each other and correspond to multiple transistors T respectively. The multiple transistors T can be arranged in a row along a direction D1. For example, the multiple gates GE can be arranged in a row along a direction D1, and the gate signal line GL is electrically connected to the multiple gates GE located in the same row so as to be configured to apply a scan signal to the multiple gates GE in the row. The multiple electrode plates CE1 are arranged at intervals from each other and correspond to multiple capacitors C respectively. The multiple electrode plates CE1 are also spaced apart from the gates GE and the gate lines GL. In some embodiments, each electrode plate CE1 has a connection area a for electrically connecting to a subsequent pixel electrode.

[0111] Figure 6 shows a schematic layout diagram of the stack of conductive layer 101 and active layer 103. Active layer 103 includes multiple active areas AL, each corresponding to a plurality of transistors. Each active area AL overlaps with a corresponding gate electrode GE in a direction perpendicular to the main surface of the substrate. For example, the orthographic projection of the active area AL on the substrate is within the orthographic projection of the corresponding gate electrode GE on the substrate, but this disclosure is not limited to this.

[0112] FIG7A shows a schematic layout diagram of a stack of conductive layer 101 , active layer 103 , and conductive layer 105 ; FIG7B shows a schematic layout diagram of conductive layer 105 .

[0113] Referring to Figures 7A and 7B , the conductive layer 105 includes the source electrodes S and drain electrodes D of multiple transistors, a data signal line SL, and the second plates CE2 of multiple capacitors C. In each transistor T, the source electrode S and drain electrode D each cover a portion of the corresponding active area AL and may overlap the corresponding gate electrode GE. One of the source and drain electrodes, for example, the source electrode S, is connected to the data signal line SL. Unless otherwise specified herein, the overlapping of multiple components described with reference to a planar layout diagram refers to the overlapping of the multiple components in a direction perpendicular to the main surface of the substrate, i.e., the orthographic projections of the multiple components on the main surface of the substrate overlap. The positional relationships between the components shown in the planar layout diagram may include or be equivalent to the positional relationships between the orthographic projections of the components on the main surface of the substrate.

[0114] In some embodiments, among the multiple data signal lines, each data signal line SL includes at least a data signal main line SLa, and one or more of the multiple data signal lines may each further include a data signal auxiliary line SLb and a transfer electrode. The data signal main line SLa and the data signal auxiliary line SLb may be electrically connected to each other via the transfer electrode. The data signal main line SLa and the data signal auxiliary line SLb may be arranged in the same layer on the conductive layer 105, while the transfer electrode may be arranged in a different layer, but the present disclosure is not limited to this. For example, the multiple data signal main lines SLa may extend substantially parallel to each other along the direction D2 and be arranged on the sides of the multiple transistors in the direction D1, such as on opposite sides. The data signal line SL connected to the source S of the transistor located at an end (e.g., the left end in the figure) may include only the data signal main line SLa, which is directly connected to the corresponding source S. For example, a portion of the data signal main line SLa serves as the source S of the corresponding transistor, and the data signal line SL may not require a data signal auxiliary line. Here, the transistor located at the end refers to a transistor located at the end in the arrangement direction of the transistors among a plurality of transistors provided corresponding to the same pixel region.

[0115] In some embodiments, the data signal lines SL of one or more transistors each include a main data signal line SLa and an auxiliary data signal line SLb. The main data signal line SLa and the auxiliary data signal line SLb may be electrically connected via a switching electrode disposed in a subsequent electrode layer. Each auxiliary data signal line SLb may be directly connected to the source S of the corresponding transistor. For example, a portion of the auxiliary data signal line SLb may serve as the source S of the transistor. The main data signal line SLa corresponding to each auxiliary data signal line SLb is disposed outside the region where the transistor is located.

[0116] In some embodiments, each drain D has a connection area (the square area shown in the figure) to be configured to be electrically connected to the pixel sub-electrode in the subsequent electrode layer. When the data signal line SL includes a data signal main line SLa and a data signal auxiliary line SLb, the data signal main line SLa and the data signal auxiliary line SLb have corresponding connection areas (for example, the square area shown in the figure) to be configured to be electrically connected to the subsequent transfer electrode. In each component, the size of the connection area may be larger than the size of other areas to provide a larger connection window, which is conducive to electrical connection with other components. The connection area of ​​each component and its other areas can be integrally formed.

[0117] In the conductive layer 105, the electrode plate CE2 is spaced apart from the source S, drain D, data signal line SL, and drain signal line DL. In direction D1, the electrode plate CE2, the source S and drain D of the multiple transistors T, and the data signal auxiliary line SLb are all located to the side of the multiple data signal main lines SLa, for example, between the data signal main lines SLa. In direction D2, the electrode plate CE2 is located to one side of the source S and drain D of the multiple transistors T and the data signal auxiliary line SLb and is spaced apart from these components of the multiple transistors T. The electrode plate CE2 is arranged opposite the multiple electrode plates CE1 in a direction perpendicular to the main surface of the substrate and can be a single continuous electrode. That is, the multiple first electrode plates CE1 of the multiple capacitors C are spaced apart from each other, while the second electrode plates CE2 of the multiple capacitors C can share the same electrode plate.

[0118] In some embodiments, the electrode plate CE2 includes an electrode main body portion CE21, an electrode protrusion portion CE22, and an electrode protrusion portion CE23. The electrode main body portion CE21 is arranged opposite to the plurality of electrode plates CE1 and overlaps in a direction perpendicular to the main surface of the substrate. For example, the electrode main body portion CE21 is block-shaped. In some embodiments, the electrode main body portion CE21 has one or more notches c1, exposing the electrode plate CE1 located thereunder. The notch c1 corresponds to the opening 105o of the conductive layer 105 in FIG4 , and may be part of the gap between the electrode plate CE2 and components such as the source and drain of the transistor. It should be understood that the notch c1 exposing the electrode plate CE1 here means that from the perspective of the planar layout, the position where the notch c1 is located overlaps with the electrode plate CE1, and the electrode plate CE1 will not be covered by the electrode plate CE2 at this position. In fact, an insulating layer is also provided between the notch c1 and the electrode plate CE1, so the notch c1 will not directly expose the electrode plate CE1.

[0119] For example, the electrode body portion CE21 may have a plurality of notches c1, each of which corresponds one-to-one to a plurality of electrode plates CE1, and each notch c1 is disposed at a position corresponding to (e.g., overlapping) a connection area a of a corresponding electrode plate CE1. However, the present disclosure is not limited thereto. In other examples, each notch c1 may correspond to a plurality of electrode plates CE1, and the number of notches c1 may be adjusted as needed, as long as the notches c1 of the electrode plate CE2 can expose a plurality of electrode plates CE1, thereby facilitating the connection of subsequent electrode layers to the electrode plates CE1.

[0120] In some embodiments, the electrode protrusion CE22 and the electrode protrusion CE23 protrude from the electrode main body CE21 in a direction parallel to the main surface of the substrate (e.g., direction D2). For example, the electrode protrusion CE22 protrudes from the electrode main body CE21 in direction D2, away from the source and drain regions of the transistor; the electrode protrusion CE23 protrudes from the electrode main body CE23 in direction D2, toward the source and drain regions of the transistor. The electrode protrusion CE23 may be adjacent to the source and drain of the transistor T (e.g., a transistor located at an end of the plurality of transistors) in direction D1, and may overlap with the source and drain of the plurality of transistors in direction D1. That is, the orthographic projection of the electrode protrusion CE23 on a data signal main line SLa in direction D1 may overlap with the orthographic projection of the source and drain of the transistor on the data signal main line SLa in direction D1. However, the present disclosure is not limited to this.

[0121] In some embodiments, the electrode protrusions CE22 and CE23 may extend beyond the edge of the electrode plate CE1 in a direction parallel to the main surface of the base substrate, ie, may not overlap with the electrode plate CE1 in a direction perpendicular to the main surface of the base substrate.

[0122] Figure 8A shows a schematic planar layout diagram of a stack of conductive layer 101, active layer 103, conductive layer 105, and multiple vias in an insulating layer. Figure 8B shows a schematic planar layout diagram of a stack of conductive layer 105 and multiple vias in an insulating layer.

[0123] 4 , 8A and 8B , in some embodiments, a plurality of vias are provided in the insulating layer for electrical connection between different layers. For example, a plurality of vias v1 are provided in the insulating layer 106 and respectively expose a portion of the surface of the drain electrode D (e.g., its connection area) of the plurality of transistors T. A plurality of vias v2 are provided in the insulating layers 106 and 102, and may be located, for example, in the notch c1 of the electrode plate CE2 and respectively expose a portion of the surface of the connection area a of the plurality of electrode plates CE1. A plurality of vias v3 are provided in the insulating layer 106 and expose a portion of the surface of the electrode plate CE2, such as a portion of the surface of the exposed electrode protrusions CE22 and CE23. In some examples, each electrode protrusion CE22, CE23 is provided with a plurality of (e.g., three) vias v3, but the present disclosure is not limited thereto. The number of vias v3 can be adjusted according to product requirements.

[0124] In some embodiments, vias v4 and v5 are further provided in the insulating layer 106. For example, multiple vias v4 expose portions of the surface of the connection areas of multiple data signal main lines SLa, and multiple vias v5 expose portions of the surface of the connection areas of multiple data signal auxiliary lines SLb. For a data signal line SL that includes a data signal main line SLa and a data signal auxiliary line SLb, vias v4 and v5 are provided corresponding to the data signal main line SLa and the data signal auxiliary line SLb, respectively, so that subsequent transfer electrodes can electrically connect the data signal main line SLa and the data signal auxiliary line SLb through vias v4 and v5. For a data signal line SL that includes only a data signal main line SLa but not a data signal auxiliary line SLb, there is no need to provide a via corresponding to the data signal main line SLa.

[0125] 9A shows a schematic plan layout diagram of a stack of conductive layer 101, active layer 103, conductive layer 105, a plurality of vias in the insulating layer, and electrode layer 107. FIG9B shows a plan layout diagram of electrode layer 107.

[0126] 9A and 9B , the electrode layer 107 includes a pixel electrode sp, a barrier electrode structure, a reflective electrode, and a transition electrode TE. In some embodiments, in the pixel region PR, the pixel electrode sp includes a plurality of pixel sub-electrodes spe; for example, the plurality of pixel sub-electrodes spe include a plurality of strip electrodes arranged along a direction D1, spaced apart from each other, and extending substantially parallel to each other along a direction D2. The barrier electrode structure includes a barrier electrode be1 and a barrier electrode be2. The barrier electrode be1 surrounds the plurality of pixel sub-electrodes spe located in the pixel region PR, and the barrier electrode be2 is located on a side of the barrier electrode be1 away from the pixel region PR in a direction parallel to the main surface of the substrate and surrounds the barrier electrode be1. In some embodiments, the blocking wall electrode be1 may be in the shape of an open ring, that is, an open ring; for example, the pixel region PR is rectangular, the blocking wall electrode be1 may surround three sides of the pixel region PR, and the other side of the pixel region PR may not be surrounded by the blocking wall electrode be1; for example, a plurality of transfer electrodes TE may be located on the side of the pixel region PR that is not surrounded by the blocking wall electrode be1, and may be located between the pixel region PR and the blocking wall electrode be2 and / or between the blocking wall electrode be1 and the blocking wall electrode be2 in the direction D2.

[0127] For example, the barrier electrode be2 encloses and defines a grid region gr, and the pixel electrode pe, the barrier electrode be1, and the transition electrode TE are all disposed in the grid region gr surrounded by the barrier electrode be2. For example, each grid region gr is provided with a pixel region, a barrier electrode be1 surrounding the pixel region, and may include a corresponding transition electrode TE.

[0128] In some embodiments, the barrier electrode structure further includes a connecting electrode ae, which connects to the barrier electrode be1 and passes through the barrier electrode be2 to connect the barrier electrode be1 to the adjacent barrier electrode be1 (Figures 10A and 10B). Alternatively, the connecting electrode ae located at the end can be used to connect a voltage signal, such as a Vcom signal. For example, the barrier electrode be2 has an opening op, i.e., multiple portions of the barrier electrode be2 are disconnected at the opening op. The connecting electrode ae can extend from the edge of the barrier electrode be1 near the barrier electrode be2, through the opening op, and further extend to the adjacent barrier electrode be1 (Figures 10A and 10B). The width of the opening op is greater than the width of the connecting electrode ae, thereby isolating the connecting electrode ae from the barrier electrode be2. It should be understood that the width of the opening op and the connecting electrode ae refers to the width in a direction (e.g., direction D2) perpendicular to the extension direction of the connecting electrode (e.g., direction D1). In some embodiments, the connected barrier electrode be1 and the connecting electrode ae can be integrally formed.

[0129] Continuing with Figures 9A and 9B , each pixel sub-electrode spe is electrically connected to the drain D of the corresponding transistor T via via v1 and to the corresponding electrode plate CE1 via via v2. The barrier electrode be1 is connected to the electrode plate CE2 via via v3. In this example, the electrode plate CE2 has two electrode protrusions CE22 and CE23 as connection areas for electrical connection to the barrier electrode be1, but the number of electrode protrusions and the number of vias corresponding to each electrode protrusion are not limited to this. In some examples, providing multiple electrode protrusions and multiple vias can facilitate a stable connection between the barrier electrode be1 and the electrode plate CE21.

[0130] In some embodiments, the transfer electrode TE may correspond one-to-one to the data signal line SL, and be electrically connected to the corresponding data signal main line SLa and data signal auxiliary line SLb through via v4 and via v5, respectively, so that the data signal main line SLa and data signal auxiliary line SLb of the data signal line SL are electrically connected to each other through the transfer electrode TE.

[0131] In some embodiments, multiple pixel sub-electrodes spe overlap with the electrode plate CE2 in a direction perpendicular to the main surface of the substrate. For example, the positive projection of at least part of each pixel sub-electrode spe on the substrate may be within the positive projection range of the electrode plate CE2 on the substrate.

[0132] In some embodiments, a plurality of data signal main lines SLa may be arranged in an area outside the corresponding pixel region PR, for example, on one side or on two opposite sides of the pixel region PR in the direction D1; the data signal main line SLa may not be arranged at a position corresponding to the gap between adjacent pixel sub-electrodes in the pixel region PR; that is, the orthographic projections of the plurality of data signal main lines SLa on the substrate are offset from the gap between the orthographic projections of the plurality of pixel sub-electrodes spe located in the same pixel region on the substrate. Such an arrangement can avoid the signal crosstalk between adjacent pixel sub-electrodes caused by the data signal main lines when the pixel electrodes in the same pixel region include a large number (for example, greater than 3) of pixel sub-electrodes. On the other hand, the electrode plate CE2 can be configured to connect the Vcom signal and reuse a signal shielding layer. Since the plurality of pixel sub-electrodes spe overlap with the electrode plate CE2 (that is, the signal shielding layer), the signal shielding layer can also help shield the signal crosstalk between the signal lines in the underlying conductive layer 101 and the pixel sub-electrodes.

[0133] In some embodiments, the barrier electrode structure, including barrier electrodes be1 and be2 and the connecting electrode ae, can also be reused as a reflective electrode re, thereby improving the white state display of the display device. In some embodiments, the pixel electrode sp and the barrier electrode structure are formed by patterning the same electrode material, and the pixel electrode sp can also serve as a reflective electrode, further improving the white state display of the display device. In alternative embodiments, the pixel electrode sp and the barrier electrode structure can also be formed using different electrode materials using different patterning processes.

[0134] 10A and 10B are schematic plan layout diagrams of multiple pixel regions and barrier wall regions of the array substrate S1a. It should be understood that the number of pixel regions shown in FIG10A and 10B is merely for illustration and the present disclosure is not limited thereto.

[0135] 10A and 10B , in some embodiments, the display area (i.e., AA area) of the array substrate S1a includes a plurality of pixel regions PR arranged in an array and a barrier wall region BR surrounding each pixel region and located between adjacent pixel regions. For example, the plurality of pixel regions PR are arranged into a plurality of pixel rows along the direction D1 and into a plurality of pixel columns along the direction D2. In each pixel row arranged along the direction D1 and each pixel column arranged along the direction D2, each two adjacent pixel regions are spaced apart from each other, and a barrier wall region is sandwiched between the two. The specific structure of each pixel region PR and its surrounding barrier wall region BR is the same as that described above with reference to FIG. 5 to FIG. 9B , and will not be repeated here.

[0136] In some embodiments, multiple barrier electrodes be1 surround the pixel electrodes pe in multiple pixel regions PR; for example, the barrier electrodes be1 may be arranged in a one-to-one correspondence with the pixel regions PR. The multiple barrier electrodes be1 may also be arranged in an array along directions D1 and D2 to correspond to the multiple pixel regions PR. In some embodiments, multiple barrier electrodes be1 located in the same row in direction D1 (i.e., multiple barrier electrodes surrounding multiple pixel regions in the same pixel row) are electrically connected to each other via connecting electrodes ae. For example, each barrier electrode be1 may be provided with connecting electrodes ae on one or two opposite sides in direction D1, and a connecting electrode ae is provided between every two adjacent barrier electrodes be1 in direction D1, thereby electrically connecting the multiple barrier electrodes be1 in the same row via connecting electrodes ae. In some embodiments, the connecting electrodes ae on the side of one or more barrier electrodes located at the end, away from the pixel regions PR, in direction D1 may be configured to connect to a voltage signal (e.g., a Vcom signal). Here, a barrier electrode located at an end refers to a barrier electrode located near the edge of the display area, with no other pixel regions located on one side of the barrier electrode in direction D1.

[0137] In some embodiments, the barrier electrode be2 surrounds multiple barrier electrodes be1, is spaced apart from the barrier electrodes be1, and is located between adjacent barrier electrodes be1; that is, each barrier electrode be1 is surrounded by the barrier electrode be2. For example, the barrier electrode be2 may be in a grid configuration, defining multiple grid regions gr; each grid region gr includes a pixel region PR and a barrier electrode be1 surrounding the pixel region PR, and may also include a transfer electrode TE. In some embodiments, an edge portion of the barrier electrode be2 (e.g., a portion near the edge of the display area) may be configured to connect to a voltage signal that is different from the voltage signal connected to the barrier electrode be1. The portion of the barrier electrode be2 located between each adjacent barrier electrode be1 in direction D1 and / or the portion of the end barrier electrode be1 located away from the pixel region may be provided with an opening op, allowing the connection electrode ae to pass through the opening for electrical connection.

[0138] In direction D1, for two adjacent pixel regions PR, the barrier region between the two pixel regions PR is provided with two portions of a barrier electrode be1 (e.g., the vertically extending portion shown in the figure) and a portion of a barrier electrode be2 (e.g., the vertically extending portion shown in the figure) sandwiched between the two barrier electrodes be1. That is, the two barrier electrodes be1 are located on opposite sides of the barrier electrode be2. The two barrier electrodes be1 are electrically connected to each other and can receive the same voltage signal (e.g., a first voltage signal), while the barrier electrode be2 receives another voltage signal (e.g., a second voltage signal), where the first voltage signal is different from the second voltage signal. In this way, two electric fields in opposite directions (e.g., the leftward and rightward electric fields in the figure) can be generated between the barrier electrode be2 and the two barrier electrodes be1, respectively. These two opposing electric fields constitute an electron barrier, preventing crosstalk between charged particles between the two adjacent pixel regions. The relevant features and principles of the electron barrier in preventing particle crosstalk can be found in the above description of Figures 2A, 3C, and 3D, and will not be further elaborated here.

[0139] In direction D2, for two adjacent pixel regions PR, the barrier electrode structure may also generate two electric fields in opposite directions (e.g., upward and downward electric fields in the figure) between the two pixel regions PR, generated by the two barrier electrodes be1 and a portion of the barrier electrode be2. For example, corresponding to a first pixel region (e.g., the lower pixel region in Figures 10A and 10B ) and a second pixel region (e.g., the upper pixel region in Figures 10A and 10B ) adjacent to each other in direction D2, a first electric field is generated between a portion of the barrier electrode be1 surrounding the first pixel region (e.g., the horizontally extending portion along direction D1 in the figure) and an adjacent portion of the barrier electrode be2 (e.g., the horizontally extending portion along direction D1 in the figure), and a second electric field is generated between a portion of the barrier electrode be1 surrounding the second pixel region (e.g., the portion of the two vertically extending portions along direction D2 in the figure adjacent to the barrier electrode be2) and an adjacent portion of the barrier electrode be2 (i.e., the horizontally extending portion in the figure); the directions of the first and second electric fields are opposite. In some embodiments, the portion of the blocking wall electrode be1 extending along the direction D2 (i.e., the vertical extension portion) may have a relatively large size (e.g., width), for example, larger than the width of its horizontal extension portion, so that the second electric field formed as described above has sufficient strength, thereby being able to effectively block crosstalk of charged particles.

[0140] Referring to Figure 10A, in some embodiments, a plurality of transistors T connected to a plurality of pixel sub-electrodes in each pixel region may be arranged in rows along direction D1. In the entire display area, a plurality of transistors T of a plurality of pixel regions PR may be arrayed into multiple rows and columns along directions D1 and D2. A plurality of transistors T (for example, their sources S) located in the same row in direction D1 may each be connected to a different data signal line SL. A plurality of transistors T located in the same column in direction D2 may be connected to the same data signal line SL. For example, a plurality of data signal main lines SLa extend along direction D2 and are located in an area outside the pixel region PR, for example, on the opposite side of the pixel region PR in direction D1; each data signal main line SLa may be configured to connect a plurality of transistors T located in the same column. When the data signal line SL includes only a data signal main line SLa, the data signal main line SLa is directly connected to a plurality of transistors T (for example, their sources S) in the same column. When the data signal line SL includes a main data signal line SLa and auxiliary data signal lines SLb, the multiple transistors T connected to the data signal line SL are located in the same column and are respectively connected to the corresponding auxiliary data signal line SLb. They are also connected to the main data signal line SLa via the corresponding auxiliary data signal line SLb and the transfer electrode TE. That is, the data signal line SL may include one main data signal line SLa and multiple auxiliary data signal lines SLb. The main data signal line SLa extends along a direction D2 and may span multiple pixel regions PR to connect multiple transistors. The multiple auxiliary data signal lines SLb may be provided in a one-to-one correspondence with the multiple transistors T. In some embodiments, the auxiliary data signal line SLb and the transfer electrode TE are located between adjacent main data signal lines SLa in the direction D1 and between the corresponding pixel region PR and the barrier electrode be2 in the direction D2.

[0141] Figure 11 shows a schematic cross-sectional view of an array substrate S1b according to other embodiments of the present disclosure. Array substrate S1b is similar to the array substrates of the aforementioned embodiments, differing in the layout of its components. For simplicity, Figure 11 only shows one pixel sub-electrode and its corresponding transistor, capacitor, and barrier electrode structure; it should be understood that other pixel sub-electrodes and other components have similar cross-sectional structures.

[0142] 11 , array substrate S1b includes a base substrate 100, a conductive layer 101, an insulating layer 102, an active layer 103, a conductive layer 105, an insulating layer 106, an electrode layer 107, and may further include an electrode layer 207 and an organic layer 208. In some embodiments, electrode layer 107 and electrode layer 207 may be referred to as a first electrode layer and a second electrode layer, respectively.

[0143] For example, the electrode layer 207 may be located on the side of the insulating layer 106 away from the base substrate 100, and the organic layer 208 may be located on the insulating layer 106 and cover the sidewalls of the electrode layer 207 and its surface away from the insulating layer 106; the electrode layer 107 is located on the side of the organic layer 208 away from the base substrate 100. In other words, the electrode layer 207 is located on the side of the electrode layer 107 closer to the base substrate 100, and between the electrode layer 107 and the conductive layer 105 / insulating layer 106, with the organic layer 208 disposed between the electrode layer 207 and the electrode layer 107. In some embodiments, the organic layer 208 may be planarized; for example, the organic layer 208 may include an organic dielectric material such as spin-on glass (SOG), and may provide a flat surface for the electrode layer 107.

[0144] In some embodiments, the gate GE of transistor T and the first plate CE1 of capacitor C are disposed on the same layer, conductive layer 101; the source / drain S / D of transistor T and the second plate CE2 of capacitor C are disposed on the same layer, conductive layer 105. One of the source / drain S / D (e.g., drain D) may be connected to the second plate CE2, i.e., they may share the same electrode plate. In some embodiments, a barrier electrode structure is disposed on the side of the multiple pixel electrodes closest to the substrate; for example, the barrier electrode structure be is disposed on electrode layer 207 and may be reused as the reflective electrode re. The pixel electrode pe is disposed on electrode layer 107.

[0145] In some embodiments, the pixel sub-electrode spe extends through the organic layer 208, the electrode layer 207, and the insulating layer 106 to electrically connect to one of the source / drain electrodes S / D of the transistor T (e.g., the drain electrode D) and the second electrode plate CE2 of the capacitor C. For example, the organic layer 208 and the insulating layer 106 have a via v1, and the electrode layer 207 has an opening 207o. The via v1 extends from the surface of the organic layer away from the base substrate into the insulating layer 106 and passes through the opening 207o. A portion of the via v1 is located in the opening 207o, has a smaller size than the opening 207o, and is spaced apart from the electrode layer 207. The via v1 exposes a portion of the surface of the conductive layer 105, so that the pixel sub-electrode spe is electrically connected to the drain electrode D (or source electrode S) located in the conductive layer 105 and the second substrate CE2 through the via v1.

[0146] In some embodiments, a portion of the barrier electrode structure be extends through the insulating layer 106, the conductive layer 105, and the insulating layer 102 to electrically connect to the electrode plate CE1 located in the conductive layer 101. For example, the insulating layers 106 and 102 include a via v3, and the conductive layer 105 includes an opening 105o. The opening 105o may be located in the second electrode plate CE2 or at an edge of the second electrode plate CE2. The via v3 passes through the opening 105o. That is, the via v3 is partially located in the opening 105o, has a smaller size than the opening 105o, and is spaced apart from the conductive layer 105. The portion of the barrier electrode structure be (for example, the barrier electrode be1 shown in FIG. 16A ) is electrically connected to the first plate CE1 of the corresponding capacitor C located in the conductive layer 101 through the via v3. In some embodiments, the portion of the barrier electrode structure be and the first plate CE1 of the capacitor C may be configured to receive a Vcom signal.

[0147] In some embodiments, at least a portion of the barrier electrode be may overlap with the second electrode plate CE2 in a direction perpendicular to the main surface of the base substrate 100 and may be reused as the third electrode plate CE3 of the capacitor C. That is, the capacitor C may include a first electrode plate CE1, a second electrode plate CE2, and a third electrode plate CE3. The first electrode plate CE1 and the third electrode plate CE3 are located on opposite sides of the second electrode plate CE2 in a direction perpendicular to the main surface of the base substrate and are electrically connected to each other. The capacitor C includes double-layer capacitors formed between the first electrode plate CE1 and the second electrode plate CE2, and between the second electrode plate CE2 and the third electrode plate CE3. This increases the capacitance area and improves the capacitance of the capacitor. In some embodiments, the first electrode plate CE1 and the third electrode plate CE3 are configured to receive a Vcom signal, but the present disclosure is not limited to this.

[0148] In this example, the pixel electrode pe and the barrier electrode structure be are disposed on different layers, and the barrier electrode structure be is reused as the reflective electrode re. In a direction perpendicular to the main surface of the base substrate, the pixel electrode pe may overlap with the barrier electrode structure be / reflective electrode re, and the orthographic projection of the reflective electrode re on the base substrate 100 may substantially cover the entire pixel area.

[0149] Figures 12 to 17B illustrate schematic planar layouts of various layers and / or multiple layers in a pixel region and its surrounding retaining wall region in an array substrate S1b according to some embodiments of the present disclosure. In this example, the pixel electrode of each pixel region includes three pixel sub-electrodes, and the corresponding array substrate is provided with three transistors, three capacitors, and three data signal lines correspondingly connected to the three pixel sub-electrodes.

[0150] FIG12 shows a planar layout diagram of the conductive layer 101. Referring to FIG12 , the conductive layer 101 includes a plurality of gates GE, a plurality of electrode plates CE1, a gate signal line GL, and an electrode signal line EL. The plurality of gates GE correspond to a plurality of transistors T, respectively, and the plurality of electrode plates CE1 correspond to a plurality of capacitors C, respectively. The gate signal line GL is connected to the plurality of gates GE so as to be configured to apply a scan signal to the gates GE. For example, the gate signal line GL extends along a direction D1 and connects a plurality of gates GE located in the same row in the direction D1. For example, a plurality of portions of the gate signal line GL can be respectively used as a plurality of gates GE of a plurality of transistors T. The plurality of electrode plates CE1 can be arranged along the direction D1 and spaced apart from each other, and the electrode signal line EL connects the plurality of electrode plates CE1 so as to be configured to apply a voltage signal, such as a Vcom signal, to the electrode plates CE1. In an alternative embodiment, the plurality of electrode plates CE1 may also share the same electrode plate, and the electrode plate may be, for example, in a block shape.

[0151] FIG13 shows a schematic planar layout diagram of a stack of conductive layer 101 and active layer 103. Active layer 103 includes multiple active areas AL, each corresponding to a plurality of transistors T. The multiple active areas AL are arranged corresponding to the multiple gates GE; for example, the multiple active layers AL overlap the multiple gates GE in a direction perpendicular to the main surface of the substrate.

[0152] FIG. 14 shows a schematic planar layout diagram of a stack of conductive layer 101 , active layer 103 , and conductive layer 105 .

[0153] 14 , the conductive layer 105 includes source electrodes S and drain electrodes D of multiple transistors T, electrode plates CE2 of multiple capacitors C, and data signal lines SL electrically connected to each of the multiple transistors T. In each transistor T, the source electrode S and drain electrode D each cover a portion of the active area AL. Another portion of the active area AL is located between the source electrode S and drain electrode D and includes the transistor's channel region. One of the source and drain electrodes S / D (e.g., the source electrode S) is electrically connected to the data signal line SL. The other of the source and drain electrodes S / D (e.g., the drain electrode D) may share the same electrode plate with the second electrode plate CE2 of the corresponding capacitor C. This electrode plate at least partially overlaps the first electrode plate CE1 in a direction perpendicular to the main surface of the substrate and extends from directly above the first electrode plate CE1 to cover the active layer AL of the corresponding transistor T.

[0154] In some embodiments, the electrode plate CE2 has a notch c1, which is located directly above the first electrode plate CE1, that is, overlapping with the first substrate CE1 in a direction perpendicular to the main surface of the base substrate. The notch c1 corresponds to the opening 105o of the conductive layer 105 in Figure 11; that is, the opening 105o may be or include the notch c1. In some examples, as shown in Figure 14, the notch c1 is located at the edge of the electrode plate CE2, but the present disclosure is not limited to this. In another example, the notch c1 may also be located in the electrode plate CE2 or any other suitable position of the conductive layer 105, as long as the via formed subsequently can pass through the notch to expose the first electrode plate CE1.

[0155] In some embodiments, a plurality of data signal lines SL extend substantially in parallel along a direction D2 and are arranged along a direction D1, and are respectively electrically connected to the source electrodes S of a plurality of transistors T. The plurality of data signal lines SL may be respectively located at positions adjacent to the sides of the corresponding transistors T. In some embodiments, when the number of transistors corresponding to the same pixel region (equal to the number of pixel sub-electrodes) is relatively small (e.g., less than or equal to 3), some of the data signal lines SL may be disposed in the pixel region (e.g., in a region corresponding to a gap between adjacent pixel sub-electrodes in the pixel region).

[0156] FIG15 shows a schematic planar layout diagram of a stack of conductive layer 101 , active layer 103 , conductive layer 105 , and vias in insulating layers.

[0157] Referring to Figure 15 , in some embodiments, the insulating layer includes a plurality of vias v1 and a plurality of vias v3. The plurality of vias v1 expose portions of the surface of the conductive layer 105 (e.g., the plurality of drain electrodes D / second electrode plates CE2), and the plurality of vias v3 expose portions of the surface of the plurality of first electrode plates CE1 in the conductive layer 101. The vias v3 can be disposed, for example, at locations corresponding to the notches in the electrode plates CE2.

[0158] 16A shows a schematic layout diagram of a stack of conductive layer 101 , active layer 103 , conductive layer 105 , vias in the insulating layer, and electrode layer 207 ; FIG. 16B shows a schematic layout diagram of electrode layer 207 .

[0159] Referring to Figures 16A and 16B , electrode layer 207 includes a barrier electrode structure and a reflective electrode. The barrier electrode structure includes barrier electrode be1 and barrier electrode be2. Electrode layer 207 is, for example, a reflective electrode layer, meaning the barrier electrode structure can be reused as a reflective electrode. In some embodiments, barrier electrode be1 can overlap with electrode plates CE2 and CE1 in a direction perpendicular to the main surface of the substrate. Barrier electrode be1 is electrically connected to multiple electrode plates CE1 via multiple vias v3 and can be reused as electrode plate CE3 for multiple capacitors C. In some embodiments, the blocking wall electrode be1 is roughly block-shaped or planar, and has multiple openings 207o, and the multiple openings 207o overlap with the multiple drain electrodes D / second electrode plates CE2 respectively; the multiple openings 207o can be arranged one-to-one with the multiple vias v1, each via v1 is located in the opening 207o, and has a size smaller than the opening 207o, so that the via v1 is separated from the blocking wall electrode be1, and exposes part of the surface of the multiple electrode plates CE2 respectively.

[0160] In some embodiments, the barrier electrode be2 surrounds the barrier electrode be1 in a direction parallel to the main surface of the substrate. The barrier electrode be2 may be ring-shaped, such as a closed ring, but the present disclosure is not limited thereto.

[0161] 17A shows a schematic layout diagram of the stack of conductive layer 101 , active layer 103 , conductive layer 105 , vias in the insulating layer, electrode layer 207 , and electrode layer 107 ; FIG. 17B shows a schematic layout diagram of the stack of electrode layer 207 and electrode layer 107 .

[0162] 17A and 17B , the electrode layer 107 includes a pixel electrode pe, and the pixel electrode pe of each pixel region PR includes a plurality of pixel sub-electrodes spe, each of which is electrically connected to the drain D of the transistor T located in the conductive layer 105 and the second plate CE2 of the capacitor C through a corresponding via v1.

[0163] In some embodiments, the plurality of pixel sub-electrodes spe overlap with the barrier electrode be1 in a direction perpendicular to the main surface of the substrate. For example, the orthographic projections of the plurality of pixel sub-electrodes spe on the substrate may be within the orthographic projection of the barrier electrode be1 on the substrate, and the orthographic projections of the plurality of pixel sub-electrodes spe on the substrate overlap with the orthographic projections of the opening 207o of the barrier electrode be1 on the substrate. For example, the orthographic projections of the barrier electrode be1 on the substrate may cover the orthographic projections of the corresponding pixel region PR / pixel electrode pe on the substrate, and the orthographic projections of the barrier electrode be1 further extend beyond the edges of the orthographic projections of the pixel region PR / pixel electrode pe to surround the pixel region PR. In other words, at least a portion of the barrier electrode be1 is located outside the pixel region PR and surrounds the pixel region PR in a direction parallel to the main surface of the substrate.

[0164] For example, each barrier electrode be1 includes a first electrode portion P1, a second electrode portion P2, and a third electrode portion P3; the first electrode portion P1 and the second electrode portion P2 are located within the pixel region PR, while the third electrode portion P3 is located outside the pixel region PR. The orthographic projection of the first electrode portion P1 on the substrate overlaps with the orthographic projection of the pixel sub-electrode SPE on the substrate, for example, having overlapping contours. The second electrode portion P2 is located between adjacent first electrode portions P1 and overlaps with the gap between adjacent pixel sub-electrodes SPE in a direction perpendicular to the main surface of the substrate; that is, the orthographic projection of the second electrode portion P2 on the substrate overlaps with the orthographic projection of the gap between adjacent pixel sub-electrodes located in the same pixel region on the substrate. The third electrode portion P1 surrounds the first electrode portion P1 and the second electrode portion P2, and the orthographic projection of the third electrode portion P1 on the substrate surrounds the orthographic projection of the pixel region PR on the substrate, for example, surrounds all sides of the orthographic projection of the pixel region PR. For example, the pixel region PR has a rectangular planar shape, and all four sides of the pixel region PR are surrounded by the third electrode portion P1. In some embodiments, the opening 207 o may be at least partially located in the corresponding first electrode portion P1 .

[0165] Figure 18A shows a schematic planar layout diagram of a plurality of pixel regions PR and a stack of multiple layers in a barrier wall region BR corresponding to the plurality of pixel regions PR according to some embodiments of the present disclosure. Figure 18B shows a schematic planar layout diagram of a plurality of pixel regions PR and a stack of electrode layers 107 and 207 in a barrier wall region BR corresponding to the plurality of pixel regions PR according to some embodiments of the present disclosure.

[0166] Referring to FIG. 18A , in some embodiments, similar to the aforementioned embodiments, an array substrate S1b includes a plurality of pixel regions PR arranged in an array; for example, the plurality of pixel regions PR are arranged in an array including multiple rows and multiple columns along directions D1 and D2. The layout of each pixel region PR and its surrounding barrier wall region BR is the same as described above with reference to FIG. 12 to FIG. 17B , and will not be further described here.

[0167] In some embodiments, in the conductive layer 101, a plurality of electrode plates CE1 are arranged in directions D1 and D2 into an array including multiple rows and columns, and a plurality of electrode lines EL extend in direction D1 substantially parallel to each other and are arranged in direction D2. For example, each electrode line EL may connect a plurality of electrode plates CE1 located in the same row. In the conductive layer 105, the sources S of a plurality of transistors T may be arranged in directions D1 and D2 into an array including multiple rows and multiple columns; the drains D (electrode plates CE2) of the plurality of transistors T may also be arranged in directions D1 and D2 into an array including multiple rows and multiple columns. A plurality of data signal lines SL may extend in direction D2 substantially parallel to each other and be arranged in direction D1. For example, each data signal line SL may connect the sources S of a plurality of transistors T located in the same column in direction D2.

[0168] Referring to Figures 18A and 18B, in some embodiments, the orthographic projection of the electrode layer 107 on the base substrate overlaps with the orthographic projection of the electrode layer 207 on the base substrate, and the orthographic projection of the electrode layer 207 also covers the orthographic projection on the base substrate of the gap region between the multiple pixel sub-electrodes spe in each pixel region PR. For example, in the electrode layer 207, multiple barrier electrodes be1 are arranged in an array along directions D1 and D2 and are respectively provided corresponding to the multiple pixel regions PR. The barrier electrode be2 surrounds the multiple barrier electrodes be1 and is located between adjacent barrier electrodes be1. The orthographic projections of the multiple barrier electrodes be1 on the base substrate overlap with the orthographic projections of the multiple pixel electrodes pe on the base substrate, and the multiple barrier electrodes be1 may each have multiple openings 207o, each of which corresponds to the multiple pixel sub-electrodes spe of the corresponding pixel electrode pe. Since the barrier electrode structure can also serve as a reflective electrode, in this example, the orthographic projection of the barrier electrode structure (i.e., the reflective electrode) covering the pixel area can increase the coverage area of ​​the reflective electrode, thereby further increasing the white state reflectivity and contrast of the display device, thereby improving the display quality of the display device.

[0169] The multiple barrier electrodes be1 are each connected to the electrode plate CE1 located on the conductive layer 101 through vias v3. Because the multiple electrode plates CE1 located in the same row are electrically connected via the electrode signal line EL, the multiple barrier electrodes be1 located in the same row and electrically connected to the electrode plates CE1 are also electrically connected to each other via the electrode plates and the electrode signal lines. In this example, a voltage signal, such as a Vcom signal, can be applied to the multiple electrode plates CE1 located in the same row and the multiple barrier electrodes be1 located in the same row and electrically connected to the multiple electrode plates CE1 via the same electrode signal line EL.

[0170] Referring to Figures 18A and 18B , each barrier electrode be1 is surrounded by a barrier electrode be2. For example, the barrier electrode be2 may be in a grid configuration, defining a plurality of grid regions gr, within which the barrier electrodes be1 and the pixel regions PR are located. For example, each grid region gr includes a pixel region PR and a barrier electrode be1. In this embodiment, since the barrier electrodes be1 in the same row are electrically connected via the electrode signal lines EL of the conductive layer 101, and voltage signals can be applied to the barrier electrodes be1 via the electrode signal lines EL, connection electrodes for connecting to the barrier electrodes be1 and / or for applying voltage signals to the barrier electrodes be1 may not be provided in the electrode layer 207, and accordingly, the barrier electrodes be2 may not be provided with openings through which the connection electrodes pass.

[0171] For example, the barrier electrode be2 can be a continuous grid-like electrode including multiple annular portions, each of which can be in a closed ring shape, surrounding each side of the barrier electrode be1. The multiple barrier electrodes be1 can be configured to receive a first voltage signal (e.g., a Vcom signal), while the barrier electrode be2 can be configured to receive a second voltage signal different from the first voltage signal, which can be greater than or less than the first voltage. In this way, between every two adjacent pixel regions PR in direction D1, there is a portion of the barrier electrode be2 (e.g., a portion extending along direction D2) and two barrier electrodes be1 located on opposite sides of the portion of the barrier electrode be2 in direction D1; the portion of the barrier electrode be2 and the corresponding portions of the two barrier electrodes be1 generate two electric fields in opposite directions (e.g., two electric fields to the left and right along direction D1 in the figure). Moreover, between every two adjacent pixel regions PR in direction D2, there is also provided a portion of the barrier electrode be2 (for example, a portion extending along direction D1) and two barrier electrodes be1 located on opposite sides of the portion of the barrier electrode be2 in direction D2; the portion of the barrier electrode be2 and the corresponding portions of the two barrier electrodes be1 generate two electric fields in opposite directions (for example, two electric fields upward and downward along direction D2 in the figure). The specific steps for generating the electron barrier are similar to those described above with reference to Figures 3C and 3D and will not be repeated here. Therefore, the electron barrier formed by the barrier electrode structure including multiple barrier electrodes be1 and barrier electrodes be2 can effectively prevent crosstalk between charged particles in any two adjacent pixel regions.

[0172] 19 shows a schematic cross-sectional view of an array substrate S1c according to some other embodiments of the present disclosure. The components of the array substrate S1c are similar to those of the aforementioned embodiments, except that the layout and / or connection relationship of the components are slightly different.

[0173] Referring to Figure 19, the array substrate S1c includes a base substrate 100, a conductive layer 101, an insulating layer 102, an active layer 103, a conductive layer 105, an insulating layer 106, an electrode layer 107, and a passivation layer 108. The gates GE of the plurality of transistors T and the first plates CE1 of the plurality of capacitors C may be located on the conductive layer 101. The source / drain electrodes S / D of the plurality of transistors T and the second plates CE2 of the plurality of capacitors C may be located on the conductive layer 105. One of the source / drain electrodes S / D of each transistor T (e.g., the drain electrode D) may be connected to the second plate CE2 of the corresponding capacitor C, or may share the same electrode plate. The pixel electrode pe, the barrier electrode be, and the reflective electrode re are located on the electrode layer 107, and the barrier electrode be and the reflective electrode re may share the same electrode. A via v1 may be provided in the insulating layer 106, and the pixel sub-electrode spe is connected to the drain electrode D and the second plate CE2 located in the conductive layer 105 through the via v1.

[0174] 20 to 24B illustrate schematic planar layouts of various layers and / or stacked layers of a pixel region and its surrounding barrier wall region of an array substrate S1 c according to some embodiments of the present disclosure.

[0175] Figure 20 shows a planar layout of the conductive layer 101 in the array substrate S1c. The conductive layer 101 includes multiple gate electrodes GE, multiple electrode plates CE1, multiple gate signal lines GL, and electrode signal lines EL. The multiple gate electrodes GE correspond to multiple transistors, and the multiple electrode plates CE1 correspond to multiple capacitors. In this example, each pixel region may include three pixel sub-electrodes, and the array substrate is provided with three transistors and three capacitors electrically connected to the three pixel sub-electrodes, respectively.

[0176] In this embodiment, the plurality of transistors corresponding to the same pixel area may not be completely arranged in a row; for example, some of the plurality of transistors may be arranged in a row (for example, the first row) along direction D1, while another portion of the transistors may be arranged in another row (for example, the second row), and the transistors in the second row are not aligned with the transistors in the first row in direction D2. For example, at least a portion of the orthographic projection of the transistors in the second row on the reference plane along direction D1 may be located between the orthographic projections of the transistors in the first row on the reference plane. A plurality of capacitors may be located between the transistors in the first row and the transistors in the second row in direction D2, the plurality of capacitors may be arranged in a row along direction D1, and some of the plurality of capacitors may have approximately the same size, while another portion of the capacitors may have different sizes. It should be understood that the positional relationship described herein with respect to the plurality of transistors and the plurality of capacitors is approximately equivalent to the positional relationship between the corresponding components of the plurality of transistors and the plurality of capacitors in each conductor layer / active layer.

[0177] For example, the multiple transistors and multiple capacitors arranged corresponding to each pixel area include transistors T1, T2, T3 and capacitors C1, C2, C3. For example, transistors T1 and T2 may be arranged in the same row along direction D1, and transistor T3 may be located on one side of transistors T1 and T2 in direction D2 and arranged in another row, and transistor T3 may not be aligned with transistors T1 or T2 in direction D2, but may be offset from transistors T1 and T2 in direction D1. For example, at least a portion of transistor T3 may be aligned with the gap between transistors T1 and T2 in direction D2. Transistor T3 may partially overlap with transistors T1 and / or T2 in direction D2, or may not overlap. In other words, at least a portion of the orthographic projection of transistor T3 on the reference plane along direction D1 is located between the orthographic projections of transistors T1 and T2 on the reference plane, and may partially overlap with the orthographic projections of transistors T1 and / or T2, or may not overlap.

[0178] Capacitors C1, C3, and C2 may be arranged sequentially along direction D1 and may be arranged in direction D2 between the transistor row where transistors T1 and T2 are located and the transistor row where transistor T3 is located. For example, capacitors C1 and C2 may at least partially overlap with transistors T1 and T2, respectively, in direction D2, capacitor C3 may overlap with transistor T3 in direction D2, and at least a portion of capacitor C3 may overlap with the gap between transistors T1 and T2 in direction D2, and may partially overlap with transistors T1 and / or T2, or may not overlap. In some embodiments, capacitors C1 and C2 may have substantially the same shape and / or size, and the shape and / or size of capacitors C1 and C2 may differ from the shape and / or size of capacitor C3.

[0179] In the conductive layer 101 , the arrangement of the gates GE of the transistors T1 - T3 and the electrode plates CE1 of the capacitors C is substantially the same as that described above for the transistors and capacitors, and will not be repeated herein.

[0180] In some embodiments, the gates GE of multiple transistors in the same row are connected to the same gate signal line GL. For example, the gates GE of transistors T1 and T2 are connected to the same gate signal line GL, while the gate GE of transistor G3 is connected to another gate signal line GL. The multiple gate signal lines GL may extend substantially parallel to one another along a direction D1 and be arranged along a direction D2.

[0181] The electrode plates of multiple capacitors in the same row can be connected to the same electrode signal line. For example, the electrode plates CE1 of capacitors C1, C2, and C3 can be connected to the same electrode signal line EL. The electrode signal line EL can extend along direction D1 and can be arranged between two adjacent gate signal lines GL in direction D2.

[0182] FIG21 shows a schematic layout diagram of a stack of conductive layer 101 and active layer 103. Active layer 103 includes multiple active areas AL, each corresponding to a plurality of transistors. Each active area AL is disposed in correspondence with a corresponding gate electrode GE and overlaps in a direction perpendicular to the main surface of the substrate. For example, the orthographic projection of the active area AL on the substrate can be within the orthographic projection of the corresponding gate electrode GE on the substrate.

[0183] Fig. 22A shows a schematic planar layout diagram of a stack of conductive layer 101, active layer 103, and conductive layer 105. Fig. 22B shows a schematic planar layout diagram of conductive layer 105.

[0184] Referring to Figures 22A and 22B , the conductive layer 105 includes multiple transistor source / drain electrodes S / D, multiple capacitor electrode plates CE2, and multiple data signal lines SL1, SL2, and SL3. One of the source / drain electrodes S / D of each transistor (e.g., the drain electrode D) can be electrically connected to the second electrode plate CE2 of the corresponding capacitor. In other words, each drain electrode D can share the same electrode plate with the corresponding second electrode plate CE2, with a portion of the electrode plate serving as the second electrode plate CE2 of the capacitor and another portion serving as the drain of the transistor. The other of the source / drain electrodes S / D (e.g., the source electrode S) is electrically connected to the corresponding data signal line. For example, the source electrodes S of transistors T1, T2, and T3 are connected to data signal lines SL1, SL2, and SL3, respectively. The source electrode S and drain electrode D each cover a portion of the active area AL and are disposed opposite each other. For example, the source electrode S can have a U-shaped groove, and at least a portion of the drain electrode D can be located within the U-shaped groove and surrounded by the source electrode S in a direction parallel to the main surface of the substrate, but the present disclosure is not limited to this. Each electrode plate CE2 is positioned opposite to the corresponding electrode plate CE1, i.e., overlapping in a direction perpendicular to the main surface of the substrate. The arrangement of the source / drain electrodes S / D of the multiple transistors and the electrode plates CE2 of the multiple capacitors is substantially the same as the arrangement of the multiple transistors and capacitors described above.

[0185] In some embodiments, the opening direction of the U-shaped groove of the source S of the transistors in the same row is the same, while the opening direction of the U-shaped groove of the source S of the transistors in adjacent rows is different. For example, as shown in Figures 22A and 22B, the opening direction of the U-shaped groove of the source S of transistors T1 and T2 is both upward, while the opening direction of the U-shaped groove of the source S of transistor T3 is downward. It should be understood that the types of transistors shown in each embodiment are for illustration only, and the present disclosure is not limited thereto. Any suitable type of transistor (for example, U-type, T-type or other type) can be selected based on product needs.

[0186] In some embodiments, for the same pixel region, the data signal lines SL1 and SL2 connected to the two transistors T1 and T2 located at the ends of the multiple transistors T1-T3 may extend substantially parallel to each other along a direction D2, and the data signal lines SL1 and SL2 may be substantially in the form of strips extending in a single direction, i.e., in a straight line; whereas the data signal line SL3 connected to the transistor T3 located in the middle may include portions extending in multiple directions, i.e., in a zigzag line. Here, the two transistors located at the ends refer to the transistors (e.g., transistors T1 and T2) located at both ends (and, for example, near the edge of the pixel region) in the row direction (e.g., direction D1) of the multiple transistors arranged corresponding to the same pixel region, and the transistor located in the middle refers to the other transistors (e.g., transistor T3) located between the end transistors (and, for example, relatively far from the edge of the pixel region in direction D1) of the multiple transistors arranged corresponding to the same pixel region. It should be understood that the transistor T3 described here as being located between the end transistors T1 and T2 does not mean that the transistor T3 is exactly in the middle of the transistors T1 and T2, but rather that the orthographic projection of the transistor T3 on the reference plane along the direction D1 is between the orthographic projections of the transistors T1 and T2 on the reference plane.

[0187] For example, the data signal line SL3 may include a first main portion L1, a second main portion L2, and a transition portion L3. The first main portion L1 and the second main portion L2 may extend along a direction D2 and be offset from each other in the direction D1. The transition portion L3 is located between the first main portion L1 and the second main portion L2, so that the first main portion L1 and the second main portion L2 can be electrically connected to each other through the transition portion L3. For example, the transition portion L3 may extend along another direction (e.g., direction D1) that intersects with the direction D2. For example, the first main portion L1 may be located between capacitors C1 and C3 and between capacitor C1 and transistor T3 in the direction D1; the second main portion L2 may be located between transistors T1 and T2 in the direction D1; and the transition portion L3 may be located between capacitor C3 and transistor T1 in the direction D2. However, the present disclosure is not limited to this. In an alternative embodiment, the data signal line SL3 may also be set at a position symmetrical to the position shown in Figure 22A; for example, the first main portion L1 may be located between capacitors C2 and C3, and between capacitor C2 and transistor T3 in the direction D1; the second main portion L2 may be located between transistors T1 and T2 in the direction D1; and the transfer portion L3 may be located between capacitor C3 and transistor T2 in the direction D2.

[0188] In some embodiments, the gates GE, source / drain electrodes S / D, active layers AL of transistors T1-T3, electrode plates CE1-CE2 of capacitors C1-C3, and data signal line SL2 connected to transistor T2 in the middle position can all be arranged in direction D1 between the data signal lines SL1 and SL2 connected to the end transistors. This arrangement can help reduce the area of ​​the pixel driving circuits corresponding to the pixel regions and minimize the spacing between adjacent pixel regions, thereby increasing pixel density and, in turn, display resolution.

[0189] In some embodiments, the drain electrode D of transistor T1 and the second electrode plate CE2 of capacitor C1 share the same electrode plate (e.g., a first electrode plate); the drain electrode D of transistor T2 and the second electrode plate CE2 of capacitor C2 share the same electrode plate (e.g., a second electrode plate). For example, the first electrode plate and the second electrode plate may be arranged symmetrically with respect to each other, for example, symmetrically along a center line CL. The center line CL may extend, for example, along a direction D2 and pass through the center of the electrode plates CE1 or CE2 of capacitor C1, or through the center of the gate electrode GE or active layer AL of transistor T3. For example, the gate electrode GE, active layer AL, and / or source / drain electrodes S / D of transistor T3, and the electrode plates CE1 and / or CE2 of capacitor C3 may each be arranged symmetrically with respect to the center line CL. For example, corresponding components of each layer of transistors T1 and T2 may be arranged symmetrically with respect to the center line CL; and corresponding components of each layer of capacitors C1 and C2 may be arranged symmetrically with respect to the center line CL. In some embodiments, this arrangement of transistors and capacitors can help minimize the spacing between adjacent pixel regions, thereby increasing pixel density and, in turn, display resolution.

[0190] FIG23 shows a schematic layout diagram of a stack of conductive layer 101 , active layer 103 , conductive layer 105 , and vias in an insulating layer.

[0191] Referring to Figure 23 , the insulating layer is provided with multiple vias v1. Each of the vias v1 can expose a portion of the surface of an electrode plate shared by multiple electrode plates CE2 and the drain electrode D. For example, the vias v1 can expose a portion of the surface of the electrode plate CE2 and be used to electrically connect the overlying pixel sub-electrodes to the electrode plate CE2 and the drain electrode D.

[0192] 24A shows a schematic plan layout diagram of a stack of conductive layer 101 , active layer 103 , conductive layer 105 , vias in the insulating layer, and electrode layer 107 ; FIG. 24B shows a schematic plan layout diagram of electrode layer 107 .

[0193] Referring to Figures 24A and 24B, in some embodiments, the pixel electrode pe, the barrier electrode structure, and the reflective electrode structure may be disposed in the same layer on the electrode layer 107. In each pixel region PR, the pixel electrode pe may include multiple (e.g., 3 or fewer) pixel sub-electrodes spe; the multiple pixel sub-electrodes spe may extend substantially parallel to one another along direction D2 and be arranged along direction D1. For example, the multiple pixel sub-electrodes spe may be strip-shaped electrodes. The barrier electrode structure may include a barrier electrode be1, a barrier electrode be2, and a connecting electrode ae. The barrier electrode be1 may be disposed in a one-to-one correspondence with each pixel region PR and located between the corresponding pixel region PR and the barrier electrode be2. For example, each barrier electrode be1 surrounds the pixel electrode pe in the pixel region PR in a direction parallel to the main surface of the substrate; the barrier electrode be1 may be annular, such as a closed ring, and the multiple pixel sub-electrodes spe may be located in an area enclosed by the inner sidewalls of the corresponding barrier electrode be1 (i.e., the sidewalls away from the barrier electrode be2). The barrier electrode be2 is located on a side of the barrier electrode be1 away from its corresponding pixel region PR and surrounds the barrier electrode be1 in a direction parallel to the main surface of the substrate. For example, each barrier electrode be1 is surrounded by the barrier electrode be2.

[0194] In some embodiments, the portion of the barrier electrode be2 corresponding to each barrier electrode be1 may be ring-shaped. For example, the barrier electrode be2 defines a grid region gr, and each grid region gr may be provided with a pixel region and a barrier electrode be1 surrounding the pixel region.

[0195] In some embodiments, the portion of the barrier electrode be2 corresponding to each barrier electrode be1 may be open ring-shaped; for example, the barrier electrode be2 may have multiple openings op, and the connecting electrode ae may be located on one or both sides of the barrier electrode be1 in direction D1. The connecting electrode ae passes through the openings op of the barrier electrode be2 to connect to the barrier electrodes be1 located in the same row in direction D1 or to connect to a voltage signal (e.g., a Vcom signal). The features related to the barrier electrode be2 and the connecting electrode ae are similar to those described above with reference to Figures 9A and 9B and are not further described here.

[0196] FIG25A shows a schematic layout diagram of various layers and / or stacks in a plurality of pixel regions PR and a barrier wall region BR corresponding to the plurality of pixel regions PR in an array substrate S1c according to some embodiments of the present disclosure. FIG25B shows a schematic layout diagram of an electrode layer 107 in a plurality of pixel regions PR and a barrier wall region BR corresponding to the plurality of pixel regions PR in an array substrate S1c according to some embodiments of the present disclosure. The layout of each pixel region PR and the layers in its corresponding barrier wall region are the same or similar to those described above with reference to FIG20 to FIG24B .

[0197] Referring to FIG. 25A , in some embodiments, the display area of ​​the array substrate S1c includes a plurality of pixel regions. The plurality of pixel regions may be arranged, for example, along directions D1 and D2 into an array comprising multiple rows and columns. For example, the plurality of pixel regions may include a plurality of pixel regions PR1 and a plurality of pixel regions PR2. The plurality of pixel regions PR1 are arranged in a row along direction D1, such as a first pixel row; the plurality of pixel regions PR2 are arranged in a row along direction D1, such as a second pixel row; and the plurality of pixel regions PR1 and PR2 may be arranged in a column along direction D2. In some embodiments, the first pixel row and the second pixel row are alternately arranged in direction D2.

[0198] The layout of each pixel region PR2 and the surrounding retaining wall region among the plurality of pixel regions PR1 and PR2 is the same as described above with reference to Figures 20 to 24B , and the layout of each pixel region PR1 and the surrounding retaining wall region is substantially the same as the layout of pixel region PR2, except that the orientation of the components in pixel region PR1 is different, for example, inverted relative to the components in pixel region PR2 in direction D2. The relative positional relationship of the components in pixel region PR1 is substantially the same as that described for pixel region PR2.

[0199] In some embodiments, the overall structure of pixel regions PR1 and PR2 located in the same column in direction D2 and located in adjacent first and second pixel rows is inverted relative to each other in direction D2. For example, the pixel regions PR1 and PR2 may be symmetrically arranged relative to each other, such as with respect to the barrier electrode be2 located therebetween. Inverting the adjacent first and second pixel rows can facilitate the arrangement of data signal lines, minimize the spacing between adjacent pixel regions, increase pixel density, and thereby improve display resolution.

[0200] For example, each pixel region includes transistors T1, T2, and T3. Multiple transistors T1 and T2 corresponding to the same row of pixel regions are arranged in a row along direction D1, for example, arranged into a first transistor row TS1, and transistors T1 and T2 are arranged alternately in the first transistor row; multiple transistors T3 corresponding to the same row of pixel regions are arranged in a row along direction D1, for example, arranged into a second transistor row TS2. Multiple transistors in multiple first transistor rows are aligned in direction D2 and arranged in columns; for example, multiple transistors T1 are arranged in columns (for example, first transistor columns) in direction D2, and multiple transistors T2 are arranged in columns (for example, second transistor columns) in direction D2. Multiple transistors T3 in multiple second transistor rows are aligned in direction D2 and arranged in columns, for example, third transistor columns. The third transistor column is arranged between adjacent first and second transistor columns in direction D1. It should be understood that the number of pixel regions shown in the figure is for illustration only and the present disclosure is not limited thereto. For example, more pixel areas may be provided in each pixel row and each pixel column; for example, a second pixel row PR2 may be provided above the first pixel row PR1 in the figure, and a first pixel row PR1 may be provided below the second pixel row PR2 in the figure.

[0201] In pixel regions PR1 and PR2 located in the same pixel column and adjacent pixel rows, multiple transistors T1-T3 in pixel region PR1 and multiple transistors T1-T3 in pixel region PR2 are symmetrically arranged. For example, a first distance exists between transistor T1 in pixel region PR1 and transistor T1 in pixel region PR2; a second distance exists between transistor T2 in pixel region PR1 and transistor T2 in pixel region PR2; and a third distance exists between transistor T3 in pixel region PR1 and transistor T3 in pixel region PR2. The first distance and the second distance are substantially the same, and the third distance is different from the first distance and the second distance. The first distance, the second distance, and the third distance are all distances in direction D2.

[0202] In some embodiments, in adjacent first and second pixel rows, transistor rows of the same type (e.g., the first transistor row or the second transistor row) are adjacent to each other in direction D2 and are disposed on opposite sides of the barrier wall region. The adjacent transistor rows may be referred to as an adjacent transistor group; while transistor rows of another type (e.g., the second transistor row or the first transistor row) are disposed on opposite sides of the adjacent transistor group in direction D2. For example, a first transistor row and a first transistor row are adjacent to each other and constitute a first adjacent transistor group, and two second transistor rows are disposed on opposite sides of the first adjacent transistor group in direction D2; or, a second transistor row and a second transistor row are adjacent to each other and constitute a second adjacent transistor group, and two first transistor rows are disposed on opposite sides of the first adjacent transistor group in direction D2.

[0203] For example, in the adjacent first pixel row and second pixel row shown in Figure 25A, the two second transistor rows TS2 are adjacent to each other in direction D2, and are arranged on opposite sides of the barrier wall area (for example, the barrier wall electrode be2), and constitute a second adjacent transistor group; the two first transistor rows TS1 are arranged in direction D2 on opposite sides of the second adjacent transistor group constituted by the two transistor rows TS2.

[0204] In some adjacent first and second pixel rows, two second transistor rows TS2 are adjacent to each other and constitute a second adjacent transistor group; in other adjacent first and second pixel rows (for example, a first pixel row in the figure and a second pixel row adjacent above it (not shown), or a second pixel row in the figure and a first pixel row adjacent below it (not shown)), two first transistor rows TS1 are adjacent to each other and constitute a first adjacent transistor group. For example, in direction D2, the first adjacent transistor groups and the second adjacent transistor groups may be arranged alternately with each other.

[0205] Referring to Figure 25A, in some embodiments, multiple data signal lines SL1 and SL2 extend in a direction D2 substantially parallel to each other, and each data signal line SL1 can be connected to the source S of multiple transistors T1 arranged in the same column in the direction D2; each data signal line SL2 can be connected to the source S of multiple transistors T2 arranged in the same column in the direction D2; each data signal line SL3 can be connected to the source S of multiple transistors T3 arranged in the same column in the direction D2; the data signal line SL3 can have a symmetrical structure; for example, the portion of the data signal line SL3 corresponding to the adjacent pixel regions PR1 and PR2 can be symmetrical relative to the barrier electrode be2 between the adjacent pixel regions. For example, the part of the data signal line SL3 corresponding to each pixel area includes a first main part L1, a second main part L2 and a transfer part L3; and the first main part L1 of the part of the data signal line SL3 corresponding to the pixel area PR1 is connected to the first main part L1 of the part of the data signal line SL3 corresponding to the pixel area PR2, and the second main part L2 of the part of the data signal line SL3 corresponding to the pixel area PR1 is connected to the second main part L2 of the part of the data signal line SL3 corresponding to the pixel area PR2.

[0206] Referring to FIG. 25B , in an array substrate S1c, the pixel electrodes pe, barrier electrode structures, and reflective electrodes in multiple pixel regions can be disposed in the same layer as the electrode layer 107. The pixel electrode pe in each pixel region can include three pixel sub-electrodes spe. The barrier electrode structure can include multiple barrier electrodes be1, barrier electrodes be2, and connecting electrodes ae. The multiple barrier electrodes be1 surround the pixel electrodes pe in the multiple pixel regions PR, respectively, and each barrier electrode be1 is surrounded by a barrier electrode be2. That is, the barrier electrode be2 surrounds the multiple barrier electrodes be1 and is disposed between adjacent barrier electrodes be1.

[0207] The multiple blocking wall electrodes be1, blocking wall electrodes be2 and connecting electrodes ae of the blocking wall electrode structure can all be arranged outside the pixel area, that is, the orthographic projection of the blocking wall electrode structure on the base substrate may not overlap with the orthographic projection of the multiple pixel sub-electrodes on the base substrate, and does not overlap with the orthographic projection of the gap between adjacent pixel sub-electrodes in the same pixel area on the base substrate.

[0208] Multiple barrier electrodes be1 are arranged in an array along directions D1 and D2. Similar to the embodiment shown in Figures 9A and 9B, the multiple barrier electrodes be1 corresponding to multiple pixel regions in the same pixel row are electrically connected to each other via connecting electrodes ae. A voltage signal, such as a Vcom signal, can be applied to the barrier electrodes be1 in that row via connecting electrodes ae located on one side of the barrier electrode be1 at the end in direction D1. In some embodiments, barrier electrodes be1 in different rows, that is, all barrier electrodes be1, can be configured to receive the same voltage signal (first voltage signal), such as a Vcom signal.

[0209] Similar to the previous embodiment, the barrier electrode be2 can be in a grid-like shape, defining a plurality of grid regions gr, each of which is provided with a pixel region and the barrier electrode be1 surrounding the pixel region. In this example, the barrier electrode be2 has multiple openings op, that is, the barrier electrode be2 has multiple disconnected portions, and the multiple portions of the barrier electrode be2 are configured to receive the same voltage signal (the second voltage signal). The first voltage signal and the second voltage signal are different, thereby generating an electric field of a predetermined direction between the adjacent barrier electrodes be1 and be2.

[0210] Between each two adjacent pixel regions PR1 or PR2 in direction D1, the barrier electrode be2 and the barrier electrodes be1 located on opposite sides thereof are configured to form two electric fields in opposite directions (for example, leftward and rightward directions in the figure). Between each two adjacent pixel regions PR1 and PR2 in direction D2, the barrier electrode be2 and the barrier electrodes be1 located on opposite sides thereof are configured to form two electric fields in opposite directions (for example, upward and downward directions in the figure). In this embodiment, the manner in which the barrier electrodes be1 and be2 form an electron barrier is similar to that described in the aforementioned embodiment with respect to FIG. 18A and FIG. 18B , and thus will not be further described here.

[0211] Figure 26 shows a schematic cross-sectional view of an array substrate S1d according to other embodiments of the present disclosure. The array substrate S1d includes a base substrate 100, a conductive layer 101, an insulating layer 102, an active layer 103, a conductive layer 105, an insulating layer 106, an electrode layer 107, and a passivation layer 108. The gates GE of multiple transistors T and the first plates CE1 of multiple capacitors C may be located on the conductive layer 101. The source and drain electrodes S / D of multiple transistors T and the second plates CE2 of multiple capacitors C may be located on the conductive layer 105. The pixel electrode pe, the barrier electrode structure be, and the reflective electrode re may be located on the electrode layer 107, and the barrier electrode structure be and the reflective electrode re may share the same electrode. A via v1 may be provided in the insulating layer 106, and the pixel sub-electrode spe is connected to one of the source and drain electrodes (e.g., the drain electrode D) of the corresponding transistor T and the second plate CE2 of the corresponding capacitor C through the via v1. Vias v2 are provided in insulating layers 106 and 102, and the pixel sub-electrode spe is connected to the electrode plate CE1 located on the corresponding capacitor C through vias v2. Vias v3 are also provided in insulating layer 106, and portions of the barrier electrode structure (e.g., barrier electrode be1) are electrically connected to the electrode plate CE2 located on the conductive layer 105 through vias v3. The structural and positional relationships of the various components in the cross-sectional structure of array substrate S1d are substantially the same as those of array substrate S1a shown in Figure 4 and will not be further described here. Array substrate S1d differs from array substrate S1a in that the planar layout of the various components may differ.

[0212] Figures 27 to 31B illustrate schematic planar layouts of various layers and / or stacks of layers in a pixel region and its surrounding retaining wall region in an array substrate S1d. In some embodiments, the pixel electrode in each pixel region of the array substrate S1d includes two pixel sub-electrodes, and the array substrate is provided with two transistors, two capacitors, and two data signal lines correspondingly connected to the two pixel sub-electrodes.

[0213] 27 shows a planar layout diagram of the conductive layer 101. The conductive layer 101 includes a plurality of gates GE, a plurality of electrode plates CE1, and a gate signal line GL. The plurality of gates GE correspond to a plurality of transistors T1 and T2, respectively, and the plurality of electrode plates CE1 correspond to a plurality of capacitors C1 and C2, respectively. The plurality of gates GE may be arranged in a row along a direction D1, and the gate signal line GL connects the plurality of gates GE located in the same row and is configured to apply a gate signal to the plurality of gates GE. In some embodiments, the two electrode plates CE1 provided corresponding to the same pixel area may be arranged along a direction D1 and may be symmetrically provided with respect to each other; the electrode plate CE1 may have a recessed area 60, and a portion of the gate GE may be located in the recessed area 60 and spaced apart from the electrode plate CE1. In some embodiments, the area (i.e., the connection area) of the plurality of electrode plates CE1 used for connection to the pixel sub-electrodes is shown in a dotted box in the figure, and the connection areas of the two electrode plates CE1 provided corresponding to the same pixel area may not be aligned in the direction D1.

[0214] Figure 28 shows a schematic layout diagram of the stack of conductive layer 101 and active layer 103. Similar to the previous embodiment, active layer 103 includes multiple active areas AL, each corresponding to a plurality of transistors T1 and T2. Each active area AL is provided in correspondence with a corresponding gate electrode GE; for example, the active area AL and the gate electrode GE overlap in a direction perpendicular to the main surface of the substrate, and the orthographic projection of the active layer AL onto the main surface of the substrate can be located within the orthographic projection of the corresponding gate electrode GE onto the main surface of the substrate.

[0215] Fig. 29A shows a schematic layout diagram of a stack of conductive layer 101, active layer 103, and conductive layer 105. Fig. 29B shows a schematic layout diagram of conductive layer 105.

[0216] Referring to Figures 29A and 29B , the conductive layer 105 includes the source / drain electrodes S / D of multiple transistors T1 and T2, the second plates CE2 of multiple capacitors, and multiple data signal lines SL. The source electrodes S and drain electrodes D of transistors T1 and T2 each cover a portion of their corresponding active area AL. The source electrode S is connected to the corresponding data signal line SL, and the drain electrode D may have a connection region Dc. This connection region Dc may be relatively larger than the rest of the drain electrode D to facilitate subsequent connection to the pixel sub-electrode. The source / drain electrodes S / D of transistors T1 and T2 may be spaced apart from the electrode plate CE2. In some embodiments, the source / drain electrodes S / D of multiple transistors and the second plates CE2 of multiple capacitors corresponding to the same pixel area may be arranged between adjacent data signal lines SL in a direction D1. The second plate CE2 is arranged opposite the first plate CE1, i.e., overlapping in a direction perpendicular to the main surface of the substrate, with the second plate CE2 exposing the connection region of the first plate CE1. In other words, the conductive layer 105 has an opening that overlaps with the first electrode plate CE1, facilitating subsequent electrical connection between the pixel sub-electrode and the first electrode plate. In some embodiments, the second plates of multiple capacitors C1 and C2 corresponding to the same pixel region can share the same electrode plate CE2; in other words, the second plates CE2 of capacitors C1 and C2 are connected to each other.

[0217] Figure 30A shows a schematic layout diagram of a stack of conductive layer 101, active layer 103, conductive layer 105 and vias in insulating layers. Figure 30B shows a schematic layout diagram of a stack of conductive layer 105 and vias in insulating layers.

[0218] 30A and 30B , multiple vias v1 expose the drains D of multiple transistors T, for example, the connection regions Dc of the drains D. Multiple vias v2 penetrate the openings of the conductive layer 105 and expose the connection regions of multiple electrode plates CE1. Multiple vias v3 expose portions of the surface of the electrode plates CE2. In some examples, multiple vias v3 are provided for the same electrode plate CE2, but the number of vias v3 is not limited to that shown in the figures.

[0219] 31A shows a schematic layout diagram of a stack of conductive layer 101, active layer 103, conductive layer 105, vias in the insulating layer, and electrode layer 107. FIG31B shows a schematic layout diagram of electrode layer 107.

[0220] 31A and 31B , in some embodiments, the pixel electrode pe, the barrier electrode structure, and the reflective electrode re may be disposed on the same layer in the electrode layer 107 , and the barrier electrode structure may be reused as the reflective electrode re. That is, the barrier electrode structure and the reflective electrode share the same electrode structure.

[0221] In some embodiments, in each pixel region, the pixel electrode pe includes a pixel sub-electrode sp1 and a pixel sub-electrode sp2 spaced apart from each other. The pixel sub-electrode sp1 may be block-shaped, for example, square, rectangular, etc., or may be a suitable shape such as circular, elliptical, etc. The pixel sub-electrode sp2 may be annular and surround the pixel sub-electrode sp1 in a direction parallel to the main surface of the substrate. In this example, unlike the strip-shaped pixel sub-electrodes used in the aforementioned embodiments, the use of pixel electrodes of this shape can achieve different stacking forms of charged particles in the dispersant layer of the display device, thereby achieving display diversification.

[0222] For example, pixel sub-electrode sp1 is connected to the drain D of transistor T1 and the first plate CE1 of capacitor C1 through vias v1 and v3, respectively. Pixel sub-electrode sp1 can also serve as the third plate of capacitor C1. Pixel sub-electrode sp2 is connected to the drain D of transistor T2 and the first plate CE1 of capacitor C2 through vias v1 and v3, respectively. Pixel sub-electrode sp2 can also serve as the third plate of capacitor C2.

[0223] In some embodiments, the barrier electrode structure includes a barrier electrode be1, a barrier electrode be2, and a connecting electrode ae. The barrier electrode be1 is annular, for example, a closed ring, surrounding the pixel electrode pe in the corresponding pixel region PR. Each barrier electrode be1 is surrounded by a barrier electrode be2. The barrier electrode be2 has an opening op. The connecting electrode ae is disposed on one side or opposite to the barrier electrode be1 in direction D1. The connecting electrode ae passes through the opening op of the barrier electrode be2 and is spaced apart from the barrier electrode be2. The connecting electrode ae is used to connect adjacent barrier electrodes be1 and / or to connect voltage signals (e.g., Vcom signals). The layout of the barrier electrode structure is similar to the embodiment shown in Figures 24A and 24B, with the difference that the barrier electrode be1 in this embodiment has a relatively small size (e.g., width) and includes a connection area 70 for connecting to the via. The connection area 70 may have a relatively large size (e.g., width) relative to other portions of the barrier electrode be1, but the present disclosure is not limited thereto. Here, the width of the barrier electrode refers to the width in a direction perpendicular to its extension direction.

[0224] The barrier electrode be1 is connected to the electrode plate CE2 located in the conductive layer 105 through the via v3. In some embodiments, the barrier electrode be1 and the electrode plate CE2 are configured to receive the Vcom signal, and the electrode plate CE2 can also serve as a signal shielding layer to shield the pixel electrode sp from signal crosstalk from the underlying signal lines (e.g., the signal lines located in the conductive layer 101).

[0225] Figure 32A shows a schematic planar layout of a multilayer stack of multiple pixel regions and their surrounding barrier wall regions in the display region of array substrate S1d. Figure 32B shows a schematic planar layout of an electrode layer 107 of multiple pixel regions and their surrounding barrier wall regions in the display region of array substrate S1d.

[0226] Referring to Figures 32A and 32B , multiple pixel regions PR may be arranged in an array comprising multiple rows and columns along directions D1 and D2. Multiple transistors are also arranged in an array along directions D1 and D2. Multiple data signal lines SL extend along direction D2 and may be arranged along direction D1. Each data signal line SL may be connected to the sources S of multiple transistors T arranged in the same column along direction D2. Multiple barrier electrodes be1 are provided in a one-to-one correspondence with the multiple pixel regions. Each barrier electrode be1 is located at the periphery of a corresponding pixel region PR, for example, on a side of the pixel sub-electrode spe2 away from the pixel sub-electrode spe1, and surrounds the pixel electrode located in that pixel region PR.

[0227] Multiple barrier electrodes be1 can be arranged in an array along directions D1 and D2, respectively. For example, multiple barrier electrodes be1 located in the same row in direction D1 can be electrically connected to each other via connecting electrodes ae. Each barrier electrode be1 is surrounded by a barrier electrode be2. The barrier electrode be2 can be roughly grid-shaped and define multiple grid regions gr, each of which is provided with a pixel electrode and a barrier electrode be1 surrounding the pixel electrode. The layout of the barrier electrode structure in the electrode layer in this embodiment is similar to the embodiment shown in Figures 24A and 24B.

[0228] In some embodiments, barrier electrodes be1 located in different rows can be configured to receive the same voltage signal (first voltage signal), for example, the Vcom signal; that is, all barrier electrodes be1 can be configured to receive the same first voltage signal. Barrier electrodes be2 can be configured to receive a second voltage signal different from the first voltage signal. For example, the first voltage can be greater than or less than the second voltage. It should be understood that when barrier electrode be2 has a notch and includes multiple disconnected portions, multiple portions of barrier electrode be2 can be configured to receive the same voltage signal.

[0229] Between every two adjacent pixel regions PR in the direction D1, the barrier electrode be2 and the barrier electrodes be1 located on opposite sides thereof are configured to form two electric fields in opposite directions (for example, in the left and right directions in the figure), thereby forming an electron barrier between the adjacent pixel regions in the direction D1. Between every two adjacent pixel regions PR in the direction D2, the barrier electrode be2 and the barrier electrodes be1 located on opposite sides thereof are configured to form two electric fields in opposite directions (for example, in the upward and downward directions in the figure), thereby forming an electron barrier between the adjacent pixel regions in the direction D2. In this embodiment, the manner in which the barrier electrodes be1 and be2 form the electron barrier is similar to that described with respect to Figures 18A and 18B in the aforementioned embodiments, and will not be repeated here.

[0230] The embodiment of the present disclosure provides an electronic paper display device, including any one of the above-mentioned array substrates S1a-S1d. The electronic paper display device may be, for example, or include any one of the electronic paper display devices shown in Figures 2A to 2D, and the array substrate serves as the first substrate of the electronic paper display device. In the electronic paper display device including the array substrate of the embodiment of the present disclosure, a barrier electrode structure is provided between any two adjacent pixel regions, and the electron barrier generated by the barrier electrode structure between the adjacent pixel regions includes two opposite electric fields, thereby effectively preventing charged particles in the electronic paper display device from crosstalking between adjacent pixel regions, thereby improving the display quality of the display device. On the other hand, the barrier electrode structure can be reused as a reflective electrode structure, thereby improving the white state reflectivity of the display device.

[0231] In an electronic paper display device including any one of the array substrates S1a-S1d, a driving method for forming an electronic barrier wall includes: applying a first voltage signal to the barrier electrode be1 in the barrier electrode structure, and applying a second voltage signal different from the first voltage signal to the barrier electrode be2 in the barrier electrode structure, so as to form two reverse electric fields between each two adjacent pixel areas, formed by the barrier electrode be2 and the corresponding parts of the two barrier electrodes be1, and the two reverse electric fields together constitute an electronic barrier wall between adjacent pixel areas.

[0232] For example, the barrier electrode be1 can be connected to a signal line provided on the same layer via a connecting electrode ae, thereby applying a first voltage signal to the barrier electrode be1 via the signal line and the connecting electrode ae; alternatively, the barrier electrode be1 can be connected to a signal line on another layer via a via, thereby applying a first voltage signal to the barrier electrode be1 via the signal line; the barrier electrode be2 (e.g., a portion thereof near the edge of the display area) can be connected to a signal line provided on the same layer, thereby applying a second voltage signal to the barrier electrode be2 via the signal line; alternatively, the barrier electrode be2 can also be connected to a signal line located on another layer via a via, thereby applying a second voltage signal to the barrier electrode be2 via the signal line; the present disclosure does not limit the manner in which the barrier electrodes be1 and be2 receive voltage signals. In some embodiments, one of the first and second voltage signals (e.g., the first voltage signal) can be the same as the voltage signal received by the common electrode 201 on the second substrate of the electronic paper display device, for example, both being Vcom signals, but the present disclosure is not limited thereto. By forming an electron barrier between each two adjacent pixel regions, crosstalk of charged particles between adjacent pixel regions can be effectively avoided, thereby improving display quality.

[0233] There are a few points to note:

[0234] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to conventional designs.

[0235] (2) Unless there is any conflict, the features of the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0236] The above are only specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. An array substrate having a plurality of pixel areas arranged in an array, and comprising: substrate substrate; as well as A plurality of pixel electrodes and a barrier electrode structure are arranged on one side of the base substrate, the plurality of pixel electrodes are respectively located in the plurality of pixel regions, and the barrier electrode structure is located between adjacent pixel regions. The plurality of pixel regions include a first pixel region and a second pixel region arranged in a first direction parallel to the main surface of the substrate and adjacent to each other, and the plurality of pixel electrodes include a first pixel electrode and a second pixel electrode respectively located in the first pixel region and the second pixel region; The barrier wall electrode structure includes a first barrier wall electrode, a second barrier wall electrode and a third barrier wall electrode, and at least a portion of the first barrier wall electrode, at least a portion of the second barrier wall electrode and at least a portion of the third barrier wall electrode are arranged in sequence between the first pixel area and the second pixel area in the first direction, the first barrier wall electrode and the second barrier wall electrode are configured to form a first electric field, the second barrier wall electrode and the third barrier wall electrode are configured to form a second electric field, the first electric field and the second electric field are in opposite directions and are configured to jointly form an electron barrier wall, wherein the second barrier wall electrode is a common electrode of the first electric field and the second electric field.

2. The array substrate according to claim 1, wherein at least a portion of the first barrier electrode is located at the periphery of the first pixel region and surrounds the first pixel region in a direction parallel to the main surface of the base substrate; At least a portion of the third barrier wall electrode is located at the periphery of the second pixel region and surrounds the second pixel region in a direction parallel to the main surface of the base substrate. 3 . The array substrate according to claim 2 , wherein the second barrier electrode surrounds the first barrier electrode and the third barrier electrode in a direction parallel to the main surface of the base substrate.

4. The array substrate according to claim 3, wherein the at least portion of the second barrier wall electrode is located between the first barrier wall electrode and the third barrier wall electrode in the first direction and has an opening, and the first barrier wall electrode and the third barrier wall electrode are electrically connected to each other via a connecting electrode passing through the opening. 5 . The array substrate according to claim 1 , wherein the plurality of pixel electrodes and the barrier electrode structure are arranged in the same layer and are spaced apart from each other.

6. The array substrate according to claim 1, wherein the barrier electrode structure is disposed on a side of the plurality of pixel electrodes close to the base substrate, and an orthographic projection of the first barrier electrode on the base substrate covers the first pixel region and extends beyond an edge of an orthographic projection of the first pixel region on the base substrate; or The orthographic projection of the third barrier wall electrode on the base substrate covers the second pixel region and extends beyond the edge of the orthographic projection of the second pixel region on the base substrate. 7 . The array substrate according to claim 1 , wherein each pixel electrode comprises a plurality of pixel sub-electrodes, the plurality of pixel sub-electrodes are spaced apart from each other and are configured to be respectively connected to a plurality of data signal lines.

8. The array substrate according to claim 7, wherein one or more of the plurality of data signal lines each comprises a data signal main line and a data signal auxiliary line connected to each other through a switching electrode, and the plurality of data signal main lines are all located in an area outside a corresponding pixel area.

9. The array substrate according to claim 8, wherein the gap between the orthographic projections of the plurality of data signal main lines on the base substrate and the orthographic projections of a plurality of pixel sub-electrodes located in the same pixel area on the base substrate is offset. 10 . The array substrate according to claim 7 , wherein the plurality of pixel sub-electrodes comprise a plurality of strip electrodes, the plurality of strip electrodes are arranged along the first direction and extend along a second direction, and the first direction and the second direction intersect each other.

11. The array substrate according to claim 7, wherein the plurality of pixel sub-electrodes include a first pixel sub-electrode and a second pixel sub-electrode, and the second pixel sub-electrode surrounds the first pixel sub-electrode in a direction parallel to the main surface of the base substrate. 12 . The array substrate according to claim 1 , wherein the barrier electrode structure is also multiplexed as a reflective electrode.

13. The array substrate according to any one of claims 1 to 12, further comprising a plurality of transistors and a plurality of capacitors, each transistor comprising a gate, a source and a drain, each capacitor comprising at least a first plate and a second plate, a pixel sub-electrode of each pixel electrode being electrically connected to one of the source and the drain of the corresponding transistor, and being electrically connected to one of the first plate and the second plate of the corresponding capacitor, and the array substrate comprising: A first conductive layer, a first insulating layer, a second conductive layer, and a second insulating layer are sequentially arranged on one side of the base substrate, the gate and the first electrode plate are located on the first conductive layer, and the source, the drain, and the second electrode plate are located on the second conductive layer; as well as A first electrode layer is located on a side of the second insulating layer away from the substrate. The plurality of pixel electrodes are arranged on the first electrode layer, the second insulating layer has a first via hole, and the pixel sub-electrodes are connected to the source or drain of the corresponding transistor through the first via hole.

14. The array substrate according to claim 13, wherein The second conductive layer has openings; The second insulating layer and the first insulating layer have a second via hole therein, and the second via hole passes through the opening of the second conductive layer and is spaced apart from the second conductive layer; and The pixel sub-electrode is electrically connected to the first plate of the capacitor through the second via hole.

15. The array substrate according to claim 14, wherein the capacitor further comprises a third plate, and the pixel sub-electrode is reused as the third plate of the capacitor, and the capacitor comprises a double-layer capacitor formed between the second plate and the first plate and between the second plate and the third plate. 16 . The array substrate according to claim 14 , wherein the second electrode plate is configured to receive a common voltage signal and multiplexed into a signal shielding structure.

17. The array substrate according to any one of claims 13-16, wherein the barrier electrode structure is located in the first electrode layer, the second insulating layer further includes a third via hole, and the first barrier electrode and the third barrier electrode are respectively connected to the second plate of the corresponding capacitor through the third via hole.

18. The array substrate according to claim 13, further comprising: A second electrode layer, located on a side of the first electrode layer close to the base substrate and between the first electrode layer and the second insulating layer; as well as an organic layer, located between the first electrode layer and the second electrode layer, The retaining wall electrode structure is located in the second electrode layer and is reused as a reflective electrode.

19. An array substrate according to claim 18, wherein the first via hole extends from the organic layer into the second insulating layer, and the second electrode layer has an opening, the first via hole passes through the opening and is spaced apart from the second electrode layer, so that the pixel sub-electrode passes through the opening to be connected to the source or drain of the corresponding transistor.

20. The array substrate according to claim 19, wherein the orthographic projections of the first barrier electrode and the third barrier electrode on the base substrate overlap with the orthographic projections of the first pixel electrode and the second pixel electrode on the base substrate respectively, and the first barrier electrode and the third barrier electrode each have the opening.

21. The array substrate according to claim 19, wherein The first insulating layer and the second insulating layer have a third via hole, and the second conductive layer has an opening, the third via hole passes through the opening and is spaced apart from the second conductive layer; and The first barrier electrode and the third barrier electrode are electrically connected to the first plates of the corresponding capacitors through the third via holes, respectively.

22. The array substrate according to claim 21, wherein the first barrier electrode and the third barrier electrode are also used as third plates of corresponding capacitors, and the capacitors each include a double-layer capacitor formed between the second plate and the first plate and between the second plate and the third plate.

23. An array substrate according to claim 18, wherein the orthographic projection of the first electrode layer on the base substrate overlaps with the orthographic projection of the second electrode layer on the base substrate, and the orthographic projection of the second electrode layer also covers the orthographic projection of the gap area between multiple pixel sub-electrodes in each pixel area on the base substrate.

24. The array substrate according to claim 13, wherein each pixel electrode comprises a first pixel sub-electrode, a second pixel sub-electrode and a third pixel sub-electrode arranged along the first direction; In each pixel area, the plurality of transistors include a first transistor, a second transistor and a third transistor, which are respectively connected to the first pixel sub-electrode, the second pixel sub-electrode and the third pixel sub-electrode; The first transistor and the second transistor are arranged along the first direction, the third transistor is located on one side of the first transistor and the third transistor in the second direction, and at least a part of the orthographic projection of the third transistor on a reference plane extending along the first direction is located between the orthographic projections of the first transistor and the second transistor on the reference plane, and the first direction and the second direction intersect.

25. The array substrate according to claim 24, wherein the plurality of pixel regions are arranged into a plurality of pixel rows along the first direction, and are arranged into a plurality of pixel columns along the second direction; In a first pixel region and a third pixel region that are in the same pixel column and located in adjacent rows, a plurality of transistors in the first pixel region and a plurality of transistors in the third pixel region are symmetrically arranged.

26. The array substrate according to claim 25, wherein a first distance exists between the first transistor in the first pixel area and the first transistor in the third pixel area; a second distance exists between the second transistor in the first pixel area and the second transistor in the third pixel area; a third distance exists between the third transistor in the first pixel area and the third transistor in the third pixel area; the first distance, the second distance and the third distance are all distances in the second direction; The first distance and the second distance are the same, and the third distance is different from the first distance and the second distance.

27. An electronic paper display device, comprising the array substrate according to any one of claims 1 to 26.

28. The electronic paper display device according to claim 27, wherein the array substrate serves as a first substrate, and the electronic paper display device further comprises: A second substrate having a common electrode and arranged opposite to the first substrate; as well as The dispersant layer is located between the first substrate and the second substrate and includes charged particles located in the plurality of pixel regions.

29. The electronic paper display device according to claim 28, wherein the charged particles include at least one of first charged particles and second charged particles, the first charged particles have a first electrical property, the second charged particles have a second electrical property, and the first electrical property and the second electrical property are opposite.

30. The electronic paper display device according to any one of claims 27 to 29, wherein no physical barrier walls are included between adjacent pixel regions.

31. The electronic paper display device according to any one of claims 27-29 further includes a physical retaining wall, which is arranged between the first substrate and the second substrate in a direction perpendicular to the main surface of the base substrate, and is arranged between adjacent pixel areas in a direction parallel to the main surface of the base substrate.

32. The electronic paper display device according to claim 31, wherein the physical barrier wall overlaps with one or more barrier wall electrodes in the barrier wall electrode structure in a direction perpendicular to the main surface of the base substrate.

33. A method for driving an electronic paper display device according to any one of claims 27 to 32, comprising: applying a first voltage, a second voltage and a third voltage to the first barrier wall electrode, the second barrier wall electrode and the third barrier wall electrode respectively, The first voltage is smaller than the second voltage, and the third voltage is smaller than the second voltage. The electron blocking wall formed by the blocking wall electrode structure between the adjacent first pixel region and the second pixel region includes two electric fields with opposite electric field directions and away from each other; or The first voltage is greater than the second voltage, and the third voltage is greater than the second voltage, so that the electron blocking wall formed by the blocking wall electrode structure between the adjacent first pixel region and the second pixel region includes two electric fields with opposite electric field directions and facing each other.

34. The driving method of the electronic paper display device according to claim 33, wherein the first voltage and the third voltage are the same.

35. An array substrate, comprising a plurality of pixel regions arranged in an array, wherein the plurality of pixel regions are arranged into a plurality of pixel rows along a first direction and into a plurality of pixel columns along a second direction, wherein the first direction and the second direction intersect, and the array substrate comprises: substrate substrate; A plurality of pixel electrodes and a barrier electrode structure are arranged on one side of the base substrate, the plurality of pixel electrodes are respectively located in the plurality of pixel regions, and the barrier electrode structure is located between adjacent pixel regions; The barrier wall electrode structure comprises a plurality of first barrier wall electrodes and a second barrier wall electrode, wherein the plurality of first barrier wall electrodes are arranged in one-to-one correspondence with the plurality of pixel regions, at least a portion of each first barrier wall electrode surrounds a corresponding pixel region in a direction parallel to the main surface of the substrate, and each first barrier wall electrode is surrounded by the second barrier wall electrode in a direction parallel to the main surface of the substrate. 36 . The array substrate according to claim 35 , wherein the plurality of first barrier wall electrodes are configured to receive a first voltage signal, the second barrier wall electrodes are configured to receive a second voltage signal, and the first voltage signal and the second voltage signal are different.

37. The array substrate according to claim 35, wherein the plurality of first barrier wall electrodes are arranged in a plurality of rows along the first direction; The second barrier wall electrode has an opening at a portion between each two adjacent first barrier wall electrodes in the same row; The barrier wall electrode structure further includes a connecting electrode, and the connecting electrode passes through the opening, so that a plurality of first barrier wall electrodes located in the same row are electrically connected to each other through the connecting electrode.

38. The array substrate according to claim 35, wherein the second barrier wall electrode is in a grid shape and defines a plurality of grid areas; A pixel area and a first barrier electrode surrounding the pixel area are arranged in each grid area. 39 . The array substrate according to claim 38 , wherein each of the plurality of first barrier wall electrodes is in a ring shape or a planar shape.

40. The array substrate according to any one of claims 35 to 39, wherein each pixel electrode comprises a plurality of pixel sub-electrodes, and the plurality of pixel sub-electrodes are respectively connected to a plurality of data signal lines; Each data signal line at least includes a data signal main line, and one or more of the plurality of data signal lines each further includes a switching electrode and a data signal auxiliary line, wherein the data signal auxiliary line is electrically connected to the data signal main line through the switching electrode; A plurality of data signal main lines extend along the second direction and are located on opposite sides of the pixel area in the first direction. The data signal auxiliary lines and the transfer electrodes are located between adjacent data signal main lines in the first direction and between the pixel area and the second barrier wall electrode in the second direction.

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