Threshold switching field-effect transistors and methods thereof

Abstract

The present invention concerns threshold switching field-effect transistor (TSFET), comprising a field-effect transistor (FET) comprising a channel, a dielectric layer comprising a two-dimensional (2D) van der Waals (vdW) structure, and an electrically conductive layer, wherein the dielectric layer is sandwiched between and contacted with the channel and the electrically conductive layer, and a threshold switching (TS) device comprising a switching layer comprising the 2D vdW structure, wherein the dielectric layer of the FET and the switching layer of the TS device form a first single entity.

Description

[0001] THRESHOLD SWITCHING FIELD-EFFECT TRANSISTORS AND METHODS THEREOF

[0002] Technical Field

[0003] The present invention relates, in general terms, to threshold switching field-effect transistors and their methods of fabrication thereof. More specifically, the present invention relates to a threshold switching field -effect transistor with a common two- dimensional van der Waals (vdW) layer.

[0004] Background

[0005] Great advances have been made in information technology by reducing the physical size of metal-oxide-semiconductor field-effect transistors (MOSFET) to keep up with Moore's law. However, power dissipation in existing devices with increasing integration density has become a serious problem and the supply voltage can no longer be scaled with downscaling of MOSFET to achieve energy-efficient operations. This is because of the fundamental thermionic limit of subthreshold swing (SS) that is not scalable and cannot be reduced to below 60 mV / dec (at room temperature) governed by the thermal voltage (kT / q) owing to the thermionic carrier injection mechanism of conventional MOSFET. Further scaling of supply voltage is restricted due to the exponential increase in OFF-state current.

[0006] To overcome this limit, researchers have made considerable efforts in developing several kinds of steep switching FETs such as tunnelling FET (TFET), negative capacitance FET (NCFET), Phase FET, impact-ionization FET (I2FET), threshold switching FET (TSFET) for low power electronics. Among them, TFET and NCFET as the most investigated devices with SS beyond the limit, use non-thermionic injection approach (quantum mechanical band-to-band tunnelling) and NC effect of ferroelectric dielectric to amplify the gate voltage, respectively. However, there are existing challenges that cannot be avoided: low ON-state current density in TFET and stringent requirement on capacitance matching in NCFET. TSFET as a new type of steep switching device has gained a substantial interest recently due to the compatibility with existing complementary MOS (CMOS) technology and low voltage operation in addition to the steep switching slope. For this type of device, a threshold switching (TS) device with a simple metal-insulator-metal (MIM) structure as an abrupt switch is connected in series with a baseline FET. Compared with phase FET using VO2 switch, TS device possesses abrupt resistive switching behaviour with lower OFF-state current and operation voltage. When the TS device reaches a threshold voltage, it shows an abrupt resistance switching from high resistance state (HRS) to low resistance state (LRS), triggering the internal voltage amplification, and thereby leading to the steep switching slope and sub-thermionic SS at the subthreshold region of the transfer curve of the TSFET device. After the steep switching, the TS device can relax back to its original state without the need of reverse voltage, which is superior to non-volatile memory device for this steep switching device application.

[0007] It is generally desirable to overcome or ameliorate one or more of the above described difficulties.

[0008] Summary

[0009] The present invention seeks to address at least one of the problems in the prior art, and to provide a threshold switching field-effect transistor with a common two- dimensional (2D) van der Waals (vdW) layer.

[0010] The present invention provides a threshold switching field-effect transistor (TSFET), comprising: a field-effect transistor (FET) comprising: a channel; a dielectric layer comprising a two-dimensional (2D) van der Waals (vdW) structure; and an electrically conductive layer; wherein the dielectric layer is sandwiched between and contacted with the channel and the electrically conductive layer; and a threshold switching (TS) device comprising: a switching layer comprising the 2D vdW structure; wherein the dielectric layer of the FET and the switching layer of the TS device form a first single entity. In some embodiments, the TSFET further comprises a source and a drain on opposite sides and at a first surface of the channel, and wherein the electrically conductive layer is configured to function as a gate.

[0011] In some embodiments, the TSFET comprises an electrode of the threshold switching (TS) device connected in series with the source of the field-effect transistor (FET).

[0012] In some embodiments, the TSFET comprises an electrode of the TS device connected in series with the gate of the FET.

[0013] In some embodiments, the TSFET comprises an electrode of the TS device and the source or the gate of the FET formed as a second single entity, the second single entity capable of electrically characterising the TS device and the FET separately.

[0014] In some embodiments, the TS device in the TSFET comprises two electrodes sandwiching the switching layer.

[0015] In some embodiments, the TS device in the TSFET comprises an electrode directly connected to the switching layer and another electrode connected to the switching layer via the electrically conductive layer.

[0016] In some embodiments, the TSFET is characterised by a subthreshold swing of between about 2.0 mV / dec to about 12.0 mV / dec.

[0017] In some embodiments, the subthreshold swing of the TSFET remains stable over an operation voltage range of the device.

[0018] In some embodiments, the TSFET comprises: a dielectric layer, wherein the dielectric layer is selected from a list of 2D vdW structures, comprising hexagonal boron nitride (hBN), calcium fluoride or a combination thereof, and wherein the dielectric layer is characterised by a thickness of between about 5 nm to about 15 nm; an electrically conductive layer, wherein the electrically conductive layer is selected from a list of materials, comprising few-layer graphene, thin metal films, or a combination thereof. In some embodiments, the TSFET is in a high resistance state (HRS) when a voltage bias of less than a predefined threshold voltage is applied, and wherein the device enters a low resistance state (LRS) when the voltage bias is increased above the predefined threshold voltage.

[0019] In some embodiments, the predefined threshold voltage is about 0.8 V to about 1.0 V.

[0020] The present invention also provides for a method of fabricating a threshold switching field-effect transistor comprising: forming a field-effect transistor (FET) by sandwiching and contacting a dielectric layer between with a channel and an electrically conductive layer; and forming a threshold switching (TS) device adjacent to the FET, the TS comprising a switching layer; wherein the dielectric layer of the FET and the switching layer of the TS device comprises a two-dimensional (2D) van der Waals (vdW) structure and is formed as a first single entity.

[0021] In some embodiments, the method further comprises depositing a source and a drain on top of the channel, wherein the source and the drain are on opposite sides and at a first surface of the channel.

[0022] In some embodiments, threshold switching is activated by an electroforming process.

[0023] In some embodiments, the electrically conductive layer is transferred and deposited by mechanical exfoliation.

[0024] In some embodiments, when an electrode of the TS device is connected in series with the source of the FET, the method further comprises a photolithography step for patterning the electrically conductive layer.

[0025] Brief description of the drawings Some embodiments of the systems and methods for this invention, in accordance with the present disclosure, will now be described, by way of non-limiting example only, with reference to the accompanying drawings, in which:

[0026] Figures 1(a) and 1(b) show the schematics of a threshold switching FET in two example embodiments.

[0027] Figure 2 shows the schematics of a threshold switching FET, in a circuit diagram and in its side view. A summary of the subthreshold swing values of the baseline FET and TSSFET are plotted.

[0028] Figure 3 shows the schematics of two types of steep switching threshold switching field-effect transistors in source and in gate configurations. The typical 1-1 / characteristics of a threshold switching device, a field-effect transistor, and a combination of the two connected in series via the source, and the gate, of the transistor are shown.

[0029] Figures 4 and 5 show the electrical characteristics of a TS connected to a FET via the source electrode. The circuit symbols denoting the source, drain, gate, and internal source electrodes are shown. The measured I-V characteristics of the TSSFET are shown. A schematic of the formation and rupture of the Ag conductive filament is shown. The transfer characteristics of the baseline FET and TSSFET are shown. The subthreshold swing for both the FET and TSSFET are shown. Finally, reproducibility of these devices is demonstrated over ten devices.

[0030] Figure 6 shows the Raman spectrum of the MoS2 / hBN / graphene heterostructure.

[0031] Figure 7 shows the gate leakage of the TSSFET over a range of I / G values from -2 V to 2 V.

[0032] Figure 8 shows the transfer characteristics of a TSSFET, as divided into three regions, that is, before, during and after, the abrupt resistive switching in the threshold switching device. It also shows the front view of the TSSFET. The transfer characteristics of the TSSFET under different values of VDand the values of VTH and SS against VDare also shown. Figure 9 shows the transfer curve of a TSSFET at a high 1 / D of 1 V. Due to the high VDvalue, the voltage drop across the TS device is high and the device is switched on a lower VG.

[0033] Figure 10 shows the electrical characteristics of a TS connected to a FET via the gate electrode. The circuit symbols denoting the source, drain, gate, and internal source electrodes are shown. The measured I- V characteristics of the TSGFET are shown. The transfer characteristics of the baseline FET and TSSFET are shown. The subthreshold swing for both the FET and TSSFET are shown. Finally, reproducibility of these devices is demonstrated over ten devices.

[0034] Figure 11 shows a step-by-step fabrication process for a TSGFET.

[0035] Figure 12 shows consecutive I-V curves of the hBN TS device of the TSG FET in a negative and in a positive direction. Figure 10 shows a transfer curve of the baseline 2D FET.

[0036] Figure 13 shows the transfer characteristics and gate leakage currents of the TSGFET.

[0037] Detailed description

[0038] Without wanting to be bound by theory, the inventors believe that the scaling limit may be overcome from a material perspective. Two-dimensional (2D) materials with unique electronic properties have drawn tremendous attention as promising candidates for various kinds of electronic devices. FETs with 2D semiconducting channel materials such as transition metal dichalcogenides (TMD) have shown excellent electrostatic control, low OFF-state current and more importantly, scaling dimensions. Resistive switching devices with 2D dielectrics such as insulating hexagonal boron nitride (hBN) have also shown robust switching and low leakage. In addition, the surface dangling bond free nature and wide range of 2D materials allow the heterogeneous van der Waals (vdW) integration of 2D heterostructures without lattice matching issues. Therefore, the integration of TS device and FET based on 2D materials holds great potential in fabricating steep switching TSFET.

[0039] The embodiments described herein aim to provide a threshold switching field-effect transistor (TSFET) device with a common insulating layer functioning as both the dielectric layer for the field-effect transistor (FET) and the threshold switching layer for the threshold switching device (TS). Figures 1(a) and 1(b) illustrate example schematics of the TSFET device. This device structure provides for a compact structure and facile fabrication.

[0040] In some embodiments, the present invention provides for a threshold switching fieldeffect transistor (TSFET) device (100, 200), comprising: a field-effect transistor (FET), comprising: a channel (112, 212); a dielectric layer comprising a two-dimensional (2D) van der Waals (vdW) structure (110, 210); and an electrically conductive layer (106, 206); wherein the dielectric layer is sandwiched between and contacted with the channel (112, 212) and the electrically conductive layer (106, 206); and a threshold switching (TS) device, comprising: a switching layer comprising the 2D vdW structure (110, 210); wherein the dielectric layer of the FET and the switching layer of the TS device form a first single entity.

[0041] The term "first single entity" refers to the 2D vdW structure which is configured to function as both the dielectric layer of the FET and the switching layer of the TS device.

[0042] In some embodiments, the threshold switching field-effect transistor (TSFET) device (100, 200), comprises: a field-effect transistor (FET), comprising: a channel (112, 212); a two-dimensional (2D) van der Waals (vdW) structure (110, 210); and an electrically conductive layer (106, 206); wherein the 2D vdW structure (110, 210) is sandwiched between and contacted with the channel (112, 212) and the electrically conductive layer (106, 206); and a threshold switching (TS) device, comprising: the 2D vdW structure (110, 210), wherein the 2D vdW structure (110, 210) is configured to function as a dielectric layer for the FET and a switching layer for the TS device. In some embodiments, the TSFET (100, 200) comprises: a field-effect transistor (FET) comprising: a channel (112, 212); a source (116, 216) and a drain (114, 214) on opposite sides and at a first surface of the channel (112, 212); a dielectric layer comprising a two-dimensional (2D) van der Waals (vdW) structure (110, 210), the 2D vdW structure (110, 210) contacted to a second surface of the channel (112, 212); and an electrically conductive layer (106, 206) contacted to the dielectric layer and configured to function as a gate; a threshold switching (TS) device comprising two electrodes (108, 208, 218) electrically connected to a switching layer, the switching layer comprising the 2D vdW structure (110, 210); wherein the dielectric layer of the FET and the switching layer of the TS device form a first single entity.

[0043] In some embodiments, the threshold switching field-effect transistor (TSFET) device (100) comprises: a field-effect transistor (FET), comprising: a channel (112); a source electrode (116) and a drain electrode (114) on opposite sides of the FET and at a first surface of the channel (112); a dielectric layer comprising a two-dimensional (2D) van der Waals (vdW) structure (110), the dielectric layer contacted to a second surface of the channel (112); and an electrically conductive layer (106) contacted to the dielectric layer, configured to function as the gate; and a substrate (102, 104); a threshold switching (TS) device, comprising: a first electrode (108); a second electrode; and a switching layer comprising the 2D vdW structure (110), the 2D vdW structure (110) sandwiched between and contacted with the first electrode (108) and the second electrode. In some embodiments, the threshold switching field-effect transistor (TSFET) device (200) comprises: a field-effect transistor (FET), comprising: a channel (212); a source electrode (216) and a drain electrode (214) on opposite sides of the FET and at a first surface of the channel (212); a dielectric layer comprising a two-dimensional (2D) van der Waals (vdW) structure (210), the dielectric layer contacted to a second surface of the channel (212); and an electrically conductive layer (206) contacted to the dielectric layer, configured to function as the gate; and a substrate (202, 204); a threshold switching (TS) device, comprising: a first electrode (208); a second electrode (218); and a switching layer comprising the 2D vdW structure (210), the switching layer electrically connected to the first electrode (208) via the electrically conductive layer (206).

[0044] The second surface of the channel may be parallel to the first surface of the channel (112, 212).

[0045] The 2D vdW structure (110, 210) forms the switching layer of the TS and the dielectric layer of the FET. In other words, the switching layer and the dielectric layer is present as a first single entity; i.e. the switching layer and the dielectric layer may be made in a single step from a single material.

[0046] The 2D vdW structure will hence, hereafter, be referred to as the dielectric layer, in the context of the FET device, and be referred to as the switching layer, in the context of the TS device. The FET and the TS device share the same 2D vdW structure, which may be a hBN layer, as the dielectric layer and the switching layer, respectively.

[0047] A 2D van der Waals (vdW) structure refers to a two-dimensional material that is held together by weak van der Waals interactions, rather than strong covalent or ionic bonds. 2D vdW structures are composed of a single layer or a few layers of atoms. The thickness of these materials is typically on the order of a few nanometres or less. The individual layers in a 2D vdW structure are held together by van der Waals forces, which are much weaker than the strong covalent or ionic bonds within each layer. This allows the layers to slide or be easily separated from each other. 2D vdW structures can be made from a wide range of materials, including graphene, transition metal dichalcogenides (TMDs), hexagonal boron nitride (hBN), and others. The properties of 2D vdW structures may thus be tailored by controlling the choice of material, the number of layers, and the stacking order or orientation of the layers.

[0048] In some embodiments, the dielectric layer and the electrically conductive layer (106, 206) may form a 2D vdW heterostructure. A 2D vdW heterostructure refers to a layered material composed of two or more different two-dimensional (2D) materials stacked on top of each other, held together by weak van der Waals forces. For example, the electrically conductive layer (106) may be a 2D vdW structure of a different material relative to the 2D vdW structure of the dielectric layer. For example, the dielectric layer may be hexagonal boron nitride (hBN) and the electrically conductive layer (106, 206) may be graphene. When the dielectric layer and the electrically conductive layer (106, 206) are contacted with each other; i.e. the dielectric layer stacked on top of the electrically conductive layer (106, 206), a 2D vdW heterostructure is formed.

[0049] In other embodiments, the dielectric layer and the channel (112, 212) may form a 2D vdW heterostructure. For example, the dielectric layer may be hBN and the channel (112, 212) may be a transition metal dichalcogenides (TMDs) such as molybdenum disulphide (M0S2).

[0050] In other embodiments, the dielectric layer, the electrically conductive layer (106, 206) and the channel (112, 212) form a 2D vdW heterostructure. For example, the dielectric layer may be hBN, the channel (112, 212) may be M0S2, and the electrically conductive layer (106, 206) may be graphene.

[0051] In one or more embodiments, a threshold switching (TS) device may be connected in series to the source electrode (116, 216) of a field-effect transistor (FET). This structure is referred to as a TSS-FET device, hereafter in the disclosure and the figures which follow. It shall be understood that a series connection refers to all circuit elements being arranged and connected in a single path - i.e., there is a single path of current through the relevant circuit elements. In this said one or more embodiments, it shall be understood that when the TS device and the source electrode of the FET are connected in series and further sharing at least one component, the source electrode of the FET (116, 216) and one of the two electrodes of the TS device form a second single entity. Figure 1(a) illustrates one embodiment in which the source electrode (116) of the FET also functions as an electrode of the TS device.

[0052] In another one or more embodiments, the TS device may be connected in series to the electrically conductive layer or gate electrode (206) of the FET. This structure is referred to as a TSG-FET device, hereafter in the disclosure and the figures which follow. Figure 1(b) illustrates one embodiment, in which one electrode (208) of the TS device and the gate electrode (206) of the FET are connected in series and the FET and TS form a first single entity via the 2D vdW structure (210) and a second single entity via the gate electrode (206).

[0053] The term "second single entity" is used to refer to a combined electrode formed by an electrode of the TS device and the source of the FET or a combined electrode formed by an electrode of the TS device and the gate of the FET.

[0054] In the devices of the present invention, the threshold switching field-effect transistor device may be formed on a support substrate. The support substrate may be a 300- nm-thick SiCh (104, 204) on Si substrate (102, 202).

[0055] In some embodiments, the source electrode (116, 216) and the drain electrode (114, 214) may be deposited on a first surface of the semiconducting channel (112, 212). In this regard, the source electrode (116, 216) and drain electrode (114, 214) may be deposited on a first surface (top facing) of the channel (112, 212). The source electrode (116, 216) and the drain electrode (114, 214) may be on opposite sides of the channel (112, 212) such that they are spaced apart and not in contact. For the purpose of this disclosure, "opposite sides" of the channel refers to any two points which are spaced apart, for e.g., a left side and a right side, wherein the left side and the right side are both on the same surface of the channel, but separated by a length, which a skilled person would understand to be the channel length of the FET.

[0056] The semiconducting channel (112, 212) may be deposited above and in direct contact with the dielectric layer. In this regard, a second surface (substrate facing) of the channel (112, 212) is in contact with a third surface (top facing) of the dielectric layer. The dielectric layer may be deposited above and in direct contact with the electrically conductive layer (106, 206). In this regard, a fourth surface (substrate facing) of the dielectric layer is contacted with a fifth surface (top facing) of the electrically conducting layer (106, 206). The electrically conductive layer (106, 206) may be the gate electrode of the FET, and may be directly deposited on the substrate. The substrate may be a SiOz on Si substrate. Such a configuration forms the bottomgate top-contact (BGTC) device architectures in FETs.

[0057] In other embodiments, the FET in the TSFET device may take on other device architectures. The electrically conductive layer (106, 206) may be deposited on the top surface of the semiconducting channel (112, 212), separated by the dielectric layer. The source electrode (116, 216) and the drain electrode (114,214) may be deposited on the same surface (i.e. the top) of the semiconducting channel as the gate, as in the case of top-gate top-contact (TGTC) devices, or on the other surface (i.e. the bottom) of the semiconducting channel as the gate, as in the case of topgate bottom-contact (TGBC) devices.

[0058] For the purposes of this disclosure and unless the context requires otherwise, having two materials in "contact" implies that the said two materials are in physical contact. When used in reference to device architectures in FETs, the terms "top contact" and "bottom contact" refer to the placement of the source electrode and the drain electrode relative to the semiconducting channel - i.e., the source electrode and the drain electrode are deposited on top of the semiconducting channel in top-contact devices, and the semiconducting channel is deposited on top of the source electrode and the drain electrode in bottom-contact devices. The components may be in contact in order for them to be electrically connected.

[0059] The source, drain and electrically conductive layer (gate) electrodes may each independently comprise a thin metal film selected from Au, Ag, Cu, or any combination thereof, or any materials which may provide suitable charge injection into the semiconducting channel material (112, 212) such as few-layer graphene. The electrodes may be deposited by means of standard electron-beam evaporation. The electrodes may be further patterned by standard electron-beam lithography followed by a lift-off process. The electrodes may have a thickness of between about 30 nm to about 40 nm, or between about 30 nm to about 60 nm, or between about 30 nm to about 120 nm. The channel material may comprise a semiconductor selected from M0S2, MoSe2, MoTe2, or other semiconducting transition metal dichalcogenide (TMD) materials, or any combination thereof. The channel material may be deposited by means of mechanical exfoliation from a bulk material. The channel material may also be deposited by means of solution processing methods such as drop-casting or spincoating. The channel material may have a thickness of between about 2 nm to about 20 nm, or about 2 nm to about 10 nm, or about 2 nm to about 5 nm.

[0060] 2D vdW structure are 2D layers of structures held together by weak van der Waals forces. The properties of 2D vdW structure may be tuned by controlling the twist angle, the stacking order, the interlayer spacing, or type of heterostructures, among other things. The 2D vdW structure may be selected from hexagonal boron nitride (hBN), calcium fluoride, Sb2O3, Bi2SeOs, or any combination thereof. The dielectric layer may be deposited by means of mechanical exfoliation from a bulk material. The dielectric layer may also be deposited by means of chemical vapour deposition, or liquid exfoliation. The dielectric layer may have a thickness of between about 5 nm to about 20 nm, or about 8 nm to about 13 nm.

[0061] In some embodiments, the 2D vdW structure is characterised by a twist angle of about 00to about 10 The twist angle refers to the relative rotational orientation between the individual 2D layers stacked on top of each other. This may be within the hBN 2D vdW structure, or between the 2D vdW heterostructures. In other embodiments, the twist angle is about 00to about 8 °, about 0 ° to about 6 °, about 0 ° to about 5 °, about 0 ° to about 4 °, about 0 ° to about 3 °, about 0 ° to about 2 °, or about 00to about 1 °. In other embodiments, the twist angle is 0 °. For example, the twist angle between graphene and h-BN may be 0 °. For example, the twist angle between M0S2 and h-BN may be 0 °.

[0062] In some embodiments, the 2D vdW structure is characterised by a AA' stacking order. In the AA' stacking configuration, the 2D vdW structure is stacked such that atoms in one layer are aligned directly above the counterpart atoms in the adjacent layer, and vice versa. For example, in hBN, the boron atoms in one h-BN layer are directly above the nitrogen atoms in the adjacent layer. The nitrogen atoms in the first layer are directly above the boron atoms in the second layer. This stacking order results in a repeating pattern of boron-nitrogen pairs between the layers.

[0063]

[0064] The electrically conducting layer (106, 206) may comprise a few layers of graphene. In some embodiments, the electrically conducting layer comprises 1 to 20 layers of graphene, 1 to 15 layers of graphene, 1 to 10 layers of graphene, or 3 to 10 layers of graphene. The few layers of graphene may be deposited by mechanical exfoliation from bulk graphite. It may also be deposited by means of thin film transfer from a source of chemical-vapour deposited (CVD) graphene on a metal foil.

[0065] The dielectric layer may also function as the switching layer in the threshold switching device. The dielectric layer may be sandwiched by two electrodes to provide for a threshold switching device. For example, in Figure la, the source electrode 116 may also double up as one of the electrode of the TS device, and the 2D vdW structure is sandwiched by the source electrode 116 and another electrode 108 to provide the TS device. As shown in Figure lb, the dielectric layer may be directly and electrically connected to one electrode (218) of the TS device, and connected to the one other electrode (208) of the TS device via a conductor. For example, the conductor may be the electrically conductive layer (206). The electrically conductive layer (206) may be few-layer graphene (FLG) as described in herein.

[0066] The threshold switching device, comprising two electrodes and a switching layer, may be connected in series with the source electrode of the field-effect transistor. The threshold switching device may also be connected in series with the gate electrode or electrically conductive layer of the field-effect transistor.

[0067] The dielectric layer of the FET and the switching layer of the TS device form a first single entity in the sense that the 2D vdW structure is formed continuously as a single structure. The dielectric layer and switching layer are thus linked to form a dielectricswitching layer, and in this way, connects the FET device to the TS device. Advantageously, a single dielectric-switching layer provides for monolithic integration, i.e. the electronics of the TS and FET devices may be integrated in a common semiconductor material via a single growth process. This also reduces the fabrication steps and enables a compact structure.

[0068] The one electrode of the threshold switching device may be formed as a second single entity together with the source or the gate of the field-effect transistor. As a second single entity, the one electrode may be capable of electrically characterizing the threshold switching device and the field-effect transistor separately.

[0069] In some embodiments, the TSFET is characterised by a subthreshold swing of about 2.0 mV / dec to about 12.0 mV / dec. The subthreshold swing may remain stable over an operation voltage range of the device.

[0070] In general, Figure 2 shows the design of steep switching TSFET combining a TS device and a baseline FET. The thermionic limit of the FET may be overcome by increasing the nonlinearity of transfer curve by means of utilising the sharp resistive switching from a high resistance state (HRS) to a low resistance state (LRS) of the TS device. This may in turn give rise to a steep slope in the transfer curve, overcoming the lower limit of 60 mV / dec, imposed on the subthreshold swing (SS) of a conventional FET. Figures 3(a) and 3(b) show the typical I-V curves and schematics for a threshold switching device and for an n-type field-effect transistor respectively.

[0071] In some embodiments, the device is in a high resistance state (HRS) when a voltage bias of less than a predefined threshold voltage is applied, and the device enters a low resistance state (LRS) when the voltage bias is increased above the predefined threshold voltage.

[0072] In some embodiments, the predefined threshold voltage is about 0.8 V to about 1.0 V.

[0073] As an internal voltage amplifier, a TS device may be connected in series with the source or gate electrode of a baseline FET to construct a TS-source FET (TSS FET) and a TS-gate FET (TSG FET), respectively. The equivalent circuit diagrams and the transfer characteristics of the two TSFETs are shown in Figures 3(c) and 3(d), respectively. The sub 60 mV / dec SS in such structures of both steep switching TSFETs is dominated by the abruptness of the resistive switching of the TS device.

[0074] In the first one or more embodiments, a TS device is connected in series with a source electrode of a baseline FET (TSSFET). Figure 4(a) shows a top-down schematic of the TSS FET in which a hBN TS device is in series connection to the source electrode of 2D FET (where the dotted areas represent the baseline 2D FET (left) and the hBN TS (right) devices, respectively). The 2D FET and TS device may share the same hBN layer as the dielectric and the switching medium, respectively. This structural design enables facile fabrication and may offer a promising approach for future monolithic integration.

[0075] For electrical characterization of the TSS FET, Vb is applied to the drain electrode (D) and the bottom few-layer graphene (FLG) as the source electrode (S) is grounded. The semiconducting channel is modulated by the bottom graphene as the back gate (G). The semiconducting channel may be a thin layer of compound such as 3-6 layers of molybdenum disulfide (M0S2). The electrode bridging two devices acts as both the internal source electrode (S') for the baseline 2D FET and the top electrode for the TS device for individual electrical characterizations. The TS device has a metalinsulator-metal (MIM) structure. The switching medium may be hexagonal boron nitride (hBN). The thickness of the switching medium may be 8-13 nm. The switching medium may be sandwiched in between S' and S electrodes.

[0076] Figure 4(b) shows the electrical characteristics of the hBN TS devices. In particular, Figure 4(b) shows the I-V characteristics of the hBN TS device. To enable threshold switching, an electroforming process may be performed, wherein electroforming is the process of creating metal parts by electrodeposition. To ensure that the switch works in the threshold switching region, and to avoid destructive electrical breakdown, a compliance current (CC) may be applied.

[0077] Figure 4(b) details the electrical activity in the device as a voltage bias is applied. During forward sweep and when the voltage bias is low, the device current increases slightly with an increase in voltage. The current values in this region are in the pA scale. The device is in a high resistance state (HRS). At a value of VSET of around 0.4 V, the device may undergo an abrupt increase in its current to the compliance current. This indicates that a transition from HRS to low resistance state (LRS) has occurred. This may be attributed to the formation of Ag filaments, which bridge the first and the second electrodes of the TS device. The formation of Ag filaments which bridge the first and the second electrodes of the TS device is shown in Figure 4(c).

[0078] The characteristics in Figure 4(b) allow for the calculation of the transition slope and the on-off ratio to be below 5 mV / dec and above 104, respectively. These values may be underestimated due to the application of a compliance current (CC) and the limitations of the measurement unit.

[0079] Spontaneously, the conductive Ag filaments which have formed during the transition from HRS to LRS may rupture, as shown in Figures 4(c) and 4(d), and the current may return to its initial state at a lower voltage during the backward sweep.

[0080] Advantageously, the spontaneous rupture of the conductive Ag filaments removes the need for an application of a reverse voltage to revert the TS to a HRS. Advantageously, the hBN TS device exhibits stable threshold switching behaviour with high non-linearity and low operation voltage.

[0081] Figure 5(a) shows the drain current (Io)-gate voltage (VG) curve of the 2D M0S2 FET at drain voltage (VD) of 0.5 V as the baseline FET, exhibiting typical n-type transfer characteristics with high on-off ratio of 107. Figure 5(a) features an inset revealing the cross-sectional transmission electron microscope (TEM) image of the MoS2 / hBN / FLG stack, which shows an atomically sharp interface. Figure 4 shows a Raman spectrum of the heterostructure stack.

[0082] Figure 5(b) shows the measured ZD-I / G characteristics of the TSS FET. TSS FET may present a low OFF-state current of about 10-13A pm-1. This value may be suppressed owing to the high resistance of the hBN TS device. ID increases dramatically by six orders of magnitude to The observed steep current transition may likely indicate that the state of the TS device has switched from HRS to LRS as a result of the formation of conductive Ag filaments. Figure 7 shows that the gate leakage current remains in pA level across a 1 / G range of -2 to 2 V. After the device is switched ON, ID follows the transfer curve of the baseline 2D FET. A steep current transition may indicate the resistance switching in the hBN TS device, resulting from the formation of conductive Ag filaments.

[0083] Figure 5(c) displays the extracted SS as a function of ID for the transfer curves of the baseline 2D FET and the TSS FET, as labelled. The lowest SS value in the subthreshold region of the baseline 2D FET is above the Boltzmann limit of 60 mV / dec at room temperature. Advantageously, as the TS device is incorporated, the TSS FET returns a significantly reduced SS of 2.2 mV / dec across a wide current transition range.

[0084] Figure 5(d) is the SS distribution comparison of ten devices showing significant SS reduction below the thermionic limit by the TSS FET approach and a correspondingly low variation. The TSS FET fabricated in this invention demonstrates low voltage operation and ultralow SS across a wide ID range without compromising the ON- current density, making it a promising candidate for future low-power electronics.

[0085] Figure 8 seeks to illustrate the operation mechanism of the TSSFET. Figure 8(a) shows the transfer curve of the TSS FET divided into three regions. During a forward sweep of the gate voltage, both the baseline 2D FET and the hBN TS device may be in their OFF-state at negative gate voltage. The overall current may remain low as a result. This corresponds to region I dominated by the current at HRS of the hBN TS device, which suppresses the OFF-state current of the TSS FET.

[0086] As the gate voltage increases to the positive region, the voltage drop across the hBN TS device may increase as the conductance of the baseline 2D FET gradually increases. ID shows abrupt transition approaching the ON-state current of the baseline 2D FET, indicating that hBN TS device may be experiencing a sudden transition to LRS when its voltage drop exceeds its threshold. Figure 8(b) shows Ag conductive filaments which may be formed bridging the Ag top (S') and FLG bottom (S) electrodes.

[0087] As the hBN TS device is highly conductive at LRS, the resistance in the TS device may be much smaller than that of the M0S2 channel. As threshold switching occurs, VDis re-distributed and the voltage drop across the M0S2 channel may undergo instantaneous internal voltage amplification leading to steep increase in ID of the TSS FET with sub-thermionic SS. This may be illustrated in region II of Figure 8(a). After the steep switch occurs, the TSS FET may follow the transfer curve of the baseline 2D FET (with slight deviation) as shown in region III. Region III is dominated by the baseline 2D FET at its ON-state.

[0088] Figure 8(c) shows the transfer characteristics over different values of VDwith steep subthreshold swing. Where steep switching occurs, VTHof the TSS FET may be modulated by changing VD. Figure 8(d) summarises VTHand SS for different VDvalues, indicating that VTHshifts to the negative direction with increasing VD, while SS remains stable.

[0089] A higher VDmay give rise to a higher voltage drop across the hBN TS device and consequently lower I / G (lower M0S2 channel conductance) may be required to induce the steep transition. Increasing VDmay result in a lower or even negative VTHand deterioration of the current switching range, which is attributed to easier formation of filaments. Figure 9 illustrates the transfer curve of the TSS FET when VDis increased to 1 V. This may lead to the switching on of the device at a lower I / G due to a larger voltage drop across the TS device.

[0090] In the first one or more embodiments, wherein the TS device is connected to the source electrode of the baseline FET, the TSSFET device demonstrates an ultralow subthreshold swing down to 2.2 mV / dec and an average subthreshold swing of 7.1 mV / dec across six decades at room temperature. It may take on a value of between about 2.0 mV / dec to about 12.0 mV / dec, or about 4.0 mV / dec to about 10.0 mV / dec, or about 6.0 mV / dec to about 8.0 mV / dec. The TSS device also possesses a high ON- state current and low voltage operation. The threshold voltage of the threshold switching field-effect transistor device can also be modulated by changing the applied drain voltage, due to voltage division between the field-effect transistor and the threshold switching device.

[0091] In the second one or more embodiments, a TS device is connected in series with a gate electrode of a baseline FET (TSGFET). Figure 10(a) shows a top-down schematic of the TSG FET in which a hBN TS device is in series connection to the gate electrode of 2D FET (where the red and green dotted areas represent the baseline 2D FET and the hBN TS device, respectively). Figure 11 illustrates a step-by-step process for the fabrication of the TSG FET. In a particular embodiment, hBN serves as the common dielectric. hBN may have a thickness of 8-13 nm. For electrical characterization of the TSG FET, VDis applied to the drain electrode (D) and the source electrode (S) is grounded. The channel material is modulated by the bottom graphene under the channel as the back gate, which acts as both the internal gate electrode (G') for the baseline 2D FET and the bottom electrode for hBN TS device (Figure 9(b)). The channel material may be a thin layer of M0S2. Electrical characterizations of hBN TS and baseline 2D FET are shown in Figure 10(c) and Figure 12.

[0092] Figure 10(d) shows the FD-I / G characteristic of the TSG FET with steep switching slope. In such an embodiment, the value of I / G was found to vary from 0.5 to -2 V. It is important that I / G does not exceed 0.5 V to ensure the hBN TS device does not enter the LRS at the beginning of the sweep.

[0093] In one particular embodiment, the TSG FET may operate at lower VDsince it does not need to meet the I / SET of the hBN TS device. In one particular embodiment, when the channel material is M0S2, the TSG FET has a relatively high current density level of As M0S2 FETs operate in depletion mode, they have an open channel for free carriers to flow between the source and drain electrodes. The gate electrode does not have effective control over the channel as G and G' are not connected when the TS device is at HRS.

[0094] As I / G sweeps in the negative voltage region, the voltage drop across the hBN TS device increases. The TSG FET may show an abrupt current change at around I / G = - 0.7 V when the voltage drop across TS device reaches its threshold voltage. Such an abrupt change can be observed across over four orders of magnitude in with a low SS of 3.5 mV / dec. (Figure 10(e)). It may take on a value of between about 2.0 mV / dec to about 12.0 mV / dec, or about 4.0 mV / dec to about 10.0 mV / dec, or about 6.0 mV / dec to about 8.0 mV / dec. The TSS device also possesses a high ON-state current and low voltage operation.

[0095] This is attributed to the transition from HRS to LRS by the formation of Ag conductive filament between G and G' (Figure 10(b) and Figure 13). The transition from HRS to LRS may also lead to a dramatic amplification of internal I / G' approaching external I / G abruptly. In one particular embodiment, TSG FET exhibits a greatly reduced SS with an average of 8.2 mV / dec, when compared to the baseline FET. This value is beyond the thermionic limit as shown in Figure 10(f).

[0096] Devices in this particular embodiment tend to face an abrupt transition in the ID characteristics and a lower ON-state current density, as compared to when the TS device is connected in series to the source electrode of the baseline FET. These problems may be greatly improved by optimizing the VTH of the baseline FET or adopting enhancement-mode FET, which may lead to an increase in ON-state current density. This may subsequently improve the current transition range with low SS. As the resistances of hBN in the TS device and hBN as a dielectric in the 2D FET, no external load resistor is required to enable the resistive switching of the TS device.

[0097] In another aspect, the present invention provides a method of fabricating a threshold switching field-effect transistor (TSFET), comprising: forming a field-effect transistor (FET) by sandwiching and contacting a dielectric layer between with a channel (112, 212) and an electrically conductive layer (106, 206); and forming a threshold switching (TS) device adjacent to the FET, the TS comprising a switching layer; wherein the dielectric layer of the FET and the switching layer of the TS device comprises a two-dimensional (2D) van der Waals (vdW) structure (110, 210) and is formed as a first single entity.

[0098] In some embodiments, the method comprises: forming a field-effect transistor (FET), the FET comprising: a channel (112, 212); a two-dimensional (2D) van der Waals (vdW) structure (110, 210); and an electrically conductive layer (106, 206); wherein the 2D vdW structure (110, 210) is sandwiched between and contacted with the channel (112, 212) and the electrically conductive layer (106, 206); and forming a threshold switching (TS) device comprising the 2D vdW structure (110, 210), wherein the 2D vdW structure (110, 210) is configured to function as the dielectric layer of the FET and the switching layer of the TS device. In some embodiments, the method of fabricating a TSFET comprises: a field-effect transistor (FET) comprising: a channel (112, 212); a source electrode (116, 216) and a drain electrode (118, 218) on opposite sides and at a first surface of the channel; a dielectric layer comprising a two-dimensional (2D) van der Waals (vdW) structure (110, 210), the 2D vdW structure contacted to a second surface of the channel; and an electrically conductive layer (106, 206) contacted to the dielectric layer and configured to function as a gate; a threshold switching (TS) device comprising: two electrodes (108, 208, 218) electrically connected to a switching layer, the switching layer comprising the 2D vdW structure (110, 210); wherein the dielectric layer of the FET and the switching layer of the TS device form a first single entity; the method comprising: depositing the electrically conductive layer on a substrate; depositing a first electrode on the substrate, the first electrode spaced apart from the electrically conductive layer; and depositing the 2D vdW structure, the 2D vdW structure at least covering both the electrically conductive layer and the first electrode.

[0099] In some embodiments, the TSFET is fabricated on a substrate by first depositing the electrically conductive layer. The electrically conductive layer may be few-layer graphene. The few-layer graphene may be deposited by mechanical exfoliation from bulk graphite. The dielectric layer may then be deposited on top of the electrically conductive layer. The dielectric layer may be hBN. The hBN layer may be deposited by mechanical exfoliation on the electrically conductive layer.

[0100] When the electrically conductive layer is few-layer graphene, the dielectric layer and the electrically conductive layer form a 2D vdW heterostructure.

[0101] In some embodiments, the method further comprises depositing the channel material on top of the dielectric layer. The channel material may be M0S2. The channel material may be exfoliated and sequentially transferred under a transfer system with an optical microscope to form the MoSz / hBN / FLG stack.

[0102] In some embodiments, the source electrode and the drain electrodes, as well as the pair of electrodes for the TS device, were deposited by e-beam evaporation followed by a lift-off process. The devices were annealed at 300 °C after each step.

[0103] In some embodiments, threshold switching in the TS device is activated by an electroforming process.

[0104] In some embodiments, wherein the devices with the electrode of the TS device connected in series with the source of the FET, the method requires that a photolithography step is carried out, for patterning the electrically conductive layer, prior to deposition of subsequent layers.

[0105] The above method is an example of how the TSFET as described herein may be fabricated. The method is described in more detail below in order to showcase the workings of the TSFET. However, the skilled person would understand that the disclosure is not limited to such and other conventional methods may also be used.

[0106] Having now generally described the invention, the same will be more readily understood through reference to the following examples, which are provided by way of illustration, and are not intended to be limiting.

[0107] Example 1

[0108] Few-layer graphene (FLG) (HQ Graphene) was mechanically exfoliated from bulk graphite and deposited on a 300 nm SiOa / Si substrate. FLG was first patterned by photolithography and etched with O2 plasma using a Vita-Mini RIE system. hBN and M0S2 were exfoliated and then sequentially transferred under transfer system with optical microscope to form MoS2 / hBN / FLG stack. 950K PMMA (MicroChem) resist was spin coated and baked at 180 °C for 2 min. All electrodes were then defined by standard e-beam lithography. Ag / Au (40 / 20 nm) were deposited by e-beam evaporation followed by lift-off process. The samples were annealed at 300 °C after each step.

[0109] Example 2 Few-layer graphene (FLG) was mechanically exfoliated from bulk graphite and deposited on a 300 nm SiOz / Si substrate. No etching is required. hBN and M0S2 were exfoliated and then sequentially transferred under transfer system with optical microscope to form MoS2 / hBN / FLG stack. 950K PMMA resist was spin coated and baked at 180 °C for 2 min. All electrodes were then defined by standard e-beam lithography. Ag / Au (40 / 20 nm) were deposited by e-beam evaporation followed by lift-off process. The samples were annealed at 300 °C after each step.

[0110] Example 3

[0111] The method in Example 1 was repeated, and the layers were characterised as follows.

[0112] Thickness of 2D materials was characterized by AFM Bruker. Raman spectra were measured using a WITec Alpha 300R confocal Raman microscope equipped with a 532 nm laser. The cross-section TEM images were captured by an FEI Titan 80-300 TEM system operating at 200 kV. Samples were prepared by dual beam focused ion beam in FEI Helios Nanolab 450S. High angle annular dark field (HAADF) STEM image and energy-dispersive X-ray spectroscopy (EDS) profiles were conducted by FEI Tecnai F20. The as-fabricated devices were wire-bonded onto chip carrier and loaded in the customized breakout box. Electrical measurements were performed using Agilent B2912A source measure unit in ambient environment.

[0113] Example 4

[0114] The method in Example 2 was repeated, and the layers were characterised as follows.

[0115] Thickness of 2D materials was characterized by AFM Bruker. Raman spectra were measured using a WITec Alpha 300R confocal Raman microscope equipped with a 532 nm laser. The cross-section TEM images were captured by an FEI Titan 80-300 TEM system operating at 200 kV. Samples were prepared by dual beam focused ion beam in FEI Helios Nanolab 450S. High angle annular dark field (HAADF) STEM image and energy-dispersive X-ray spectroscopy (EDS) profiles were conducted by FEI Tecnai F20. The as-fabricated devices were wire-bonded onto chip carrier and loaded in the customized breakout box. Electrical measurements were performed using Agilent B2912A source measure unit in ambient environment.

[0116] It will be appreciated that many further modifications and permutations of various aspects of the described embodiments are possible. Accordingly, the described aspects are intended to embrace all such alterations, modifications, and variations that fall within the spirit and scope of the appended claims.

[0117] Throughout this specification and the claims which follow, unless the context requires otherwise, the word "comprise", and variations such as "comprises" and "comprising", will be understood to imply the inclusion of a stated integer or step or group of integers or steps but not the exclusion of any other integer or step or group of integers or steps.

[0118] Throughout this specification and the claims which follow, unless the context requires otherwise, the phrase "consisting essentially of", and variations such as "consists essentially of" will be understood to indicate that the recited element(s) is / are essential i.e. necessary elements of the invention. The phrase allows for the presence of other non-recited elements which do not materially affect the characteristics of the invention but excludes additional unspecified elements which would affect the basic and novel characteristics of the method defined.

[0119] The reference in this specification to any prior publication (or information derived from it), or to any matter which is known, is not, and should not be taken as an acknowledgment or admission or any form of suggestion that that prior publication (or information derived from it) or known matter forms part of the common general knowledge in the field of endeavour to which this specification relates.

Claims

Claims1. A threshold switching field-effect transistor (TSFET), comprising : a field-effect transistor (FET) comprising: a channel; a dielectric layer comprising a two-dimensional (2D) van der Waals (vdW) structure; and an electrically conductive layer; wherein the dielectric layer is sandwiched between and contacted with the channel and the electrically conductive layer; and a threshold switching (TS) device comprising: a switching layer comprising the 2D vdW structure; wherein the dielectric layer of the FET and the switching layer of the TS device form a first single entity.

2. The TSFET according to claim 1, further comprising a source and a drain on opposite sides and at a first surface of the channel, and wherein the electrically conductive layer is configured to function as a gate.

3. The TSFET according to claim 1 or 2, wherein an electrode of the TS device is connected in series with the source of the FET.

4. The TSFET according to claim 1 or 2, wherein an electrode of the TS device is connected in series with the gate of the FET.

5. The TSFET according to any one of claims 2 to 4, wherein the electrode for the TS device and the source or gate of the FET is formed as a second single entity, the second single entity capable of electrically characterising the TS device and the FET separately.

6. The TSFET according to any one of claims 1 to 5, wherein the TS device comprises two electrodes sandwiching the switching layer.

7. The TSFET according to any one of claims 1 to 6, wherein the TS device comprises an electrode directly connected to the switching layer and another electrode connected to the switching layer via the electrically conductive layer.

8. The TSFET according to any one of claims 1 to 7, wherein the TSFET is characterised by a subthreshold swing of about 2.0 mV / dec to about 12.0 mV / dec.

9. The TSFET according to claim 8, wherein the subthreshold swing remains stable over an operation voltage range of the device.

10. The TSFET according to any one of claims 1 to 9, wherein the 2D vdW structure is selected from hexagonal boron nitride, calcium fluoride, or a combination thereof.

11. The TSFET according to any one of claims 1 to 10, wherein the dielectric layer is characterised by a thickness of between about 5 nm to about 15 nm.

12. The TSFET according to any one of claims 1 to 11, wherein the electrically conductive layer is selected from few-layer graphene, thin metal film, or a combination thereof.

13. The TSFET according to any one of claims 1 to 12, wherein the device is in a high resistance state (HRS) when a voltage bias of less than a predefined threshold voltage is applied, and wherein the device enters a low resistance state (LRS) when the voltage bias is increased above the predefined threshold voltage.

14. The TSFET according to claim 13, wherein the predefined threshold voltage is about 0.8 V to about 1.0 V.

15. A method of fabricating a threshold switching field-effect transistor (TSFET) according to any one of claims 1 to 14, the method comprising: forming a field-effect transistor (FET) by sandwiching and contacting a dielectric layer between with a channel and an electrically conductive layer; and forming a threshold switching (TS) device adjacent to the FET, the TS comprising a switching layer; wherein the dielectric layer of the FET and the switching layer of the TS device comprises a two-dimensional (2D) van der Waals (vdW) structure and is formed as a first single entity.

16. The method according to claim 15, further comprising depositing a source and a drain on top of the channel, wherein the source and the drain are on opposite sides and at a first surface of the channel.

17. The method according to claim 15 or 16, wherein threshold switching is activated by an electroforming process.

18. The method according to any one of claims 15 to 17, wherein the electrically conductive layer is transferred and deposited by mechanical exfoliation.

19. The method according to any one of claims 15 to 18, wherein when an electrode of the TS device is connected in series with the source of the FET, the method further comprises a photolithography step for patterning the electrically conductive layer.

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