Semiconductor structure and method for forming same, and semiconductor device

Abstract

The present disclosure relates to a semiconductor structure and a method for forming same, and a semiconductor device. The semiconductor structure comprises: a stack structure; a semiconductor layer located on the stack structure; a channel structure running through the stack structure and extending into the semiconductor layer; a contact structure extending in the stacking direction of the stack structure; and a first welding structure and a second welding structure, wherein the first welding structure passes through the semiconductor layer to be connected to the contact structure, and the second welding structure is connected to the semiconductor layer.

Description

Semiconductor structure and forming method thereof, and semiconductor device Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same, and a semiconductor device. Background Art

[0002] Three-dimensional memory is an emerging type of flash memory that addresses the limitations of two-dimensional or planar flash memory by vertically stacking multiple layers of data storage cells. 3D memory offers superior precision, enabling higher storage capacity within a smaller footprint, while also offering low cost and power consumption, meeting a wide range of requirements.

[0003] However, three-dimensional memory still faces many challenges.

[0004] Summary of the Invention

[0005] The present disclosure provides a semiconductor structure and a method for forming the same, as well as a semiconductor device, for solving the problem that the semiconductor structure and the process are relatively complex and the process cost is high due to the special requirements of each conductive through-hole structure and each pad on the material.

[0006] To solve the above problems, the technical solution of the present disclosure is implemented as follows:

[0007] The present disclosure provides a semiconductor structure, comprising:

[0008] stacked structure;

[0009] a semiconductor layer, located on the stacked structure;

[0010] a channel structure, penetrating the stacked structure and extending into the semiconductor layer;

[0011] a contact structure extending along a stacking direction of the stacking structure;

[0012] A first welding structure and a second welding structure; wherein the first welding structure penetrates the semiconductor layer and is connected to the contact structure, and the second welding structure is connected to the semiconductor layer.

[0013] In one embodiment of the present disclosure, the first welding structure and the second welding structure both include a first part and a second part located on the first part; wherein, the size of the second part along the first direction is larger than the size of the first part along the first direction, and the first direction is perpendicular to the stacking direction.

[0014] In one embodiment of the present disclosure, the size of the first portion along the first direction is a first size, and the size of the first portion along the stacking direction is a second size; the ratio of the second size to the first size is less than 1:5.

[0015] In one embodiment of the present disclosure, the first portion and the second portion are integrally formed.

[0016] In one embodiment of the present disclosure, a dimension of a portion of the channel structure extending to the semiconductor layer along the stacking direction is less than 200 nm.

[0017] In one embodiment of the present disclosure, a top surface of the semiconductor layer directly above the channel structure is flush with a top surface of the semiconductor layer directly above the stacked structure.

[0018] In one embodiment of the present disclosure, a top surface of the semiconductor layer located directly above the channel structure is higher than a top surface of the semiconductor layer located directly above the stacked structure.

[0019] In one embodiment of the present disclosure, the material of the first welding structure and the material of the second welding structure both include aluminum.

[0020] In one embodiment of the present disclosure, the semiconductor structure further includes:

[0021] The isolation structure is located at least between the first welding structure and the semiconductor layer.

[0022] In one embodiment of the present disclosure, the stacking structure includes alternating first material layers and insulating layers, the stacking structure includes a third part and a fourth part arranged in parallel along a direction perpendicular to the stacking direction, the contact structure passes through the third part, the channel structure passes through the fourth part, the first material layer in the third part includes a sacrificial layer, and the first material layer in the fourth part includes a conductive layer.

[0023] In one embodiment of the present disclosure, the channel structure includes a functional layer and a channel layer, the functional layer is located in the stacked structure, the channel layer is located in the stacked structure and extends into the semiconductor layer, and the functional layer covers the sidewall of the channel layer located in the stacked structure.

[0024] To solve the above technical problems, the present disclosure further provides a semiconductor device, comprising a first semiconductor structure and the semiconductor structure according to any of the above embodiments;

[0025] The first semiconductor structure is located on one side of the semiconductor structure that is opposite to each other along the stacking direction and is far away from the semiconductor layer. The first semiconductor structure is connected to the semiconductor structure through hybrid bonding.

[0026] In one embodiment of the present disclosure, the first semiconductor structure includes:

[0027] A peripheral circuit is connected to the contact structure in the semiconductor structure.

[0028] To solve the above technical problems, the present disclosure further proposes a method for forming a semiconductor structure, comprising:

[0029] Providing a stacking structure, a contact structure, and a channel structure, wherein the channel structure penetrates the stacking structure and protrudes from the stacking structure, and the contact structure extends along a stacking direction of the stacking structure;

[0030] forming a semiconductor layer on the stack structure and the channel structure from a side of the channel structure protruding from the stack structure;

[0031] A first welding structure and a second welding structure are formed, wherein the first welding structure penetrates the semiconductor layer and is connected to the contact structure, and the second welding structure is connected to the semiconductor layer.

[0032] In one embodiment of the present disclosure, forming a semiconductor layer on the stacked structure and the channel structure includes:

[0033] Semiconductor material layers are formed on the stacked structure, the channel structure, and the contact structure; the top surfaces of the semiconductor material layers directly above the channel structure and the contact structure are higher than the top surface of the semiconductor material layer directly above the stacked structure; a portion of the semiconductor material layer is removed to form a first opening and expose the contact structure, and the remaining semiconductor material layer forms the semiconductor layer.

[0034] In one embodiment of the present disclosure, the forming of a semiconductor layer on the stacked structure and the channel structure further includes:

[0035] Before forming the first opening, the semiconductor material layer is planarized so that the top surface of the semiconductor material layer directly above the channel structure is flush with the top surface of the semiconductor material layer directly above the stacked structure.

[0036] In one embodiment of the present disclosure, the method further includes: forming an isolation layer covering the sidewalls and bottom wall of the first opening and the semiconductor layer;

[0037] At least the isolation layer on the bottom wall of the first opening is removed to expose the contact structure; and part of the isolation layer on the semiconductor layer is removed to form a second opening, wherein the second opening exposes the semiconductor layer; the remaining isolation layer forms an isolation structure.

[0038] In one embodiment of the present disclosure, forming the first welding structure and the second welding structure includes:

[0039] After forming the isolation structure, the first welding structure is formed at least in the first opening, and the second welding structure is formed at least in the second opening, wherein the first welding structure and the second welding structure each include a first portion and a second portion located on the first portion, the first portion of the first welding structure is located in the first opening, and the second portion of the second welding structure is located in the second opening.

[0040] In one embodiment of the present disclosure, providing a stack structure, a contact structure, and a channel structure includes:

[0041] forming a stacking structure, a contact structure, and a channel structure on a base structure; the base structure includes a substrate and a first semiconductor layer between the substrate and the stacking structure, and the channel structure extends into the first semiconductor layer; or the base structure includes a substrate, and the channel structure extends into the substrate;

[0042] The base structure is removed to expose a portion of the channel structure.

[0043] In one embodiment of the present disclosure, the channel structure includes a channel layer and a functional layer surrounding the channel layer. After removing the base structure, a portion of the functional layer is exposed. The method further includes:

[0044] After removing the base structure, the exposed functional layer is removed to expose a portion of the channel layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to make the above-mentioned objects, features and advantages of the present disclosure more clearly understood, the specific embodiments of the present disclosure are described in detail below with reference to the accompanying drawings, wherein:

[0046] FIG1 is a schematic diagram of a semiconductor structure in some embodiments;

[0047] FIG2A is a first schematic diagram of a semiconductor structure along the AA′ and BB′ cross sections provided by an embodiment of the present disclosure;

[0048] FIG2B is a schematic top view of a semiconductor structure provided by an embodiment of the present disclosure;

[0049] 3A and 3B are schematic structural diagrams of a first part and a second part provided in an embodiment of the present disclosure;

[0050] FIG4 is a second schematic diagram of a semiconductor structure along the AA′ and BB′ cross sections provided by an embodiment of the present disclosure;

[0051] FIG5 is a third schematic diagram of a semiconductor structure along the AA′ and BB′ cross sections provided by an embodiment of the present disclosure;

[0052] FIG6 is a schematic flow chart of a method for forming a semiconductor structure according to an embodiment of the present disclosure;

[0053] 7 to 21 are schematic diagrams of a semiconductor structure forming process along cross sections AA' and BB' according to an embodiment of the present disclosure;

[0054] 22 and 23 are schematic diagrams of the semiconductor device forming process along the AA′ cross section and the BB′ cross section according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0055] In order to make the above-mentioned objects, features and advantages of the present disclosure more obvious and easy to understand, the specific embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0056] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure. However, the present disclosure may also be implemented in other ways different from those described herein. Therefore, the present disclosure is not limited to the specific embodiments disclosed below.

[0057] As used in this application and the claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" are not intended to refer to the singular but may include the plural. Generally speaking, the terms "comprises" and "include" only indicate the inclusion of the steps and elements specifically identified, and these steps and elements do not constitute an exclusive list. A method or apparatus may also include other steps or elements.

[0058] When describing the embodiments of the present disclosure, for ease of explanation, cross-sectional views of device structures may be partially enlarged and not to scale. Furthermore, these schematic views are merely illustrative and should not limit the scope of protection of the present disclosure. Furthermore, in actual production, three-dimensional dimensions, including length, width, and depth, should be included.

[0059] For ease of description, spatial relational terms such as "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatial relational terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. For example, if the device in the drawings is flipped, the orientation of the element described as "below" or "below" or "below" other elements or features will be changed to "above" the other elements or features. Thus, the exemplary terms "below" and "below" can encompass both the up and down directions. The device may also have other orientations (rotated 90 degrees or in other orientations), so the spatial relational descriptors used herein should be interpreted accordingly. In addition, it will be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can be one or more intervening layers.

[0060] In the context of the present application, a description of a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first and second features, such that the first and second features may not be in direct contact.

[0061] In addition, it should be noted that the use of terms such as "first" and "second" to limit components is only for the convenience of distinguishing the corresponding components. Unless otherwise stated, the above terms have no special meaning and therefore cannot be understood as limiting the scope of protection of this application.

[0062] As used herein, the term "three-dimensional memory" refers to a semiconductor device having a vertically oriented string of memory cell transistors (referred to herein as a "memory string," such as a NAND string) on ​​a laterally oriented substrate, such that the memory string extends in a vertical direction relative to the substrate. As used herein, the term "vertical" refers to being nominally perpendicular to a lateral surface of the substrate.

[0063] As used herein, the term "substrate" refers to the material onto which subsequent material layers are added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate can include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0064] The term "layer" as used in this application refers to a portion of a material including an area having a thickness. A layer may extend over the entire underlying or superstructure, or may have an extent that is less than the extent of the underlying or superstructure. In addition, a layer may be an area of ​​a uniform or non-uniform continuous structure having a thickness that is less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes thereat. A layer may extend horizontally, vertically and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers thereon, above and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (with contacts, interconnects and / or vias formed therein) and one or more dielectric layers.

[0065] Flowcharts are used in this application to illustrate the operations performed by systems according to embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed in exact order. Instead, the various steps may be processed in reverse order or simultaneously. Furthermore, other operations may be added to these processes, or one or more operations may be removed from these processes.

[0066] In some embodiments, as shown in FIG1 , the channel structure of the semiconductor structure includes a functional layer and a channel layer, wherein the functional layer covers a portion of the sidewalls of the channel layer. In some embodiments, during the formation of the channel structure, the depth of the channel structure extending beyond the stacked structure is difficult to control within a small range, resulting in the channel layer not covered by the functional layer having a relatively high height along the Z direction. The semiconductor structure also includes a contact structure and a gate line slit structure (GLS). The tops of the channel structure and the gate line slit structure are further covered by a semiconductor layer, which is further covered by an isolation layer. When the top height of the contact structure and the top height of the semiconductor layer at the top of the gate line slit structure are both much lower than the top height of the isolation layer, in order to lead the contact structure and the channel structure out, a first conductive via structure can be provided that penetrates the isolation layer and connects to the contact structure, as well as a second conductive via structure that penetrates the isolation layer and connects to the semiconductor layer at the top of the gate line slit structure, and / or a third conductive via structure that penetrates the isolation layer and connects to the semiconductor layer at the top of the channel structure. It should be noted that the aforementioned top refers to the highest point of the semiconductor structure in the Z direction. Furthermore, a first pad may be provided above the first conductive via structure, a second pad may be provided above the second conductive via structure, and a third pad may be provided above the third conductive via structure.

[0067] It can be understood that, since the functional layer not covered by the channel layer in the above-mentioned semiconductor structure has a relatively high height along the Z direction, the thickness of the isolation layer in the Z direction is relatively thick, which further causes the above-mentioned conductive through-hole structures to have a relatively high aspect ratio. In addition, the above-mentioned conductive through-hole structure is filled with conductive material. Since the step coverage of aluminum is relatively poor, it is not suitable for the case where the conductive through-hole structure in Figure 1 has a high aspect ratio. For filling through-holes with a high aspect ratio, metal tungsten can be considered, but the cost of metal tungsten is relatively high. In addition, since each pad can also be used in the testing stage, it is necessary to select a metal material that is not easily deformed. The material used for each pad can be metal aluminum. Due to the special requirements of each conductive through-hole structure and each pad on the material in the above-mentioned semiconductor structure, the semiconductor structure and the process are relatively complex and the process cost is relatively high.

[0068] To solve one or more of the above problems, referring to FIG. 2A and FIG. 2B , an embodiment of the present disclosure provides a semiconductor structure, including:

[0069] Stacked structure 100; semiconductor layer 110, located on stacked structure 100; channel structure 210, penetrating stacked structure 100 along the Z direction and extending into semiconductor layer 110; contact structure 220, extending along the stacking direction (i.e., Z direction) of stacked structure 100; FIG2A is a schematic cross-sectional view of the semiconductor structure provided by the present disclosure along the AA' and BB' lines shown in FIG2B, and FIG2B is a schematic top view of the semiconductor structure provided by the present disclosure. The number of channel structures 210, contact structures 220, and gate line gap structures 230 in FIG2B and FIG2A is only an example and does not correspond to each other. FIG2B also includes a contact area, which includes a plurality of word line contact structures 221. The word line contact structures 221 are used to lead out word lines in the stacked structure 100. FIG2B also includes a first welding structure 310 and a second welding structure 320. The first welding structure 310 is used to lead out the contact structure 220, and the second welding structure 320 is used to lead out the channel structure 210.

[0070] In some embodiments, the channel structure 210 includes a functional layer and a channel layer. The functional layer is located in the stacked structure 100. The channel layer is located in the stacked structure 100 and extends into the semiconductor layer 110. The functional layer covers the sidewalls of the channel layer located in the stacked structure 100. The channel layer extending into the semiconductor layer 110 is not covered by the functional layer. Furthermore, the height of the channel layer extending into the semiconductor layer 110 in the Z direction is less than a first predetermined value.

[0071] In some embodiments, the functional layer includes a barrier layer, a capture layer, and a tunnel layer. The material of the channel layer includes but is not limited to polysilicon.

[0072] In some embodiments, the dimension of the portion of the channel structure 210 extending into the semiconductor layer 110 along the stacking direction is less than 200 nm, that is, the first preset value is 200 nm.

[0073] It should be noted that the first preset value given in the above embodiment is only an exemplary demonstration and is not used to limit the specific value of the first preset value in the embodiment of the present disclosure.

[0074] The semiconductor structure shown in FIG2A further includes a first welding structure 310 and a second welding structure 320. The first welding structure 310 penetrates the semiconductor layer 110 and connects to the contact structure 220, while the second welding structure 320 connects to the semiconductor layer 110. The first welding structure 310 is used to lead out the contact structure 220, while the second welding structure 320 is used to lead out the channel structure 210. It should be noted that the second welding structure 320 does not directly lead out the channel structure 210, but rather indirectly leads out the channel structure 210 through the semiconductor layer 110.

[0075] In some specific examples, the material of the semiconductor layer 110 includes, but is not limited to, polysilicon. The semiconductor layer 110 can be used as a source layer.

[0076] It can be understood that in the embodiment of the present disclosure, based on the fact that the size of the portion of the channel structure 210 extending to the semiconductor layer 110 along the stacking direction is small and the size of the semiconductor layer 110 along the stacking direction is also correspondingly small, the first welding structure 310 is directly in contact with the contact structure 220, and the second welding structure 320 is directly in contact with the semiconductor layer 110. In other words, the contact structure 220 and the channel structure 210 are directly led out through the second welding structure 320 and the first welding structure 310, without having to additionally form a tungsten-filled contact structure between the first welding structure 310 and the contact structure 220 and between the second welding structure 320 and the semiconductor layer 110. This simplifies the semiconductor structure and saves corresponding process steps, thereby reducing process costs.

[0077] In some embodiments, the material of the first welding structure 310 and the material of the second welding structure 320 may both include aluminum, but the materials of the first welding structure 310 and the second welding structure 320 are not limited thereto.

[0078] In some embodiments, as shown in Figures 3A and 3B, the first welding structure 310 and the second welding structure 320 both include a first part 301 and a second part 302 located on the first part 301; wherein the size of the second part 302 along the first direction (i.e., the X direction) is larger than the size of the first part 301 along the first direction, and the first direction is perpendicular to the stacking direction (i.e., the Z direction).

[0079] In some embodiments, the size of the first portion 301 along the first direction is a first size, and the size of the first portion 301 along the stacking direction is a second size; the ratio of the second size to the first size is less than 1:5.

[0080] It should be noted that, as shown in FIG3A , first portion 301 may be an inverted trapezoid. For an inverted trapezoid, the first dimension taken at different heights along the Z direction is different. Here, the first dimension may be the minimum dimension of the inverted trapezoid along the X direction, that is, the dimension of the bottom of first portion 301 along the X direction in FIG3A . In some embodiments, as shown in FIG3B , first portion 301 may be a rectangle. The first dimension taken at different heights along the Z direction is the same. The first dimension may be the dimension of the rectangle along the X direction at any height in the Z direction.

[0081] In some embodiments, the first portion 301 and the second portion 302 are integrally formed, thereby simplifying the process flow, saving process time and cost, and reducing the complexity of the lead process.

[0082] In the embodiment of the present disclosure, the conductive material used for the first part 301 and the second part 302 is the same material, including but not limited to aluminum.

[0083] In some embodiments, as shown in FIG. 4 , a top surface of the semiconductor layer 110 located directly above the channel structure 210 is higher than a top surface of the semiconductor layer 110 located directly above the stacked structure 100 .

[0084] In the embodiment of the present disclosure, the top surface of the semiconductor layer 110 is irregular and is related to the profile of the portion of the channel structure 210 protruding from the stacked structure 100 .

[0085] Specifically, the semiconductor layer 110 can be formed by depositing semiconductor materials on the side walls and top surfaces of the stacking structure 100 and the channel structure 210 through a deposition process / epitaxial growth process to form a semiconductor layer 110 with an irregular upper surface morphology. The semiconductor layer 110 with an irregular upper surface morphology has the same thickness in the Z direction. Since the channel structure 210 protrudes from the stacking structure 100, the top surface of the semiconductor layer 110 located directly above the channel structure 210 is higher than the top surface of the semiconductor layer 110 located directly above the stacking structure 100.

[0086] In some embodiments, as shown in FIG4 , the semiconductor structure further includes a gate line slit structure 230, which penetrates the stacked structure 100 and extends into the semiconductor layer 110. It will be appreciated that the top surface of the semiconductor layer 110 directly above the gate line slit structure 230 is also higher than the top surface of the semiconductor layer 110 directly above the stacked structure 100.

[0087] In some specific examples, the material of the gate line gap structure 230 can be one or more of dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, and semiconductor materials such as polysilicon.

[0088] In some embodiments, as shown in FIG. 2A , a top surface of the semiconductor layer 110 directly above the channel structure 210 is flush with a top surface of the semiconductor layer 110 directly above the stacked structure 100 .

[0089] Specifically, in the corresponding formation process, the semiconductor layer 110 with an irregular upper surface morphology as shown in FIG4 can be formed first, and then the top surface of the semiconductor layer 110 with an irregular upper surface morphology is smoothed by chemical mechanical polishing (CMP), and finally the semiconductor layer 110 with a flat surface in the X direction as shown in FIG2A is formed.

[0090] In some embodiments, as shown in FIG2A , a stacked structure 100 includes alternating first material layers 101 and insulating layers 102. The stacked structure 100 includes a third portion 100 b (e.g., a contact region) and a fourth portion 100 a (e.g., an array region) arranged side by side in a direction perpendicular to the stacking direction. A contact structure 220 extends through the third portion 100 b, and a channel structure 210 extends through the fourth portion 100 a. The first material layer 101 in the third portion 100 b includes a sacrificial layer, and the first material layer 101 in the fourth portion 100 a includes a conductive layer.

[0091] In the embodiment of the present disclosure, the conductive layer in the fourth portion 100a can be replaced by a sacrificial layer. During the replacement process, the sacrificial layer in the third portion 100b will not be replaced. The contact structure 220 in the third portion 100b can provide support for the stacked structure 100 during the replacement process.

[0092] In some specific examples, the material used for the conductive layer may include one or more conductive materials such as tungsten, cobalt, copper, aluminum, and metal silicide. The material used for the sacrificial layer may include, but is not limited to, silicon nitride. The material used for the insulating layer 102 may include, but is not limited to, silicon oxide.

[0093] In some embodiments, as shown in FIG. 2A , the semiconductor structure further includes:

[0094] The isolation structure 120 is at least located between the first welding structure 310 and the semiconductor layer 110 .

[0095] In the embodiment of the present disclosure, the isolation structure 120 is used to isolate the first welding structure 310 from the semiconductor layer 110, so that the first welding structure 310 and the second welding structure 320 can respectively lead out the contact structure 220 and the channel structure 210. In some specific examples, the material of the isolation structure 120 includes but is not limited to silicon oxide.

[0096] An embodiment of the present disclosure provides a semiconductor device, as shown in FIG5 , comprising a first semiconductor structure 400 and a semiconductor structure according to any of the above embodiments;

[0097] The first semiconductor structure 400 is located on one side of the semiconductor structure that is opposite to each other along the stacking direction and is farther from the semiconductor layer 110 . The first semiconductor structure 400 is connected to the semiconductor structure by hybrid bonding.

[0098] In some embodiments, the first semiconductor structure 400 includes:

[0099] The peripheral circuit is connected to the contact structure 220 in the semiconductor structure.

[0100] In some embodiments, the semiconductor structure includes a first bonding layer, which is located on one of two opposite sides of the semiconductor structure along the Z direction and farther from the semiconductor layer 110. The first semiconductor structure 400 also includes a second bonding layer. The first bonding layer and the second bonding layer can be bonded using a hybrid bonding process.

[0101] In some embodiments, the first semiconductor structure 400 can be bonded to the semiconductor structure provided by the embodiment of the present disclosure through fusion bonding and direct wafer bonding processes, and after the bonding is completed, the side of the substrate away from the stacked structure 100 faces upward.

[0102] It should be noted that the embodiment of the present disclosure takes the example of bonding the storage array wafer including the stacking structure 100 to the first semiconductor structure 400 including the peripheral circuit, and then performing the subsequent back side lead-out process from the side of the substrate away from the stacking structure 100. In other embodiments, after performing the back side lead-out process, the storage array wafer may be bonded to the first semiconductor structure 400 including the peripheral circuit, or only the storage array wafer may be formed and the back side lead-out process may be performed on the storage array wafer.

[0103] In some specific examples, as shown in FIG5 , the contact structure 220 can be connected to the peripheral circuit in the first semiconductor structure 400 through the interconnect structure in the interconnect layer 410. The peripheral circuit may include CMOS (Complementary Metal Oxide Semiconductor) and MOS (Metal Oxide Semiconductor) devices. The CMOS devices and MOS devices in the peripheral circuit can be electrically connected through the interconnect structure, the contact structure 220, and the first welding structure 310. The first welding structure 310 can be used to receive a first voltage and transmit the first voltage to the peripheral circuit through the contact structure 220. The second welding structure 320 can be used to receive a second voltage, and the semiconductor layer 110 is used to receive the second voltage and provide it as a source voltage to the multiple channel structures 210. The isolation structure 120 located between the first welding structure 310 and the semiconductor layer 110 prevents the first welding structure 310 and the second welding structure 320 from interfering with each other.

[0104] An embodiment of the present disclosure provides a method for forming a semiconductor structure. FIG6 is a flow chart of the method for forming a semiconductor structure provided by an embodiment of the present disclosure. As shown in FIG6 , the method for forming a semiconductor structure includes:

[0105] Step S10: providing a stacking structure, a contact structure, and a channel structure, wherein the channel structure penetrates the stacking structure and protrudes from the stacking structure, and the contact structure extends along a stacking direction of the stacking structure;

[0106] Step S20: forming a semiconductor layer on the stack structure and the channel structure from a side of the channel structure protruding from the stack structure;

[0107] Step S30 : forming a first welding structure and a second welding structure, wherein the first welding structure penetrates the semiconductor layer and is connected to the contact structure, and the second welding structure is connected to the semiconductor layer.

[0108] 7 to 19 are schematic structural diagrams of a semiconductor structure forming process according to an embodiment of the present disclosure. Below, the method for forming the semiconductor structure according to an embodiment of the present disclosure will be described in detail in conjunction with FIG. 6 to 19 .

[0109] 7 , step S10 is performed to provide a stack structure 100 , a contact structure 220 , and a channel structure 210 . The channel structure 210 penetrates the stack structure 100 and protrudes from the stack structure 100 . The contact structure 220 extends along the stacking direction of the stack structure 100 .

[0110] In some embodiments, the stacked structure 100 includes a third portion 100b (e.g., a contact region) and a fourth portion 100a (e.g., an array region) arranged side by side in a direction perpendicular to the stacking direction. The third portion 100b includes a sacrificial layer 101b and an insulating layer 102 arranged sequentially along the Z direction. The fourth portion 100a includes a conductive layer 101a and an insulating layer 102 arranged sequentially along the Z direction.

[0111] In some specific examples, a base structure may be provided, which may include a first region and a second region arranged side by side along the X-direction. The process of forming the stacked structure 100 includes: first, forming an insulating layer 102 and a sacrificial layer 101b alternately stacked along the Z-direction on both the first and second regions through a deposition process; after forming a gate line slit (GLS), removing the sacrificial layer 101b on the second region while retaining the sacrificial layer 101b on the first region; and depositing a conductive layer 101a on the second region at the location where the sacrificial layer 101b was removed. This forms the third portion 100b of the stacked structure 100 on the first region, and the fourth portion 100a of the stacked structure 100 on the second region. In some specific examples, the method further includes filling the gate line slit to form a gate line slit structure 230.

[0112] 7 is merely an example, and the present disclosure does not limit the specific number of sacrificial layers 101b, insulating layers 102, and conductive layers 101a. It is understood that the number of sacrificial layers 101b is the same as the number of conductive layers 101a.

[0113] In the embodiments of the present disclosure, the deposition process includes but is not limited to chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD) and atomic layer deposition (ALD).

[0114] In the disclosed embodiment, the channel structure 210 includes a functional layer and a channel layer, with the functional layer covering portions of the channel layer's sidewalls. Furthermore, the top surface of the functional layer is flush with the top surface of the stacked structure 100, while the channel layer protrudes from the top surface of the stacked structure 100. The channel structure 210 can be formed by etching an initial channel structure, which includes an initial functional layer and the channel layer, with the initial functional layer covering the channel layer's sidewalls and top. The portion of the initial functional layer that protrudes above the stacked structure 100 is removed to form the functional layer.

[0115] In the embodiment of the present disclosure, the material of the contact structure 220 may be one or more of conductive materials such as tungsten, cobalt, copper, aluminum, and metal silicide.

[0116] The present disclosure provides various embodiments for forming the semiconductor layer, the first welding structure, and the second welding structure. Figures 8 to 13 are schematic diagrams illustrating a process for forming the semiconductor layer, the first welding structure, and the second welding structure. Below, the method for forming the semiconductor layer, the first welding structure, and the second welding structure according to one embodiment of the present disclosure will be described in detail with reference to Figures 6 and 8 to 13.

[0117] 8 and 9 , step S20 is performed to form a semiconductor layer 110 on the stacked structure 100 and the channel structure 210 from a side of the channel structure 210 protruding from the stacked structure 100. The material of the semiconductor layer 110 includes at least one of the following: polysilicon, polycrystalline germanium, or polycrystalline silicon germanium.

[0118] In some embodiments, referring to FIG. 8 and FIG. 9 , forming a semiconductor layer 110 on the stacked structure 100 and the channel structure 210 includes:

[0119] A semiconductor material layer 111 as shown in FIG8 is formed on the stacked structure 100, the channel structure 210, and the contact structure 220 through a deposition process. The upper surface of the semiconductor material layer 111 has different concave and convex shapes. The semiconductor material layer 111 can be conformally formed according to the channel structure 210 and the contact structure 220, so the thickness of the semiconductor material layer 111 in the Z direction is the same. Because the channel structure 210 and the contact structure 220 protrude from the stacked structure 100, the top surface of the semiconductor material layer 111 located directly above the channel structure 210 and the contact structure 220 is higher than the top surface of the semiconductor material layer 111 located directly above the stacked structure 100. A portion of the semiconductor material layer 111 is removed, and this portion of the semiconductor material layer 111 located above the contact structure 220 is removed. In some embodiments, at least the portion of the contact structure 220 that is higher than the top surface of the stacked structure 100 can also be removed to form a first opening 501 and expose the contact structure 220. The remaining semiconductor material layer 111 forms the semiconductor layer 110 shown in FIG9.

[0120] 10 , step S30 is performed to form a first welding structure 310 and a second welding structure 320 . The first welding structure 310 penetrates the semiconductor layer 110 and is connected to the contact structure 220 . The second welding structure 320 is connected to the semiconductor layer 110 .

[0121] The first welding structure 310 is used to lead out the contact structure 220, and the second welding structure 320 is used to lead out the channel structure 210. The conductive material used for the first welding structure 310 and the second welding structure 320 includes, but is not limited to, aluminum.

[0122] In the embodiment of the present disclosure, a welding layer can be first formed on the semiconductor layer 110, and then the welding layer is subjected to photolithography and etching processes to form the first welding structure 310 and the second welding structure 320. It should be noted that the number of the first welding structure 310 and the second welding structure 320 in Figure 10 is only an example, and the present disclosure does not limit the specific number of the first welding structure 310 and the second welding structure 320.

[0123] 11 to 13 , the method further includes forming an isolation layer 121 by a deposition process, as shown in FIG11 , to cover the sidewalls and bottom wall of the first opening 501 and the semiconductor layer 110; the isolation layer 121 completely covers the semiconductor layer 110. Materials used for the isolation layer 121 include, but are not limited to, silicon oxide.

[0124] An etching process is used to remove at least the isolation layer 121 on the bottom wall of the first opening 501 to expose the contact structure 220; and a portion of the isolation layer 121 on the semiconductor layer 110 is removed to form a second opening 502, which exposes the semiconductor layer 110; the remaining isolation layer 121 forms the isolation structure 120 shown in Figure 12.

[0125] It should be noted that the number of the first openings 501 and the second openings 502 in FIG. 12 is only an example, and the present disclosure does not limit the specific number of the first openings 501 and the second openings 502 .

[0126] In some embodiments, referring to FIG. 12 and FIG. 13 , forming a first welding structure 310 and a second welding structure 320 includes:

[0127] After forming the isolation structure 120, a first welding structure 310 is formed at least in the first opening 501 using a deposition process, and a second welding structure 320 is formed at least in the second opening 502 using a deposition process. The top surfaces of the first welding structure 310 and the second welding structure 320 are both higher than the top surface of the isolation structure 120. The first welding structure 310 and the second welding structure 320 each include a first portion 301 and a second portion 302 located on the first portion 301. The first portion 301 of the first welding structure 310 is located in the first opening 501, and the first portion 301 of the second welding structure 320 is located in the second opening 502.

[0128] In the embodiment of the present disclosure, the first part 301 and the second part 302 may be formed by an integral molding method.

[0129] It is understandable that in the above embodiment, after forming the semiconductor material layer 111 , no planarization process is performed, and the opening 501 is directly formed and the semiconductor layer 110 is formed, which can save process flow and process time.

[0130] Figures 14 to 19 are another schematic diagram of the process of forming the semiconductor layer, the first welding structure, and the second welding structure provided by the present disclosure. Below, the method of forming the semiconductor layer, the first welding structure, and the second welding structure provided by the embodiment of the present disclosure will be described in detail in conjunction with Figures 6, 14 to 19.

[0131] 14 to 16 , step S20 is performed to form a semiconductor layer 110 on the stack structure 100 and the channel structure 210 from a side of the channel structure 210 protruding from the stack structure 100 .

[0132] In some embodiments, referring to FIG. 14 to FIG. 16 , a semiconductor layer 110 is formed on the stacked structure 100 and the channel structure 210 , further comprising:

[0133] Before forming the first opening 501, the semiconductor material layer 111 shown in Figure 14 is planarized. After the planarization, as shown in Figure 15, the top surface of the semiconductor material layer 111 located directly above the channel structure 210 is flush with the top surface of the semiconductor material layer 111 located directly above the stacked structure 100.

[0134] Part of the semiconductor material layer 111 in FIG. 15 , which is located above the contact structure 220 , is removed, ultimately forming a first opening 501 and exposing the contact structure 220 . The remaining semiconductor material layer 111 forms the semiconductor layer 110 shown in FIG. 16 .

[0135] In the embodiment of the present disclosure, a semiconductor material layer 111 can be formed by a deposition process, and then the semiconductor material layer 111 is etched to form a semiconductor layer 110. Finally, the semiconductor layer 110 is laser crystallized to form a laser crystallized semiconductor layer 110, for example, to form laser crystallized polysilicon.

[0136] In some embodiments, the semiconductor material layer 111 may be laser crystallized to form a laser crystallized semiconductor material layer 111 , and then the laser crystallized semiconductor material layer 111 may be etched to form a laser crystallized semiconductor layer 110 .

[0137] 19 , step S30 is performed to form a first welding structure 310 and a second welding structure 320 . The first welding structure 310 penetrates the semiconductor layer 110 and is connected to the contact structure 220 , and the second welding structure 320 is connected to the semiconductor layer 110 .

[0138] The first welding structure 310 is used to lead out the contact structure 220, and the second welding structure 320 is used to lead out the channel structure 210. The conductive material used for the first welding structure 310 and the second welding structure 320 includes, but is not limited to, aluminum.

[0139] 17 to 19 , the method further includes forming an isolation layer 121 by a deposition process, as shown in FIG17 , to cover the sidewalls and bottom wall of the first opening 501 and the semiconductor layer 110; the isolation layer 121 completely covers the semiconductor layer 110. Materials used for the isolation layer 121 include, but are not limited to, silicon oxide.

[0140] An etching process is used to remove at least the isolation layer 121 on the bottom wall of the first opening 501 to expose the contact structure 220; and a portion of the isolation layer 121 on the semiconductor layer 110 is removed to form a second opening 502, which exposes the semiconductor layer 110; the remaining isolation layer 121 forms the isolation structure 120 shown in Figure 18.

[0141] It should be noted that the number of the first openings 501 and the second openings 502 in FIG. 18 is only an example, and the present disclosure does not limit the specific number of the first openings 501 and the second openings 502 .

[0142] In some embodiments, referring to FIG. 19 , forming a first welding structure 310 and a second welding structure 320 includes:

[0143] After forming the isolation structure 120, a first welding structure 310 is formed at least in the first opening 501 using a deposition process, and a second welding structure 320 is formed at least in the second opening 502 using a deposition process. The top surfaces of the first welding structure 310 and the second welding structure 320 are both higher than the top surface of the isolation structure 120. The first welding structure 310 and the second welding structure 320 each include a first portion 301 and a second portion 302 located on the first portion 301. The first portion 301 of the first welding structure 310 is located in the first opening 501, and the first portion 301 of the second welding structure 320 is located in the second opening 502.

[0144] The first welding structure 310 and the second welding structure 320 can be used for testing and can also be used to connect to other external components or other semiconductor structures. In some embodiments, the size of the second part 302 along the X direction is larger than the size of the first part 301 along the X direction, which can increase the contact area with other components and reduce the occurrence of poor contact between other components and the above-mentioned welding structure.

[0145] In the embodiment of the present disclosure, the first portion 301 and the second portion 302 are integrally formed. A deposition process can be used to form a welding layer covering the isolation structure 120 on the isolation structure 120 , and then the welding layer is grooved to form the first welding structure 310 and the second welding structure 320 .

[0146] In the disclosed embodiment, the conductive material used for the first welding structure 310 and the second welding structure 320 can both be aluminum. The first welding structure 310 and the second welding structure 320 can be formed through a single deposition process, saving process costs. The first welding structure 310 and the second welding structure 320 can be used to lead out the contact structure 220 and the channel structure 210, respectively, avoiding the use of high-aspect-ratio conductive through-hole structures to lead out the contact structure 220 and the channel structure 210. Etching to form high-aspect-ratio through-holes is not only difficult, but also further limits the type of conductive material that can be filled in the through-holes.

[0147] In some embodiments, a stack structure 100 , a contact structure 220 , and a channel structure 210 are provided, including:

[0148] 20 and 21 , a stacked structure 100, a contact structure 220, and a channel structure 210 are formed on a base structure 600. The base structure 600 includes a substrate 610 and a first semiconductor layer 620 between the substrate 610 and the stacked structure 100. The channel structure 210 extends into the first semiconductor layer 620. Alternatively, the base structure 600 includes a substrate 610, and the channel structure 210 extends into the substrate 610.

[0149] The base structure 600 is removed to expose a portion of the channel structure 210 .

[0150] 20 , the base structure 600 may include a substrate 610 and a first semiconductor layer 620 . The channel structure 210 extends into the first semiconductor layer 620 .

[0151] 21 , the base structure 600 may include a substrate 610 . The channel structure 210 extends into the substrate 610 .

[0152] The substrate 610 may be a single semiconductor material substrate (eg, a silicon substrate, a germanium substrate, etc.), a compound semiconductor material substrate (eg, a germanium silicon substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc.

[0153] The material used for the first semiconductor layer 620 includes, but is not limited to, polysilicon, polycrystalline germanium, and polycrystalline silicon germanium.

[0154] The embodiment of the present disclosure further provides a method for forming a semiconductor device, which will be further described below with reference to FIG. 22 and FIG. 23 .

[0155] In some embodiments, a first semiconductor structure 400 as shown in FIG. 22 may be provided, the first semiconductor structure 400 including a peripheral circuit (not shown in FIG. 22 ), and then the first semiconductor structure 400 may be bonded to a side of the structure shown in FIG. 20 or FIG. 21 away from the base structure 600 along the Z direction, as shown in FIG. 22 , so that the base structure 600 faces upward, and then the substrate 610 and the first isolation layer between the substrate 610 and the first semiconductor layer 620 in FIG. 20 are removed by an etching process, or the substrate 610 in FIG. 21 is removed by an etching process to form the structure shown in FIG. 23 , and then the first semiconductor layer 620 in FIG. 23 is further removed, and then the semiconductor layer, the first contact structure, and the second contact structure are formed using the above-mentioned method for forming a semiconductor structure, thereby forming a semiconductor device. It should be noted that FIG. 7 to FIG. 21 may also include a first semiconductor structure (not shown).

[0156] In other embodiments, the semiconductor layer, the first welding structure and the second welding structure may be formed using the above method for forming a semiconductor structure, and then the first semiconductor structure may be bonded to the side of the semiconductor structure away from the semiconductor layer along the Z direction to form a semiconductor device.

[0157] In some embodiments, the channel structure 210 includes a channel layer and a functional layer surrounding the channel layer. After removing the base structure 600 , a portion of the functional layer is exposed. The method further includes:

[0158] After removing the base structure 600 , the exposed functional layer is removed to expose a portion of the channel layer.

[0159] In some embodiments, the channel structure 210 can be formed by etching the initial channel structure 211 shown in FIG. 20 or FIG. 21 . The initial channel structure 211 includes an initial functional layer and a channel layer. After removing the base structure 600, the initial functional layer is exposed above the top of the stacked structure 100. An etching process can be used to remove the portion of the initial functional layer above the stacked structure 100 to form a functional layer, exposing a portion of the channel layer.

[0160] Although the present disclosure has been described with reference to the current specific embodiments, ordinary technicians in this technical field should recognize that the above embodiments are only used to illustrate the present disclosure, and various equivalent changes or substitutions can be made without departing from the spirit of the present disclosure. Therefore, as long as the changes and modifications to the above embodiments are within the scope of the essential spirit of the present disclosure, they will fall within the scope of the claims of this application.

Claims

1. A semiconductor structure comprising: Stacked structure; A semiconductor layer, located on the stacked structure; A channel structure, penetrating the stacked structure and extending into the semiconductor layer; A contact structure extending along a stacking direction of the stacking structure; A first welding structure and a second welding structure; wherein the first welding structure penetrates the semiconductor layer and is connected to the contact structure, and the second welding structure is connected to the semiconductor layer.

2. The semiconductor structure according to claim 1, wherein: The first welding structure and the second welding structure each include a first portion and a second portion located on the first portion; wherein a size of the second portion along a first direction is greater than a size of the first portion along the first direction, and the first direction is perpendicular to the stacking direction.

3. The semiconductor structure according to claim 2, wherein: The size of the first part along the first direction is a first size, and the size of the first part along the stacking direction is a second size; the second size: the first size is less than 1:

5.

4. The semiconductor structure according to claim 2, wherein: The first part and the second part are integrally formed.

5. The semiconductor structure according to claim 1, wherein: A dimension of a portion of the channel structure extending to the semiconductor layer along the stacking direction is less than 200 nm.

6. The semiconductor structure according to claim 1, wherein: A top surface of the semiconductor layer located directly above the channel structure is flush with a top surface of the semiconductor layer located directly above the stacked structure.

7. The semiconductor structure according to claim 1, wherein: A top surface of the semiconductor layer located directly above the channel structure is higher than a top surface of the semiconductor layer located directly above the stacked structure.

8. The semiconductor structure according to claim 1, wherein: The material of the first welding structure and the material of the second welding structure both include aluminum.

9. The semiconductor structure according to claim 1, wherein: The semiconductor structure further comprises: The isolation structure is at least located between the first welding structure and the semiconductor layer.

10. The semiconductor structure according to claim 1, wherein: The stacking structure includes alternately stacked first material layers and insulating layers, the stacking structure includes a third part and a fourth part arranged in parallel along a direction perpendicular to the stacking direction, the contact structure runs through the third part, the channel structure runs through the fourth part, the first material layer in the third part includes a sacrificial layer, and the first material layer in the fourth part includes a conductive layer.

11. The semiconductor structure according to claim 1, wherein: The channel structure comprises a functional layer and a channel layer, wherein the functional layer is located in the stacked structure, the channel layer is located in the stacked structure and extends into the semiconductor layer, and the functional layer covers a side wall of the channel layer located in the stacked structure.

12. A semiconductor device comprising a first semiconductor structure and the semiconductor structure according to any one of claims 1 to 11; The first semiconductor structure is located on one side of the semiconductor structure that is opposite to each other along the stacking direction and is far away from the semiconductor layer. The first semiconductor structure is connected to the semiconductor structure by hybrid bonding.

13. The semiconductor device according to claim 12, wherein: The first semiconductor structure comprises: A peripheral circuit is connected to the contact structure in the semiconductor structure.

14. A method for forming a semiconductor structure, comprising: Providing a stacking structure, a contact structure, and a channel structure, wherein the channel structure penetrates the stacking structure and protrudes from the stacking structure, and the contact structure extends along a stacking direction of the stacking structure; forming a semiconductor layer on the stack structure and the channel structure from a side of the channel structure protruding from the stack structure; A first welding structure and a second welding structure are formed, wherein the first welding structure penetrates the semiconductor layer and is connected to the contact structure, and the second welding structure is connected to the semiconductor layer.

15. The forming method according to claim 14, wherein: The forming of a semiconductor layer on the stacked structure and the channel structure comprises: Semiconductor material layers are formed on the stacked structure, the channel structure, and the contact structure; the top surfaces of the semiconductor material layers directly above the channel structure and directly above the contact structure are higher than the top surface of the semiconductor material layer directly above the stacked structure; a portion of the semiconductor material layer is removed to form a first opening and expose the contact structure, and the remaining semiconductor material layer forms the semiconductor layer.

16. The forming method according to claim 15, wherein: The forming of a semiconductor layer on the stacked structure and the channel structure further includes: Before forming the first opening, the semiconductor material layer is planarized so that the top surface of the semiconductor material layer directly above the channel structure is flush with the top surface of the semiconductor material layer directly above the stacked structure.

17. The forming method according to claim 15, wherein: The method further includes: forming an isolation layer covering the sidewalls and bottom wall of the first opening and the semiconductor layer; At least the isolation layer on the bottom wall of the first opening is removed to expose the contact structure; and a portion of the isolation layer on the semiconductor layer is removed to form a second opening, wherein the second opening exposes the semiconductor layer; the remaining isolation layer forms Isolation structure.

18. The forming method according to claim 17, wherein: The forming of the first welding structure and the second welding structure comprises: After forming the isolation structure, the first welding structure is formed at least in the first opening, and the second welding structure is formed at least in the second opening, wherein the first welding structure and the second welding structure each include a first part and a second part located on the first part, the first part of the first welding structure is located in the first opening, and the second part of the second welding structure is located in the second opening.

19. The forming method according to claim 14, wherein: The stacking structure, the contact structure and the channel structure are provided, including: A stacking structure, a contact structure, and a channel structure are formed on a base structure; the base structure includes a substrate and a first semiconductor layer between the substrate and the stacking structure, and the channel structure extends into the first semiconductor layer; or the base structure includes a substrate, and the channel structure extends into the substrate; The base structure is removed to expose a portion of the channel structure.

20. The forming method according to claim 19, wherein: The channel structure includes a channel layer and a functional layer surrounding the channel layer. After removing the substrate structure, a portion of the functional layer is exposed. The method further includes: After removing the substrate structure, the exposed functional layer is removed to expose a portion of the channel layer.

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