ITO thin-film transistor with high withstand voltage and low on-resistance, and preparation method therefor

Abstract

Disclosed in the present invention are an ITO thin-film transistor with a high withstand voltage and a low on-resistance, and a preparation method therefor. The method comprises the following steps: S10, acquiring a substrate; S20, forming a gate electrode on the substrate; S30, forming a gate oxide on the gate electrode; S40, forming an ITO active layer on the gate oxide; S50, forming an ITO step layer on one side of the ITO active layer; and S60, forming a drain electrode on the ITO step layer, and forming a source electrode on the side of the ITO active layer that is not provided with the ITO step layer. In the present invention, by means of increasing the horizontal distance between the drain electrode and the gate electrode, the breakdown voltage of the ITO thin-film transistor is significantly increased; moreover, the ITO step layer is introduced, and by using the characteristic that the current capacity of an ITO material can be easily regulated by means of regulating the thickness thereof, the on-resistance of an ITO channel in a non-overlapping region is reduced, so that an improved relationship between the on-resistance and the breakdown voltage is obtained.

Description

A high-voltage, low-on-resistance ITO thin-film transistor and its preparation method Technical Field

[0001] The present invention belongs to the field of thin film transistors and their preparation, and in particular relates to a high-voltage, low-on-resistance ITO thin film transistor and a preparation method thereof. Background Art

[0002] Indium tin oxide (ITO) material has the advantages of low resistivity and high transmittance, and is widely used in electrode materials and display fields. In addition, as an oxide semiconductor, ITO material has good mobility (30cm 2 V -1 s -1 ), wide band gap (3.5eV), etc., researchers are considering applying it to the active layer of thin-film transistors (TFTs) to improve the electrical properties of the devices. However, due to the high degeneracy of ITO materials, they usually exhibit conductor properties and require special process treatment before they can be used as semiconductor materials. To date, there have been many papers studying ITO as an active layer. For example, this can be achieved by reducing the thickness of the ITO active layer to increase the scattering intensity of the carriers therein, or by doping the ITO active layer with a large amount of oxygen to reduce the number of oxygen vacancies therein and thereby reduce the carrier density. Due to the diversity of ITO materials in terms of electrical properties, ITO thin-film transistors have broad application prospects.

[0003] Power management circuits are crucial in integrated flexible electronic systems, and the application of high-voltage TFTs is essential for achieving high-performance flexible power management circuits. ITO has shown great potential in high-voltage devices due to its excellent electrical properties, especially the advantage of wide bandgap. In order to increase the breakdown voltage of ITO thin-film transistors, there are currently two mainstream methods. One is to apply materials with higher dielectric constants to gate oxides and increase their thickness to increase the withstand voltage of ITO thin-film transistors; the other is to offset the horizontal distance between the drain and the gate, and increase the withstand voltage of ITO thin-film transistors by adjusting the size of the horizontal distance. However, both of the above methods will significantly increase the on-resistance (R on ), it is difficult to achieve a good compromise between on-resistance and breakdown voltage. Therefore, it is of great significance to prepare an ITO thin film transistor with high withstand voltage and low on-resistance.

[0004] Summary of the Invention

[0005] The purpose of the present invention is to provide a high-voltage, low-on-resistance ITO thin-film transistor and a preparation method thereof. The voltage resistance is improved by offsetting the horizontal distance between the drain and gate of the device, and an ITO step layer is introduced to reduce its on-resistance, so as to solve the technical problem that the existing methods significantly increase the on-resistance of the device and it is difficult to achieve an excellent compromise between on-resistance and breakdown voltage.

[0006] In order to solve the above technical problems, the specific technical solutions of the present invention are as follows:

[0007] A method for preparing a high-voltage, low-on-resistance ITO thin-film transistor comprises the following steps:

[0008] obtaining a second substrate;

[0009] forming a second gate on the second substrate;

[0010] forming a second gate oxide on the second gate;

[0011] forming a second ITO active layer on the second gate oxide;

[0012] forming an ITO stepped layer on one side of the second ITO active layer;

[0013] forming a second drain electrode on the ITO stepped layer;

[0014] A second source electrode is formed on a side of the second ITO active layer where no ITO stepped layer is provided.

[0015] Furthermore, the second gate is a patterned molybdenum (Mo) metal film layer, and other metal materials with excellent conductive properties, such as nickel (Ni) and titanium (Ti), can also be used. The magnetron sputtering process is preferably used during production, and the thickness of the prepared second gate is 100nm.

[0016] Furthermore, the second gate oxide is a silicon oxide (SiO2) film layer, and other common second gate oxide materials can also be used, such as aluminum oxide (Al2O3), hafnium oxide (HfO2), etc. The PECVD process is preferably used during production, and the thickness of the prepared second gate oxide is 100nm.

[0017] Furthermore, the second ITO active layer is prepared by a magnetron sputtering process and has a thickness of 4 to 10 nm.

[0018] Furthermore, the ITO stepped layer is prepared by a magnetron sputtering process and has a thickness of 8 to 20 nm.

[0019] Furthermore, the second source and the second drain are patterned molybdenum (Mo) metal film layers, and other metal materials with excellent conductive properties, such as nickel (Ni) and titanium (Ti), may also be used. Magnetron sputtering process is preferably used during production.

[0020] The present invention also discloses a high-voltage-withstand, low-on-resistance ITO thin-film transistor, comprising a second substrate, a second gate, a second gate oxide, a second ITO active layer, an ITO stepped layer, a second source electrode, and a second drain electrode. The second gate electrode is arranged on the second substrate, the second gate oxide covers the second gate electrode, the second ITO active layer is arranged on the second gate oxide, the ITO stepped layer is arranged on one side of the second ITO active layer, the second source electrode is arranged on the side of the second ITO active layer where the ITO stepped layer is not arranged, and the second drain electrode is arranged on the ITO stepped layer.

[0021] Furthermore, the second gate oxide fully covers the second substrate and the second gate.

[0022] Furthermore, there is a 5 μm overlapping region between the second source and the second gate in the horizontal direction, and a horizontal length of a non-overlapping region between the second drain and the second gate in the horizontal direction is 2 μm, where the horizontal length of the non-overlapping region is represented by L.

[0023] Furthermore, the second substrate uses a rigid semiconductor, a flexible or rigid material as the second substrate.

[0024] A high-voltage, low-on-resistance ITO thin-film transistor and a preparation method thereof of the present invention have the following advantages: the present invention avoids the situation in which voltage breakdown easily occurs in the vertical direction and between the overlapping region of the second drain and the second gate in the traditional structure by offsetting the horizontal distance between the second drain and the second gate. Most of the voltage drops in the non-overlapping region in the horizontal direction between the second drain and the second gate, significantly improving the breakdown voltage of the ITO thin-film transistor; at the same time, an ITO stepped layer is introduced, and the characteristic that the current capacity of the ITO material is easily controlled by thickness is utilized to reduce the on-resistance of the ITO channel in the non-overlapping region, thereby obtaining a more excellent relationship between on-resistance and breakdown voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] FIG1 is a schematic diagram of an existing conventional bottom-gate staggered ITO thin film transistor;

[0026] FIG2 is a schematic diagram of an ITO thin film transistor according to an embodiment of the present invention;

[0027] 3 is a flow chart of a method for preparing an ITO thin film transistor according to an embodiment of the present invention;

[0028] FIG4 is a diagram showing the breakdown voltage of ITO thin film transistors according to an embodiment of the present invention and a comparative example;

[0029] FIG5 is a current curve diagram of an ITO thin film transistor according to an embodiment of the present invention and a comparative example;

[0030] Explanation of the marks in the figure: 110, first substrate; 120, first gate; 130, first gate oxide; 140, first ITO active layer; 150, first source; 152, first drain; 210, second substrate; 220, second gate; 230, second gate oxide; 240, second ITO active layer; 250, ITO stepped layer; 260, second source; 262, second drain. DETAILED DESCRIPTION

[0031] In order to better understand the purpose, structure and function of the present invention, the following is a further detailed description of a high-voltage, low-on-resistance ITO thin-film transistor and a preparation method thereof in conjunction with the accompanying drawings.

[0032] An embodiment of the present invention is shown in FIG2 . However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide the reader with a more thorough and comprehensive understanding of the present disclosure. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one skilled in the art to which this invention belongs.

[0033] FIG1 is a schematic diagram of a comparative example of a conventional ITO thin-film transistor. The comparative example comprises, from bottom to top, a first substrate 110, a first gate electrode 120 based on a molybdenum (Mo) metal film layer, a first gate oxide 130 based on silicon oxide (SiO2), a first ITO active layer 140, a first source electrode 150 based on a molybdenum (Mo) metal film layer, and a first drain electrode 152. Because the first drain electrode 152 and the first gate electrode 120 overlap in a vertical direction, when a large voltage is applied to the first drain electrode 152, the first gate oxide 130 in the overlapping region is easily broken down. FIG2 is a schematic diagram of an ITO thin-film transistor with an ITO stepped layer in one embodiment of the present invention. The biggest difference between the embodiment and the comparative example is that the embodiment eliminates the vertical overlap between the second gate electrode and the second drain electrode. FIG3 is a flow chart of a method for preparing an ITO thin-film transistor in one embodiment. The method can be used to prepare the ITO thin-film transistor shown in FIG2, and includes the following steps:

[0034] S10, obtaining a second substrate 210.

[0035] The second substrate 210 can be a rigid or flexible substrate known in the art. In an embodiment of the present invention, the second substrate 210 is a semiconductor substrate, such as a silicon / silicon oxide substrate. The second substrate is ultrasonically cleaned for five minutes at 100 W using deionized water, acetone, ethanol, and deionized water, in that order, to obtain a second substrate suitable for subsequent processing.

[0036] S20 , forming a second gate 220 on the second substrate 210 .

[0037] In an embodiment of the present invention, a patterned photoresist is obtained by performing coating, drying, photolithography, exposure, and development processes on the surface of the second substrate 210 (S10). A molybdenum (Mo) metal layer is formed on the second substrate using a magnetron sputtering process. A lift-off process is further used to obtain a patterned second gate 220. Other materials / structures well known in the art can be used as the gate electrode layer. In this embodiment, the prepared second gate 220 has a thickness of 100 nm and a horizontal length of 58 μm.

[0038] S30 , forming a second gate oxide 230 on the second gate 220 .

[0039] In an embodiment of the present invention, a second gate oxide 230 made of silicon oxide (SiO2) is completely covered on the second gate 220 (S20) using a PECVD process. The PECVD process parameters employed in this embodiment are as follows: operating pressure of 1000 mTorr, a ratio of 710:170 of N2O and 5% SiH4, power of 100 W, and a reaction temperature of 300°C. In this embodiment, the thickness of the second gate oxide 230 is 100 nm. In one embodiment, the prepared silicon oxide is further subjected to thermal annealing.

[0040] S40 , forming a second ITO active layer 240 on the second gate oxide 230 .

[0041] In an embodiment of the present invention, a second ITO active layer 240 is formed on the second gate oxide 230 (S30) by a magnetron sputtering process. The magnetron sputtering process parameters used in this embodiment are as follows: sputtering pressure 0.4 Pa, a ratio of Ar and O2 introduced of 45:5, a sputtering power of 60 W, and a sputtering time of 417 s. By performing a coating, drying, photolithography, exposure, and development process on the surface of the second ITO active layer 240, a patterned photoresist can be obtained. The sample surface is etched using dilute hydrochloric acid (~1%) to etch away the second ITO active layer 240 outside the area covered by the patterned photoresist. After a stripping process, the patterned second ITO active layer 240 can be obtained. In this embodiment, the thickness of the prepared second ITO active layer 240 is 4 nm.

[0042] S50 , forming an ITO stepped layer 250 on the second ITO active layer 240 .

[0043] In an embodiment of the present invention, an ITO step layer 250 is formed on the second ITO active layer 240 (S40) by a magnetron sputtering process. The magnetron sputtering process parameters used in this embodiment are as follows: sputtering pressure 0.4 Pa, the ratio of Ar and O2 introduced is 45:5, the sputtering power is 60 W, and the sputtering time is 1043 s. By performing coating, drying, photolithography (the mask used in this step is different from S40), exposure and development on the surface of the ITO step layer 250, a patterned photoresist can be obtained. The etching process in S40 is repeated to obtain a patterned ITO step layer 250, which is then annealed. The annealing conditions in this embodiment are as follows: temperature is 200 ° C, annealing atmosphere is air, and annealing time is 30 min. In this embodiment, the thickness of the prepared ITO step layer 250 is 10 nm.

[0044] S60 , forming a second source electrode 260 and a second drain electrode 262 on the ITO stepped layer 250 .

[0045] In an embodiment of the present invention, a patterned photoresist is obtained by performing coating, drying, photolithography, exposure, and development processes on the surface of the ITO step layer 250 (S50). A molybdenum (Mo) metal layer is formed on the surface of the ITO step layer 250 and the second ITO active layer 240 using a magnetron sputtering process. A lift-off process is then used to obtain a patterned second source electrode 260 and a second drain electrode 262. In other embodiments, other materials well known in the art may also be used as the materials for the second source electrode and the second drain electrode. In this embodiment, the second source electrode 260 and the second drain electrode 262 are prepared to have a thickness of 100 nm, and the spacing between the second source electrode 260 and the second drain electrode 262 is 50 μm. There is a 5 μm overlap between the second source electrode 260 and the second gate electrode 220 in the horizontal position, and the horizontal length of the non-overlapping region between the second drain electrode 262 and the second gate electrode 220 in the horizontal direction is 2 μm. This non-overlapping region is represented by L.

[0046] The present invention also discloses a high-voltage, low-on-resistance ITO thin-film transistor, comprising a second substrate 210, a second gate 220, a second gate oxide 230, a second ITO active layer 240, an ITO stepped layer 250, a second source 260, and a second drain 262. The second gate 220 is disposed on the second substrate 210, the second gate oxide 230 covers the second gate 220, the second ITO active layer 240 is disposed on the second gate oxide 230, the ITO stepped layer 250 is disposed on one side of the second ITO active layer 240, the second source 260 is disposed on a side of the second ITO active layer 240 where the ITO stepped layer 250 is not disposed, and the second drain 262 is disposed on the ITO stepped layer 250.

[0047] The second substrate 210 is a rigid semiconductor second substrate, and can also be made of a flexible or rigid material known in the art.

[0048] Figure 4 is a breakdown voltage diagram of the embodiment of the present invention and the comparative example, and Figure 5 is a current curve diagram of the embodiment of the present invention and the comparative example. The comparative example is a traditional bottom-gate staggered ITO thin-film transistor, and the embodiment is an ITO thin-film transistor with an ITO stepped layer.

[0049] In Figure 4, the vertical axis is the numerical value of the drain current, and the horizontal axis is the magnitude of the applied drain voltage, and the gate and source are short-circuited for measurement. It can be seen that the breakdown voltage of the comparative example is about 58V, while the breakdown voltage of this embodiment is about 200V. Compared with the comparative example, the voltage resistance of the embodiment is significantly improved by nearly four times. Figure 5 is a current curve diagram of the embodiment of the present invention and the comparative example. The vertical axis of Figure 5 is the numerical value of the drain current, and the horizontal axis is the magnitude of the applied gate voltage. It can be seen that compared with the comparative example, the current capacity of the transistor in this embodiment is not only not reduced, but even slightly improved while the voltage resistance is significantly improved. When the gate voltage is greater than 2V, the current of this embodiment is improved by an order of magnitude compared with that of the comparative example.

[0050] It will be understood that the present invention is described by way of some embodiments, and it will be appreciated by those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are intended to be protected by the present invention.

Claims

1. A method for preparing a high withstand voltage and low on-resistance ITO thin film transistor, characterized in that: The following steps are involved: S10, obtaining a second substrate (210); S20, forming a second gate (220) on the second substrate (210); S30, forming a second gate oxide (230) on the second gate (220); S40, forming a second ITO active layer (240) on the second gate oxide (230); S50, forming an ITO stepped layer (250) on one side of the second ITO active layer (240); S60, forming a second drain electrode (262) on the ITO stepped layer (250); and forming a second source electrode (260) on a side of the second ITO active layer (240) where the ITO stepped layer (250) is not provided.

2. The method for preparing a high withstand voltage, low on-resistance ITO thin film transistor according to claim 1, characterized in that: The second gate (220) is a metal film layer having conductive properties. The metal film layer comprises patterned molybdenum (Mo), nickel (Ni) or titanium (Ti). The magnetron sputtering process is adopted during the manufacturing process. The thickness of the manufactured second gate (220) is 100 nm.

3. The method for preparing a high withstand voltage, low on-resistance ITO thin film transistor according to claim 1, characterized in that: The second gate oxide (230) is a silicon oxide (SiO2) film layer, an aluminum oxide (Al2O3) film layer or a hafnium oxide (HfO2) film layer, and is manufactured using a PECVD process. The thickness of the second gate oxide (230) is 20-100 nm.

4. The method for preparing a high withstand voltage and low on-resistance ITO thin film transistor according to claim 1, characterized in that: The second ITO active layer (240) is prepared by a magnetron sputtering process and has a thickness of 4 to 10 nm.

5. The method for preparing a high withstand voltage and low on-resistance ITO thin film transistor according to claim 1, characterized in that: The ITO stepped layer (250) is prepared by a magnetron sputtering process and has a thickness of 8 to 20 nm.

6. The method for preparing a high withstand voltage and low on-resistance ITO thin film transistor according to claim 1, characterized in that: The second source electrode (260) and the second drain electrode (262) are metal film layers, the metal film layers have conductive properties, the metal film layers include patterned molybdenum (Mo), nickel (Ni) or titanium (Ti), and are manufactured using a magnetron sputtering process.

7. The high withstand voltage, low on-resistance ITO thin film transistor according to claim 1, characterized in that: The invention comprises a second substrate (210), a second gate electrode (220), a second gate oxide (230), a second ITO active layer (240), an ITO stepped layer (250), a second source electrode (260) and a second drain electrode (262), wherein the second gate electrode (220) is arranged on the second substrate (210), the second gate oxide (230) covers the second gate electrode (220), the second ITO active layer (240) is arranged on the second gate oxide (230), the ITO stepped layer (250) is arranged on one side of the second ITO active layer (240), the second source electrode (260) is arranged on the side of the second ITO active layer (240) where the ITO stepped layer (250) is not arranged, and the second drain electrode (262) is arranged on the ITO stepped layer (250).

8. The high withstand voltage, low on-resistance ITO thin film transistor according to claim 7, characterized in that: The second gate oxide (230) completely covers the second substrate (210) and the second gate (220).

9. The high withstand voltage, low on-resistance ITO thin film transistor according to claim 7, characterized in that: There is a 5 μm overlap region between the second source (260) and the second gate (220) in the horizontal direction, and a horizontal length of a non-overlap region between the second drain (262) and the second gate (220) in the horizontal direction is 2 μm.

10. The high withstand voltage, low on-resistance ITO thin film transistor according to claim 7, characterized in that: The second substrate (210) uses a rigid semiconductor, a flexible or a rigid material as the second substrate.

Images