Array substrate and display panel comprising same

Abstract

An array substrate (100) and a display panel (300) comprising same. Resistance compensation units (R) are connected in series on first scanning signal lines (Scan_1), first driving signal lines (EM_1), and first reset signal lines (Vint_1), so as to compensate for the resistance of n rows of pixels in an under-display camera area; an extension line of each first scanning signal line (Scan_1) and an extension line of a corresponding first driving signal line (EM_1) have a projection overlapping area, at least part of the projection overlapping area constitutes a capacitance compensation unit (C), and the first scanning signal line (Scan_1), the first driving signal line (EM_1), and a corresponding first reset signal line (Vint_1) are all connected in parallel to the capacitance compensation unit (C), so as to compensate for the capacitance of n columns of pixels in the under-display camera area. Therefore, the problem of display difference between n rows of pixels in an under-display camera area and pixels in other areas is solved.

Description

Array substrate and display panel thereof

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority based on Chinese patent application 2023110999656 filed on August 30, 2023, and all its contents are incorporated herein by reference.

Technical field

[0003] The present application relates to the field of display technology, and in particular to an array substrate and a display panel thereof. [Background Technology]

[0004] In order to pursue a high screen-to-body ratio, existing display devices set up an under-screen camera (UDC) area in the display area, and the under-screen camera area must take into account both shooting and display functions. Therefore, the transmittance of the under-screen camera area must be greater than that of the normal display area to ensure that sufficient light enters the under-screen camera area to meet shooting requirements. Pixel circuits need to be set in the under-screen camera area to meet the corresponding display functions.

[0005] However, to ensure that the transmittance of the under-screen camera area is greater than that of the normal display area, it is necessary to set the pixel density of the under-screen camera area to be smaller than that of the normal display area, or to set the size of the pixel unit in the under-screen camera area to be smaller than that of the pixel unit in the normal display area, resulting in display differences between the n rows of pixels in the under-screen camera area and other areas.

[0006] [Summary of the invention]

[0007] The present application provides an array substrate and a display panel thereof, which can solve the problem of display differences between the n rows of pixels in the under-screen camera area and other areas.

[0008] In order to solve the above technical problems, the first technical solution provided in the present application is: providing an array substrate, comprising a plurality of pixel units arranged in an array, scanning signal lines and driving signal lines connecting a plurality of rows of the pixel units, and a reset signal line connecting a plurality of columns of the pixel units; wherein the plurality of pixel units include a first pixel unit arranged in a first display area and a second pixel unit arranged in a second display area, at least part of the first pixel units and at least part of the second pixel units are arranged in the same row and connected through a first scanning signal line and a first driving signal line, and at least part of the first pixel units and at least part of the second pixel units are arranged in the same column and connected through a first reset signal line; the transmittance of the first display area is greater than the transmittance of the second display area; a resistance compensation unit is connected in series to the first scanning signal line, the first driving signal line, and the first reset signal line, and an extension line of the first scanning signal line and an extension line of the first driving signal line have a projected overlapping area, at least part of the projected overlapping area constitutes a capacitance compensation unit, and the first scanning signal line, the first driving signal line, and the first reset signal line are all connected in parallel with the capacitance compensation unit.

[0009] Wherein, the array substrate comprises: a substrate; a semiconductor layer, arranged on a first surface of the substrate, wherein the semiconductor layer comprises a first semiconductor layer for forming the first pixel unit, a second semiconductor layer for forming the second pixel unit, and a semiconductor trace for forming the resistance compensation unit; a gate insulating layer, arranged on a surface of the semiconductor layer away from the substrate; a first metal layer, arranged on a surface of the gate insulating layer away from the substrate; wherein the first metal layer comprises a first gate for forming the first pixel unit, a second gate for forming the second pixel unit, and a first metal trace for forming part of the first scanning signal line and its extension line and part of the first driving signal line and its extension line; layer An interlayer dielectric layer is arranged on the first surface of the substrate and covers the semiconductor layer and the first metal layer; a second metal layer is arranged on the surface of the interlayer dielectric layer away from the gate insulating layer, the second metal layer includes a first source and a first drain that are insulated and used to form the first pixel unit, a second source and a second drain that are insulated and used to form the second pixel unit, and a second metal routing that is used to form part of the first scanning signal line and its extension line and part of the first driving signal line and its extension line; wherein the extension line of the first scanning signal line overlaps at least part of the projection of the first driving signal line on the substrate with at least part of the projection of the extension line of the first driving signal line on the substrate to serve as the capacitance compensation unit.

[0010] Wherein, the semiconductor routing includes a first sub-semiconductor routing and a second sub-semiconductor routing; the first metal routing includes a first sub-metal routing for forming part of the first scanning signal line, a second sub-metal routing for forming part of the extension line of the first scanning signal line, and a third sub-metal routing for forming part of the first driving signal line; the second metal routing includes a fourth sub-metal routing and a fifth sub-metal routing for forming part of the first scanning signal line, a sixth sub-metal routing for forming part of the extension line of the first driving signal line, and a seventh sub-metal routing for forming part of the extension line of the first driving signal line; wherein, the first sub-metal routing is connected to the fourth sub-metal routing through a first contact hole penetrating the interlayer dielectric layer, the fourth sub-metal routing is connected to the first sub-semiconductor routing through a second contact hole, and the first sub-semiconductor routing is connected to the first sub-semiconductor routing through a third contact hole. Five sub-metal routings, the fifth sub-metal routing is connected to the second sub-metal routing through a fourth contact hole; the first sub-semiconductor routing serves as the resistance compensation unit on the first scanning signal line; the third sub-metal routing is connected to the sixth sub-metal routing through a fifth contact hole penetrating the interlayer dielectric layer, the sixth sub-metal routing is connected to the second sub-semiconductor routing through a sixth contact hole, and the second sub-semiconductor routing is connected to the seventh sub-metal routing through a seventh contact hole; the second sub-semiconductor routing serves as the resistance compensation unit on the first drive signal line; and the projection of the second sub-metal routing on the substrate at least partially overlaps with the projection of the seventh sub-metal routing on the substrate, and the overlapping area of ​​the projection of the second sub-metal routing and the seventh sub-metal routing serves as a capacitance compensation unit on the first scanning signal line, the first drive signal line and / or the first reset signal line.

[0011] In which, the array substrate also includes: a passivation layer, which is arranged on the surface of the interlayer dielectric layer away from the gate insulation layer and covers the second metal layer; a third metal layer, which is arranged on the surface of the passivation layer away from the interlayer dielectric layer, and at least part of the projection of the third metal layer on the substrate overlaps with at least part of the projection of the extension line of the first scanning signal line and / or the extension line of the first driving signal line on the substrate, and at least part of the overlapping area of ​​the projection of the third metal layer and the extension line of the first scanning signal line and / or the extension line of the first driving signal line serves as the capacitance compensation unit.

[0012] Wherein, the semiconductor routing includes a third sub-semiconductor routing and a fourth sub-semiconductor routing; the first metal routing includes an eighth sub-metal routing for forming part of the first scanning signal line, a ninth sub-metal routing for forming part of the first driving signal line, and a tenth sub-metal routing for forming part of the extension line of the first scanning signal line; the second metal routing includes an eleventh sub-metal routing and a twelfth sub-metal routing for forming part of the first scanning signal line, a thirteenth sub-metal routing for forming part of the first driving signal line, and a fourteenth sub-metal routing and a fifteenth sub-metal routing for forming part of the extension line of the first driving signal line; the third metal layer includes a sixteenth sub-metal routing; wherein, the eighth sub-metal routing is connected to the eleventh sub-metal routing through an eighth contact hole penetrating the interlayer dielectric layer, the eleventh sub-metal routing is connected to the third sub-semiconductor routing through a ninth contact hole, the third sub-semiconductor routing is connected to the twelfth sub-metal routing through a tenth contact hole, and the twelfth sub-metal routing is connected to the tenth sub-metal routing through a tenth contact hole. A contact hole connects the sixteenth sub-metal routing; the third sub-semiconductor routing serves as the resistance compensation unit on the first scanning signal line; the ninth sub-metal routing is connected to the thirteenth sub-metal routing through the twelfth contact hole penetrating the interlayer dielectric layer, the thirteenth sub-metal routing is connected to the fourth sub-semiconductor routing through the thirteenth contact hole, the fourth sub-semiconductor routing is connected to the fourteenth sub-metal routing through the fourteenth contact hole, and the fourteenth sub-metal routing is connected to the tenth sub-metal routing through the fifteenth contact hole; the fourth sub-semiconductor routing serves as the resistance compensation unit on the first driving signal line; and the projection of the sixteenth sub-metal routing on the substrate at least partially overlaps with the projection of the tenth sub-metal routing on the substrate and / or the projection of the fifteenth sub-metal routing on the substrate, and the overlapping area of ​​the projection of the sixteenth sub-metal routing and the tenth sub-metal routing and / or the fifteenth sub-metal routing serves as the capacitance compensation unit on the first scanning signal line, the first driving signal line and / or the first reset signal line.

[0013] The fifteenth sub-metal wiring is also connected to a preset potential.

[0014] The resistance of the resistance compensation unit is related to the size and doping concentration of the semiconductor wiring; the overlapping area of ​​the capacitance compensation unit and the extension line of the first scanning signal line and the extension line of the first driving signal line in the projected overlapping area of ​​the substrate is related; the resistance of the resistance compensation unit is less than or equal to 1KΩ; the capacitance of the capacitance compensation unit is less than or equal to 10pF.

[0015] The density of the first pixel units in the first display area is the same as the density of the second pixel units in the second display area, and the size of the first pixel units is smaller than that of the second pixel units.

[0016] In which, the resistance compensation unit and the capacitance compensation unit are both arranged in the first display area; or, the resistance compensation unit and the capacitance compensation unit are both arranged in the second display area; or, part of the resistance compensation unit is arranged in the first display area, and another part of the resistance compensation unit is arranged in the second display area; and, part of the capacitance compensation unit is arranged in the first display area, and another part of the capacitance compensation unit is arranged in the second display area.

[0017] In order to solve the above technical problems, the second technical solution provided in this application is: providing a display panel, comprising: an array substrate, the array substrate being any of the array substrates described above; and an opposing substrate, disposed on one side of the array substrate.

[0018] Beneficial effects of the present application: Different from the prior art, the array substrate and the display panel provided by the present application, by connecting a resistance compensation unit in series on the first scanning signal line, the first driving signal line and the first reset signal line, so as to not compensate for the resistance of the n rows of pixels where the under-screen camera area is located; and the extension line of the first scanning signal line and the extension line of the first driving signal line have a projected overlapping area, at least part of the projected overlapping area constitutes a capacitance compensation unit, and the first scanning signal line, the first driving signal line and the first reset signal line are all connected in parallel with the capacitance compensation unit to compensate for the capacitance of the n columns of pixels where the under-screen camera area is located; thereby solving the problem of display differences between the n rows of pixels where the under-screen camera area is located and other areas.

Brief Description of the Drawings

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0020] FIG1 is a schematic structural diagram of an embodiment of an array substrate provided by the present application;

[0021] FIG2 is a schematic diagram of a module of a pixel unit at position A in FIG1 ;

[0022] FIG3 is a schematic diagram of a circuit structure of an embodiment of a first pixel unit and a second pixel unit provided by the present application;

[0023] FIG4 is an equivalent circuit diagram of an embodiment of a capacitance and resistance compensation unit provided by the present application;

[0024] FIG5 is a schematic diagram of a film layer structure of an embodiment of an array substrate provided in the present application;

[0025] FIG6 is an RC compensation design provided in the first embodiment of the present application;

[0026] FIG7 is an RC compensation design provided in the second embodiment of the present application;

[0027] FIG8 is a schematic structural diagram of an embodiment of a display panel provided in the present application.

[0028] DESCRIPTION OF REFERENCE NUMERALS: Array substrate 100; Counter substrate 200; Display panel 300; First display area A1; Second display area A2; Pixel unit P; First pixel unit P1; Second pixel unit P2; Scan signal line Scan; First scan signal line Scan_1; Second scan signal line Scan_2; Drive signal line EM; First drive signal line EM_1; Second drive signal line EM_2; Reset signal line Vint; First reset signal line Vint_1; Second reset signal line Vint_2; Capacitance and resistance compensation unit RC; Resistance compensation unit R; Capacitance compensation unit C; Substrate 10; Semiconductor layer 20; Gate insulation layer 30; First metal layer 40; Interlayer dielectric layer 50; Second metal layer 60; Passivation layer 70; Third metal layer 80; Planarization layer 91; Anode layer 92; Pixel definition layer 93; Support layer 94; First sub-semiconductor trace 21; Second sub-semiconductor trace 22; Third sub-semiconductor trace 23; Fourth sub-semiconductor trace 24; a first sub-metal trace 41; a second sub-metal trace 42; a third sub-metal trace 43; an eighth sub-metal trace 44; a ninth sub-metal trace 45; a tenth sub-metal trace 46; a fourth sub-metal trace 61; and a fifth sub-metal trace 62; a sixth sub-metal trace 63; a seventh sub-metal trace 64; an eleventh sub-metal trace 65; a twelfth sub-metal trace 66; a thirteenth sub-metal trace 67; a fourteenth sub-metal trace 68; a fifteenth sub-metal trace 69; a sixteenth sub-metal trace 81; a first contact hole H1; a second contact hole H2; a third contact hole H3; a fourth contact hole H4; a fifth contact hole H5; a sixth contact hole H6; a seventh contact hole H7; an eighth contact hole H8; a ninth contact hole H9; a tenth contact hole H10; an eleventh contact hole H11; a twelfth contact hole H12; a thirteenth contact hole H13; a fourteenth contact hole H14; a fifteenth contact hole H15; and an opening X1. [Specific implementation method]

[0029] The following describes the embodiments of the present application in detail with reference to the accompanying drawings.

[0030] In the following description, for the purpose of explanation rather than limitation, specific details such as specific system structures, interfaces, and technologies are provided to facilitate a thorough understanding of the present application.

[0031] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0032] The terms "first," "second," and "third" in this application are used only for descriptive purposes and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of such features. In the description of this application, "multiple" means at least two, for example, two, three, etc., unless otherwise specifically defined. All directional indications in the embodiments of this application (such as up, down, left, right, front, back...) are only used to explain the relative positional relationship, movement, etc. between the components under a specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indications also change accordingly. In addition, the terms "including" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products, or devices.

[0033] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0034] 1 and 2 , FIG1 is a schematic structural diagram of an embodiment of an array substrate provided in the present application; FIG2 is a schematic module diagram of a pixel unit at position A in FIG1 .

[0035] An embodiment of the present application provides an array substrate 100, comprising a first display area A1 and a second display area A2, wherein the transmittance of the first display area A1 is greater than the transmittance of the second display area A2. The array substrate 100 further comprises a plurality of pixel units P arranged in an array, scan signal lines Scan and drive signal lines EM connecting multiple rows of the pixel units P, and a reset signal line Vint connecting multiple columns of the pixel units P. The plurality of pixel units P include first pixel units P1 disposed in the first display area A1 and second pixel units P2 disposed in the second display area A2, and it is defined that at least some of the first pixel units P1 and at least some of the second pixel units P2 are arranged in the same row and connected via a first scan signal line Scan_1 and a first drive signal line EM_1, and at least some of the first pixel units P1 and at least some of the second pixel units P2 are arranged in the same column and connected via a first reset signal line Vint_1. It is defined that a row of pixel units P only includes the second pixel units P2 and is connected via the second scan signal line Scan_2 and the second drive signal line EM_2 , and a column of pixel units P only includes the second pixel units P2 and is connected via the second reset signal line Vint_2 .

[0036] Among them, the first display area A1 can be the under-screen camera area (or UDC area), the second display area A2 can be the normal display area (or AA area), and the second display area A2 can be arranged around at least one side of the first display area A1. For example, the second display area A2 can be arranged around the first display area A1, or the second display area A2 can be arranged semi-surrounding the first display area A1, etc., which is not limited here.

[0037] However, since the first display area A1 is a UDC area, to ensure high light transmittance in the first display area A1, the pixel density in the UDC area needs to be set lower than that in the normal display area; or the size of the pixel units P in the UDC area needs to be set smaller than that in the normal display area to reduce the number of traces in the UDC area. However, the applicant has discovered that this arrangement results in a difference in the circuit architecture in the UDC area from that in the normal display area, resulting in display differences between the n rows of pixels in the UDC area and other areas under the screen.

[0038] As shown in Figure 2, in an embodiment of the present application, in order to ensure the display effect of the UDC area, the pixel density of the UDC area is set to be equal to the pixel density of the normal display area, and the size of the first pixel unit P1 in the UDC area is set to be smaller than the size of the second pixel unit P2 in the normal display area.

[0039] Specifically, as shown in Figure 3, Figure 3 is a circuit structure diagram of an embodiment of the first pixel unit and the second pixel unit provided in the present application. In the embodiment provided in the present application, the UDC area adopts a simple 2T1C circuit architecture, and the AA area other than the UDC area adopts a circuit architecture with a compensation function (such as 3T1C, 4T2C, 5T2C, 6T1C, 7T1C and other circuit architectures). In the embodiment of the present application, the AA area adopts a 6T1C circuit architecture.

[0040] As shown in Figure 3, the difference in circuit architecture between the UDC area and the AA area shows that due to the simplified circuit architecture of the first pixel unit P1 in the UDC area, there is an RC loading difference between the first scanning signal line Scan_1 (such as Scan2), the second driving signal line EM_1 (such as EM1&2) and the first reset signal line Vint_1 (such as Vint) and the second scanning signal line Scan_2, the second driving signal line EM_2 and the second reset signal line Vint_2, resulting in a display difference between the n rows of pixels in the UDC area under the screen and other areas.

[0041] To solve the above problems, please refer to Figures 2 and 4. Figure 4 is an equivalent circuit diagram of an embodiment of a capacitance and resistance compensation unit provided by the present application. In the embodiment of the present application, a capacitance and resistance compensation unit RC is provided on the first scan signal line Scan_1, the first drive signal line EM_1, and the first reset signal line Vint_1, wherein the capacitance and resistance compensation unit RC includes a resistance compensation unit R and a capacitance compensation unit C. Specifically, the first scan signal line Scan_1, the first drive signal line EM_1, and the first reset signal line Vint_1 are connected in series with the resistance compensation unit R, which is used to compensate for the resistance difference between the n rows of pixel units P (each row of pixel units P includes a first pixel unit P1 and a second pixel unit P2) in the UDC area and the other rows of pixel units P (each row of pixels includes only a second pixel unit P2). The extension line of the first scanning signal line Scan_1 and the extension line of the first driving signal line EM_1 have a projected overlapping area, and at least part of the projected overlapping area constitutes a capacitance compensation unit C. The first scanning signal line Scan_1, the first driving signal line EM_1 and the first reset signal line Vint_1 are all connected in parallel to the capacitance compensation unit C. The capacitance compensation unit C is used to compensate for the capacitance difference between the n-row pixel units P where the UDC area is located and the pixel units P in other rows, thereby improving the display difference problem between the n-row pixel units P where the UDC area is located and other areas.

[0042] In FIG4 , “Signal-in” represents the signal input terminal, and “Signal-out” represents the signal output terminal, and their specific connection relationship is set based on the signal flow direction on the signal line.

[0043] Specifically, in the n rows of pixel units P where the UDC area is located, each row of the first scanning signal line Scan_1 is connected in series with a resistance compensation unit R and a parallel capacitance compensation unit C to perform RC compensation on each row of the first scanning signal line Scan_1, which can compensate for the resistance and capacitance differences between the first scanning signal line Scan_1 and the second scanning signal line Scan_2; in the n rows of pixel units P where the UDC area is located, each row of the first driving signal line EM_1 is connected in series with a resistance compensation unit R and a parallel capacitance compensation unit C to perform RC compensation on each row of the first driving signal line EM_1, which can compensate for the resistance and capacitance differences between the first driving signal line EM_1 and the second driving signal line EM_2; in the n rows of pixel units P where the UDC area is located, each column of the first reset signal line Vint_1 is connected in series with a resistance compensation unit R and a parallel capacitance compensation unit C to perform RC compensation on each column of the first reset scanning signal line, which can compensate for the resistance and capacitance differences between the first reset signal line Vint_1 and the second reset signal line Vint_2. By performing RC compensation on the first scan signal line Scan_1, the first drive signal line EM_1, and the first reset signal line Vint_1 connected to the n rows of pixel cells P in the UDC area, the electrical properties of the first scan signal line Scan_1, the first drive signal line EM_1, and the first reset signal line Vint_1 connected to the n rows of pixel cells P in other areas are made consistent, thereby improving the display difference between the n rows of pixel cells P in the UDC area and other areas.

[0044] In this embodiment, the resistance compensation unit R and the capacitance compensation unit C can both be disposed in the first display area A1. Specifically, because the second pixel units P2 in the second display area A2 have complex circuit structures and are relatively large in size, the gaps between the second pixel units P2 are small. In this embodiment, the resistance compensation unit R and the capacitance compensation unit C are both disposed in the first display area A1. This eliminates the need to occupy space in the second display area A2, simplifying the manufacturing process of the resistance compensation unit R and the capacitance compensation unit C. The resistance compensation unit R and the capacitance compensation unit C can be disposed at the edge of the first display area A1 near the second display area A2 to minimize impact on the light transmittance of the first display area A1.

[0045] Alternatively, in this embodiment, both the resistance compensation unit R and the capacitance compensation unit C can be disposed in the second display area A2. Specifically, when the first display area A1 is a UDC area, the first display area A1 requires a high light transmittance to meet photography requirements. Therefore, to prevent the resistance compensation unit R and the capacitance compensation unit C from affecting the light transmittance of the first display area A1, the resistance compensation unit R and the capacitance compensation unit C are disposed in the second display area A2. The resistance compensation unit R and the capacitance compensation unit C can be disposed at the edge of the second display area A2 near the first display area A1 to greatly simplify the fabrication process of the resistance compensation unit R and the capacitance compensation unit C in the second display area A2.

[0046] Alternatively, some resistance compensation units R can be disposed in the first display area A1, while others can be disposed in the second display area A2; and some capacitance compensation units C can be disposed in the first display area A1, while others can be disposed in the second display area A2. Specifically, by rationally arranging the resistance compensation units R and capacitance compensation units C in the first display area A1 and the second display area A2, the light transmittance of the first display area A1 can be guaranteed, while the fabrication process of the resistance compensation units R and capacitance compensation units C in the second display area A2 can be simplified.

[0047] Specifically, see Figure 5, which is a schematic diagram of the film layer structure of an embodiment of an array substrate provided in this application. In this embodiment of the application, the array substrate 100 includes a substrate 10, a semiconductor layer 20, a gate insulation layer 30, a first metal layer 40, an interlayer dielectric layer 50, and a second metal layer 60.

[0048] Specifically, the semiconductor layer 20 is disposed on the first surface of the substrate 10 , wherein the semiconductor layer 20 includes a first semiconductor layer for forming the first pixel unit P1 , a second semiconductor layer for forming the second pixel unit P2 , and a semiconductor trace for forming the resistance compensation unit R.

[0049] The gate insulating layer 30 is disposed on a surface of the semiconductor layer 20 facing away from the substrate 10 , and is used to isolate the first metal layer 40 from the semiconductor layer 20 .

[0050] In which, the first metal layer 40 is arranged on the surface of the gate insulation layer 30 facing away from the substrate 10; in which, the first metal layer 40 includes a first gate for forming a first pixel unit P1, a second gate for forming a second pixel unit P2, and a first metal routing for forming part of the first scanning signal line Scan_1 and its extension line and part of the first driving signal line EM_1 and its extension line.

[0051] The interlayer dielectric layer 50 is disposed on the first surface of the substrate 10 and covers the semiconductor layer 20 and the first metal layer 40 , and is used to isolate the first metal layer 40 , the interlayer dielectric layer 50 and the second metal layer 60 .

[0052] Among them, the second metal layer 60 is arranged on the surface of the interlayer dielectric layer 50 away from the gate insulation layer 30, and the second metal layer 60 includes an insulating arrangement and a first source and a first drain for forming the first pixel unit P1, an insulating arrangement and a second source and a second drain for forming the second pixel unit P2, and a second metal routing for forming part of the first scanning signal line Scan_1 and its extension line and part of the first driving signal line EM_1 and its extension line.

[0053] At least a portion of a projection of an extension line of the first scan signal line Scan_1 on the substrate 10 overlaps with at least a portion of a projection of an extension line of the first drive signal line EM_1 on the substrate 10 to serve as a capacitance compensation unit C.

[0054] Please refer to Figure 6, which shows the RC compensation design provided in the first embodiment of the present application. Specifically, in the first embodiment of the present application, the semiconductor routing includes a first sub-semiconductor routing 21 and a second sub-semiconductor routing 22. The first metal routing includes a first sub-metal routing 41 for forming a portion of the first scan signal line Scan_1, a second sub-metal routing 42 for forming a portion of an extension of the first scan signal line Scan_1, and a third sub-metal routing 43 for forming a portion of the first drive signal line EM_1. The second metal routing includes a fourth sub-metal routing 61 and a fifth sub-metal routing 62 for forming a portion of the first scan signal line Scan_1, a sixth sub-metal routing 63 for forming a portion of an extension of the first drive signal line EM_1, and a seventh sub-metal routing 64 for forming a portion of an extension of the first drive signal line EM_1.

[0055] Among them, the first sub-metal routing 41 is connected to the fourth sub-metal routing 61 through the first contact hole H1 penetrating the interlayer dielectric layer 50, the fourth sub-metal routing 61 is connected to the first sub-semiconductor routing 21 through the second contact hole H2, the first sub-semiconductor routing 21 is connected to the fifth sub-metal routing 62 through the third contact hole H3, and the fifth sub-metal routing 62 is connected to the second sub-metal routing 42 through the fourth contact hole H4; the first sub-semiconductor routing 21 serves as the resistance compensation unit R on the first scanning signal line Scan_1.

[0056] The third sub-metal routing 43 is connected to the sixth sub-metal routing 63 through the fifth contact hole H5 penetrating the interlayer dielectric layer 50, the sixth sub-metal routing 63 is connected to the second sub-semiconductor routing 22 through the sixth contact hole H6, and the second sub-semiconductor routing 22 is connected to the seventh sub-metal routing 64 through the seventh contact hole H7; the second sub-semiconductor routing 22 serves as the resistance compensation unit R on the first driving signal line EM_1.

[0057] The projection of the second sub-metal routing 42 on the substrate 10 at least partially overlaps with the projection of the seventh sub-metal routing 64 on the substrate 10, and the overlapping area of ​​the projections of the second sub-metal routing 42 and the seventh sub-metal routing 64 serves as a capacitance compensation unit C on the first scan signal line Scan_1, the first drive signal line EM_1 and / or the first reset signal line Vint_1.

[0058] Specifically, FIG6 shows a design for RC compensation of lateral traces. A resistance compensation unit R is formed by providing a first sub-semiconductor trace 21 and a second sub-semiconductor trace 22, and a capacitance compensation unit C is formed by the projected overlap area of ​​the second sub-metal trace 42 and the seventh sub-metal trace 64. The resistance of the resistance compensation unit R is related to the size and doping concentration of the first / second sub-semiconductor trace 21 / 22, while the capacitance compensation unit C is related to the overlap area of ​​the projected overlap area of ​​the second / seventh sub-metal trace 42 / 64 on the substrate 10. Therefore, by varying the length, width, and doping concentration of the first / second sub-semiconductor trace 21 / 22, the resistance of the resistance compensation unit R is adjusted, while by varying the projected overlap area of ​​the second / seventh sub-metal trace 42 / 64, the capacitance of the capacitance compensation unit C is adjusted, thereby designing compensation for the row in which the UDC region resides based on actual conditions.

[0059] In addition, in the first embodiment of the present application, a resistance compensation unit R on the first scanning signal line Scan_1 and the first driving signal line EM_1 is formed respectively by setting the first sub-semiconductor routing 21 and the second sub-semiconductor routing 22; and a capacitance compensation unit C on the first scanning signal line Scan_1 and the first driving signal line EM_1 is formed by the projected overlapping area of ​​the second sub-metal routing 42 and the seventh sub-metal routing 64, so that the wiring area can be reduced.

[0060] Continuing to refer to FIG. 5 , in the embodiment of the present application, the array substrate 100 further includes a passivation layer 70 and a third metal layer 80 .

[0061] The passivation layer 70 is disposed on a surface of the interlayer dielectric layer 50 facing away from the gate insulation layer 30 and covers the second metal layer 60 , so as to isolate the second metal layer 60 from the third metal layer 80 .

[0062] In which, the third metal layer 80 is arranged on the surface of the passivation layer 70 away from the interlayer dielectric layer 50, and at least part of the projection of the third metal layer 80 on the substrate 10 overlaps with at least part of the projection of the extension line of the first scanning signal line Scan_1 and / or the extension line of the first driving signal line EM_1 on the substrate 10, and at least part of the overlapping area of ​​the projection of the third metal layer 80 and the extension line of the first scanning signal line Scan_1 and / or the extension line of the first driving signal line EM_1 serves as a capacitance compensation unit C.

[0063] Please refer to Figure 7, which shows the RC compensation design provided in the second embodiment of the present application. Specifically, in the second embodiment of the present application, the semiconductor routing includes a third sub-semiconductor routing 23 and a fourth sub-semiconductor routing 24. The first metal routing includes an eighth sub-metal routing 44 for forming a portion of the first scan signal line Scan_1, a ninth sub-metal routing 45 for forming a portion of the first drive signal line EM_1, and a tenth sub-metal routing 46 for forming a portion of an extension of the first scan signal line Scan_1. The second metal routing includes an eleventh sub-metal routing 65 and a twelfth sub-metal routing 66 for forming a portion of the first scan signal line Scan_1, a thirteenth sub-metal routing 67 for forming a portion of the first drive signal line EM_1, and a fourteenth sub-metal routing 68 and a fifteenth sub-metal routing 69 for forming a portion of an extension of the first drive signal line EM_1. The third metal layer 80 includes a sixteenth sub-metal routing 81.

[0064] Among them, the eighth sub-metal routing 44 is connected to the eleventh sub-metal routing 65 through the eighth contact hole H8 penetrating the interlayer dielectric layer 50, the eleventh sub-metal routing 65 is connected to the third sub-semiconductor routing 23 through the ninth contact hole H9, the third sub-semiconductor routing 23 is connected to the twelfth sub-metal routing 66 through the tenth contact hole H10, and the twelfth sub-metal routing 66 is connected to the sixteenth sub-metal routing 81 through the eleventh contact hole H11; the third sub-semiconductor routing 23 serves as the resistance compensation unit R on the first scanning signal line Scan_1.

[0065] The ninth sub-metal routing 45 is connected to the thirteenth sub-metal routing 67 through the twelfth contact hole H12 penetrating the interlayer dielectric layer 50, the thirteenth sub-metal routing 67 is connected to the fourth sub-semiconductor routing 24 through the thirteenth contact hole H13, the fourth sub-semiconductor routing 24 is connected to the fourteenth sub-metal routing 68 through the fourteenth contact hole H14, and the fourteenth sub-metal routing 68 is connected to the tenth sub-metal routing 46 through the fifteenth contact hole H15; the fourth sub-semiconductor routing 24 serves as the resistance compensation unit R on the first driving signal line EM_1.

[0066] Moreover, the projection of the sixteenth sub-metal routing 81 on the substrate 10 at least partially overlaps with the projection of the tenth sub-metal routing 46 on the substrate 10 and / or the projection of the fifteenth sub-metal routing 69 on the substrate 10, and the overlapping area of ​​the projections of the sixteenth sub-metal routing 81 and the tenth sub-metal routing 46 and / or the fifteenth sub-metal routing 69 serves as a capacitance compensation unit C on the first scan signal line Scan_1, the first drive signal line EM_1 and / or the first reset signal line Vint_1.

[0067] Specifically, Figure 7 shows another RC compensation design for lateral wiring, in which a resistance compensation unit R is formed by the third sub-semiconductor wiring 23 and the fourth sub-semiconductor wiring 24, and a capacitance compensation unit C is formed by overlapping the sixteenth sub-metal wiring 81 with the tenth sub-metal wiring 46 and / or the fifteenth sub-metal wiring 69, and the resistance value of the resistance compensation unit R is related to the size and doping concentration of the third sub-semiconductor wiring 23 / the fourth sub-semiconductor wiring 24; the capacitance value of the capacitance compensation unit C is related to the overlapping area of ​​the projected overlapping area of ​​the sixteenth sub-metal wiring 81 and the tenth sub-metal wiring 46 and / or the fifteenth sub-metal wiring 69 on the substrate 10. Therefore, the resistance value of the resistance compensation unit R is changed by changing the length, width and doping concentration of the third sub-semiconductor routing 23 / the fourth sub-semiconductor routing 24, and the capacitance value of the resistance compensation unit R is changed by changing the overlapping area of ​​the projected overlapping area of ​​the sixteenth sub-metal routing 81 and the tenth sub-metal routing 46 and / or the fifteenth sub-metal routing 69 on the substrate 10, so as to design the compensation of the row where the UDC area is located according to actual conditions.

[0068] In addition, in the second embodiment of the present application, a resistance compensation unit R is formed on the first scanning signal line Scan_1 and the first driving signal line EM_1 respectively by setting a third sub-semiconductor routing 23 and a fourth sub-semiconductor routing 24; and a capacitance compensation unit C is formed on the first scanning signal line Scan_1 and the first driving signal line EM_1 by the projected overlapping area of ​​the sixteenth sub-metal routing 81 and the tenth sub-metal routing 46 and / or the fifteenth sub-metal routing 69, so that the wiring area can be reduced.

[0069] Furthermore, in the second embodiment of the present application, the fifteenth sub-metal trace 69 is also connected to a preset potential. Specifically, the preset potential is a fixed potential. By setting the fifteenth sub-metal trace 69 to be connected to the preset potential, the anti-interference capability of the capacitor formed by the fifteenth sub-metal trace 69 and the sixteenth sub-metal trace 81 can be improved, as can the anti-interference capability of the capacitor formed by the fifteenth sub-metal trace 69 and the tenth sub-metal trace 46, thereby reducing signal interference between signals.

[0070] In the first and / or second embodiments, the resistance of the resistor compensation unit R is less than or equal to 1 kΩ, and the capacitance of the capacitor compensation unit C is less than or equal to 10 pF. Of course, in other embodiments, based on the different resolutions of different display panels, the resistance of the resistor compensation unit R and the capacitance of the capacitor compensation unit C can be set according to actual conditions.

[0071] Specifically, the above first embodiment and / or second embodiment are only examples and can be designed according to actual needs.

[0072] 5 , in this embodiment, the array substrate 100 further includes a planarization layer 91 , an anode layer 92 , a pixel definition layer 93 and a support layer 94 .

[0073] Among them, the planarization layer 91 is arranged on the side of the passivation layer 70 away from the interlayer dielectric layer 50 and covers the third metal layer 80; the anode layer 92 is arranged on the side of the planarization layer 91 away from the passivation layer 70; and the anode layer 92 is connected to the source / drain through a contact hole; the pixel definition layer 93 is arranged on the side of the planarization layer 91 away from the passivation layer 70, wherein the pixel definition layer 93 has an opening X1 for accommodating the light-emitting device, and at least part of the anode layer 92 is exposed from the opening X1; the support layer 94 is arranged on the side of the pixel definition layer 93 away from the planarization layer 91.

[0074] Specifically, an embodiment of the present application provides an array substrate 100 in which a resistance compensation unit R is connected in series with a first scan signal line Scan_1, a first drive signal line EM_1, and a first reset signal line Vint_1. The resistance compensation unit R is used to compensate for the resistance difference between n rows of pixel cells P in a UDC region and other rows of pixel cells P. Furthermore, an extension of the first scan signal line Scan_1 and an extension of the first drive signal line EM_1 have a projected overlapping region, at least part of which constitutes a capacitance compensation unit C. Furthermore, the first scan signal line Scan_1, the first drive signal line EM_1, and the first reset signal line Vint_1 are all connected in parallel with the capacitance compensation unit C. The capacitance compensation unit C is used to compensate for the capacitance difference between n rows of pixel cells P in the UDC region and other rows of pixel cells P, thereby improving the display difference between n rows of pixel cells P in the UDC region and other regions.

[0075] Referring to Figure 8 , which is a schematic structural diagram of an embodiment of a display panel provided in this application, this application also provides a display panel 300 comprising an array substrate 100 and an opposing substrate 200 . The array substrate 100 is any of the array substrates 100 provided in the aforementioned embodiments; the opposing substrate is disposed on one side of the array substrate 100 .

[0076] Among them, the opposing substrate 200 can serve as a packaging cover for the display panel 300 to prevent moisture, dust, etc. from entering the display panel 300 and provide a certain degree of rigidity; further, the opposing substrate 200 can also serve as a color filter substrate for the display panel 300.

[0077] The above is only an implementation method of the present application and does not limit the scope of patent protection of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of this application, or directly or indirectly applied in other related technical fields, are also included in the scope of patent protection of the present application.

Claims

1. An array substrate, comprising a plurality of pixel units arranged in an array, scanning signal lines and driving signal lines connecting a plurality of rows of the pixel units, and reset signal lines connecting a plurality of columns of the pixel units; wherein: The plurality of pixel units include a first pixel unit disposed in a first display area and a second pixel unit disposed in a second display area, at least part of the first pixel units and at least part of the second pixel units are arranged in the same row and connected through a first scanning signal line and a first driving signal line, at least part of the first pixel units and at least part of the second pixel units are arranged in the same column and connected through a first reset signal line; the transmittance of the first display area is greater than the transmittance of the second display area; Among them, a resistance compensation unit is connected in series on the first scanning signal line, the first driving signal line and the first reset signal line, and the extension line of the first scanning signal line and the extension line of the first driving signal line have a projected overlapping area, at least part of the projected overlapping area constitutes a capacitance compensation unit, and the first scanning signal line, the first driving signal line and the first reset signal line are all connected in parallel with the capacitance compensation unit.

2. The array substrate according to claim 1, wherein: The array substrate comprises: substrate; A semiconductor layer, disposed on the first surface of the substrate, wherein the semiconductor layer includes a first semiconductor layer for forming the first pixel unit, a second semiconductor layer for forming the second pixel unit, and a semiconductor trace for forming the resistance compensation unit; A gate insulating layer, disposed on a surface of the semiconductor layer facing away from the substrate; A first metal layer is disposed on a surface of the gate insulating layer away from the substrate; wherein the first metal layer includes a first gate for forming a first pixel unit, a second gate for forming a second pixel unit, and a first metal routing for forming part of the first scanning signal line and its extension line and part of the first driving signal line and its extension line; an interlayer dielectric layer, disposed on the first surface of the substrate and covering the semiconductor layer and the first metal layer; A second metal layer is arranged on a surface of the interlayer dielectric layer away from the gate insulating layer, the second metal layer comprising a first source and a first drain which are insulated and used to form the first pixel unit, a second source and a second drain which are insulated and used to form the second pixel unit, and a second metal routing which is used to form part of the first scanning signal line and its extension line and part of the first driving signal line and its extension line; Wherein, at least a portion of a projection of an extension line of the first scanning signal line on the substrate overlaps with at least a portion of a projection of an extension line of the first driving signal line on the substrate to serve as the capacitance compensation unit.

3. The array substrate according to claim 2, wherein: The semiconductor routing includes a first sub-semiconductor routing and a second sub-semiconductor routing; The first metal routing includes a first sub-metal routing for forming a portion of the first scanning signal line, a second sub-metal routing for forming a portion of an extension line of the first scanning signal line, and a third sub-metal routing for forming a portion of the first driving signal line; The second metal routing includes a fourth sub-metal routing and a fifth sub-metal routing for forming a portion of the first scanning signal line, a sixth sub-metal routing for forming a portion of an extension line of the first driving signal line, and a seventh sub-metal routing for forming a portion of an extension line of the first driving signal line; Wherein, the first sub-metal routing is connected to the fourth sub-metal routing through a first contact hole penetrating the interlayer dielectric layer, the fourth sub-metal routing is connected to the first sub-semiconductor routing through a second contact hole, the first sub-semiconductor routing is connected to the fifth sub-metal routing through a third contact hole, and the fifth sub-metal routing is connected to the second sub-metal routing through a fourth contact hole; the first sub-semiconductor routing serves as the resistance compensation unit on the first scanning signal line; The third sub-metal routing is connected to the sixth sub-metal routing through a fifth contact hole penetrating the interlayer dielectric layer, the sixth sub-metal routing is connected to the second sub-semiconductor routing through a sixth contact hole, and the second sub-semiconductor routing is connected to the seventh sub-metal routing through a seventh contact hole; the second sub-semiconductor routing serves as the resistance compensation unit on the first driving signal line; And the projection of the second sub-metal routing on the substrate at least partially overlaps with the projection of the seventh sub-metal routing on the substrate, and the overlapping area of ​​the projection of the second sub-metal routing and the seventh sub-metal routing serves as a capacitance compensation unit on the first scanning signal line, the first driving signal line and / or the first reset signal line.

4. The array substrate according to claim 2, wherein: The array substrate further includes: A passivation layer, disposed on a surface of the interlayer dielectric layer away from the gate insulating layer and covering the second metal layer; A third metal layer is arranged on the surface of the passivation layer away from the interlayer dielectric layer, and at least part of the projection of the third metal layer on the substrate overlaps with at least part of the projection of the extended line of the first scanning signal line and / or the extended line of the first driving signal line on the substrate, and at least part of the overlapping area of ​​the projection of the third metal layer and the extended line of the first scanning signal line and / or the extended line of the first driving signal line serves as the capacitance compensation unit.

5. The array substrate according to claim 4, wherein: The semiconductor routing includes a third sub-semiconductor routing and a fourth sub-semiconductor routing; The first metal routing includes an eighth sub-metal routing for forming part of the first scanning signal line, a ninth sub-metal routing for forming part of the first driving signal line, and a tenth sub-metal routing for forming part of the extension line of the first scanning signal line; The second metal wiring includes an eleventh sub-metal wiring and a twelfth sub-metal wiring for forming part of the first scan signal line, a thirteenth sub-metal wiring for forming part of the first drive signal line, and a and a fourteenth sub-metal wiring and a fifteenth sub-metal wiring for forming a portion of an extension line of the first driving signal line; The third metal layer includes a sixteenth sub-metal trace; The eighth sub-metal routing is connected to the eleventh sub-metal routing through an eighth contact hole penetrating the interlayer dielectric layer, the eleventh sub-metal routing is connected to the third sub-semiconductor routing through a ninth contact hole, the third sub-semiconductor routing is connected to the twelfth sub-metal routing through a tenth contact hole, and the twelfth sub-metal routing is connected to the sixteenth sub-metal routing through an eleventh contact hole; the third sub-semiconductor routing serves as the resistance compensation unit on the first scanning signal line; The ninth sub-metal routing is connected to the thirteenth sub-metal routing through the twelfth contact hole penetrating the interlayer dielectric layer, the thirteenth sub-metal routing is connected to the fourth sub-semiconductor routing through the thirteenth contact hole, the fourth sub-semiconductor routing is connected to the fourteenth sub-metal routing through the fourteenth contact hole, and the fourteenth sub-metal routing is connected to the tenth sub-metal routing through the fifteenth contact hole; the fourth sub-semiconductor routing serves as the resistance compensation unit on the first driving signal line; Furthermore, a projection of the sixteenth sub-metal routing on the substrate at least partially overlaps with a projection of the tenth sub-metal routing on the substrate and / or a projection of the fifteenth sub-metal routing on the substrate, and an overlapping area of ​​the projections of the sixteenth sub-metal routing and the tenth sub-metal routing and / or the fifteenth sub-metal routing serves as a capacitance compensation unit on the first scan signal line, the first drive signal line and / or the first reset signal line.

6. The array substrate according to claim 5, wherein: The fifteenth sub-metal wiring is also connected to a preset potential.

7. The array substrate according to claim 4, wherein: The resistance value of the resistance compensation unit is related to the size and doping concentration of the semiconductor wiring; The capacitance compensation unit is related to an overlapping area of ​​a projection overlap region of an extension line of the first scanning signal line and an extension line of the first driving signal line on the substrate; Wherein, the resistance value of the resistance compensation unit is less than or equal to 1KΩ; the capacitance value of the capacitance compensation unit is less than or equal to 10pF.

8. The array substrate according to claim 1, wherein: The density of the first pixel units in the first display area is the same as the density of the second pixel units in the second display area, and the size of the first pixel units is smaller than the size of the second pixel units.

9. The array substrate according to claim 1, wherein: The resistance compensation unit and the capacitance compensation unit are both arranged in the first display area; Or, the resistance compensation unit and the capacitance compensation unit are both arranged in the second display area; Or, some of the resistance compensation units are arranged in the first display area, and other parts of the resistance compensation units are arranged in the second display area; and some of the capacitance compensation units are arranged in the first display area, Another part of the capacitance compensation unit is disposed in the second display area.

10. A display panel, wherein: include: An array substrate, wherein the array substrate is the array substrate according to any one of claims 1 to 9; The counter substrate is arranged on one side of the array substrate.

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