Circuit board and semiconductor package comprising same

Abstract

A circuit board according to an embodiment includes a first circuit layer; a first insulating layer disposed on the first circuit layer; a second circuit layer disposed on the first insulating layer; and a second insulating layer disposed on the second circuit layer. The first circuit layer includes a first circuit pattern provided along the circumferential direction of the outer surface of the first insulating layer at a position closest to the outer surface of the first insulating layer. The second circuit layer includes a second circuit pattern provided along the circumferential direction of the outer surface of the second insulating layer at a position closest to the outer surface of the second insulating layer. A first separation distance in the horizontal direction between the outer surface of the first insulating layer and the first circuit pattern is different from a second separation distance in the horizontal direction between the outer surface of the second insulating layer and the second circuit pattern.

Description

Circuit boards and semiconductor packages including the same

[0001] The embodiment relates to a circuit board and a semiconductor package board including the same.

[0002] As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to accommodate a greater number of semiconductor devices on a limited-size semiconductor package substrate. However, conventional semiconductor packages typically consist of a single semiconductor device, limiting their ability to achieve desired performance.

[0003] Accordingly, semiconductor packages that utilize multiple substrates to arrange multiple semiconductor devices have recently been developed. These semiconductor packages have a structure in which multiple semiconductor devices are connected to each other horizontally and / or vertically on the substrate. Accordingly, these semiconductor packages have the advantage of efficiently utilizing the mounting area of ​​the semiconductor devices and enabling high-speed signal transmission through short signal transmission paths between the semiconductor devices.

[0004] In addition, semiconductor packages applied to products that provide the Internet of Things (IoT), autonomous vehicles, and high-performance servers are expanding their concept to semiconductor chiplets as the number of semiconductor elements and / or the size of each semiconductor element increases in line with the trend toward high integration, or as the functional parts of semiconductor elements are divided.

[0005] Meanwhile, as the number of semiconductor devices and / or semiconductor chiplets mounted on a semiconductor package increases, the area of ​​the semiconductor package is also increasing. Furthermore, as the area of ​​the semiconductor package increases, the circuit board tends to warp more. If the circuit board warps significantly, the semiconductor devices may not be stably attached to the circuit board. For example, the circuit board has pad portions that are connected to the terminals of the semiconductor devices. If the circuit board warps significantly in a specific direction, a deviation in the height of the multiple pad portions may occur, preventing the semiconductor devices from being stably attached.

[0006] Additionally, as the number of terminals on a semiconductor device increases, or the functions required for the semiconductor device increase and / or performance improves, the amount of power required by the semiconductor device may also increase. Consequently, conventional semiconductor packages may experience problems such as insufficient power supplied to the semiconductor device and connecting components, such as bridges, resulting in instability in the operation of the semiconductor device or connecting components.

[0007] Therefore, there is a need for a method that can provide stable power supply to semiconductor elements or connecting members while alleviating warpage of the circuit board.

[0008] The embodiment provides a circuit board and semiconductor package of a novel structure.

[0009] In addition, the embodiment provides a circuit board having a structure capable of alleviating bending in a specific direction and a semiconductor package including the same.

[0010] In addition, the embodiment provides a circuit board capable of stably supplying power to a connecting member and / or a semiconductor element, and a semiconductor package including the same.

[0011] The technical tasks to be achieved in the proposed embodiment are not limited to the technical tasks mentioned above, and other technical tasks not mentioned can be clearly understood by a person having ordinary skill in the technical field to which the proposed embodiment belongs from the description below.

[0012] A circuit board according to an embodiment comprises: a first circuit layer; a first insulating layer disposed on the first circuit layer; a second circuit layer disposed on the first insulating layer; and a second insulating layer disposed on the second circuit layer; wherein the first circuit layer comprises a first circuit pattern provided along a circumferential direction of an outer surface of the first insulating layer at a position closest to an outer surface of the first insulating layer, and the second circuit layer comprises a second circuit pattern provided along a circumferential direction of an outer surface of the second insulating layer at a position closest to the outer surface of the second insulating layer, wherein a first horizontal distance between the first circuit patterns from the outer surface of the first insulating layer is different from a second horizontal distance between the second circuit patterns from the outer surface of the second insulating layer.

[0013] Additionally, the first insulating layer is provided to surround a side surface of the first circuit pattern, and the second insulating layer is provided to surround a side surface of the second circuit pattern.

[0014] In addition, the lower surface of the first insulating layer is positioned on the same plane as the lower surface of the first circuit pattern, and the lower surface of the second insulating layer is positioned on the same plane as the lower surface of the second circuit pattern.

[0015] Additionally, the first circuit pattern has a first width along the circumferential direction of the outer surface of the first insulating layer, and the second circuit pattern has a second width along the circumferential direction of the outer surface of the second insulating layer.

[0016] Additionally, the first separation distance is greater than the second separation distance, and the first width is smaller than the second width.

[0017] Additionally, the first separation distance is smaller than the second separation distance, and the first width is larger than the second width.

[0018] Additionally, each of the first and second circuit patterns has a closed loop shape.

[0019] In addition, the first circuit pattern includes a first portion and a second portion that are provided along the circumferential direction of the outer surface of the first insulating layer and are spaced apart from each other, and the second circuit pattern includes a third portion and a fourth portion that are provided along the circumferential direction of the outer surface of the second insulating layer and are spaced apart from each other.

[0020] In addition, the circuit board further includes a third circuit layer disposed on the second insulating layer; and a protective layer disposed on the third circuit layer, wherein the third circuit layer includes a third circuit pattern provided along a circumferential direction of an outer surface of the protective layer at a position closest to an outer surface of the protective layer, and a third horizontal separation distance between the third circuit pattern and the outer surface of the protective layer is different from the first and second separation distances.

[0021] In addition, the circuit board further includes a first via electrode disposed between the first circuit pattern and the second circuit pattern; and a second via electrode disposed between the second circuit pattern and the third circuit pattern, wherein a fourth horizontal distance between the first via electrodes from an outer surface of the first insulating layer is different from a fifth horizontal distance between the second via electrodes from an outer surface of the second insulating layer.

[0022] Additionally, the horizontal width of the first via electrode is different from the horizontal width of the second via electrode.

[0023] Additionally, the fourth separation distance is greater than the fifth separation distance, and the horizontal width of the first via electrode is smaller than the horizontal width of the second via electrode.

[0024] Additionally, the fourth separation distance is smaller than the fifth separation distance, and the horizontal width of the first via electrode is larger than the horizontal width of the second via electrode.

[0025] In addition, the circuit board further includes a core layer disposed on a lower surface of the first insulating layer; a fourth circuit layer disposed on a lower surface of the core layer; a third insulating layer disposed on a lower surface of the fourth circuit layer; a fifth circuit layer disposed on a lower surface of the third insulating layer; and a fourth insulating layer disposed on a lower surface of the fifth circuit layer, wherein the fourth circuit layer includes a fourth circuit pattern provided along a circumferential direction of an outer surface of the third insulating layer at a position closest to an outer surface of the third insulating layer, and the fifth circuit layer includes a fifth circuit pattern provided along a circumferential direction of an outer surface of the fourth insulating layer at a position closest to an outer surface of the fourth insulating layer, and a fourth horizontal separation distance between the fourth circuit patterns from the outer surface of the third insulating layer is different from a fifth horizontal separation distance between the fifth circuit patterns from the outer surface of the fourth insulating layer.

[0026] Additionally, the first separation distance is greater than the second separation distance, and the fourth separation distance is less than the fifth separation distance.

[0027] Additionally, the first separation distance is smaller than the second separation distance, and the fourth separation distance is larger than the fifth separation distance.

[0028] In addition, the circuit board further includes a connecting member arranged on the core layer, the core layer having a through hole extending through the upper surface and the lower surface, and the connecting member is arranged within the through hole.

[0029] Additionally, the connecting member includes a plurality of pad portions, and the first circuit layer further includes a connecting pattern connecting the first circuit pattern and at least one of the plurality of pad portions.

[0030] In addition, according to another embodiment, a circuit board includes a first circuit layer; a first insulating layer disposed on the first circuit layer; a second circuit layer disposed on the first insulating layer; and a second insulating layer disposed on the second circuit layer; wherein the first circuit layer includes a first circuit pattern provided along a circumferential direction of an outer surface of the first insulating layer at a position closest to an outer surface of the first insulating layer and having a first width in a horizontal direction, and wherein the second circuit layer includes a second circuit pattern provided along a circumferential direction of an outer surface of the second insulating layer at a position closest to an outer surface of the second insulating layer and having a second width in the horizontal direction, wherein the first width is different from the second width.

[0031] The circuit board of the embodiment can solve the problem of insufficient power supplied to the semiconductor element and / or connecting member by enabling a stable power supply to the semiconductor element and / or connecting member, thereby improving the operating characteristics of the semiconductor element and / or connecting member.

[0032] By way of example, a circuit board of an embodiment includes a plurality of circuit layers stacked in a vertical direction, and a plurality of insulating layers disposed on the plurality of circuit layers. The plurality of circuit layers have circuit patterns disposed closest to the outer surfaces of each of the plurality of insulating layers. At this time, the circuit patterns closest to the outer surfaces of each insulating layer can be used as power patterns that supply power to semiconductor devices and / or connecting members disposed on the circuit board. At this time, each circuit layer of the circuit board has a signal pattern in addition to the power pattern. At this time, the power pattern must be disposed far from the signal pattern. This is because when the power pattern is located adjacent to the signal pattern, mutual interference occurs, resulting in transmission loss of a signal transmitted through the signal pattern. In contrast, the circuit patterns functioning as the power patterns of the embodiment can be disposed closest to the outer surfaces of each insulating layer, thereby allowing the width to be increased without affecting the signal pattern. At this time, if the width of the circuit pattern used as the power pattern increases, the intensity of power that can be transmitted through each circuit pattern can increase, thereby enabling a stable power supply to the semiconductor element and / or connecting member.

[0033] Additionally, the circuit patterns used as power patterns can improve the rigidity of the circuit board while supplying power to the semiconductor devices and / or connecting members. That is, the circuit patterns used as power patterns are arranged along the circumferential direction of the outer surface of each insulating layer, thereby improving the rigidity of the circuit board. This can improve the positional alignment between the via electrodes and the circuit layer during the circuit board manufacturing process, thereby enhancing the electrical and / or mechanical reliability of the circuit board.

[0034] In particular, the circuit board includes a first circuit layer, a first insulating layer disposed on the first circuit layer, a second circuit layer disposed on the first insulating layer, and a second insulating layer disposed on the second circuit layer. At this time, the first circuit layer includes a first circuit pattern provided along the circumferential direction of the outer surface of the first insulating layer at a position closest to the outer surface of the first insulating layer. Furthermore, the second circuit layer includes a second circuit pattern provided along the circumferential direction of the outer surface of the second insulating layer at a position closest to the outer surface of the second insulating layer. At this time, a first horizontal separation distance between the first circuit patterns from the outer surface of the first insulating layer is different from a second horizontal separation distance between the second circuit patterns from the outer surface of the second insulating layer. That is, the embodiment makes the first separation distance and the second separation distance different, thereby alleviating warpage of the circuit board, reducing unevenness in the height of a pad portion for connection with a semiconductor element, and improving connection reliability between the semiconductor element and the circuit board. For example, when the circuit board is concavely bent in the smile direction, the first separation distance is greater than the second separation distance, and when the circuit board is convexly bent in the cry direction, the first separation distance is less than the second separation distance. Through this, the embodiment can prevent the circuit board from being significantly bent in a specific direction, and can ensure that the semiconductor element is stably positioned on the circuit board. Through this, the embodiment can ensure that the semiconductor element operates stably, and the semiconductor package including the same can operate stably. Furthermore, the embodiment can ensure that a product such as a sub to which the semiconductor package is applied operates stably, and thereby improve product reliability.

[0035] In addition, the horizontal width of the first circuit pattern may be different from the horizontal width of the second circuit pattern. That is, the embodiment can adjust the horizontal width of the first circuit pattern and the horizontal width of the second circuit pattern depending on the direction in which the circuit board is bent. For example, when the circuit board is bent concavely in the smile direction, the horizontal width of the first circuit pattern is made smaller than the horizontal width of the second circuit pattern, and when the circuit board is bent convexly in the cry direction, the horizontal width of the first circuit pattern is made larger than the horizontal width of the second circuit pattern. Through this, the embodiment can further alleviate the circuit board from being bent significantly in a specific direction, further reduce the unevenness in the height of the pad portion for connection with the semiconductor element, and further improve the connection reliability between the semiconductor element and the circuit board.

[0036] In addition, the circuit board further includes a first via electrode disposed between the first circuit board and the second circuit pattern, and a second via electrode disposed between the second circuit pattern and the third circuit pattern. At this time, a distance between the outer surface of the first insulating layer and the first via electrode and a distance between the outer surface of the second insulating layer and the second via electrode are different from each other. Furthermore, a horizontal width of the first via electrode and a horizontal width of the second via electrode are different from each other. That is, depending on the direction in which the circuit board is bent, a distance between the first via electrode and the outer surface of the first insulating layer and a distance between the second via electrode and the outer surface of the second insulating layer may be different from each other, or a horizontal width of the first via electrode and a horizontal width of the second via electrode may be different from each other. Through this, the embodiment can further alleviate the circuit board from being significantly bent in a specific direction, further reduce the unevenness in the height of the pad portion for connection with the semiconductor element, and further improve the connection reliability between the semiconductor element and the circuit board.

[0037] Figure 1 is a cross-sectional view illustrating a circuit board according to the first embodiment.

[0038] Fig. 2 is a plan view showing the first circuit layer arranged on the lower surface of the first insulating layer of Fig. 1.

[0039] Fig. 3 is a plan view showing a second circuit layer arranged on the lower surface of the second insulating layer of Fig. 1.

[0040] FIG. 4 is a cross-sectional view illustrating via electrodes located closest to the outer surface of the circuit board of FIG. 1.

[0041] FIG. 5 is a plan view showing a modified example of the first circuit pattern of the first circuit layer and the second circuit pattern of the second circuit layer shown in FIGS. 2 and 3.

[0042] Fig. 6 is a cross-sectional view showing a modified example of via electrodes located closest to the outer surface of the circuit board of Fig. 1.

[0043] Fig. 7 is a cross-sectional view illustrating a circuit board according to the second embodiment.

[0044] Figure 8 is a drawing illustrating a circuit board according to the third embodiment.

[0045] Fig. 9 is a plan view showing the connection structure of the first circuit pattern and connecting member of the circuit board illustrated in Fig. 8.

[0046] Fig. 10 is a drawing showing a semiconductor package according to an embodiment.

[0047] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

[0048] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0049] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by those of ordinary skill in the technical field to which the present invention pertains, unless explicitly and specifically defined and described, and commonly used terms, such as terms defined in a dictionary, may be interpreted in consideration of the contextual meaning of the relevant technology. In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention.

[0050] In this specification, singular forms may also include plural forms unless specifically stated otherwise in the phrase, and when it is described as “A and / or at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C. In addition, when describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used.

[0051] These terms are only intended to distinguish the component from other components, and are not intended to limit the nature, order, or sequence of the component by the term. In addition, when a component is described as being "connected," "coupled," or "connected" to another component, it may include not only cases where the component is directly connected, coupled, or connected to the other component, but also cases where the component is "connected," "coupled," or "connected" by another component between the component and the other component.

[0052] Additionally, when described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Furthermore, when expressed as "above" or "below", it may include the meaning of the downward direction as well as the upward direction based on one component.

[0053] The terminology used in this application is only used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, it should be understood that the terms "comprise" or "have" indicate the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0054] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and shall not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0055]

[0056] Hereinafter, embodiments will be described in detail with reference to the attached drawings. Regardless of the drawing symbols, identical or corresponding components are given the same reference numbers, and redundant descriptions thereof will be omitted.

[0057]

[0058] Before describing the embodiment, an electronic device (not shown) to which the semiconductor package of the embodiment is applied will be briefly described. The electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive device, etc. However, the electronic device is not limited thereto, and it goes without saying that the electronic device may be any other electronic device that processes data.

[0059] An electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to a semiconductor package of the embodiment. Furthermore, the semiconductor package includes a circuit board, a semiconductor chip, a bonding portion for electrically connecting the semiconductor element and the circuit board, a resin portion for filling the space between the semiconductor element and the circuit board, and a molding portion for entirely enclosing the semiconductor element.

[0060] Semiconductor devices may include active and / or passive components and may have various functions. Active devices may be in the form of integrated circuits (ICs) in which hundreds to millions of transistors are integrated into a single semiconductor device, and may be, for example, logic chips, memory chips, etc. For example, the logic chip may be an application processor (AP) device including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), etc., or a set of devices including a specific combination of the above. The memory chip may be a stacked memory such as HBM. In addition, the memory chip may include a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), or a flash memory.

[0061] The semiconductor package of the embodiment may be any one of a CSP (Chip Scale Package), an FC-CSP (Flip Chip-Chip Scale Package), an FC-BGA (Flip Chip Ball Grid Array), a POP (Package On Package), and a SIP (System In Package), but is not limited thereto.

[0062]

[0063] FIG. 1 is a cross-sectional view illustrating a circuit board according to a first embodiment, FIG. 2 is a plan view illustrating a first circuit layer disposed on a lower surface of a first insulating layer of FIG. 1, FIG. 3 is a plan view illustrating a second circuit layer disposed on a lower surface of a second insulating layer of FIG. 1, FIG. 4 is a cross-sectional view illustrating via electrodes positioned closest to an outer surface of the circuit board of FIG. 1, FIG. 5 is a plan view illustrating a modified example of a first circuit pattern of the first circuit layer and a second circuit pattern of the second circuit layer illustrated in FIGS. 2 and 3, FIG. 6 is a cross-sectional view illustrating a modified example of via electrodes positioned closest to an outer surface of the circuit board of FIG. 1, FIG. 7 is a cross-sectional view illustrating a circuit board according to a second embodiment, FIG. 8 is a diagram illustrating a circuit board according to a third embodiment, FIG. 9 is a plan view illustrating a connection structure of a first circuit pattern and a connection member of the circuit board illustrated in FIG. 8, and FIG. 10 is a cross-sectional view illustrating a semiconductor package according to an embodiment. It's a drawing.

[0064] Referring to FIG. 1, the circuit board (100) includes a core layer (101), a first build-up layer (102) disposed on one surface of the core layer (101), and a second build-up layer (103) disposed on the other surface of the core layer (101). Here, the meaning of being disposed on one surface and the other surface should not be understood only as a configuration in direct contact with the one surface and the other surface, but should also be understood as having another configuration between the one surface and the first build-up layer (102), and between the other surface and the second build-up layer (103).

[0065] The core layer (101) is composed of a resin such as epoxy resin or BT (bismaleimide triazine) and a reinforcing material such as glass fiber, and has the function of improving the rigidity of the circuit board (100).

[0066] As the number of terminals of semiconductor devices arranged on a recent circuit board (100) increases, wiring becomes more complex, and accordingly, the thickness of the first and second build-up layers (102, 103) is increasing. Accordingly, the core layer (101) of the present embodiment may have a thickness of 120 μm to 1200 μm in order to improve the overall rigidity of the circuit board (100) and prevent excessive signal loss. A via hole penetrating one surface and the other surface may be formed in the core layer (101). The via hole of the core layer (101) may be formed using a mechanical drilling process or a CO2 laser, etc. When a via hole of the core layer (101) is formed using a mechanical drill, the slope of the inner wall of the via hole may be perpendicular to one surface and / or the other surface of the core layer (101), and when a via hole of the core layer (101) is formed using a CO2 laser, the inner wall of the via hole may have a plurality of concave portions and / or convex portions that are alternately stacked along the vertical direction. Here, the concave portion may mean a concave region that is concave in a direction away from the horizontal center of the via hole provided in the core layer (101), and the convex portion may mean a region that protrudes and / or is convex toward the horizontal center of the via hole provided in the core layer (101). In addition, the concave portions and the convex portions may be alternately provided on the inner wall forming the via hole of the core layer (101) along the vertical direction. Here, being alternately provided may mean that the convex portion is provided between a plurality of concave portions, and that the concave portion is provided between a plurality of convex portions. In the case of via holes formed using a mechanical drilling process, the path for transmitting electrical signals is shortened, which may be advantageous for electrical characteristics, but the process cost may increase. In addition, in the case of forming concave and convex portions on the inner wall of the via hole using a CO2 laser, the thickness of the core via electrode (118) provided on the inner wall of the via hole can be thickened in a subsequent process, which may have the advantage of lowering the impedance and lowering the process cost.Accordingly, the processing method of the via hole provided in the core layer (101) can be freely and selectively used depending on the application field of the semiconductor package.

[0067] A core via electrode (120) may be placed within the via hole of the core layer (101). The core via electrode (120) functions to electrically connect the first build-up layer (102) and the second build-up layer (103). Therefore, it is desirable for the core via electrode (120) to densely fill the via hole for resistance or heat dissipation. However, when the thickness of the core layer (101) becomes thick as described above, it may become difficult for the core via electrode (120) to densely fill the via hole. For example, when attempting to fill the via hole provided in the thick core layer (101) as described above according to the plating process, a void may occur within the core via electrode (120). The void expands due to heat generated during the operation of the semiconductor package, which becomes a factor that lowers the mechanical reliability of the circuit board. Accordingly, a core via electrode (120) having a predetermined thickness is arranged on the inner wall of the via hole of the core layer (101). The thickness of the core via electrode (120) refers to the thickness in the horizontal direction perpendicular thereto, not the thickness in the vertical direction in which the first build-up layer (102), the core layer (101), and the second build-up layer (103) are laminated. The thickness of the core via electrode (120) may be arranged to have a thickness of 5 μm to 20 μm in order to prevent a voltage drop that occurs as the thickness of the core layer (101) increases and to prevent the occurrence of voids. The inner side of the core via electrode (120) is difficult to densely fill with metal through a process such as plating, resulting in the creation of empty spaces. The empty spaces may cause a problem in that it is difficult to evenly arrange the first build-up layer (102) when laminating the first build-up layer (102).

[0068] Accordingly, the insulating member (121) can be placed on the inner side of the core via electrode (120), thereby ensuring the flatness of the core layer (101). For example, the insulating member (121) can be placed in the via hole of the core layer (101), and the core via electrode (120) can surround the side of the insulating member (121) and be placed between the inner wall of the via hole and the outer surface of the insulating member (121).

[0069] The upper surface of the insulating member (121) may be on the same plane as the upper surface of the core layer (101), or may be arranged closer to the first build-up layer (102) in the vertical direction than the upper surface of the core layer (101). The lower surface of the insulating member (121) may be on the same plane as the lower surface of the core layer (101), or may be arranged closer to the second build-up layer (103) in the vertical direction than the lower surface of the core layer (101). This can be freely designed to solve the flatness when laminating the first build-up layer (102) and the second build-up layer (103), or to secure the flatness of the first circuit layer (110) and / or the third circuit layer (112) to be described later.

[0070] A first build-up layer (102) is arranged on one side of the core layer (101). The first build-up layer (102) includes a plurality of insulating layers (104, 105), a plurality of circuit layers (110, 111, 112), a plurality of via electrodes (116, 117), and a first protective layer (108).

[0071] The plurality of circuit layers (110, 111, 112) of the first build-up layer (102) may include a first circuit layer (110) that is most adjacent to the core layer (101) in the vertical direction, a second circuit layer (111) that is positioned further from the core layer (101) in the vertical direction than the first circuit layer (110), and a third circuit layer (112) that is positioned further from the core layer (101) in the vertical direction than the second circuit layer (111). The first to third circuit layers (110, 111, 112) may function to electrically connect to semiconductor elements arranged on the circuit board (100). Each of the first to third circuit layers (110, 111, 112) may be freely designed in consideration of impedance.

[0072] Additionally, via electrodes (116, 117) may be arranged to connect the first to third circuit layers (110, 111, 112), respectively. For example, the first via electrode (116) is arranged between the first circuit layer (110) and the second circuit layer (111), and the second via electrode (117) is arranged between the second circuit layer (111) and the third circuit layer (112), thereby electrically connecting the first to third circuit layers (110, 111, 112).

[0073] The first and second via electrodes (116, 117) can be formed simultaneously in the process of arranging the first to third circuit layers (110, 111, 112). For example, in the process of arranging the second circuit layer (111) on the first circuit layer (110), a through hole can be formed in the first insulating layer (104) to expose a portion of the first circuit layer (110), and through this, the second circuit layer (111) can be arranged together with the first via electrode (116) filling the through hole of the first insulating layer (104). Therefore, the first via electrode (116) can be distinguished as a protrusion of the second circuit layer (111). Likewise, each of the first and second via electrodes (116, 117) may be connected to another circuit layer disposed below each circuit layer by being separated by a protrusion of the second and third circuit layers (111, 112).

[0074] The first circuit layer (110) may be in contact with one surface of the core layer (101). In this case, a part of the first circuit layer (110) may be arranged to cover the insulating member (121) described above. The part of the first circuit layer (110) that covers the insulating member (121) may be thinner than the remaining parts that do not vertically overlap the insulating member (121). Here, the thickness of the first circuit layer (110) refers to the thickness in the vertical direction. When designing the first circuit layer (110), the insulating member (121) may be covered or not covered depending on the degree of freedom of wiring, and thus the freedom of wiring connection may be increased. When the first circuit layer (110) does not cover the insulating member (121), the insulating member (121) may be in direct contact with the first insulating layer (104). When the first circuit layer (110) and the first insulating layer (104) are in contact with each other, the bonding strength may be better and heat dissipation may be advantageous compared to when the insulating member (121) and the first insulating layer (104) are in direct contact. However, in order to reduce the process cost, the first circuit layer (110) may be arranged so as not to cover the insulating member (121). Furthermore, depending on the design of the first via electrode (116), the first circuit layer (110) may or may not cover the insulating member (121). For example, when the first via electrode (116) is arranged to overlap the first circuit layer (110) in the vertical direction, the first circuit layer (110) may be provided to cover the insulating member (121) in order to secure electrical connectivity and / or mechanical coupling between the first circuit layer (110) and the first via electrode (116). Additionally, when the first via electrode (116) that vertically overlaps the first circuit layer (110) is not arranged, the third circuit layer (112) may be provided without covering the insulating member (121).

[0075] The plurality of insulating layers (104, 105) of the first build-up layer (102) may include a first insulating layer (104) that is closest to the core layer (101) in a direction perpendicular to the core layer (101) and a second insulating layer (105) that is positioned further from the core layer (101) in a direction perpendicular to the first insulating layer (104). In this case, the first build-up layer (102) is illustrated as including the first and second insulating layers (104, 105), but is not limited thereto. For example, the first build-up layer (102) may include three or more insulating layers, thereby enabling a smoother electrical connection between the semiconductor element and the semiconductor package substrate.

[0076] The first and second insulating layers (104, 105) are arranged to vertically insulate between the first to third circuit layers (110, 111, 112) described above. For example, the first and second insulating layers (104, 105) may be formed using a thermosetting insulating material containing an inorganic filler in a resin, and Ajinomoto Build-up Film (ABF) of Ajinomoto Co., Ltd. may be used. However, the embodiment is not limited thereto, and a photo-curable insulating material (Photo Imageable Dielectric, PID) for forming a fine pattern may be used.

[0077] The first protective layer (108) can protect the third circuit layer (112) from external moisture or contaminants. In addition, when semiconductor elements are arranged on the circuit board (100) using a material such as solder, the first protective layer (108) functions to prevent short circuits between solders due to its low wettability with the solder. The first protective layer (108) can be formed using a photocurable insulating material, and for example, a solder resist can be used.

[0078] A second build-up layer (103) is arranged on the other side of the core layer (101). The second build-up layer (103) includes a plurality of insulating layers (106, 107), a plurality of circuit layers (113, 114, 115), a plurality of via electrodes (118, 119), and a second protective layer (109).

[0079] The plurality of circuit layers (113, 114, 115) of the second build-up layer (103) may include a fourth circuit layer (113) that is most adjacent to the core layer (101) in the vertical direction, a fifth circuit layer (114) arranged under the fourth circuit layer (113), and a sixth circuit layer (115) arranged under the fifth circuit layer (114). The fourth to sixth circuit layers (113, 114, 115) may function to electrically connect a main board (not shown) of an electronic device and a semiconductor element arranged on a circuit board (100). Each of the fourth to sixth circuit layers (113, 114, 115) may be freely designed in consideration of impedance.

[0080] Additionally, via electrodes (118, 119) may be arranged to connect the fourth to sixth circuit layers (113, 114, 115), respectively. The third via electrode (118) is arranged between the fourth circuit layer (113) and the fifth circuit layer (114), and the fourth via electrode (119) is arranged between the fifth circuit layer (114) and the sixth circuit layer (115), thereby electrically connecting the fourth to sixth circuit layers (113, 114, 115).

[0081] As described above with respect to the first and second via electrodes (116, 117) of the first build-up layer (102), the arrangement of the third and fourth via electrodes (118, 119) can also be performed simultaneously in the process of arranging the fourth to sixth circuit layers (113, 114, 115). Therefore, as described above, the third via electrode (118) can be distinguished as a protrusion of the fourth circuit layer (114). However, since the fourth to sixth circuit layers (113, 114, 115) of the second build-up layer (103) are laminated in a different direction from the first build-up layer (102), the slope direction of each via electrode (116, 117) of the first build-up layer (102) may have a direction opposite to the slope direction of each via electrode (118, 119) of the second build-up layer (103). For example, each via electrode (116, 117) of the first build-up layer (102) may have a slope whose width becomes narrower as it approaches the core layer (101), and each via electrode (118, 119) of the second build-up layer (103) may also have a slope whose width becomes narrower as it approaches the core layer (101). For example, the slope of each via electrode (116, 117) of the first build-up layer (102) may be symmetrical with respect to the slope of each via electrode (118, 119) of the second build-up layer (103) with respect to the core layer (101).

[0082] The fourth circuit layer (125) may be in contact with the other surface of the core layer (101). In this case, a part of the fourth circuit layer (113) may be arranged to cover the insulating member (121) described above. The part of the fourth circuit layer (113) that covers the insulating member (121) may be thinner than the remaining parts that do not vertically overlap the insulating member (121). Here, the thickness of the fourth circuit layer (113) refers to the thickness in the vertical direction. When designing the fourth circuit layer (113), the insulating member (121) may be covered or not covered depending on the degree of freedom of wiring, and thus the freedom of wiring connection may be increased. When the fourth circuit layer (113) does not cover the insulating member (121), the insulating member (121) may be in direct contact with the third insulating layer (106). Compared to the case where the insulating member (121) and the third insulating layer (106) are in direct contact, when the fourth circuit layer (113) and the third insulating layer (106) are in contact, the bonding strength may be better and heat dissipation may be advantageous. However, in order to reduce the process cost, the fourth circuit layer (113) may be arranged so as not to cover the insulating member (121). Furthermore, depending on the design of the third via electrode (118), the fourth circuit layer (113) may or may not cover the insulating member (121). For example, when the third via electrode (118) is arranged to vertically overlap the fourth circuit layer (113), the fourth circuit layer (113) may be provided to cover the insulating member (121) in order to secure electrical connectivity and / or mechanical coupling between the fourth circuit layer (113) and the third via electrode (118). Additionally, when the third via electrode (118) that vertically overlaps the fourth circuit layer (113) is not arranged, the fourth circuit layer (113) may be provided without covering the insulating member (121).

[0083] The plurality of insulating layers (106, 107) of the second build-up layer (103) may include a third insulating layer (106) that is most adjacent to the core layer (101) in the vertical direction, and a fourth insulating layer (107) that is arranged under the third insulating layer (106). The third and fourth insulating layers (106, 107) are arranged to insulate in the vertical direction between the fourth to sixth circuit layers (113, 114, 115) described above. In addition, as an example, the third and fourth insulating layers (106, 107) may use a thermosetting insulating material containing an inorganic filler in a resin, and Ajinomoto Build-up Film (ABF) of Ajinomoto Co., Ltd. may be used. However, the embodiment is not limited thereto, and a photo-curable insulating material (Photo Imageable Dielectric, PID) for forming a fine pattern may be used.

[0084] The second protective layer (109) can protect the sixth circuit layer (115) from external moisture or contaminants. In addition, when semiconductor elements are arranged on the circuit board (100) using a material such as solder, the second protective layer (109) functions to prevent short circuits between solders due to its low wettability with the solder. The second protective layer (109) can be formed using a photocurable insulating material, and for example, a solder resist can be used.

[0085] The structure of the circuit board (100) described above is only an example for explaining the present invention, and the technical idea of ​​the present invention is not limited to the laminated structure of the present embodiment.

[0086] The circuit board (100) may warp depending on the heat and / or pressure applied during the process, the thickness of each insulating layer, the thickness of each protective layer, and the density or thickness of the circuit layer. Warp may be caused by warping in the smile direction (∪) and warping in the cry direction (∩), and warping in these two directions may be applied in combination. Warping in the smile direction means that the upper and / or lower surface of the circuit board (100) is warped concavely so that the center is lower than the edge of the circuit board (100), and may also be referred to as a concave direction. In addition, warping in the cry direction means that the upper and / or lower surface of the circuit board (100) is warped convexly so that the center is higher than the edge of the circuit board (100), in a direction opposite to the warping in the smile direction, and may also be referred to as a convex direction.

[0087] This warpage of the circuit board (100) may be a factor that prevents the semiconductor elements placed on the first protective layer (108) from being uniformly bonded to each other, such as by solder bonding, across the entire circuit board (100), thereby lowering the reliability of the semiconductor package.

[0088] In addition, the circuit board (100) must supply stable power to the semiconductor elements and / or connecting members described below. At this time, as the functions and performance of the semiconductor elements and / or connecting members increase and improve, the intensity of power to be supplied to the semiconductor elements and / or connecting members also increases.

[0089] However, according to the prior art, it is not possible to supply stable power to the semiconductor elements and / or connecting members while preventing bending of the circuit board (100), and if the circuit board (100) is greatly bent in a specific direction, or if stable power is not supplied to the semiconductor elements and / or connecting members, a power shortage phenomenon may occur and the semiconductor elements and / or connecting members may not operate stably.

[0090] Accordingly, the embodiment allows the circuit board (100) to be substantially warped in a specific direction while ensuring stable power supply to the semiconductor elements and / or connecting members by changing the design of the circuit layers and / or via electrodes of the circuit board (100).

[0091] Referring to (a) and (b) of FIG. 2, the first circuit layer (110) is disposed between the core layer (101) and the first insulating layer (104). That is, the first circuit layer (110) is disposed on the lower surface of the first insulating layer (104). The first circuit layer (110) includes a plurality of circuit patterns.

[0092] The first circuit layer (110) includes a first circuit pattern (110A). The first circuit pattern (110A) refers to a circuit pattern that is arranged closest to the outer surface (104S) of the first insulating layer (104) among the plurality of circuit patterns of the first circuit layer (110). In addition, the first circuit layer (110) further includes an inner circuit pattern (110B) that is arranged further away from the outer surface (104S) of the first insulating layer (104) than the first circuit pattern (110A).

[0093] The first circuit pattern (110A) may be provided along the circumferential direction of the outer surface (104S) of the first insulating layer (104) on the lower surface of the first insulating layer (104). The first circuit pattern (110A) refers to a circuit pattern arranged at the outermost side among the plurality of circuit patterns of the first circuit layer (110), and may function as a power transmission pattern. Through this, the embodiment can increase the width of the first circuit pattern (110A) in the horizontal direction by the first circuit pattern (110A) functioning as a power transmission pattern being arranged at the outermost side among the plurality of circuit patterns of the first circuit layer (110), thereby enabling a stable power supply to the semiconductor element and / or the connecting member.

[0094] That is, in addition to the power pattern that functions as a power transmission function, the circuit board (100) also has signal patterns for signal transmission. At this time, the power pattern must be arranged far away from the signal pattern. This is because, if the power pattern is located adjacent to the signal pattern, mutual interference may occur, resulting in transmission loss of the signal transmitted through the signal pattern. In contrast, the first circuit pattern (110A) that functions as the power pattern of the embodiment may be located on the outermost portion closest to the outer surface (104S) of the first insulating layer (104) among the plurality of circuit patterns of the first circuit layer (110). Through this, the embodiment can increase the width of the first circuit pattern (110A) compared to the prior art. At this time, when the width of the first circuit pattern (110A) increases, the intensity of the power that can be transmitted through the first circuit pattern (110A) may increase, thereby enabling a stable power supply to the semiconductor element and / or the connecting member.

[0095] In addition, the first circuit pattern (110A) may function as a power pattern that supplies power to semiconductor elements and / or connecting members, while also functioning as a reinforcement pattern that alleviates warpage to improve the rigidity of the circuit board (100). That is, since the first circuit pattern (110A) is provided along the circumferential direction of the outer surface (104S) of the first insulating layer (104) on the lower surface of the first insulating layer (104), the outer region of the first insulating layer (104) can be prevented from warping in the upward and / or downward direction, thereby improving the rigidity of the circuit board (100).

[0096] Furthermore, the first circuit pattern (110A) can also function as a warpage prevention pattern that mitigates warping of the circuit board (100) in a specific direction. In an embodiment, the horizontal distance between the circuit patterns arranged at the outermost edge of each insulating layer and the insulating layer in each circuit layer of the first build-up layer (102) can be varied, thereby preventing the circuit board (100) from warping in a specific direction.

[0097] For example, the first circuit pattern (110A) may be provided with a first separation distance (d1) from the outer surface (104S) of the first insulating layer (104) along the circumferential direction of the outer surface (104S) of the first insulating layer (104). In addition, the first separation distance (d1) may be different from a second separation distance (d2) between the second insulating layer (105) disposed thereon and the second circuit pattern (111A), which will be described later. At this time, the first separation distance (d1) and the second separation distance (d2) may be determined depending on the direction in which the first circuit layer (110) is bent. This will be described later.

[0098] In addition, referring to (a) of FIG. 2, the first circuit pattern (110A) may have a closed loop shape and may be provided along the circumferential direction of the outer surface (104S) of the first insulating layer (104) from the lower surface of the first insulating layer (104), but is not limited thereto, and as shown in (b) of FIG. 2, the first circuit pattern (110A) may have an open loop shape and may be provided along the circumferential direction of the outer surface (104S) of the first insulating layer (104) from the lower surface of the first insulating layer (104). For example, according to the embodiment of (b) of FIG. 2, the first circuit pattern (110A) may be provided along the circumferential direction of the outer surface (104S) of the first insulating layer (104) from the lower surface of the first insulating layer (104) and may include a first portion (110A1) and a second portion (110A2) that are spaced apart from each other. At this time, the first circuit pattern (110A) functions as a power pattern, and accordingly, in the case of the embodiment of FIG. 2 (b), the first part (110A1) of the first circuit pattern (110A) can function as a power line supplying power of the first polarity (e.g., + polarity), and the second part (110A2) can function as a power line supplying power of the second polarity (e.g., - polarity), but is not limited thereto.

[0099] Also, referring to (a) and (b) of FIG. 3, the second circuit layer (111) is disposed between the first insulating layer (104) and the second insulating layer (105). That is, the second circuit layer (111) is disposed on the lower surface of the second insulating layer (105). The second circuit layer (111) includes a plurality of circuit patterns. The second circuit layer (111) includes a second circuit pattern (111A). The second circuit pattern (111A) refers to a circuit pattern disposed closest to the outer surface (105S) of the second insulating layer (105) among the plurality of circuit patterns of the second circuit layer (111). In addition, the second circuit layer (111) further includes, in addition to the second circuit pattern (111A), an inner circuit pattern (111B) that is arranged further away from the outer surface (105S) of the second insulating layer (105) than the second circuit pattern (111A).

[0100] Referring to (a) of FIG. 3, the second circuit pattern (111A) has a closed loop shape and may be provided along the circumferential direction of the outer surface (105S) of the second insulating layer (105) on the lower surface of the second insulating layer (105), but is not limited thereto, and as shown in (b) of FIG. 3, the second circuit pattern (111A) may be provided along the circumferential direction of the outer surface (105S) of the second insulating layer (105) on the lower surface of the second insulating layer (105) and have an open loop shape. For example, according to the embodiment of (b) of FIG. 3, the second circuit pattern (111A) may be provided along the circumferential direction of the outer surface (105S) of the second insulating layer (105) on the lower surface of the second insulating layer (105) and may include a first portion (111A1) and a second portion (111A2) that are spaced apart from each other. At this time, the second circuit pattern (111A) functions as a power pattern, and accordingly, in the case of the embodiment of FIG. 3 (b), the first part (111A1) of the second circuit pattern (111A) can function as a power line supplying power of the first polarity (e.g., + polarity), and the second part (111A2) can function as a power line supplying power of the second polarity (e.g., - polarity), but is not limited thereto.

[0101] In addition, the second circuit pattern (111A) may be provided along the circumferential direction of the outer surface (105S) of the second insulating layer (105) on the lower surface of the second insulating layer (105). The second circuit pattern (111A) refers to a circuit pattern arranged at the outermost side among the plurality of circuit patterns of the second circuit layer (111), which may function as a power transmission pattern. Through this, the embodiment can increase the width of the second circuit pattern (111A) in the horizontal direction by having the second circuit pattern (111A) functioning as a power transmission pattern be arranged at the outermost side among the plurality of circuit patterns of the second circuit layer (111), thereby enabling a stable power supply to the semiconductor element and / or the connecting member. That is, the second circuit pattern (111A) functioning as a power pattern may be located at the outermost portion closest to the outer surface (105S) of the second insulating layer (105) among the plurality of circuit patterns of the second circuit layer (111). Through this, the width of the second circuit pattern (111A) may be determined without significantly considering the problem of signal interference with signal patterns, thereby increasing the width of the second circuit pattern (111A). At this time, when the width of the second circuit pattern (111A) increases, the intensity of power that can be transmitted through the second circuit pattern (111A) may increase, thereby enabling a stable power supply to the semiconductor element and / or the connecting member.

[0102] In addition, the second circuit pattern (111A) can function as a power pattern that supplies power to semiconductor elements and / or connecting members, while also functioning as a reinforcement pattern that alleviates warpage to improve the rigidity of the circuit board (100). That is, since the second circuit pattern (111A) is provided along the circumferential direction of the outer surface (105S) of the second insulating layer (105) on the lower surface of the second insulating layer (105), the outer region of the second insulating layer (105) can be prevented from warping in the upward and / or downward direction, thereby improving the rigidity of the circuit board (100).

[0103] Furthermore, the second circuit pattern (111A) can also function as a warpage prevention pattern that mitigates warping of the circuit board (100) in a specific direction. In an embodiment, the horizontal distance between the circuit patterns arranged at the outermost edge of each insulating layer and the insulating layer in each circuit layer of the first build-up layer (102) can be varied, thereby preventing the circuit board (100) from warping in a specific direction.

[0104] For example, the second circuit pattern (111A) may be provided with a second separation distance (d2) from the outer surface (105S) of the second insulating layer (105) along the circumferential direction of the outer surface (105S) of the second insulating layer (105). In addition, the second separation distance (d2) may be different from the first separation distance (d1) between the first insulating layer (104) and the first circuit pattern (110A).

[0105] At this time, the size of the first separation distance (d1) and the second separation distance (d2) may be determined depending on the direction in which the circuit board (100) is bent. For example, the circuit board (100) may be bent to have a concave shape in the smile direction. In this case, the first separation distance (d1) may be greater than the second separation distance (d2). That is, the fact that the first separation distance (d1) is greater than the second separation distance (d2) may mean that the second circuit pattern (111A) of the second circuit layer (111) is arranged further outward in the second insulating layer (105) than the first circuit pattern (110A) of the first circuit layer (110). And, when the second circuit pattern (111A) located relatively higher is located further outward than the first circuit pattern (110A), the circuit board (100) can be induced to have a convex shape, thereby alleviating the warpage of the circuit board (100) that is bent in the smile direction. However, the embodiment is not limited thereto, and when the circuit board (100) is bent convexly in the cry direction, the first separation distance (d1) can be made smaller than the second separation distance (d2) so that the first circuit pattern (110A) is located further outward than the second circuit pattern (111A). Through this, the warpage of the circuit board (110) can be alleviated by making the first separation distance (d1) and the second separation distance (d2) different, the unevenness in the height of the pad portion for connection with the semiconductor element among the third circuit layer (112) can be reduced, and the connection reliability between the semiconductor element and the circuit board (100) can be improved.

[0106] At this time, in (a) and (b) of FIG. 2, the first separation distance (d1) between the outer surface of the first insulating layer (104) and the first circuit pattern (110A) along the circumferential direction of the outer surface of the first insulating layer (104) is illustrated as being the same, but is not limited thereto. For example, the first separation distance (d1) between the outer surface of the first insulating layer (104) and the first circuit pattern (110A) along the circumferential direction of the outer surface of the first insulating layer (104) may include different 1-1 separation distances and 1-2 separation distances.

[0107] The outer side of the first insulating layer (104) may include a first side, a second side facing the first side, a third side disposed between the first and second sides, and a fourth side facing the third side. At this time, the separation distance between the first side of the first insulating layer (104) and the first circuit pattern (110A) and the separation distance between the second side of the first insulating layer (104) and the first circuit pattern (110A) may be equal to the 1-1 separation distance. The separation distance between the third side of the first insulating layer (104) and the first circuit pattern (110A) and the separation distance between the fourth side of the first insulating layer (104) and the first circuit pattern (110A) may be equal to the 1-2 separation distance. However, the 1-1 separation distance and the 1-2 separation distance may be different from each other, and may be designed in consideration of the direction in which the circuit board (100) is bent and / or the direction of stress acting on the circuit board (100).

[0108] Accordingly, in (a) and (b) of FIG. 3, the second separation distance (d2) between the outer surface of the second insulating layer (105) and the second circuit pattern (111A) along the circumferential direction of the outer surface of the second insulating layer (105) is illustrated as being the same, but is not limited thereto. For example, the second separation distance (d2) between the outer surface of the second insulating layer (105) and the second circuit pattern (111A) along the circumferential direction of the outer surface of the second insulating layer (105) may include different 2-1 separation distances and 2-2 separation distances. The outer surface of the second insulating layer (105) may include a first side surface, a second side surface facing the first side surface, a third side surface disposed between the first and second side surfaces, and a fourth side surface facing the third side surface. At this time, the separation distance between the first side of the second insulating layer (105) and the second circuit pattern (111A) and the separation distance between the second side of the second insulating layer (105) and the second circuit pattern (111A) may be equal to the 2-1 separation distance. The separation distance between the third side of the second insulating layer (105) and the second circuit pattern (111A) and the separation distance between the fourth side of the second insulating layer (105) and the second circuit pattern (111A) may be equal to the 2-2 separation distance. However, the 2-1 separation distance and the 2-2 separation distance may be different from each other, and may be designed in consideration of the direction in which the circuit board (100) is bent and / or the direction of stress acting on the circuit board (100).

[0109] Furthermore, the 1-1 separation distance between the first insulating layer (104) and the first circuit pattern (110A) may be different from the 2-1 separation distance between the second insulating layer (105) and the second circuit pattern (111A) which are arranged to overlap in the vertical direction therewith. Alternatively, the 1-2 separation distance between the first insulating layer (104) and the first circuit pattern (110A) may be different from the 2-2 separation distance between the second insulating layer (105) and the second circuit pattern (111A) which are arranged to overlap in the vertical direction therewith. This allows the circuit board (100) to be more efficiently mitigated from being bent in a specific direction.

[0110] In addition, a third circuit layer (112) is arranged on the lower surface of the first protective layer (108). In addition, the third circuit layer (112) includes a third circuit pattern (112A) arranged most adjacent to the outer surface of the first protective layer (108). At this time, the third circuit pattern (112A) of the third circuit layer (112) and the outer surface of the first protective layer (108) may have a third separation distance (d3, see FIG. 1). At this time, the third separation distance (d3) may be different from the first separation distance (d1) and the second separation distance (d2). That is, when the circuit board (100) is bent in the smile direction, the first separation distance (d1) may be the largest among the first to third separation distances (d1, d2, d3), and the third separation distance (d3) may be the smallest.

[0111] As described above, the circuit layers (110, 111, 112) provided on each insulating layer (104, 105) of the first build-up layer (102) have circuit patterns that are closest to the outer surface of each insulating layer (104, 105). In addition, the circuit patterns of each circuit layer (110, 111, 112) may be provided along the circumferential direction of the outer surface of each insulating layer (104, 105). At this time, the circuit patterns (110A, 111A, 112A) arranged at the outermost edge of each circuit layer (110, 111, 112) may function as power patterns, and may be designed to enable sufficient power supply to the semiconductor element and / or the connecting member through this. Therefore, the embodiment may enable stable power supply to the semiconductor element and / or the connecting member, and may improve the operating characteristics of the semiconductor element and / or the connecting member. Furthermore, the circuit patterns (110A, 111A, 112A) arranged at the outermost edge described above can function as a reinforcing pattern that improves the rigidity of the circuit board. In addition, by making the distance between the outermost circuit patterns of each circuit layer (110, 111, 112) and the outer surface of each insulating layer (104, 105) different depending on the direction in which the circuit board is bent, the bending of the circuit board in a specific direction can be mitigated. Accordingly, the bending of the circuit board (110) can be mitigated, the unevenness in the height of the pad portion for connection with the semiconductor element among the third circuit layers (112) can be reduced, and the connection reliability between the semiconductor element and the circuit board (100) can be improved.

[0112] Furthermore, the circuit layers (113, 114, 115) disposed on the insulating layer (106, 107) / second protective layer (109) of the second build-up layer (103) also include circuit patterns (113A, 114A, 115A) disposed most adjacent to the outer surface of the insulating layer (106, 107) / second protective layer (109), and the separation distance between the circuit patterns (113A, 114A, 115A) and the insulating layer (106, 107) / second protective layer (109) may be different. However, the relationship between the distance between the circuit patterns of the circuit layers (110, 111, 112) provided in the first build-up layer (102) and the insulating layer (104, 105) / the first protective layer (108) may be opposite to the relationship between the distance between the circuit patterns (113A, 114A, 115A) of the circuit layers (113, 114, 115) provided in the second build-up layer (103) and the insulating layer (106, 107) / the second protective layer (109).

[0113] That is, when the circuit board (100) is concavely bent in the smile direction, the first circuit pattern (110A) of the first circuit layer (110) located closest to the core layer (101) among the circuit layers (110, 111, 112) of the first build-up layer (102) has the largest first separation distance (d1), and the third circuit pattern of the third circuit layer (112) located farthest from the core layer (101) has the smallest third separation distance (d3). In addition, when the circuit board (100) is convexly bent in the cry direction, the first circuit pattern (110A) of the first circuit layer (110) located closest to the core layer (101) among the circuit layers (110, 111, 112) of the first build-up layer (102) has the smallest first separation distance (d1), and the third circuit pattern (112A) of the third circuit layer (112) located farthest from the core layer (101) has the largest third separation distance (d3).

[0114] And, the fourth circuit layer (113) of the second build-up layer (103) includes a fourth circuit pattern (113A) arranged most adjacent to the outer surface of the third insulating layer (106). At this time, the fourth circuit pattern (113A) of the fourth circuit layer (113) may be spaced apart from the outer surface of the third insulating layer (106) by a fourth separation distance (d4, see FIG. 1). The fifth circuit layer (114) of the second build-up layer (103) includes a fifth circuit pattern (114A) arranged most adjacent to the outer surface of the fourth insulating layer (107). At this time, the fifth circuit pattern (114A) of the fifth circuit layer (114) may be spaced apart from the outer surface of the fourth insulating layer (107) by a fifth separation distance (d5, see FIG. 1) that is different from the fourth separation distance (d4). The sixth circuit layer (115) of the second build-up layer (103) includes a sixth circuit pattern (115A) arranged most adjacent to the outer surface of the second protective layer (109). At this time, the sixth circuit pattern (115A) of the sixth circuit layer (115) may be spaced apart from the outer surface of the second protective layer (109) by a sixth separation distance (d6, see FIG. 1) that is different from the fourth separation distance (d4) and the fifth separation distance (d5). At this time, the relationship between the fourth to sixth separation distances (d4, d5, d6) may be opposite to the relationship between the first to third separation distances (d1, d2, d3).

[0115] That is, when the circuit board (100) is concavely bent in the smile direction, the fourth circuit pattern (113A) of the fourth circuit layer (113) located closest to the core layer (101) among the circuit layers (113, 114, 115) of the second build-up layer (103) has the smallest fourth separation distance (d4), and the sixth circuit pattern (115A) of the sixth circuit layer (115) located farthest from the core layer (101) has the largest sixth separation distance (d6). In addition, when the circuit board (100) is convexly bent in the cry direction, the fourth circuit pattern (113A) of the fourth circuit layer (113) located closest to the core layer (101) among the circuit layers (113, 114, 115) of the second build-up layer (102) has the largest fourth separation distance (d4), and the sixth circuit pattern (115A) of the sixth circuit layer (115) located farthest from the core layer (101) has the smallest sixth separation distance (d6).

[0116]

[0117] Referring to FIG. 4, the embodiment makes it possible to further alleviate warpage of the circuit board (100) by making the distance between the circuit patterns located at the outermost edge of each circuit layer of the circuit board (100) and the outer surface of the insulating layer / protective layer different, and by making the distance between the via electrode penetrating each insulating layer and the outer surface of the insulating layer different.

[0118] Referring to FIG. 4, the circuit board (100) includes a core layer (101), a first insulating layer (104), a second insulating layer (105), a first protective layer (108), a third insulating layer (106), a fourth insulating layer (107), and a second protective layer (109). In addition, the circuit board (100) includes a first circuit pattern (110A) disposed most adjacent to the outer surface of the first insulating layer (104) among the first circuit layers (110) disposed within the first insulating layer (104), a second circuit pattern (111A) disposed most adjacent to the outer surface of the second insulating layer (105) among the second circuit layers (111) disposed within the second insulating layer (105), a third circuit pattern (112A) disposed most adjacent to the outer surface of the first protective layer (108) among the third circuit layers disposed within the first protective layer (108), a fourth circuit pattern (113A) disposed most adjacent to the outer surface of the third insulating layer (106) among the fourth circuit layers disposed within the third insulating layer (205), and a fifth circuit pattern (113A) disposed most adjacent to the outer surface of the fourth insulating layer (107) among the fifth circuit layers disposed within the fourth insulating layer (107). The circuit board (100) may include a fifth circuit pattern (114A) and a sixth circuit pattern (115A) that is arranged most adjacent to the outer surface of the second protective layer (109) among the sixth circuit layers arranged within the second protective layer (109). In addition, the circuit board (100) includes a first via electrode (116) connecting between the first circuit pattern (110A) and the second circuit pattern (111A), a second via electrode (117) connecting between the second circuit pattern (111A) and the third circuit pattern (112A), a third via electrode (118) connecting between the fourth circuit pattern (113A) and the fifth circuit pattern (114A), and a fourth via electrode (119) connecting between the fifth circuit pattern (114A) and the sixth circuit pattern (115A).

[0119] In addition, the first circuit pattern (110A) is arranged with a first separation distance (d1) from the outer surface of the first insulating layer (104), the second circuit pattern (111A) is arranged with a second separation distance (d2) from the outer surface of the second insulating layer (105), the third circuit pattern (112A) is arranged with a third separation distance (d3) from the outer surface of the first protective layer (108), the fourth circuit pattern (113A) is arranged with a fourth separation distance (d4) from the outer surface of the third insulating layer (106), the fifth circuit pattern (114A) is arranged with a fifth separation distance (d5) from the outer surface of the fourth insulating layer (107), and the sixth circuit pattern (115A) is arranged with a sixth separation distance (d6) from the outer surface of the second protective layer (109).

[0120] At this time, the distance between the via electrodes arranged in each insulating layer and each insulating layer may also be different from each other in accordance with the relationship between the distance between each circuit pattern and the insulating layer.

[0121] For example, the first via electrode (116) connects the first circuit pattern (110A) and the second circuit pattern (111A). At this time, the first via electrode (116) may be arranged with a seventh separation distance (d7) from the outer surface of the first insulating layer (104). In addition, the second via electrode (117) may be arranged with an eighth separation distance (d8) from the outer surface of the second insulating layer (105). At this time, the seventh separation distance (d7) may be different from the eighth separation distance (d8). For example, when the circuit board (100) is concavely bent in the smile direction, the seventh separation distance (d7) may be greater than the eighth separation distance (d8). For example, when the circuit board (100) is concavely bent in the smile direction, the distance between the via electrode provided at the outermost portion of each insulating layer and the outer surface of each insulating layer may decrease as it moves upward away from the upper surface of the core layer (101). For example, when the circuit board (100) is convexly bent in the cry direction, the seventh separation distance (d7) may be smaller than the eighth separation distance (d8). For example, when the circuit board (100) is convexly bent in the cry direction, the distance between the via electrode provided at the outermost portion of each insulating layer and the outer surface of each insulating layer may increase as it moves upward away from the upper surface of the core layer (101).

[0122] In addition, the third via electrode (118) connects between the fourth circuit pattern (113A) and the fifth circuit pattern (114A). At this time, the third via electrode (118) may be arranged with a ninth separation distance (d9) from the outer surface of the third insulating layer (106). In addition, the fourth via electrode (119) may be arranged with a tenth separation distance (d10) from the outer surface of the fourth insulating layer (107). At this time, the ninth separation distance (d9) may be different from the tenth separation distance (d10). For example, when the circuit board (100) is concavely bent in the smile direction, the ninth separation distance (d9) may be smaller than the tenth separation distance (d10). For example, when the circuit board (100) is concavely bent in the smile direction, the distance between the via electrode provided at the outermost surface of each insulating layer and the outer surface of each insulating layer may increase as it moves away from the lower surface of the core layer (101) in the downward direction. For example, when the circuit board (100) is convexly bent in the cry direction, the ninth separation distance (d9) may be greater than the tenth separation distance (d10). For example, when the circuit board (100) is convexly bent in the cry direction, the distance between the via electrode provided at the outermost surface of each insulating layer and the outer surface of each insulating layer may decrease as it moves away from the lower surface of the core layer (101) in the downward direction.

[0123]

[0124] According to another embodiment of Fig. 5, the distance between each circuit pattern arranged closest to the outer surface of each insulating / protective layer described above and the outer surface of each insulating / protective layer may be changed so that each circuit pattern has a different width. However, in Fig. 5, different drawing reference numerals are given to each component illustrated in Figs. 1 to 4. However, each component of Fig. 5 may represent a modified example of a component having the same name in Figs. 1 to 4.

[0125] Referring to FIG. 5, the circuit board may include a first circuit pattern (302) disposed most adjacent to the outer surface (301S) of the first insulating layer (301) among the first circuit layers disposed on the lower surface of the first insulating layer (301). The first circuit pattern (302) may be spaced apart from the outer surface (301S) of the first insulating layer (301) by a first separation distance (d1). At this time, the first circuit pattern (302) may have a first width (w1) in the horizontal direction along the circumferential direction of the outer surface (301S) of the first insulating layer (301).

[0126] In addition, the circuit board may include a second circuit pattern (304) disposed most adjacent to the outer surface (303S) of the second insulating layer (303) among the second circuit layers disposed on the lower surface of the second insulating layer (303). The second circuit pattern (304) may be spaced apart from the outer surface (303S) of the second insulating layer (303) by a second separation distance (d2). At this time, the second circuit pattern (304) may have a second width (w2) in the horizontal direction along the circumferential direction of the outer surface (303S) of the second insulating layer (303).

[0127] The first width (w1) may be different from the second width (w2). That is, by making the first separation distance (d1) and the second separation distance (d2) different, the first width (w1) and the second width (w2) are different so that warpage of the circuit board can be further reduced.

[0128] For example, when the circuit board (100) is concavely bent in the smile direction, the first separation distance (d1) may be greater than the second separation distance (d2), and the first width (w1) may be smaller than the second width (w2). Conversely, when the circuit board (100) is convexly bent in the cry direction, the first separation distance (d1) may be smaller than the second separation distance (d2), and the first width (w1) may be larger than the second width (w2).

[0129] Accordingly, by changing the distance between each circuit pattern arranged closest to the outer surface of each insulating layer / protective layer and the outer surface of each insulating layer / protective layer described above, and by making each circuit pattern have a different width, warpage of the circuit board (110) can be further alleviated, the unevenness in the height of the pad portion for connection with the semiconductor element among the third circuit layers (112) can be reduced, and the connection reliability between the semiconductor element and the circuit board (100) can be improved.

[0130]

[0131] According to another embodiment according to FIG. 6, the spacing distance of the circuit pattern described above, the width of the circuit pattern, the spacing distance of the via electrode can be changed, and further, the width of the via electrode can be changed.

[0132] Referring to FIG. 6, the circuit board includes a first via electrode (304) disposed between a first circuit pattern (301) and a second circuit pattern (302). In addition, the circuit board (100) includes a second via electrode (305) disposed between a second circuit pattern (302) and a third circuit pattern (303). At this time, the first via electrode (304) may have a seventh separation distance (d7) from an outer surface of the first insulating layer (306) and a third width (w3) in a horizontal direction. In addition, the second via electrode (305) may have an eighth separation distance (d8) from an outer surface of the second insulating layer (307) and a fourth width (w4) in a horizontal direction.

[0133] At this time, the seventh separation distance (d7) and the eighth separation distance (d8) may be different from each other, and the third width (w3) and the fourth width (w4) may be different from each other. For example, when the circuit board (100) is concavely bent in the smile direction, the seventh separation distance (d7) may be greater than the eighth separation distance (d8), and the third width (w3) may be smaller than the fourth width (w4). Conversely, when the circuit board (100) is convexly bent in the cry direction, the seventh separation distance (d7) may be smaller than the eighth separation distance (d8), and the third width (w3) may be larger than the fourth width (w4).

[0134] Accordingly, by changing the distance between each via electrode positioned closest to the outer surface of each insulating / protective layer and the outer surface of each insulating / protective layer described above, and by making each via electrode have a different width, warpage of the circuit board (110) can be further alleviated, the unevenness in the height of the pad portion for connection with the semiconductor element among the third circuit layer (112) can be reduced, and the connection reliability between the semiconductor element and the circuit board (100) can be improved.

[0135]

[0136] According to another embodiment according to FIG. 7, a portion of the third circuit layer (112) may include a pad portion exposed from the first protective layer (108). In addition, as the density of terminals of the semiconductor device increases, a problem of solder short-circuiting between adjacent pad portions may occur with conventional solder bonding. Therefore, in order to reduce the amount of solder used as the density of terminals of the semiconductor device increases, the semiconductor device and the circuit board may be bonded to each other through a thermal compression bonding method. When using thermal compression bonding, the circuit board may further include a bump layer (403) protruding on the first protective layer (108). The bump layer (403) may have a protrusion protruding on the upper surface of the first protective layer (108) and a penetration portion (402) penetrating the first protective layer (108) to contact the third circuit layer (112). In addition, when bonding a circuit board and a semiconductor element using a thermal compression bonding method, a crack may occur in the penetration portion (402) of the bump layer (403) due to the load generated thereby. Therefore, cracks can be prevented by placing a material having an elasticity higher than the elasticity of the third circuit layer (112) in the penetration portion (402) of the bump layer (403) adjacent to the third circuit layer (112). This material may be nickel (Ni), but a copper layer having a low grain density can be placed by electroless plating.

[0137] The bump layer (403) and the through-hole (402) illustrated in FIG. 7 can be arranged in various ways. For example, a process may be performed in which the first protective layer (108) is exposed and developed to form an opening in the first protective layer (108), and then the bump layer (403) and the through-hole (402) are arranged in the opening. Alternatively, a process may be performed in which a through-hole in the first protective layer (108) is formed using a laser, and then the bump layer (403) and the through-hole (402) are arranged in the opening. In addition, by using DFR (Dry Film resist), DFR is first placed in the area where the penetration portion (402) is to be placed, and then the first protective layer (108) is placed so that the DFR is covered, and then a part of the first protective layer (108) is etched with a chemical solution to expose the DFR, and then the DFR is peeled off to form an opening in the first protective layer (108), and then the bump layer (403) and the penetration portion (402) can be placed. Accordingly, the penetration portion (402) can have various shapes depending on the process method. For example, when the opening of the first protective layer (108) is formed through an exposure process, the side surface of the penetration portion (402) may have a structure in which the width gradually narrows toward the third circuit layer (112). When the opening of the first protective layer (108) is formed through a laser process, the side surface of the penetration portion (402) may have a vertical side surface and a curved side surface adjacent to the third circuit layer (112). When the opening of the first protective layer (108) is formed using DFR, the side surface of the penetration portion (402) may only have a vertical side surface. As described above, when the semiconductor element is bonded to the circuit board (100) through thermocompression bonding, a load may be applied to the penetration portion (402). In this case, in the case of the penetration portion (402) using DFR, the stress may be applied uniformly, so that the manufacturing yield may be increased.

[0138]

[0139] Referring to FIG. 8, the circuit board may further include at least one connecting member (504). Recently, as the number of signals that semiconductor devices must process increases, the size of semiconductor devices is trending toward larger areas, which lowers the yield of semiconductor devices. Therefore, there is a trend to divide the pattern size or functional part of semiconductor devices, place chiplets on the circuit board, and embed connecting members (504) that have the function of electrically connecting them within the circuit board. However, the connecting members (504) are not limited thereto, and may also connect semiconductor devices with other functions, such as memory. In addition, the connecting members (504) may be disposed in the core layer (501) of the circuit board. For example, the core layer (501) may have a through hole (502), and the connecting members (504) may be disposed within the through hole (502) of the core layer (501). At this time, the first insulating layer (104) of the first build-up layer (102) and the second insulating layer (106) of the second build-up layer (103) can surround the side of the connecting member (504) and fill the through hole (502) of the core layer (501). However, the embodiment is not limited thereto, and the connecting member (504) can be embedded in the first build-up layer (102) instead of the core layer (501). For example, when the connecting member (504) is embedded in the first build-up layer (102), the signal transmission distance with the semiconductor element can be reduced, which is advantageous in preventing signal loss. That is, the connecting member (504) electrically connects between a plurality of semiconductor elements arranged on the circuit board (100), and thus, reducing the signal transmission distance while being adjacent to the plurality of semiconductor elements can be advantageous in reducing signal transmission loss. At this time, when the connecting member (504) is placed on the first build-up layer (102), the first insulating layer (104) and the second insulating layer (105) of the first build-up layer (102) may have a cavity.In the past, a cavity was provided in only one specific insulating layer to embed the connecting member (504), but in this case, the flatness of the uppermost insulating layer may deteriorate. In addition, if the thickness of the connecting member (504) is thicker than the thickness of a specific insulating layer of the first build-up layer (102), the problem of deteriorating flatness may become more serious. Therefore, it is necessary to improve the flatness by reducing the difference between the thickness of the connecting member (504) and the depth of the cavity. At this time, when cavities are provided in the first insulating layer (104) and the second insulating layer (105), the cavity of the second insulating layer (105) may be formed to have a second inclination angle that is gentler than the first inclination angle of the inner wall forming the cavity of the first insulating layer (104). In this case, the positional alignment of the connecting member (504) can be improved, and the occurrence of voids when the cavity is embedded with another insulating layer can be prevented.

[0140] In addition, the first via electrode penetrating the first insulating layer (104) may have different widths depending on the location. For example, the first via electrode may include a first via portion (507) that vertically overlaps the connecting member (504), and a second via portion (506) that horizontally overlaps the first via portion (507) and does not vertically overlap the connecting member (504). The above-described first via portion (507) may be directly connected to a pad portion (505) provided on the upper surface of the connecting member (504). The horizontal width of the first via portion (507) may be smaller than the horizontal width of the second via portion (506).

[0141] Accordingly, the second via electrode penetrating the second insulating layer (105) may have different widths depending on the location. For example, the second via electrode may include a third via portion (509) that vertically overlaps the connecting member (504), and a fourth via portion (508) that horizontally overlaps the third via portion (509) and does not vertically overlap the connecting member (504). In addition, the horizontal width of the third via portion (509) may be smaller than the horizontal width of the fourth via portion (508).

[0142]

[0143] According to another embodiment illustrated in FIG. 9, a first circuit layer disposed on a lower surface of a first insulating layer (601) includes a first circuit pattern (602). The first circuit pattern (602) includes a first portion (603) and a second portion (604). The first portion (603) of the first circuit pattern (602) can transmit first power to a connecting member (609). To this end, the first circuit layer includes a first connection pattern (605) connecting the first portion (603) of the first circuit pattern (602) and a first pad (610) of the connecting member (609). The first connection pattern (605) can extend from the first portion (603) of the first circuit pattern (602) and be connected to the first pad (610). In one embodiment, the first pad (610) may be a pad disposed on the inner side among the pads provided in the connecting member (609). In this case, the first connecting pattern (605) may include a region whose width changes from the first circuit pattern (602) toward the first pad (610). For example, the first connecting pattern (605) may include a first portion (606) extending from the first portion (603) of the first circuit pattern (603) and disposed between a plurality of pads of the connecting member (609), and a second portion (607) extending from the first portion (606) and wrapping around the first pad (610). Through this, the embodiment may enable a stable supply of power to the connecting member (609).

[0144] Additionally, the first circuit layer may include a second connection pattern (608) connecting the second portion (604) of the first circuit pattern (602) and the second pad (611) of the connection member (609). The second pad (611) may be a pad disposed on the outer side among the pads provided in the connection member (609). In this case, the second connection pattern (608) may be provided to extend from the second portion (604) of the first circuit pattern (602) and wrap around the second pad (611) without a region in which the width changes.

[0145]

[0146] The circuit board (100) described above can be used as an interposer provided between the semiconductor package substrate and the semiconductor element of the semiconductor package.

[0147] According to the embodiment illustrated in FIG. 10, the semiconductor package includes an interposer (710). The interposer (710) may refer to the circuit board (100) described with reference to FIGS. 1 to 9. That is, as the terminal density of the semiconductor element increases, the wiring becomes more complex, and accordingly, the thickness of the circuit board increases. However, as the thickness increases, a problem may arise in that the yield of the circuit board decreases. Therefore, the circuit board may be divided into an interposer (710) and a semiconductor package board (770) and used, and the above-described circuit board (100) may be used not only as the semiconductor package board (770) but also as the interposer (710).

[0148] Semiconductor elements (730, 740) are arranged on the interposer (710). The semiconductor elements (730, 740) may be provided in multiple numbers on the interposer (710) while being spaced apart from each other in the horizontal direction, but are not limited thereto. For example, the semiconductor elements (730, 740) may be arranged and stacked on the interposer (710) not only in the horizontal direction but also in the vertical direction.

[0149] A bonding member (750, 760) may be provided between the interposer (710) and the semiconductor elements (730, 740). In one embodiment, the bonding member (750, 760) may be placed on a bump layer (see FIG. 7) provided on the interposer (710), through which the semiconductor elements (730, 740) may be attached to the interposer (710) by a thermocompression bonding method. At this time, the semiconductor elements (730, 740) may be provided with terminals (731, 741), and the terminals (731, 741) may be electrically connected to the bump layer and the circuit layer of the interposer (710) through the bonding member (750, 760).

[0150] A connecting member (720) is embedded within the interposer (710). The connecting member (720) may function to electrically connect terminals (731, 741) of semiconductor elements (730, 740) disposed on the interposer (710). In this case, the connecting member (720) may be a bridge die. For example, the connecting member (720) partially vertically overlaps the semiconductor elements (730, 740) disposed on the interposer (710). In addition, the connecting member (720) electrically connects a portion of the terminal (731) of the first semiconductor element (730) and a portion of the terminal (741) of the second semiconductor element (740). The connecting member (720) may be formed of the same material as the semiconductor element, such as silicon, or may be formed of an organic material, such as a photosensitive resin or a thermosetting resin. A plurality of semiconductor devices having different functions, such as a CPU and GPU, a GPU and HBM, or a chiplet unit separated according to function and / or pitch, may be mounted on a circuit board, and a connecting member (720) may function to horizontally electrically connect them.

[0151] A semiconductor package substrate (770) is placed on the lower surface of the interposer (710). The semiconductor package substrate (770) can electrically connect the main board of an electronic device and the interposer (710).

[0152] At this time, a bonding member (780) may be placed between the interposer (710) and the semiconductor package substrate (770), through which the interposer (710) and the semiconductor package substrate (770) may be electrically bonded.

[0153]

[0154] Meanwhile, when a circuit board having the characteristics of the invention described above is used in IT devices such as smartphones, server computers, TVs, or home appliances, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the characteristics of the invention performs a semiconductor package function, it can safely protect semiconductor chips from external moisture or contaminants, and can solve problems such as leakage current or electrical shorts between terminals, or electrical open circuits in terminals supplying semiconductor chips. Furthermore, when it performs a signal transmission function, it can solve noise problems. Through this, the circuit board having the characteristics of the invention described above can maintain the stable function of IT devices or home appliances, thereby enabling the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability with each other.

[0155] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of the terminal supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0156] The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by a person skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be interpreted as being included within the scope of the embodiments.

[0157] Although the above has been described focusing on embodiments, these are merely examples and are not intended to limit the embodiments. Those skilled in the art to which the embodiments pertain will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the embodiments. For example, each component specifically shown in the embodiments can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

1. First circuit layer; A first insulating layer disposed on the first circuit layer; A second circuit layer disposed on the first insulating layer; and A second insulating layer disposed on the second circuit layer; The first circuit layer includes a first circuit pattern provided along the circumferential direction of the outer surface of the first insulating layer at a position closest to the outer surface of the first insulating layer, The second circuit layer includes a second circuit pattern provided along the circumferential direction of the outer surface of the second insulating layer at a position closest to the outer surface of the second insulating layer, A circuit board, wherein a first horizontal distance between the first circuit patterns from the outer surface of the first insulating layer is different from a second horizontal distance between the second circuit patterns from the outer surface of the second insulating layer.

2. In paragraph 1, The first insulating layer is provided to surround the side of the first circuit pattern, A circuit board, wherein the second insulating layer is provided to surround the side of the second circuit pattern.

3. In paragraph 1, The lower surface of the first insulating layer is positioned on the same plane as the lower surface of the first circuit pattern, A circuit board, wherein the lower surface of the second insulating layer is located on the same plane as the lower surface of the second circuit pattern.

4. In paragraph 1, The above first circuit pattern has a first width along the circumferential direction of the outer surface of the first insulating layer, A circuit board, wherein the second circuit pattern has a second width along the circumferential direction of the outer surface of the second insulating layer.

5. In paragraph 4, The above first separation distance is greater than the above second separation distance, A circuit board wherein the first width is smaller than the second width.

6. In paragraph 4, The above first separation distance is smaller than the above second separation distance, A circuit board wherein the first width is greater than the second width.

7. In paragraph 1, A circuit board, wherein each of the first and second circuit patterns has a closed loop shape.

8. In paragraph 1, The first circuit pattern includes a first portion and a second portion that are provided along the circumferential direction of the outer surface of the first insulating layer and are spaced apart from each other, A circuit board, wherein the second circuit pattern includes a third section and a fourth section that are spaced apart from each other and are provided along the circumferential direction of the outer surface of the second insulating layer.

9. In paragraph 1, a third circuit layer disposed on the second insulating layer; and Further comprising a protective layer disposed on the third circuit layer, The third circuit layer includes a third circuit pattern provided along the circumferential direction of the outer surface of the protective layer at a position closest to the outer surface of the protective layer, A circuit board, wherein a third horizontal separation distance between the third circuit patterns from the outer surface of the protective layer is different from the first and second separation distances.

10. In paragraph 9, a first via electrode disposed between the first circuit pattern and the second circuit pattern; and Further comprising a second via electrode disposed between the second circuit pattern and the third circuit pattern, A circuit board, wherein a fourth horizontal distance between the first via electrodes from the outer surface of the first insulating layer is different from a fifth horizontal distance between the second via electrodes from the outer surface of the second insulating layer.

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