Logical operation unit circuit and adder circuit
By optimizing the circuit structure of P logic and G logic, a simple adder circuit is designed, which solves the problem that the adder circuit is difficult to balance between high speed and low power consumption in the prior art, and achieves higher frequency and performance.
Patent Information
- Application Number
- PCT/CN2023/117758
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2023-09-08
- Publication Date
- 2025-05-08
AI Technical Summary
While pursuing high rates, existing adder circuits are difficult to reduce power consumption, or it is difficult to adopt a topological structure with smaller area and lower power consumption in specific rate scenarios, making it difficult to achieve the balance between power consumption and rate.
A logic operation unit circuit and adder circuit were designed. By optimizing the circuit structure of P logic and G logic, it was implemented using the circuit with the simplest structure and the least logic gate. The adder circuit structure is simple, with better area and delay and lower power consumption.
It realizes a reduction in power consumption while ensuring high speed, or adopts a topological structure with a smaller area and lower power consumption in specific rate scenarios, which well balances the relationship between power consumption and rate, making the circuit run faster and perform better.
Smart Images
Figure CN2023117758_08052025_PF_FP_ABST
Abstract
Description
A logic operation unit circuit and adder circuit Technical Field
[0001] The present application relates to, but is not limited to, digital circuit technology, and in particular to a logic operation unit circuit and an adder circuit. Background Art
[0002] As the most basic logical unit, adders are widely used in various types of processors. In circuit systems, adders are primarily responsible for calculations and indexing. They are also crucial components of other hardware logical units, such as multipliers and subtractors. Adders can be categorized based on their circuit topology. Common adder topologies include ripple carry and carry-lookahead.
[0003] Adders of different topologies have varying area and speed requirements. With the increasing demand for high operating frequencies and low power consumption in processor cores, higher requirements are being placed on adders. Balancing power consumption and speed has become a pressing issue: how to maintain high speed while reducing power consumption? Or, in specific speed scenarios, adopting a topology with a smaller area and lower power consumption.
[0004] SUMMARY OF THE INVENTION
[0005] The present application provides a logic operation unit circuit and an adder circuit, which have a simple circuit structure and can well balance the relationship between power consumption and speed.
[0006] The embodiment of the present application provides a first logic operation unit circuit, which is applied to a multi-bit adder. The logic operation unit circuit is used to implement !G logic and !P logic, including: an AND-NOR gate, a NAND gate;
[0007] The three inputs of the AND-NOR gate are P i:k , G k-1:j and G i:k , the output of the AND-NOR gate is! G i:j ;
[0008] The two inputs of the NAND gate are P k-1:j 、The P i:k , the output of the NAND gate is! P i:j ;
[0009] Wherein, i, k, and j respectively represent the bit data of the input data of the adder, i>k>j.
[0010] The embodiment of the present application also provides a second logic operation unit circuit, which is applied to a multi-bit adder. The logic operation unit circuit is used to implement G logic and P logic, including: an OR-NAND gate, a NOR gate;
[0011] The three inputs of the OR-NAND gate are: i:k ,! G k-1:j and! G i:k , the output of the OR-NAND gate is G i:j ;
[0012] The two inputs of the NOR gate are respectively! k-1:j , as mentioned! P i:k , the output of the NOR gate is P i:j ;
[0013] Wherein, i, k, and j respectively represent the bit data of the input data of the adder, i>k>j.
[0014] The present application embodiment further provides a third logic operation unit circuit, which is applied to a multi-bit adder. The logic operation unit circuit is used to implement P logic, including: two NAND gates and one NOR gate; wherein,
[0015] The two inputs of a NAND gate are P i:k 、P k-1:m , the output is !P i:m ;
[0016] The two inputs of the other NAND gate are P m-1:n 、P n-1:j , the output is !P m-1:j ;
[0017] The two inputs of the NOR gate are the outputs of the two NAND gates, and the output of the NOR gate is P i:j ; Wherein, i, k, m, n, j respectively represent the bit data of the input data of the adder, i>k>m>n>j.
[0018] The present application further provides a fourth logic operation unit circuit, which is applied to a multi-bit adder. The logic operation unit circuit is used to implement G logic, including: two AND-NOR gates and one OR-NAND gate; wherein,
[0019] The three inputs of an AND-NOR gate are P i:k , G k-1:m and G i:k , the output is !G i:m ;
[0020] The three inputs of the other AND-NOR gate are P m-1:n , G n-1:j and G m-1:n , the output is !G m-1:j ;
[0021] The three inputs of the OR-NAND gate are the outputs of the two AND-NOR gates, and !P i:m , the output is G i:j ; Wherein, i, k, m, n, j respectively represent the bit data of the input data of the adder, i>k>m>n>j.
[0022] An embodiment of the present application further provides an adder circuit, comprising any of the above-mentioned logic operation unit circuits.
[0023] In an exemplary embodiment, the adder is a Dobit LFA adder or a Dobit BK adder.
[0024] The embodiment of the present application further provides an adder circuit, wherein the adder is an n+1=32-bit LFA adder; the LFA adder includes seven stages of sequentially connected arithmetic units, wherein:
[0025] The first-level operation unit includes n+1 first unit circuits, wherein the first unit circuit is used to generate P logic and G logic. i =and(a i ,b i ), P i =xor(a i ,b i ), a i 、b i Respectively represent the i-th bit data of data a and data b participating in the LFA adder operation;
[0026] The second-level arithmetic unit includes A logic operation unit circuit as described in the first embodiment, a seventh unit circuit; wherein the seventh unit circuit is used to implement G logic, including: an AND-NOR gate, the three inputs of the AND-NOR gate are P i:k , G k-1:j and G i:k , the output of the AND-NOR gate is! G i:j , wherein i, k, and j respectively represent the bit data of the input data of the adder, i>k>j;
[0027] The third-level arithmetic unit includes A NOT gate, A logic operation unit circuit as described in the second type, and two eighth unit circuits; wherein the eighth unit circuit is used to implement G logic, including: an OR-NAND gate, the three inputs of the OR-NAND gate are respectively! P i:k ,! G k-1:j and! G i:k , the output of the OR-NAND gate is G i:j, wherein i, k, and j respectively represent the bit data of the input data of the adder, i>k>j;
[0028] The fourth-level arithmetic unit includes A NOT gate, a logic operation unit circuit as described in the first embodiment, and four of the seventh unit circuits;
[0029] The fifth-level arithmetic unit includes A NOT gate, a logic operation unit circuit as described in the second embodiment, and eight of the eighth unit circuits;
[0030] The sixth level arithmetic unit includes The seventh unit circuit, and 5 NOT gates;
[0031] The seventh-level operation unit includes n fourth unit circuits and 21 NOT gates, wherein the fourth unit circuit is used to implement S i =xor(P i ,G i-1,0 ), S i represents the i-th bit data after operation by the LFA adder.
[0032] The embodiment of the present application further provides an adder circuit, wherein the adder is an n+1=32-bit BK adder; the BK adder includes ten stages of sequentially connected arithmetic units, wherein:
[0033] The first-level operation unit includes n+1 first unit circuits, wherein the first unit circuit is used to generate P logic and G logic. i =and(a i ,b i ), P i =xor(a i ,b i ), a i 、b i Respectively represent the i-th bit data of data a and data b participating in the LFA adder operation;
[0034] The second-level arithmetic unit includes A logic operation unit circuit as described in the first embodiment, a seventh unit circuit; wherein the seventh unit circuit is used to implement G logic, including: an AND-NOR gate, the three inputs of the AND-NOR gate are P i:k , G k-1:j and G i:k , the output of the AND-NOR gate is! G i:j , wherein i, k, and j respectively represent the bit data of the input data of the adder, i>k>j;
[0035] The third-level arithmetic unit includes A logic operation unit circuit as described in the second type, and an eighth unit circuit; wherein the eighth unit circuit is used to implement G logic, including: an OR-NAND gate, the three inputs of the OR-NAND gate are respectively! P i:k ,! G k-1:j and! G i:k , the output of the OR-NAND gate is G i:j , wherein i, k, and j respectively represent the bit data of the input data of the adder, i>k>j;
[0036] The fourth-level arithmetic unit includes a logic operation unit circuit as described in the first embodiment, and one seventh unit circuit;
[0037] The fifth-level operation unit includes a logic operation unit circuit as described in the second embodiment, and the eighth unit circuit described in 1;
[0038] The sixth-level arithmetic unit includes two seventh-unit circuits and one NOT gate;
[0039] The seventh-level arithmetic unit includes two eighth-unit circuits, two NOT gates, and one seventh-unit circuit;
[0040] The eighth-level arithmetic unit includes four seventh-unit circuits, four NOT gates, and three eighth-unit circuits;
[0041] The ninth-level arithmetic unit includes seven seventh-unit circuits, eight eighth-unit circuits, and eight NOT gates;
[0042] The tenth-level operation unit includes n fourth unit circuits and 7 NOT gates; wherein the fourth unit circuit is used to implement S i =xor(P i ,G i-1,0 ), S i represents the i-th bit data after operation by the LFA adder.
[0043] The adder circuit provided in the embodiment of the present application adopts a circuit with the simplest structure and the least logic gates. The adder circuit has a simple structure, is better in terms of area and delay, has lower power consumption, and has a good balance between power consumption and speed, thereby making the circuit run at a faster frequency and have better performance.
[0044] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present invention. The purposes and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the description, claims and drawings.
[0045] Summary of the Figures
[0046] The accompanying drawings are used to provide a further understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.
[0047] FIG1 is a schematic diagram of the circuit topology structure of the core logic operation unit in the mainstream adder in the related art;
[0048] FIG2( a ) is a schematic diagram of a circuit structure for implementing continuous two-level P logic in one embodiment;
[0049] FIG2( b ) is a schematic diagram of a circuit structure for implementing continuous two-level P logic in another embodiment;
[0050] FIG3( a ) is a schematic diagram of a circuit structure for implementing continuous two-stage G logic in one embodiment;
[0051] FIG3( b ) is a schematic diagram of a circuit structure for implementing continuous two-stage G logic in another embodiment;
[0052] FIG4 is a schematic diagram of a topological structure of an LFA adder circuit;
[0053] FIG5( a ) is a schematic diagram of the circuit structure and corresponding schematic symbols of the first unit circuit in the LFA adder circuit shown in FIG4 ;
[0054] FIG5( b ) is a schematic diagram of the circuit structure and corresponding schematic symbols of the second unit circuit in the LFA adder circuit shown in FIG4 ;
[0055] FIG5( c ) is a schematic diagram of the circuit structure and corresponding schematic symbols of the third unit circuit in the LFA adder circuit shown in FIG4 ;
[0056] FIG5( d ) is a schematic diagram of the circuit structure and corresponding schematic symbols of the fourth unit circuit in the LFA adder circuit shown in FIG4 ;
[0057] FIG6( a ) is a schematic diagram of the circuit structure and corresponding schematic symbols of the fifth unit circuit in the LFA adder circuit according to another embodiment;
[0058] FIG6( b ) is a circuit structure diagram and corresponding schematic symbols of the sixth unit circuit in the LFA adder circuit of another embodiment;
[0059] FIG6( c ) is a schematic diagram of the circuit structure and corresponding schematic symbols of the seventh unit circuit in the LFA adder circuit of another embodiment;
[0060] FIG6( d ) is a schematic diagram of the circuit structure and corresponding schematic symbols of the eighth unit circuit in the LFA adder circuit according to another embodiment;
[0061] FIG7 is a schematic diagram of the topological structure of an LFA adder circuit in one embodiment of the present invention;
[0062] FIG8 is a schematic diagram of the topological structure of a BK adder circuit in one embodiment;
[0063] FIG9 is a schematic diagram of a topological structure of a BK adder circuit in another embodiment.
[0064] Details
[0065] To make the purpose, technical solutions and advantages of this application more clear, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless there is a conflict, the embodiments and features in the embodiments of this application can be combined with each other in any way.
[0066] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.
[0067] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.
[0068] In the mainstream adder topology, the core logic operation unit includes Propagate logic (abbreviated as P logic) and Generate logic (abbreviated as G logic). The circuit structure diagram is shown in Figure 1. P logic consists of an AND gate. i:j =and(P i:k ,P k-1:j ); G logic consists of an AND-OR gate, G i:j =or(G i:k ,and(P i:k ,G k-1:j ))=ao(G i:k ,P i:k ,G k-1:j); wherein, i>k>j, i, k, j respectively represent the bit of the input data, such as i represents the i-th bit.
[0069] To implement equivalent logic using the simplest possible circuit structure and the fewest logic gates, the present application proposes a logic operation unit circuit, including a P logic circuit and / or a G logic circuit. The P logic circuit includes a NOR gate and / or a NAND gate to implement P logic or P NOT (!P) logic; the G logic circuit includes an AND-NOR (AOI) gate and / or an OR-NAND (OAI) gate to implement G logic or !G logic.
[0070] In an exemplary embodiment, taking continuous two-level P logic as an example, FIG2(a) is a schematic diagram of the circuit structure for implementing continuous two-level P logic in one embodiment, and FIG2(b) is a schematic diagram of the circuit structure for implementing continuous two-level P logic in another embodiment. The two circuit structures of FIG2(a) and FIG2(b) are equivalent, wherein i>k>m>n>j, i, k, m, n, j respectively represent the bit number of the input data. When these two circuits are applied to an adder, i, k, m, n, j respectively represent the bit number of the data involved in the addition operation, such as i represents the i-th bit. As shown in FIG2(a), the circuit structure for implementing continuous two-level P logic is composed of three AND gates, and as shown in FIG2(b), the circuit structure for implementing continuous two-level P logic is composed of two NAND gates and one NOR gate. In one embodiment, the circuit structure for implementing continuous two-level P logic of P logic includes: two NAND gates and one NOR gate; wherein, the two inputs of one NAND gate are P respectively. i:k 、P k-1:m , the output is !P i:m ; The two inputs of the other NAND gate are P m-1:n 、P n-1:j , the output is !P m-1:j ; The two inputs of the NOR gate are the outputs of the two NAND gates! i:m and! P m-1:j , the output of the NOR gate is P i:j , where i>k>m>n>j, P i:j =nor(nand(P i:k ,P k-1:m ),nand(P m-1:n ,P n-1:j )).
[0071] In the two circuit structures shown in Figures 2(a) and 2(b), compared with the AND gate and the NAND gate, the AND gate uses one more inverter (inv) and has an additional delay of one inv. Compared with the NAND gate and the NOR gate, the areas used and the delays used by the two are almost the same. So, in general, the circuit structure for implementing two-stage continuous P logic in the embodiment of the present application shown in Figure 2(b) saves three invs in area compared to the typical circuit structure for implementing two-stage continuous P logic shown in Figure 2(a), and the longest path delay of the circuit is reduced by 2 invs. It can be seen that the P logic provided in the embodiment of the present application uses the simplest structure and the least logic gates to achieve the same function as the typical P logic. In other words, the P logic circuit structure provided in the embodiment of the present application is simple, better in area and delay, and has a good balance between power consumption and speed.
[0072] In an exemplary embodiment, taking continuous two-stage G logic as an example, FIG3(a) is a schematic diagram of the circuit structure for implementing continuous two-stage G logic in one embodiment, and FIG3(b) is a schematic diagram of the circuit structure for implementing continuous two-stage G logic in another embodiment. The two circuit structures of FIG3(a) and FIG3(b) are equivalent, wherein i>k>m>n>j, i, k, m, n, j respectively represent the bit of the input data. When these two circuits are applied to an adder, i, k, m, n, j respectively represent the bit of the data involved in the addition operation, such as i represents the i-th bit. Assume that the expression of FIG3(a) is: G i:j =function1(G i:k ,P i:k ,G k-1:m ,G m-1:n ,P m-1:n ,G n-1:j ,P i:m ), is a continuous two-stage G logic circuit structure in an embodiment. Assume that the expression of FIG3(b) is: G i:j =function2(G i:k ,P i:k ,G k-1:m ,G m-1:n ,P m-1:n ,G n-1:j ,! P i:m ). Comparing the two expressions, the results on the left side of the two equations are the same, and there is one different input item on the right side of the two equations. The different part is P i:m and! P i:m According to relevant technology, P i:m =and(P i:k ,P k-1:m ),! P i:m =nor(P i:k ,P k-1:m), therefore, under the premise of the same input items, P i:m and! P i:m The implementation can be converted using AND gate and NOR gate.
[0073] As shown in FIG3(a), in one embodiment, a circuit structure for realizing a continuous two-stage G logic is composed of three ao gates. As shown in FIG3(b), in another embodiment, a circuit structure for realizing a continuous two-stage G logic is composed of two and-or-invert (aoi) gates and one or-and-invert (oai) gate. In one embodiment, a circuit structure for realizing a continuous two-stage G logic of G logic includes: two and-or-invert gates and one or-and-invert gate; wherein, the three inputs of one of the and-or-invert gates are P i:k , G k-1:m and G i:k , the output is !G i:m ; The three inputs of the other AND-NOR gate are P m-1:n , G n-1:j and G m-1:n , the output is !G m-1:j ; The three inputs of the OR-NAND gate are the outputs of the two AND-NOR gates, namely! G i:m and! G m-1:j , and! P i:m , the output is G i:j , where i>k>m>n>j,
[0074] In the two circuit structures shown in Figures 3(a) and 3(b), compared with the aoi gate, the ao gate has an area of 1 more inv and a delay of 1 more inv. Compared with the aoi gate and the oai gate, the two have similar areas and delays. So, in general, the circuit structure of the embodiment of the present application shown in Figure 3(b) that implements continuous two-stage G logic saves 3 inv in area and reduces the longest path delay of the circuit by 2 inv compared to the typical circuit structure for implementing continuous two-stage G logic shown in Figure 3(a). It can be seen that the P logic provided in the embodiment of the present application uses the simplest structure and the least logic gates to achieve the same function as the typical G logic. That is to say, the G logic circuit structure provided in the embodiment of the present application is simple, better in area and delay, and has a good balance between power consumption and speed.
[0075] The adder is the most basic logical unit. In mainstream adder topologies, the core logic units include P logic circuits and G logic circuits. Reducing the adder circuit's footprint, power consumption, and latency to achieve higher frequencies and better performance is a pressing issue.
[0076] In an exemplary embodiment, an LFA adder is taken as an example, where LFA is the abbreviation of Lander Fischer Adder, and the LFA adder is derived using PG logic. FIG4 is a schematic diagram of a topological structure of an LFA adder circuit. The logic circuit represented by the black hexagonal schematic symbol in FIG4 is the first unit circuit shown in FIG5(a). The first unit circuit is used to generate P logic, G logic, and G i =and(a i ,b i ), P i =xor(a i ,b i ), a i 、b i The logic circuit represented by the black square symbol in FIG4 is the second unit circuit shown in FIG5(b). The second unit circuit is used to realize P i:j =and(P i-1:j ,P i:k ), G i:j =ao(G i:k ,P i:k ,G k-1:j ). The logic circuit represented by the gray square schematic symbol in FIG4 is shown as the third unit circuit in FIG5(c). The third unit circuit is used to implement G i:j =ao(G i:k ,P i:k ,G k-1:j ). The logic circuit represented by the gray hexagonal schematic symbol in FIG4 is the fourth unit circuit shown in FIG5(d). The fourth unit circuit is used to implement S i =xor(P i ,G i-1,0 ), S i The logic circuit represented by the black square symbol in FIG4 is a P logic + G logic circuit.
[0077] To reduce the LFA adder circuit's footprint, power consumption, and circuit delay, as shown in FIG7 , a combination of the fifth unit circuit (black pentagon symbol) shown in FIG6(a) and the sixth unit circuit (black diamond symbol) shown in FIG6(b) is employed, as well as a combination of the seventh unit circuit (gray pentagon symbol) shown in FIG6(c) and the eighth unit circuit (gray diamond symbol) shown in FIG6(d) is employed. The logic circuit represented by the black pentagonal symbol in FIG7 is a P logic + G logic circuit implemented using the P logic circuit and G logic circuit provided in an embodiment of the present application, as shown in FIG6(a). The logic circuit represented by the black diamond symbol in FIG7 is a P logic + G logic circuit implemented using the P logic circuit and G logic circuit provided in an embodiment of the present application, as shown in FIG6(b). The logic circuit represented by the gray pentagonal symbol in FIG7 is a G logic circuit implemented using the G logic circuit provided in an embodiment of the present application, as shown in FIG6(c). The logic circuit represented by the gray diamond schematic symbol in FIG7 is a G logic circuit implemented by the G logic circuit provided in an embodiment of the present application as shown in FIG6(d).
[0078] In one embodiment, FIG6(c) provides an implementation! The circuit structure of the G logic is the seventh unit circuit, as shown in FIG6(c). The G logic circuit in this embodiment includes an AND-NOR gate, and the three inputs of the AND-NOR gate are P i:k , G k-1:j and G i:k , the output of the AND-NOR gate is! G i:j , that is! G i:j =aoi(G i:k ,P i:k ,G k-1:j ), where i>k>j.
[0079] In one embodiment, FIG6(a) provides a circuit structure for implementing !P logic and !G logic, namely, the fifth circuit unit. As shown in FIG6(a), the P logic + G logic circuit in this embodiment further includes a NAND gate based on FIG6(c). As shown in FIG6(a), the three inputs of the AND-NOR gate are P i:k , G k-1:j and G i:k , the output of the AND-NOR gate is! G i:j ,! G i:j =aoi(G i:k ,P i:k ,G k-1:j );The two inputs of the NAND gate are P k-1:j 、P i:k , the output of the NAND gate is! Pi:j ,! P i:j =nand(P k-1:j ,P i:k ).
[0080] In one embodiment, FIG6(d) provides a circuit structure for implementing G logic, namely, the eighth circuit unit. As shown in FIG6(d), the G logic circuit in this embodiment includes an OR-NAND gate, and the three inputs of the OR-NAND gate are respectively! P i:k ,! G k-1:j and! G i:k , the output of the OR-NAND gate is G i:j , that is, G i:j =oai(!G i:k ,! P i:k ,! G k-1:j ).
[0081] In one embodiment, FIG6(b) provides a circuit structure for implementing P logic and G logic, namely the sixth circuit unit. As shown in FIG6(b), the P logic + G logic circuit in this embodiment further includes a NOR gate based on FIG6(d). As shown in FIG6(b), the three inputs of the OR-NAND gate are respectively! P i:k ,! G k-1:j and! G i:k , the output of the OR-NAND gate is G i:j , G i:j =oai(!G i:k ,! P i:k ,! G k-1:j ); The two inputs of the NOR gate are respectively! P k-1:j ,! P i:k , the output of the NOR gate is P i:j , P i:j =nor(!P k-1:j ,! P i:k ).
[0082] As shown in FIG7 , taking a multi-bit LFA adder of n+1=32 bits as an example, the LFA adder circuit provided in the embodiment of the present application includes seven stages of sequentially connected operation units, wherein the first stage operation unit includes n+1 first unit circuits; the second stage operation unit includes The third-level operation unit includes a fifth unit circuit and a seventh unit circuit; A NOT gate, The fourth-level operation unit includes a sixth unit circuit and two eighth unit circuits; A NOT gate, The fifth unit circuit and four seventh unit circuits; the fifth-level operation unit includes A NOT gate, The sixth unit circuit and eight eighth unit circuits; the sixth level operation unit includes The seventh unit circuit and 5 NOT gates; the seventh-level operation unit includes n fourth unit circuits and 21 NOT gates; among them,
[0083] In the first-level operation unit, each first unit circuit has an input including a i and b i , which is used to output G after operation i and P i ; Among them, a i is the information of each bit of data a involved in the addition operation, b i is the bit information of data b involved in the addition operation, i=0, 1, 2...n, n+1 represents the number of bits of data a and data b involved in the addition operation.
[0084] In the second-level operation unit, each fifth unit circuit has an input including G i:k 、P i:k , G k-1:j 、P k-1:j , which is used to output after operation! G i:j and! P i:j , where k=i, j=i-1, i=3, n-26, n-24…n-6, n-4, n-2, n; the input of the seventh unit circuit includes G i:k 、P i:k , G k-1:j , which is used to output after operation! G i:j , where k=i, j=i-1, i=1.
[0085] In the third-level arithmetic unit, every two sixth-unit circuits and a NOT gate form a third-level small arithmetic unit (called the first third-level small arithmetic unit), and two eighth-unit circuits and a NOT gate form another third-level small arithmetic unit (called the second third-level small arithmetic unit). In the first third-level small arithmetic unit, the input of the NOT gate is G i-1 and P i-1 , used to output !G i-1 and! P i-1 ; One of the inputs of the sixth unit circuit includes! G i:k ,! P i:k ,! G k-1:j ,! P k-1:j , which is used to output G after operation i:j and P i:j ; The input of another sixth unit circuit includes the output of the NOT gate, namely G i-1:k ,! P i-1:k And! G k-1:j ,! P k-1:j, which is used to output G after operation i-1:j and P i-1:j , where k = i-1, j = i-3, i = 7, n-20, n-16, n-12, n-8, n-4, n. In the second and third level small operation units, the input of the NOT gate is G i-1 and P i-1 , used to output !G i-1 and! P i-1 ; One of the inputs of the eighth unit circuit includes! G i:k ,! P i:k ,! G k-1:j , which is used to output G after operation i:j ; The input of another eighth unit circuit includes the output of the NOT gate, namely! G i-1 ,! P i-1 And! G k-1:j , which is used to output G after operation i-1:j , where k=i-1, j=i-3, i=3.
[0086] In the fourth-level arithmetic unit, every four fifth-unit circuits and a NOT gate form a fourth-level small arithmetic unit (called the first fourth-level small arithmetic unit), and four seventh-unit circuits and a NOT gate form another fourth-level small arithmetic unit (called the second fourth-level small arithmetic unit). In the first fourth-level small arithmetic unit, the input of the NOT gate is! G i-2:k and! P i-2:k , used to output G i-2:k and P i-2:k ; One of the fifth unit circuit inputs includes G i:k 、P i:k , G k-1:j 、P k-1:j , which is used to output after operation! G i:j and! P i:j ; Another fifth unit circuit input includes G i-1:k-1 、P i-1:k-1 , G k-1:j 、P k-1:j , which is used to output after operation! G i-1:j and! P i-1:j ; Another fifth unit circuit input includes the output of the NOT gate, namely G i-2:k 、P i-2:k , G k-1:j 、P k-1:j , which is used to output after operation! G i-2:j and! P i-2:j ; Another fifth unit circuit input includes G i-3:k 、P i-3:k , G k-1:j 、P k-1:j, which is used to output after operation! G i-3:j and! P i-3:j , where k = i-3, j = i-7, i = n-16, n-8, n. In the second and fourth level small operation units, the input of the NOT gate is! G i-2:k and! P i-2:k , used to output G i-2:k and P i-2:k ; One of the seventh unit circuit inputs includes G i:k 、P i:k , G k-1:j , which is used to output after operation! G i:j ; Another seventh unit circuit input includes G i-1:k 、P i-1:k , G k-1:j , which is used to output after operation! G i-1:j ; Another seventh unit circuit input includes the output of the NOT gate, namely G i-2:k 、P i-2:k and G k-1:j , which is used to output after operation! G i-2:j ; Another seventh unit circuit input includes G i-3:k 、P i-3:k , G k-1:j , which is used to output after operation! G i-3:j , where k=i-3, j=i-7, i=n-24.
[0087] In the fifth-level arithmetic unit, every eight sixth-unit circuits and three NOT gates form a fifth-level small arithmetic unit (called the first fifth-level small arithmetic unit), and eight eighth-unit circuits and three NOT gates form another fifth-level small arithmetic unit (called the second fifth-level small arithmetic unit). In the first fifth-level small arithmetic unit, the input of the first NOT gate is G i-4:k 、P i-4:k , the output is !G i-4:k ,! P i-4:k ;The input of the second NOT gate is G i-5:k 、P i-5:k , the output is !G i-5:k ,! P i-5:k ;The input of the third NOT gate is G i-7 、P i-7 , the output is !G i-7 ,! P i-7 ; Wherein, the input of the first and sixth unit circuits include! G i:k ,! P i:k ,! G k-1:j ,! P k-1:j , which is used to output G after operation i:j and P i:j; The inputs of the second and sixth unit circuits include! G i-1:k ,! P i-1:k ,! G k-1:j ,! P k-1:j , which is used to output G after operation i-1:j and P i-1:j ; The inputs of the third and sixth unit circuits include! G i-2:k ,! P i-2:k ,! G k-1:j ,! P k-1:j , which is used to output G after operation i-2:j and P i-2:j ; The inputs of the fourth and sixth unit circuits include! G i-3:k ,! P i-3:k ,! G k-1:j ,! P k-1:j , which is used to output G after operation i-3:j and P i-3:j The input of the fifth and sixth unit circuits includes the output of the first NOT gate, namely G i-4:k ,! P i-4:k And! G k-1:j ,! P k-1:j , which is used to output G after operation i-4:j and P i-4:j ; The input of the sixth unit circuit includes the output of the second NOT gate, that is, G i-5:k ,! P i-5:k And! G k-1:j ,! P k-1:j , which is used to output G after operation i-5:j and P i-5:j The input of the seventh and sixth unit circuits includes the output of the first NOT gate, namely G i-6:k ,! P i-6:k And! G k-1:j ,! P k-1:j , which is used to output G after operation i-6:j and P i-6:j ; The input of the eighth and sixth unit circuits includes the output of the third NOT gate, namely! G i-7:k ,! P i-7:k And! G k-1:j ,! P k-1:j , which is used to output G after operation i-7:j and P i-7:j ; Wherein, k = i-7, j = i-15, i = n, and in this embodiment, n = 31. In the second and fifth level small operation units, the input of the first NOT gate is G i-4:k 、P i-4:k , the output is !G i-4:k ,! P i-4:k ;The input of the second NOT gate is G i-5:k 、Pi-5:k , the output is !G i-5:k ,! P i-5:k ;The input of the third NOT gate is G i-7 、P i-7 , the output is !G i-7 ,! P i-7 ; Among them, the input of the first and eighth unit circuits includes! G i:k ,! P i:k ,! G k-1:j , which is used to output G after operation i:j ; The input of the second and eighth unit circuits include! G i-1:k ,! P i-1:k ,! G k-1:j , which is used to output G after operation i-1:j ; The inputs of the third and eighth unit circuits include! G i-2:k ,! P i-2:k ,! G k-1:j , which is used to output G after operation i-2:j ; The inputs of the fourth and eighth unit circuits include! G i-3:k ,! P i-3:k ,! G k-1:j , which is used to output G after operation i-3:j The input of the fifth and eighth unit circuits includes the output of the first NOT gate, namely G i-4:k ,! P i-4:k And! G k-1:j , which is used to output G after operation i-4:j The input of the sixth and eighth unit circuits includes the output of the second NOT gate, namely G i-5:k ,! P i-5:k And! G k-1:j , which is used to output G after operation i-5:j The input of the seventh and eighth unit circuits includes the output of the first NOT gate, namely G i-6:k ,! P i-6:k And! G k-1:j , which is used to output G after operation i-6:j ; The input of the eighth unit circuit includes the output of the third NOT gate, that is, G i-7:k ,! P i-7:k And! G k-1:j , which is used to output G after operation i-7:j ; Among them, k=i-7, j=i-15, i=n-16.
[0088] The sixth level arithmetic unit includes The seventh unit circuit and 5 NOT gates, where the input of each NOT gate is! G i-8-P:k and! P i-8-P:k , used to output G i-8-P:k and Pi-8-P:k , p = 0, 1, 2, 3 and 6; the input of each seventh unit circuit includes G n-m:k 、P n-m:k , G k-1:j , which is used to output after operation! G n-m:j , where k=i-15, j=i-31, i=17, 18, 19...n; m=0, 1, 2...15.
[0089] The seventh-level operation unit includes n fourth unit circuits and 21 NOT gates, where the input of each NOT gate is! G n-P:0 and! P n-P:0 , used to output G n-P:0 and P n-P:0 , p=0,1,2,3…15,24,25,26,27 and 30; the input of each fourth unit circuit includes G i-1:0 、P i , used to output S after addition operation i , where i = 1, 2, 3...n, S0 = P0, carry = G 31:0 .
[0090] By comparing FIG4 and FIG7 , it is not difficult to see that the topology of the entire LFA adder circuit reconstructed as shown in FIG7 , compared with the topology of the LFA adder circuit shown in FIG4 , combined with the analysis of FIG2( b ) and FIG3( b ), adopts a circuit with the simplest structure and the least logic gates to implement the LFA adder. In other words, the LFA adder circuit provided in the embodiment of the present application has a simple structure, is better in terms of area and latency, has lower power consumption, and strikes a good balance between power consumption and speed, thereby making the circuit run at a faster frequency and have better performance.
[0091] It should be noted that, as shown in FIG7, some NOT gate circuits will be added when necessary, as shown in FIG7 As shown in the schematic diagram symbols, correct logic implementation is ensured, which is something that a person skilled in the art can easily think of when implementing an LFA adder based on the P logic circuit and the G logic circuit provided in the embodiment of the present application.
[0092] In one exemplary embodiment, a BK adder is used as an example, where BK stands for Brent Kung Adder. The BK adder was proposed by Richard P. Brent and Professor H.T. Kung in the 1980s and is derived using typical PG logic. FIG8 is a schematic diagram of the topology of a BK adder circuit in one embodiment, and FIG9 is a schematic diagram of the topology of a BK adder circuit in another embodiment. In this embodiment, the BK adder circuit of the present application shown in FIG9 also uses a combination of the fifth unit circuit shown in FIG6(a), whose corresponding schematic symbol is a black pentagon, and the sixth unit circuit shown in FIG6(b), whose corresponding schematic symbol is a black diamond. Furthermore, a combination of the seventh unit circuit shown in FIG6(c), whose corresponding schematic symbol is a gray pentagon, and the eighth unit circuit shown in FIG6(d), whose corresponding schematic symbol is a gray diamond, is used.
[0093] As shown in FIG9 , taking a multi-bit BK adder of n+1=32 bits as an example, the BK adder circuit provided in the embodiment of the present application includes ten stages of sequentially connected operation units, wherein the first stage operation unit includes n+1 first unit circuits; the second stage operation unit includes The third-level operation unit includes a fifth unit circuit and a seventh unit circuit; The fourth-level operation unit includes a sixth unit circuit and an eighth unit circuit; The fifth unit circuit and the seventh unit circuit are included; the fifth-level operation unit includes one sixth unit circuit and one eighth unit circuit; the sixth-level operation unit includes two seventh unit circuits and one NOT gate; the seventh-level operation unit includes two eighth unit circuits and two NOT gates, and one seventh unit circuit; the eighth-level operation unit includes four seventh unit circuits and four NOT gates, and three eighth unit circuits; the ninth-level operation unit includes seven seventh unit circuits, eight eighth unit circuits, and eight NOT gates; the tenth-level operation unit includes n fourth unit circuits and nine NOT gates; among them,
[0094] In the first-level operation unit, each first unit circuit has an input including a i and b i , which is used to output G after operation i and P i ; Among them, a i is the information of each bit of data a involved in the addition operation, b i is the information of each bit of data b involved in the addition operation, i=0, 1, 2...n, n represents the number of bits of data a and data b involved in the addition operation.
[0095] In the second-level operation unit, each fifth unit circuit has an input including G i:k 、Pi:k , G k-1:j 、P k-1:j , which is used to output after operation! G i:j and! P i:j , where k=i, j=i-1, i=n, n-2, n-4, n-6…n-24, n-26, 3; the input of the seventh unit circuit includes G i:k 、P i:k , G k-1:j , which is used to output after operation! G i:j , where k=i, j=i-1, i=1.
[0096] In the third-level operation unit, the input of each sixth unit circuit includes! G i:k ,! P i:k ,! G k-1:j ,! P k-1:j , which is used to output G after operation i-m:j and P i-m:j ; Wherein, k = i-1, j = i-3, i = n, n-4, n-8, n-2, n-12, n-16, n-20, 7. The input of the eighth unit circuit includes! G i:k ,! P i:k ,! G k-1:j , which is used to output G after operation i:j , where k=i-1, j=i-3, i=3.
[0097] In the fourth-level operation unit, the input of each fifth unit circuit includes G i:k 、P i:k , G k-1:j 、P k-1:j , which is used to output after operation! G i:j and! P i:j , where k = i-3, j = i-7, i = n, n-8, n-16. The seventh unit circuit input includes G i:k 、P i:k , G k-1:j , which is used to output after operation! G i:j , where k=i-3, j=i-7, i=7.
[0098] In the fifth-level operation unit, the input of a sixth unit circuit includes! G i:k ,! P i:k ,! G k-1:j ,! P k-1:j , which is used to output G after operation i:j and P i:j ; Wherein, k = i-7, j = i-15, i = n; the input of an eighth unit circuit includes! Gi:k ,! P i:k ,! G k-1:j , which is used to output G after operation i:j , where k=i-7, j=i-15, i=n-16=15.
[0099] In the sixth-level operation unit, the input of a NOT gate is! G i-8:k and! P i-8:k , used to output G i-8:k and P i-8:k ; One of the seventh unit circuit inputs includes G i:k 、P i:k , G k-1:j , which is used to output after operation! G i:j The input of the seventh unit circuit includes the output of the NOT gate, namely G i-8:k 、P i-8:k and G k-1:j , which is used to output after operation! G i-8:j , where k=i-15, j=i-31, i=n.
[0100] In the seventh-level arithmetic unit, the input of a seventh unit circuit includes G i-12:k 、P i-12:k and G k-1:j , which is used to output after operation! G i-12:j ; The input of one of the NOT gates (the first NOT gate) is G i-4:k+8 and P i-4:k+8 , used to output !G i-4:k+8 and! P i-4:k+8 , one of the inputs of the eighth unit circuit includes the output of the first NOT gate, that is! G i-4:k+8 and! P i-4:k+8 And! G k-1:j , which is used to output G after operation i-4:j ; The input of the other NOT gate (the second NOT gate) is G i-20:k-8 and P i-20:k-8 , used to output !G i-20:k-8 and! P i-20:k-8 , the input of another eighth unit circuit includes the output of the second NOT gate, that is! G i-20:k-8 and! P i-20:k-8 And! G k-1:j , which is used to output G after operation i-20:j ; Among them, k=16, j=i-31, i=n.
[0101] In the eighth-level arithmetic unit, the inputs of the four NOT gates are:! G i:k and! P i:k ,! G i-12:k-12 and! Pi-12:k-12 ,! G i-16:k and! P i-16:k ,! G i-24:k and! P i-24:k , respectively used to output G i:k and P i:k , G i-12:k-12 and P i-12:k-12 , G i-16:k and P i-16:k , G i-24:k and P i-24:k ; The inputs of the 4 seventh unit circuits include: the output of the NOT gate, i.e. G i:k 、P i:k and G k-2:j The output of the NOT gate is G i-12:k-12 、P i-12:k-12 and G k-14:j The output of the NOT gate is G i-16:k-16 、P i-16:k-16 and G k-18:j The output of the NOT gate is G i-24:k-24 、P i-24:k-24 and G k-26:j , which are used to output respectively after operation:! G i:j ,! G i-12:j ,! G i-16:j and,! G i-24:j ; The inputs of the three eighth unit circuits include:! G i-4:k-4 ,! P i-4:k-4 and! G k-5:j ,! G i-8:k-8 ,! P i-8:k-8 and! G k-9:j ,! G i-20:k-20 ,! P i-20:k-20 and! G k-21:j , which are used to output G after operation. i-4:j , G i-8:j and G i-20:j ; Among them, k=i-1, j=i-29, i=n-2.
[0102] In the ninth-level arithmetic unit, the inputs of the seven seventh-unit circuits are: G i:k 、P i:k and G k-1:j , used to output after operation! G i:j , where k=i, j=0, and the values of i for the seven seventh unit circuits are: i=n-3, n-5, n-9, n-15, n-19, n-21, n-27; the input of each NOT gate is: G i:k and P i:k , for output! G i:k and! Pi:k , the output of each NOT gate is connected to an input of each eighth unit circuit, and the input of each eighth unit circuit includes! G i:k ,! P i:k and! G k-1:j-i , which are used to output G after operation i-4:j ; Among them, k=i, j=i, and the values of i corresponding to the 8 NOT gates are: i=n-1, n-7, n-11, n-13, n-17, n-23, n-25, n-29.
[0103] The tenth-level operation unit includes n fourth unit circuits and 9 NOT gates, where the input of each NOT gate is! G i-P:0 and! P i-P:0 , used to output G i-P:0 and P i-P:0 , the value of i corresponding to each NOT gate is n, p=0, 3, 5, 9, 15, 19, 21, 27 and 30; the input of each fourth unit circuit includes G i-1:0 、P i , used to output S after operation i , where the value of i corresponding to each fourth unit is: i=1, 2, 3…n, except S0=P0, carry=G 31:0 .
[0104] By comparing Figure 8 and Figure 9, it is not difficult to see that the topology of the reconstructed entire BK adder circuit shown in Figure 9, relative to the topology of the BK adder circuit shown in Figure 8, combined with the analysis of Figure 2(b) and Figure 3(b), adopts the circuit with the simplest structure and the least logic gates to implement the BK adder. That is, the BK adder circuit provided in the embodiment of the present application has a simple structure, is better in terms of area and delay, has lower power consumption, and has a good balance between power consumption and rate, thereby making the circuit run faster and having better performance.
[0105] It should be noted that, as shown in FIG9 , some NOT gate circuits will be added when necessary, as shown in FIG9 As shown in the schematic diagram symbols, correct logic implementation is ensured, which is something that a person skilled in the art can easily think of when implementing an LFA adder based on the P logic circuit and the G logic circuit provided in the embodiment of the present application.
[0106] As described above, an embodiment of the present application provides an adder circuit, wherein the P logic circuit adopts the P logic circuit provided by any one of the embodiments of the present application, and wherein the G logic circuit adopts the G logic circuit provided by any one of the embodiments of the present application.
[0107] Although the embodiments disclosed in this application are as described above, the contents described are merely embodiments adopted to facilitate understanding of this application and are not intended to limit this application. Any person skilled in the art to which this application belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application. However, the scope of patent protection of this application shall still be based on the scope defined by the attached claims.
Claims
1. A logic operation unit circuit, characterized in that: Applied to a multi-bit adder, the logic operation unit circuit is used to implement !G logic and !P logic, including: an AND-NOR gate, an NAND gate; The three inputs of the AND-NOR gate are P i:k , G k-1:j and G i:k , the output of the AND-NOR gate is! G i:j ; The two inputs of the NAND gate are P k-1:j , the P i:k , the output of the NAND gate is! P i:j ; Among them, i, k, and j respectively represent the bit data of the input data of the adder, i>k>j.
2. A logic operation unit circuit, characterized in that: Applied to a multi-bit adder, the logic operation unit circuit is used to implement G logic and P logic, including: an OR-NAND gate, an NOR gate; The three inputs of the OR-NAND gate are respectively! i:k ,! G k-1:j and! G i:k , the output of the OR-NAND gate is G i:j ; The two inputs of the NOR gate are respectively! k-1:j , as mentioned! i:k , the output of the NOR gate is P i:j ; Among them, i, k, and j respectively represent the bit data of the input data of the adder, i>k>j.
3. A logic operation unit circuit, characterized in that: Applied to a multi-bit adder, the logic operation unit circuit is used to implement P logic, including: two NAND gates and one NOR gate; wherein, The two inputs of a NAND gate are P i:k , P k-1:m , the output is! P i:m ; The two inputs of the other NAND gate are P m-1:n , P n-1:j , the output is! P m-1:j ; The two inputs of the NOR gate are the outputs of the two NAND gates, and the output of the NOR gate is P i:j ; Wherein, i, k, m, n, j respectively represent the bit data of the input data of the adder, i>k>m>n>j.
4. A logic operation unit circuit, characterized in that: Applied to a multi-bit adder, the logic operation unit circuit is used to implement G logic, including: two AND-NOR gates and one OR-NAND gate; wherein, The three inputs of an AND-NOR gate are P i:k , G k-1:m and G i:k , the output is! G i:m ; The three inputs of the other AND-NOR gate are P m-1:n , G n-1:j and G m-1:n , the output is! G m-1:j ; The three inputs of the OR-NAND gate are the outputs of the two AND-NOR gates, and! i:m , the output is G i:j ; Wherein, i, k, m, n, j respectively represent the bit data of the input data of the adder, i>k>m>n>j.
5. An adder circuit, characterized in that: A logic operation unit circuit comprising any combination of claims 1 to 4.
6. The adder circuit according to claim 5, wherein: The adder is an LFA adder or a BK adder.
7. An adder circuit, characterized in that: The adder is an n+1=32-bit LFA adder; the LFA adder includes seven stages of sequentially connected operation units, wherein: The first-level operation unit includes n+1 first unit circuits, wherein the first unit circuits are used to generate P logic and G logic. i =and(a i ,b i ), P i =xor(a i ,b i ), a i 、b i Respectively represent the i-th bit data of data a and data b participating in the LFA adder operation; The second-level computing unit includes a logic operation unit circuit as claimed in claim 1, and a seventh unit circuit; wherein, The seventh unit circuit is used to implement !G logic, including: an AND-NOR gate, the three inputs of the AND-NOR gate are P i:k , G k-1:j and G i:k , the output of the AND-NOR gate is! G i:j , wherein i, k, and j respectively represent the bit data of the input data of the adder, i>k>j; The third-level computing unit includes A NOT gate, A logic operation unit circuit as claimed in claim 2, and two eighth unit circuits; wherein, The eighth unit circuit is used to implement G logic, including: an OR-NAND gate, and the three inputs of the OR-NAND gate are respectively! i:k ,! G k-1:j and! G i:k , the output of the OR-NAND gate is G i:j , wherein i, k, and j respectively represent the bit data of the input data of the adder, i>k>j; The fourth level arithmetic unit includes A NOT gate, a logic operation unit circuit as claimed in claim 1, and four of the seventh unit circuits; The fifth level arithmetic unit includes A NOT gate, a logic operation unit circuit as claimed in claim 2, and eight of the eighth unit circuits; The sixth level arithmetic unit includes The seventh unit circuit, and 5 NOT gates; The seventh-level operation unit includes n fourth unit circuits and 21 NOT gates, wherein the fourth unit circuit is used to implement S i =xor(P i ,G i-1,0 ), S i Represents the i-th bit data after being operated by the LFA adder.
8. An adder circuit, characterized in that: The adder is an n+1=32-bit BK adder; the BK adder includes ten stages of sequentially connected operation units, wherein: The first-level operation unit includes n+1 first unit circuits, wherein the first unit circuits are used to generate P logic and G logic. i =and(a i ,b i ), P i =xor(a i ,b i ), a i 、b i Respectively represent the i-th bit data of data a and data b participating in the LFA adder operation; The second-level computing unit includes a logic operation unit circuit as claimed in claim 1, and a seventh unit circuit; wherein, The seventh unit circuit is used to implement !G logic, including: an AND-NOR gate, the three inputs of the AND-NOR gate are P i:k , G k-1:j and G i:k , the output of the AND-NOR gate is! G i:j , wherein i, k, and j respectively represent the bit data of the input data of the adder, i>k>j; The third-level computing unit includes a logic operation unit circuit as claimed in claim 2, and an eighth unit circuit; wherein, The eighth unit circuit is used to implement G logic, including: an OR-NAND gate, and the three inputs of the OR-NAND gate are respectively! i:k ,! G k-1:j and! G i:k , the output of the OR-NAND gate is G i:j , wherein i, k, and j respectively represent the bit data of the input data of the adder, i>k>j; The fourth level arithmetic unit includes a logic operation unit circuit as claimed in claim 1, and a seventh unit circuit; The fifth-level operation unit comprises a logic operation unit circuit as claimed in claim 2, and the eighth unit circuit as claimed in claim 1; The sixth-level operation unit includes two seventh-unit circuits and one NOT gate; The seventh-level operation unit includes two of the eighth unit circuits and two NOT gates, and one of the seventh unit circuits; The eighth-level operation unit includes four seventh-unit circuits and four NOT gates, and three eighth-unit circuits; The ninth-level operation unit includes 7 of the seventh unit circuits, 8 of the eighth unit circuits and 8 NOT gates; The tenth-level operation unit includes n fourth unit circuits and 7 NOT gates; wherein the fourth unit circuit is used to implement S i =xor(P i ,G i-1,0 ), S i Represents the i-th bit data after being operated by the LFA adder.