Circuit board, and semiconductor package comprising same

Abstract

A circuit board according to an embodiment comprises: a build-up structure including an insulating layer and a wiring layer; a protective layer arranged on the build-up structure; and bonding portions passing through the protective layer and electrically connected to the build-up structure, wherein a side surface of the bonding portions includes a portion that does not overlap the protective layer in the horizontal direction and has a reduced inclination angle with respect to the upper surface of the protective layer.

Description

Circuit boards and semiconductor packages including the same

[0001] The embodiment relates to a circuit board and a semiconductor package board including the same.

[0002] As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to accommodate a greater number of semiconductor devices on a limited-size semiconductor package substrate. However, conventional semiconductor packages typically consist of a single semiconductor device, limiting their ability to achieve desired performance.

[0003] Accordingly, semiconductor packages that incorporate multiple semiconductor devices across multiple circuit boards have recently been developed. These semiconductor packages have a structure in which multiple semiconductor devices are connected horizontally and / or vertically on the circuit board. Consequently, semiconductor packages offer the advantages of efficiently utilizing the mounting area of ​​semiconductor devices and enabling high-speed signal transmission through short signal transmission paths between semiconductor devices.

[0004] In addition, semiconductor packages applied to products that provide the Internet of Things (IoT), autonomous vehicles, and high-performance servers are expanding their concept to semiconductor chiplets as the number of semiconductor elements and / or the size of each semiconductor element increases in line with the trend toward high integration, or as the functional parts of semiconductor elements are divided.

[0005] Accordingly, intercommunication between semiconductor elements and / or semiconductor chiplets is becoming more important, and accordingly, there is a trend toward placing an interposer between the semiconductor element and the semiconductor package substrate connected to the main board of the electronic device.

[0006] An interposer can function as a redistribution layer that gradually increases the width or depth of a circuit pattern from a semiconductor device toward a semiconductor package to facilitate communication between semiconductor devices and / or semiconductor chiplets, or to interconnect a semiconductor device and a semiconductor package substrate. This allows for the smooth transmission of electrical signals between the semiconductor device and a semiconductor package substrate having a relatively large circuit pattern compared to the circuit pattern of the semiconductor device.

[0007] Meanwhile, a semiconductor package substrate and / or interposer applied to a semiconductor package comprises a build-up structure (100) having an insulating layer and a wiring layer stacked in a vertical direction, a protective layer disposed on the build-up structure (100), and a plurality of bonding portions electrically connected to the build-up structure (100) by penetrating the protective layer. At this time, the plurality of bonding portions are configured to be formed by performing a plating process at the very end in the manufacturing process of the semiconductor package substrate and / or interposer. At this time, a difference in plating conditions such as a plating current applied to each bonding portion during the plating process of the plurality of bonding portions may occur, and thus the plurality of bonding portions may have different heights. Due to this, a height deviation occurs between the plurality of bonding portions, and semiconductor elements may not be stably placed on the plurality of bonding portions.

[0008] Additionally, a connecting member may be embedded in the semiconductor package substrate and / or interposer. At this time, the package substrate and / or interposer may be provided with a plurality of bonding portions that are connected to the semiconductor element and / or semiconductor chiplet. The bonding portion may include a first bonding portion that does not vertically overlap with the connecting member, and a second bonding portion that vertically overlaps with the connecting member and horizontally overlaps with the first bonding portion.

[0009] At this time, the first bonding portion and the second bonding portion may have different widths along the horizontal direction and / or different thicknesses along the vertical direction. That is, the width and / or thickness of the second bonding portion may depend on the width of the pad provided on the connecting member and the height of the upper surface of the pad, but the width and height of the first bonding portion are not dependent on the width and / or height of the pad provided on the connecting member. That is, when the integration of the number of I / O (Input and Output) terminals of the connecting member increases, the amount of current generated during plating of the first and second bonding portions differs depending on the diameter and density of the through-holes of the insulating layer and / or protective layer arranged on the pad of the connecting member, and accordingly, the height of the second bonding portion may be different from the height of the first bonding portion.

[0010] Therefore, the plurality of bonding portions according to the prior art may have height deviations due to differences in width and / or thickness between them. In addition, when a height deviation occurs between the plurality of bonding portions, a problem may arise in which the semiconductor elements and / or semiconductor chiplets cannot be stably mounted on the plurality of bonding portions. As a result, problems may arise in which the operating characteristics, reliability, and yield of the semiconductor elements and / or semiconductor chiplets deteriorate.

[0011] The embodiment provides a circuit board of a novel structure and a semiconductor package including the same.

[0012] In addition, the embodiment provides a circuit board and a semiconductor package including the same that improves the height deviation between a plurality of bonding portions.

[0013] In addition, the embodiment provides a circuit board capable of miniaturizing a plurality of bonding portions and a semiconductor package including the same.

[0014] In addition, the embodiment provides a circuit board and a semiconductor package including the same that can improve electrical reliability problems that may occur when a plurality of adjacent bonding members are connected to each other.

[0015] The technical tasks to be achieved in the proposed embodiment are not limited to the technical tasks mentioned above, and other technical tasks not mentioned can be clearly understood by a person having ordinary skill in the technical field to which the proposed embodiment belongs from the description below.

[0016] A circuit board according to an embodiment comprises a build-up structure including an insulating layer and a wiring layer; a protective layer disposed on the build-up structure; and a bonding portion electrically connected to the build-up structure by penetrating the protective layer, wherein a side surface of the bonding portion does not overlap the protective layer along a horizontal direction and includes a portion having a small inclination angle with respect to an upper surface of the protective layer.

[0017] In addition, the side surface of the bonding portion includes a first side surface that overlaps the protective layer in a horizontal direction, and a second side surface that is disposed on the first side surface and corresponds to a portion where the inclination angle decreases, and the second side surface has a predetermined inclination with respect to the first side surface, and the vertical length of the first side surface is greater than the vertical length of the second side surface.

[0018] Additionally, the vertical length of the first side is smaller than the vertical thickness of the protective layer.

[0019] Additionally, the side surface of the protective layer includes an inner side surface forming a through hole and an outer side surface surrounding the inner side surface, and the second side surface does not contact the inner side surface of the protective layer.

[0020] Additionally, the difference between the vertical thickness of the protective layer and the vertical length of the first side is smaller than the vertical length of the first side.

[0021] Additionally, the difference between the vertical thickness of the protective layer and the vertical length of the first side is smaller than the vertical length of the second side.

[0022] Additionally, the upper surface of the protective layer has at least one of a convex portion and a concave portion.

[0023] Additionally, the protective layer has a plurality of fillers, and each of the plurality of fillers does not contact the bonding portion.

[0024] Additionally, at least one of the plurality of fillers is exposed to the upper surface of the protective layer.

[0025] Additionally, the circuit board further includes a connecting member embedded within the build-up structure, the connecting member overlapping the side surface of the bonding portion along a vertical direction.

[0026] Additionally, at least one of the plurality of fillers is in contact with at least one of the insulating layer and the wiring layer of the build-up structure.

[0027] In addition, the lower surface of the protective layer has at least one of a concave portion and a convex portion, and at least one of the insulating layer and the wiring layer of the build-up structure has a convex portion and a concave portion corresponding to at least one of the concave portion and the convex portion provided on the lower surface of the protective layer.

[0028] In addition, the insulating layer has a recess on the upper surface, the wiring layer is disposed within the recess of the insulating layer, and the bonding portion vertically overlaps the wiring layer disposed within the recess.

[0029] In addition, the wiring layers are provided in a plurality of pieces spaced apart along a vertical direction, and the build-up structure includes a plurality of through electrodes connecting the plurality of wiring layers, side surfaces of the plurality of through electrodes have the same inclination, and the inclination of the second side surface of the bonding portion is inclined in the same direction as the inclination of the side surfaces of the plurality of through electrodes.

[0030] Additionally, the circuit board further includes a connecting member embedded within the build-up structure, and a pad portion of the connecting member is electrically connected to the bonding portion through the wiring layer.

[0031] Additionally, at least a portion of the second side overlaps the protective layer in a horizontal direction and is spaced apart from the inner surface of the through hole of the protective layer.

[0032] Additionally, the vertical length of the first side satisfies a range of 1.2 to 3 times the vertical length of the second side.

[0033] Meanwhile, a circuit board according to an embodiment includes a build-up structure including an insulating layer and a wiring layer; a protective layer disposed on the build-up structure; and a bonding portion electrically connected to the build-up structure by penetrating the protective layer, wherein the bonding portion includes an upper surface, a lower surface, and a side surface between the upper surface and the lower surface, and the side surface of the bonding portion includes a first side surface having a first inclination angle with respect to the lower surface of the bonding portion, and a second side surface having a second inclination angle smaller than the first inclination angle with respect to the lower surface of the bonding portion, and a vertical length of the first side surface is greater than a vertical length of the second side surface.

[0034] Additionally, the first side overlaps the protective layer entirely in a horizontal direction, the second side overlaps the protective layer partially in a horizontal direction, and the second side includes a portion that overlaps the protective layer in a horizontal direction and does not contact the inner surface of the through hole of the protective layer.

[0035] Additionally, the upper surface of the protective layer is provided with unevenness.

[0036] Additionally, the protective layer includes a plurality of fillers, and at least one of the plurality of fillers is in contact with at least one of the insulating layer and the wiring layer.

[0037] An embodiment includes a build-up structure including an insulating layer and a wiring layer, a protective layer disposed on the build-up structure, and a bonding portion electrically connected to the build-up structure by penetrating the protective layer. At this time, the bonding portion may be formed preferentially over the build-up structure in a manufacturing process of a circuit board. Specifically, the embodiment may prepare a carrier member having a metal member, and then form the bonding portion on the metal member of the carrier member. In addition, after laminating a protective layer covering the bonding portion on the metal member of the carrier member, the protective layer may be etched with a chemical solution so that the thickness of the protective layer becomes less than or equal to the thickness of the bonding portion, and thereafter, a process of laminating the build-up structure in a state where the bonding portion and the protective layer are disposed may be performed. Through this, the embodiment may allow a plurality of bonding portions to have a uniform height since the bonding portion is formed preferentially in the manufacturing process of the circuit board. Accordingly, the embodiment may enable a semiconductor device to be stably mounted on the bonding portion, and thus improve the connection reliability between the semiconductor device and the circuit board.

[0038] In addition, the bonding portion may have a side surface between the upper surface and the lower surface. And the side surface of the bonding portion may have a first portion that overlaps the protective layer in a horizontal direction, and a second portion that does not overlap the protective layer in a horizontal direction. At this time, the first side surface of the first portion of the bonding portion may have a first slope, and the first slope may be perpendicular to the upper surface and / or the lower surface of the bonding portion. At this time, when the first slope is greater than 90°, it may be difficult to refine the pitch between the plurality of bonding portions. Therefore, by making the first slope close to 90° with respect to the lower surface of the bonding portion, the pitch between the plurality of bonding portions may be refined while increasing the contact area between the bonding portion and the wiring layer, thereby improving the adhesion.

[0039] In addition, the second part of the bonding portion may have a second side having a second slope different from the first slope of the first side of the first part, and in particular, may have a slope that increases in the horizontal width along the direction from the upper surface to the lower surface of the bonding portion. At this time, the second side of the second part of the bonding portion is a part that comes into contact with a bonding member such as solder, and by having the second side of the second part of the bonding portion have the above-described slope, the horizontal spacing between the plurality of bonding portions can be increased while maintaining the pitch between the plurality of bonding portions. That is, the embodiment can increase the separation distance between the second parts of each of the plurality of bonding portions by utilizing the slope of the second side of the second part of the bonding portion. Through this, the embodiment can further prevent an electrical short-circuit problem caused by two adjacent bonding members being connected to each other, and can improve the mechanical reliability and / or electrical reliability of the circuit board and the semiconductor package accordingly.

[0040] Furthermore, the embodiment can improve the flowability of the bonding member by allowing the bonding member to flow along the inclination of the second side of the second portion of the bonding portion. In addition, the direction in which the inclination of the second side of the second portion of the bonding portion is inclined can be the same as the direction in which the inclination of the through electrode provided in the build-up structure is inclined. Through this, the embodiment can easily control the stress applied to the circuit board, and further, it can easily design the thickness, wiring density, and width of the wiring layer and the through electrode to prevent the circuit board from being bent in a specific direction.

[0041] In addition, the vertical length of the first side of the first part of the bonding portion may be greater than the vertical length of the second side of the second part of the bonding portion. Through this, the embodiment can ensure that the bonding portion is stably protected by the protective layer, and can improve the adhesion between the bonding portion and the protective layer and / or the wiring layer. For example, when the vertical length of the first side of the first part is less than the vertical length of the second side of the second part, stress may be applied to the bonding portion during the process of removing a part of the protective layer by etching with a chemical solution, which may cause a problem in that the bonding portion is peeled off from the wiring layer and / or the protective layer. Therefore, the embodiment can improve the reliability problem in that the bonding portion is peeled off from the protective layer and / or the wiring layer by making the vertical length of the first side of the first part of the bonding portion greater than the vertical length of the second side of the second part.

[0042] In addition, the vertical length of the first side of the first part of the bonding portion may be smaller than the thickness of the protective layer. That is, the lowermost end of the second side of the second part of the bonding portion may be positioned lower than the upper surface of the protective layer. At least a portion of the second side of the second part of the bonding portion may horizontally overlap the protective layer and be spaced apart from the inner surface of the through hole of the protective layer. For example, a space may be provided between the second side of the second part of the bonding portion and the inner surface of the protective layer. The space may function as a dam that blocks the flow of the bonding member applied on the bonding portion. That is, when the bonding member applied on the bonding portion spreads horizontally, the space may prevent the bonding member from spreading to a location where another adjacent bonding member is arranged, thereby further improving the electrical reliability of the circuit board and / or semiconductor package.

[0043] At this time, the difference between the vertical thickness of the protective layer and the vertical length of the first side of the first part of the bonding portion may be smaller than the vertical length of the first side of the first part and / or the vertical length of the second side of the second part. Through this, the embodiment can prevent the bonding portion from being excessively removed in the process of removing a portion of the protective layer, thereby preventing deformation of the bonding portion, and since the bonding portion does not protrude above the protective layer, the semiconductor element may not be stably mounted.

[0044] Additionally, the upper surface of the protective layer may be provided with convex portions and / or concave portions. The convex portions and / or concave portions provided on the upper surface of the protective layer may function to increase the contact area with the molding member for molding the semiconductor element, thereby improving the adhesion between the protective layer and the molding member.

[0045] In addition, the convex and concave portions provided on the upper surface of the protective layer can increase the surface area of ​​the upper surface of the protective layer. Through this, the embodiment can prevent cracks from occurring in the bonding portion due to stress caused by a heat cycle. For example, a circuit board may experience stress due to heat cycles caused by thermal expansion and / or thermal contraction in a manufacturing process and / or an operating environment, and the stress may be transmitted to the bonding portion. In addition, if the stress continues to be applied to the bonding portion, cracks may occur in the bonding portion, which may cause mechanical reliability and / or electrical reliability problems. Furthermore, if the above-described stress acts on a bonding member such as a solder, cracks may occur in the bonding member, which may cause an electrical open problem between the semiconductor element and the bonding portion. In this case, the convex and / or concave portions provided on the upper surface of the protective layer function to increase the surface area, thereby increasing the transmission distance of the stress acting along the upper surface of the protective layer, thereby minimizing the magnitude of the stress transmitted to the bonding portion. Through this, the embodiment can minimize the stress transmitted to the bonding portion, thereby enabling the semiconductor element to be stably attached to the circuit board, thereby improving the mechanical and electrical reliability between the circuit board and the semiconductor element. Furthermore, the embodiment can enable the semiconductor element to operate stably, thereby improving the operational reliability of electronic products such as servers to which the semiconductor package is applied.

[0046] Additionally, at least one filler may be exposed on the upper surface of the protective layer. In this case, the exposed filler may function to prevent horizontal stress from being transmitted to the bonding portion, thereby further improving the electrical reliability and / or mechanical reliability of the bonding portion.

[0047] Additionally, at least one filler may be exposed on the lower surface of the protective layer, and an insulating layer provided on the uppermost side of the build-up structure may be in contact with the filler provided in the protective layer. In this case, the insulating layer has better adhesion with the filler of the protective layer than with the resin of the protective layer, thereby further improving the bonding strength between the protective layer and the insulating layer.

[0048] In addition, the lower surface of the protective layer may be provided with convex portions and / or concave portions. Accordingly, the upper surface of the insulating layer and / or the upper surface of the wiring layer may be provided with concave portions and / or convex portions corresponding to the convex portions and / or concave portions provided on the lower surface of the protective layer. Through this, the embodiment can further improve the adhesion between the protective layer and the insulating layer and / or the wiring layer, thereby further improving the mechanical reliability of the circuit board and the semiconductor package.

[0049] FIG. 1a is a cross-sectional view illustrating a circuit board according to an embodiment.

[0050] Figure 1b is a drawing showing a bonding buoy curved section according to the prior art.

[0051] Fig. 2 is an enlarged view of area A of Fig. 1 according to the first embodiment.

[0052] FIG. 3a is an enlarged view of area A of FIG. 1 according to the second embodiment.

[0053] FIG. 3b is an enlarged view of area A of FIG. 1 according to the third embodiment.

[0054] FIG. 4a is an enlarged view of area A of FIG. 1 according to the fourth embodiment.

[0055] FIG. 4b is an enlarged view of area A of FIG. 1 according to the fifth embodiment.

[0056] FIG. 5 is a cross-sectional view illustrating a circuit board and a semiconductor package including the same according to the sixth embodiment.

[0057] Fig. 6 is a cross-sectional view illustrating a semiconductor package according to an embodiment.

[0058] Figures 7 to 17 are cross-sectional views showing the manufacturing method of the circuit board illustrated in Figure 1 in process order.

[0059] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

[0060] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0061] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by those of ordinary skill in the technical field to which the present invention pertains, unless explicitly and specifically defined and described, and commonly used terms, such as terms defined in a dictionary, may be interpreted in consideration of the contextual meaning of the relevant technology. In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention.

[0062] In this specification, singular forms may also include plural forms unless specifically stated otherwise in the phrase, and when it is described as “A and / or at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C. In addition, when describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used.

[0063] These terms are only intended to distinguish the component from other components, and are not intended to limit the nature, order, or sequence of the component by the term. In addition, when a component is described as being "connected," "coupled," or "connected" to another component, it may include not only cases where the component is directly connected, coupled, or connected to the other component, but also cases where the component is "connected," "coupled," or "connected" by another component between the component and the other component.

[0064] Additionally, when described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Furthermore, when expressed as "above" or "below", it may include the meaning of the downward direction as well as the upward direction based on one component.

[0065] The terminology used in this application is only used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, it should be understood that the terms "comprise" or "have" indicate the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0066] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and shall not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0067]

[0068] Hereinafter, embodiments will be described in detail with reference to the attached drawings. Regardless of the drawing symbols, identical or corresponding components are given the same reference numbers, and redundant descriptions thereof will be omitted.

[0069]

[0070] Before describing the embodiment, an electronic device (not shown) to which the semiconductor package of the embodiment is applied will be briefly described. The electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive device, etc. However, the electronic device is not limited thereto, and it goes without saying that the electronic device may be any other electronic device that processes data.

[0071] An electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to a semiconductor package of the embodiment. Furthermore, the semiconductor package includes a circuit board, a semiconductor element, a bonding portion for electrically connecting the semiconductor element and the circuit board, a resin portion for filling the space between the semiconductor element and the circuit board, and a molding portion for entirely enclosing the semiconductor element.

[0072] Semiconductor devices may include active and / or passive components and may have various functions. Active devices may be in the form of integrated circuits (ICs) in which hundreds to millions of transistors are integrated into a single semiconductor device, and may be, for example, logic chips, memory chips, etc. For example, the logic chip may be an application processor (AP) device including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), etc., or a set of devices including a specific combination of the above. The memory chip may be a stacked memory such as HBM. In addition, the memory chip may include a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), or a flash memory.

[0073] The semiconductor package of the embodiment may be any one of a CSP (Chip Scale Package), an FC-CSP (Flip Chip-Chip Scale Package), an FC-BGA (Flip Chip Ball Grid Array), a POP (Package On Package), and a SIP (System In Package), but is not limited thereto.

[0074]

[0075] FIG. 1 is a cross-sectional view illustrating a circuit board according to an embodiment, FIG. 2 is an enlarged view of area A of FIG. 1 according to a first embodiment, FIG. 3a is an enlarged view of area A of FIG. 1 according to a second embodiment, FIG. 3b is an enlarged view of area A of FIG. 1 according to a third embodiment, FIG. 4a is an enlarged view of area A of FIG. 1 according to a fourth embodiment, FIG. 4b is an enlarged view of area A of FIG. 1 according to a fifth embodiment, FIG. 5 is a cross-sectional view illustrating a circuit board and a semiconductor package including the same according to a sixth embodiment, and FIG. 6 is a cross-sectional view illustrating a semiconductor package according to an embodiment.

[0076] Hereinafter, a circuit board and a semiconductor package including the same according to an embodiment will be specifically described with reference to FIGS. 1 to 6.

[0077] Referring to FIG. 1, a circuit board (10) includes a build-up structure (100), a protective layer (140) disposed on an upper surface and / or a lower surface of the build-up structure (100), and a bonding portion (150) electrically connected to the build-up structure (100) by penetrating the protective layer (140). The protective layer (140) may include a first protective layer (141) disposed on one surface of the build-up structure (100) and a second protective layer (142) disposed on the other surface of the build-up structure (100), and the bonding portion (150) may be provided by penetrating the first protective layer (141) disposed on one surface of the build-up structure (100). Here, the meaning of being arranged on one side and the other side should not be understood only as a configuration in direct contact with the one side and the other side, but should also be understood as having another configuration between one side of the build-up structure (100) and the first protective layer (141), and between the other side of the build-up structure (100) and the second protective layer (142).

[0078] The build-up structure (100) includes an insulating layer (110), a wiring layer (120), and a through electrode (130).

[0079] The insulating layer (110) may have a structure in which a plurality of layers are laminated along the vertical direction. The insulating layer (110) may include a first insulating layer (111) that is closest to the first protective layer (140) or the bonding portion (150) along the vertical direction, a second insulating layer (112) that is further away from the first protective layer (140) or the bonding portion (150) along the vertical direction than the first insulating layer (111), a third insulating layer (113) that is further away from the first protective layer (140) or the bonding portion (150) along the vertical direction than the second insulating layer (112), and a fourth insulating layer (114) that is further away from the first protective layer (140) or the bonding portion (150) along the vertical direction than the third insulating layer (113). In this case, the first insulating layer (111) may mean the uppermost insulating layer positioned at the top in the insulating layer (110) having a structure in which multiple layers are laminated, and the fourth insulating layer (114) may mean the lowermost insulating layer positioned at the bottom in the insulating layer (110) having a structure in which multiple layers are laminated. However, the present invention is not limited thereto, and the insulating layer (110) may further include a fifth insulating layer (not shown) positioned between the fourth insulating layer (114) and the second protective layer (125), a sixth insulating layer (not shown) positioned between the fifth insulating layer (not shown) and the second protective layer (125), etc.

[0080] The first to fourth insulating layers (111, 112, 113, 114) are arranged to vertically insulate between the first to fifth wiring layers (121, 122, 123, 124, 125) to be described later. For example, the first to fourth insulating layers (111, 112, 113, 114) may be formed using a thermosetting insulating material containing an inorganic filler in a resin, and Ajinomoto Build-up Film (ABF) of Ajinomoto Co., Ltd. may be used. However, the embodiment is not limited thereto, and a photo-curable insulating material (Photo Imageable Dielectric, PID) for forming a fine pattern may be used.

[0081] At least one of the first to fourth insulating layers (111, 112, 113, 114) may include an insulating material different from at least one other. For example, at least one of the first to fourth insulating layers (111, 112, 113, 114) may include a reinforcing member (114R). In one embodiment, the reinforcing member (114R) may mean glass fiber. In another embodiment, the reinforcing member (114R) may mean GCP (Glass Core Primer). The reinforcing member (114R) may be provided in at least one of the first to fourth insulating layers (111, 112, 113, 114) to improve the rigidity of the circuit board (10). The reinforcing member (114R) can prevent the circuit board (10) from being significantly bent in a specific direction, thereby improving the positional alignment of the wiring layer (120) and the through-electrode (130), thereby improving the electrical reliability and / or mechanical reliability of the circuit board (10) and the semiconductor package. In addition, the reinforcing member (114R) can improve the rigidity of the circuit board (10), thereby improving the processability in the process of mounting a semiconductor element on the circuit board (10), and improving the product yield. Therefore, the reinforcing member (114R) can enable the semiconductor element to be stably mounted on the circuit board (10) and can enable the semiconductor element to operate stably. Through this, electronic products such as servers to which the semiconductor package is applied can be stably operated, thereby improving the operational reliability. As illustrated in FIG. 1, the reinforcing member (114R) can be provided on the fourth insulating layer (114). That is, the circuit board (10) is manufactured in a state in which a carrier member (not shown) is arranged, and the fourth insulating layer (114) is the layer furthest from the carrier member. At this time, when the reinforcing member (114R) is arranged on the fourth insulating layer (114), the circuit board (10) can be further prevented from being bent in a specific direction during the process of removing the carrier member.However, the embodiment is not limited thereto, and the reinforcing member (114R) may be provided in an insulating layer other than the fourth insulating layer (114). For example, the reinforcing member (114R) may be alternately arranged in the vertical direction within the first to fourth insulating layers (111, 112, 113, 114), thereby further improving the rigidity of the circuit board (10).

[0082] The wiring layer (120) may include a first wiring layer (121) that is most adjacent to the first protective layer (141) or bonding portion (150) in the vertical direction, a second wiring layer (122) that is further away from the first protective layer (141) or bonding portion (150) than the first wiring layer (121), a third wiring layer (123) that is further away from the first protective layer (141) or bonding portion (150) than the second wiring layer (122), a fourth wiring layer (124) that is further away from the first protective layer (141) or bonding portion (150) than the third wiring layer (121), and a fifth wiring layer (125) that is further away from the first protective layer (141) or bonding portion (150) than the fourth wiring layer (124). The wiring layer (120) may have, for example, an ETS (Embedded Trace Substrate) structure to implement a fine pattern. Specifically, the wiring layer arranged on the uppermost or lowermost side among the first to fifth wiring layers (121, 122, 123, 124, 125) may be embedded in the insulating layer (110). Here, being embedded means that at least a portion of a side of the wiring layer having the ETS structure is covered with the insulating layer (110). The first wiring layer (121) may be embedded in the first insulating layer (121). The first wiring layer (121) is the wiring layer closest to the semiconductor element arranged on the circuit board (10). At this time, when the first wiring layer (121) is manufactured using the ETS method, the pads and traces constituting the first wiring layer (121) can be stably protected by the insulating layer, thereby enabling miniaturization and improving the circuit integration of the first wiring layer (121). Accordingly, it is possible to more easily electrically connect to the semiconductor element placed on the circuit board (10), and to enable the semiconductor element to operate more stably.

[0083] In addition, according to an embodiment having an ETS structure, a concave recess may be provided on the upper surface of the first insulating layer (111) toward the lower surface of the first insulating layer (110), and the first wiring layer (121) may be disposed within the recess of the first insulating layer (111). In addition, the second wiring layer (122) may be disposed within the recess provided on the upper surface of the second insulating layer (112), the third wiring layer (123) may be disposed within the recess provided on the upper surface of the third insulating layer (113), the fourth wiring layer (124) may be disposed within the recess provided on the upper surface of the fourth insulating layer (114), and the fifth wiring layer (125) may protrude below the lower surface of the fourth insulating layer (114). Accordingly, as described above, the circuit integration can be improved by miniaturizing the first to fifth wiring layers (121, 122, 123, 124, 125), the first to fifth wiring layers (121, 122, 123, 124, 125) can be protected from external contaminants such as moisture, and the reliability of the semiconductor package can be improved.

[0084] The first to fifth wiring layers (121, 122, 123, 124, 125) may each include traces for transmitting signals and / or power, and pads for connecting the traces of each of the first to fifth wiring layers (121, 122, 123, 124, 125) to other components. For example, referring to FIG. 1, the first wiring layer (121) and the second wiring layer (122) are connected by the first through electrode (131). At this time, in order for the traces of the first through electrode (131) and the second wiring layer (122) to be connected, the second wiring layer (122) may include a pad connected to the first through electrode (131). In addition, the first wiring layer (121) includes a bonding portion (150) to be connected to the external configuration of the build-up structure (100) such as a semiconductor element, and this bonding portion (150) is connected to the pad of the first wiring layer (121). That is, although FIG. 1 only illustrates the pad of the first wiring layer (121), the first wiring layer (121) may further include traces connecting between the plurality of pads illustrated in FIG. 1. In addition, when the first wiring layer (121) includes traces, a first protective layer (141) must be necessarily disposed to protect the traces, and in this case, the effect of the structural characteristics of the bonding portion (150) described below can be further maximized.

[0085] The first to fifth wiring layers (121, 122, 123, 124, 125) may function to electrically connect with semiconductor elements arranged on a circuit board (10). Each of the first to fifth wiring layers (121, 122, 123, 124, 125) may be freely designed in consideration of impedance. In addition, a through electrode (130) may be arranged within the insulating layer (110) to connect each of the first to fifth wiring layers (121, 122, 123, 124, 125). The through electrode (130) may include the first to fourth through electrodes (131, 132, 133, 134). For example, the first through-electrode (131) is disposed between the first wiring layer (121) and the second wiring layer (122), the second through-electrode (132) is disposed between the second wiring layer (122) and the third wiring layer (123), the third through-electrode (133) is disposed between the third wiring layer (123) and the fourth wiring layer (124), and the fourth through-electrode (134) is disposed between the fourth wiring layer (124) and the fifth wiring layer (125). The first to fifth wiring layers (121, 122, 123, 124, 125) are electrically connected to each other through the first to fourth through-electrodes (131, 132, 133, 134).

[0086] The first to fourth through-hole electrodes (131, 132, 133, 134) can be formed simultaneously in the process of arranging the second to fifth wiring layers (122, 123, 124, 125). For example, in the process of arranging the second wiring layer (122) under the first wiring layer (121), a through-hole can be formed in the first insulating layer (111) to expose a portion of the first wiring layer (121), thereby forming the second wiring layer (122) together with the first through-hole electrode (131) filling the through-hole of the first insulating layer (111). Therefore, the first through-hole electrode (131) can be distinguished as a protrusion of the second wiring layer (122). Likewise, each of the second to fourth through-hole electrodes (132, 133, 134) is distinguished by a protrusion of each of the third to fifth wiring layers (123, 234, 125) and can be connected to another wiring layer disposed on each wiring layer.

[0087] In addition, since the first to fifth wiring layers (121, 122, 123, 124, 125) are sequentially laminated along the vertical direction on the lower surface of the first protective layer (141), the inclination directions of each of the first to fourth through-electrodes (131, 132, 133, 134) may be the same. For example, each of the first to fourth through-electrodes (131, 132, 133, 134) provided in the build-up structure (100) may have an inclination that becomes wider as it goes toward the second protective layer (142).

[0088] The protective layer (140) may include a first protective layer (141) disposed on the upper surface of the build-up structure (100) and / or a second protective layer (142) disposed on the lower surface of the build-up structure (100). The first protective layer (141) may protect the upper surface of the first wiring layer (121) and / or the first insulating layer (111) from external moisture or contaminants. In addition, when a semiconductor element is disposed on the circuit board (10) using a material such as solder, the first protective layer (141) functions to prevent short circuits between solders due to low wettability with the solder. The first protective layer (141) may use a photocurable insulating material, and for example, a solder resist may be used. However, the embodiment is not limited thereto, and the first protective layer (141) may include a thermocurable insulating material that is the same insulating material as the insulating layer (110). The first protective layer (141) may have the same insulating material as the first insulating layer (111), and may be provided as, for example, ABF (Ajinomoto Build-up Film) from Ajinomoto Corporation.

[0089] The bonding portion (150) penetrates the first protective layer (141) and is electrically connected to the build-up structure (100). For example, the first protective layer (141) may have a through hole (141H) that vertically overlaps the first wiring layer (121), and the bonding portion (150) may be disposed within the through hole of the first protective layer (141) to be electrically connected to the first wiring layer (121). The bonding portion (150) may mean an electrode on which a bonding member such as solder is disposed for bonding with a semiconductor element, and may have a protrusion (152a, see FIG. 2) that protrudes above the first protective layer (141). Recently, as the functions provided by semiconductor elements increase and the performance of semiconductor elements improves, the number of I / O terminals provided in semiconductor elements is also increasing. Accordingly, as the width and / or pitch of the I / O terminals provided in the semiconductor device become smaller, an electrical short circuit may occur in which a plurality of bonding members come into contact with each other in the process of connecting the I / O terminals of the semiconductor device through bonding members such as solder. Therefore, as the density of the terminals of the semiconductor device increases, in order to reduce the amount of bonding members such as solder used, a bonding member may be applied to the upper surface of the protrusion (152a) of the bonding portion (150) protruding above the first protective layer (141), and a micro-bonding process such as thermal compression bonding (hereinafter referred to as 'TC bonding') may be performed. In addition, when the micro-bonding process is performed, the bonding portion (150) may be provided with the protrusion (152a) as described above in order to improve the alignment between the terminal of the semiconductor device and the bonding portion (150).

[0090] The structure of the circuit board (10) described above is only an example for explaining the present invention, and the technical idea of ​​the present invention is not limited to the laminated structure of the present embodiment.

[0091] The circuit board (10) requires uniformity in the height of the bonding portion (150) to stably mount the semiconductor element. Here, the uniformity in height refers to the uniformity in height between the upper surfaces of the second (152) of each of the plurality of bonding portions (150). In addition, the reliability of the connection between the semiconductor element and the circuit board (10) is determined according to the uniformity in the height of the bonding portion (150).

[0092] A conventional circuit board (10) is manufactured by a manufacturing process in which a bonding portion (150) is finally placed after the build-up structure (100) is manufactured. In this case, a difference in the current applied during the plating process may occur due to a process deviation in the plating process of the plurality of bonding portions (150) and / or a difference in the horizontal width and / or area of ​​the bottom surface of each of the plurality of bonding portions (150), which may cause a change in the speed of the plating process. As a result, the heights of the plurality of bonding portions (150) may become uneven. If the heights of the bonding portions (150) are uneven, the semiconductor element may not be stably mounted on the bonding portions (150), and the reliability of the electrical connection between the semiconductor element and the circuit board (10) may deteriorate. For example, if a height deviation of the bonding portions (150) occurs, at least one bonding portion may not be electrically connected to the terminal of the semiconductor element, which may cause an electrical open problem. In addition, when increasing the volume of a bonding member such as solder placed on the bonding portion (150) to solve an electrical open problem, the pressure applied in the process of mounting a semiconductor element may cause horizontal diffusion of the bonding member, which may cause an electrical short-circuit problem in which a plurality of adjacent bonding members are connected to each other.

[0093] To solve this, the embodiment forms the bonding portion (150) before forming the build-up structure (100) in the process of manufacturing the circuit board (10). For example, a carrier member having a metal layer may be prepared, and then the bonding portion (150) may be formed on the metal layer of the carrier member. In addition, after laminating a first protective layer (141) covering the bonding portion (150) on the metal layer of the carrier member, a portion of the first protective layer (141) may be etched with a chemical solution and / or dry process so that the first protective layer (141) has a thickness less than or equal to the thickness of the bonding portion (150), and then a process of laminating the build-up structure (100) may be performed in a state where the bonding portion (150) and the first protective layer (141) are arranged. At this time, the plurality of bonding portions (150) may have one surface that contacts the metal layer of the carrier member and the other surface that contacts the build-up structure (100). In addition, the metal layer of the carrier member can be flat with a uniform thickness, and thus, one surface of the plurality of bonding portions (150) in contact with the metal layer of the carrier member can have a uniform height. Furthermore, one surface of the plurality of bonding portions (150) in contact with the metal layer of the carrier member is used as a bonding surface on which a bonding member for mounting a semiconductor element is arranged, and thereby, the uniformity of the height of the bonding portions (150) can be improved, thereby improving the reliability of the connection between the semiconductor element and the circuit board (10).

[0094] In addition, the bonding portion (150) can be implemented by filling the through-hole of DFR (Dry Film Resist, hereinafter, DFR) disposed on the metal layer of the carrier member with a conductive material, thereby minimizing the width and / or pitch of the bonding portion (150) compared to the conventional method of forming a through-hole in the first protective layer (141) and then filling the through-hole of the first protective layer (141) with a conductive material. Through this, the embodiment can improve the circuit integration by minimizing the width and / or pitch of the bonding portion (150), and can solve the problem of electrical short-circuiting caused by a plurality of bonding members such as solders coming into contact with each other.

[0095] In addition, conventionally, as illustrated in FIG. 1b, after forming a wiring layer (2) on the upper surface of an insulating layer (1), a protective layer (3) is laminated, and a bonding portion (4) is formed on the protective layer (3). At this time, conventionally, in order to refine the width and / or pitch of the bonding portion (4), a through hole is formed in the protective layer (3) by a laser process or an exposure process, and thereby the side surface of the bonding portion (4) has a curved portion (5) adjacent to the wiring layer (2). At this time, when the bonding portion (4) has a curved portion (5), when a semiconductor element is bonded to a circuit board through thermocompression bonding, a crack may occur as a load is applied to the curved portion (5) of the bonding portion (4). In contrast, the embodiment forms the bonding portion (150) using a dry film prior to the build-up structure (100), thereby minimizing the bonding portion (150) and eliminating a curved portion that may be provided in the bonding portion (150). In addition, the circuit board (10) may be subject to stress due to heat cycles such as thermal shrinkage and / or thermal expansion in the manufacturing environment and / or the operating environment, and the embodiment can more stably protect the bonding portion (150) from the above-described stress by removing the curved portion, thereby solving electrical reliability and / or mechanical reliability problems in which the bonding portion (150) is peeled off from the build-up structure (100) or the bonding portion (150) is separated from the terminal of the semiconductor element.

[0096] According to the embodiment illustrated in FIG. 2, the bonding portion (150) may have an upper surface (150T), a lower surface (150B) opposite to the upper surface (150T), and a side surface (150S) between the upper surface (150T) and the lower surface (150B). The lower surface (150B) of the bonding portion (150) may be in contact with the upper surface of the first wiring layer (121). The upper surface (150T) of the bonding portion (150) may be positioned higher than the upper surface of the first protective layer (141). The upper surface (150T) of the bonding portion (150) may be a bonding surface on which a bonding material such as solder is applied for mounting a semiconductor element. The side surface (150S) of the bonding portion (150) may connect the upper surface (150T) and the lower surface (150B) of the bonding portion (150). The bonding portion (150) may include a first portion (151) that overlaps the first protective layer (141) in a horizontal direction, and a second portion (152) that does not overlap the first protective layer (141) in a horizontal direction. The second portion (152) of the bonding portion (150) may include a protrusion (152a) that does not overlap the first protective layer (141) in a horizontal direction and protrudes above the first protective layer (141), and a connecting portion (152b) that is provided between the protrusion (152a) and the first portion (151) and has a side surface that overlaps the first protective layer (141) in a horizontal direction and does not contact the first protective layer (141). The first portion (151) of the bonding portion (150) may refer to a portion having a side surface (151S) that contacts the first protective layer (141) among the entire area of ​​the bonding portion (150), and the second portion (152) may refer to a portion having a side surface (152S) that does not contact the first protective layer (151) among the entire area of ​​the bonding portion (150), and this may include a protrusion (152a) and a connecting portion (152b). Accordingly, the lower surface (150B) of the bonding portion (150) may refer to the lower surface of the first portion (151), and the upper surface (150T) of the bonding portion (150) may refer to the upper surface of the second portion (152).The side surface (150S) of the bonding portion (150) may include a first side surface (151S) of the first portion (151) that overlaps the first protective layer (141) along the horizontal direction, and a second side surface (152S) of the second portion (152) that does not overlap the first protective layer (141) along the horizontal direction. At this time, the second side surface (152S) of the second portion (152) of the bonding portion (150) may be provided on the first side surface (151S) of the first portion (151) of the bonding portion (150) and may have a predetermined inclination with respect to the first side surface (151S) of the first portion (151).

[0097] That is, the first side surface (151S) of the first portion (151) of the bonding portion (150) may be provided to be connected to the lower surface (150B) of the bonding portion (150) and have a first slope toward the upper surface (150T) of the bonding portion (150). The first side surface (151S) of the first portion (151) of the bonding portion (150) may be in contact with the first protective layer (141) while horizontally overlapping the first protective layer (141). That is, the first protective layer (141) may include an inner surface forming a through hole (141H) and an outer surface surrounding the inner surface of the through hole (141H), and the first side surface (151S) of the first portion (151) of the side surface (150S) of the bonding portion (150) may be in contact with the inner surface of the first protective layer (141). The first side surface (151S) of the first portion (151) of the side surface (150S) of the bonding portion (150) may be perpendicular to the lower surface (150B) of the bonding portion (150). That is, the inclination of the first side surface (151S) of the first portion (151) of the bonding portion (150) may be closer to 90° than the inclination of each of the first to fourth through-electrodes (131, 132, 133, 134) provided in the build-up structure (100). Through this, the contact area between the bonding portion (150) and the first wiring layer (121) may be increased while the pitch between the plurality of bonding portions (150) is refined, thereby improving the adhesion. For example, if the inclination of the first side surface (151S) of the first portion (151) of the bonding portion (150) with respect to the lower surface (150B) of the bonding portion (150) is greater than 90°, it may be difficult to refine the pitch between the plurality of bonding portions (150). However, the present invention is not limited thereto, and if the bonding force between the bonding member and the upper surface of the second portion (152) of the bonding portion (150) is secured, the inclination of the first side surface (151S) of the first portion (151) may be provided to be less than 90° in order to provide finer bonding between the semiconductor element and the build-up structure (100).

[0098] The second side surface (152S) of the second portion (152) of the bonding portion (150) has a predetermined incline with respect to the first side surface (151S) of the first portion (151) and may be provided between the upper surface (150T) of the bonding portion (150) and the first side surface (151S) of the first portion (151). That is, the incline of the second side surface (152S) of the second portion (152) may be smaller than the incline of the first side surface (151S) of the first portion (151). For example, the inclination of the first side surface (151S) of the first portion (151) of the side surface (150S) of the bonding portion (150) with respect to the lower surface (150B) of the bonding portion (150) may be greater than and 90° or less than the inclination of the second side surface (152S) of the second portion (152) of the bonding portion (150) with respect to the lower surface (150B) of the bonding portion (150). The second side surface (152S) of the second portion (152) of the bonding portion (150) may have an inclination such that the horizontal width of the bonding portion (150) increases along the direction from the upper surface (150T) of the bonding portion (150) toward the lower surface (150B) of the bonding portion (150). Accordingly, the side surface (150S) of the bonding portion (150) has a first side surface (151S) of a first portion (151) having little change in width along the direction from the lower surface (150B) to the upper surface (150T), and a second side surface (152S) of a second portion (152) that is inclined so that the width narrows along the direction from the lower surface (150B) to the upper surface (150T). The second portion (152) of the bonding portion (150) is a portion where a bonding member such as solder is applied, and by having the second side surface (152S) of the second portion (152) of the bonding portion (150) having the above-described inclination, the horizontal distance between the plurality of bonding portions (150) can be increased while maintaining the pitch between the plurality of bonding portions (150). That is, the embodiment can increase the separation distance between the second parts (152) of the plurality of bonding parts (150) by utilizing the inclination of the second side (152S) of the second part (152) of the bonding part (150).Through this, the embodiment can further prevent an electrical short circuit problem caused by two adjacent bonding members being connected to each other, and can improve the mechanical reliability and / or electrical reliability of the circuit board and the semiconductor package accordingly. Furthermore, the embodiment can improve the flowability of the bonding member by allowing the bonding member to flow along the incline of the second side surface (152S) of the second portion (152) of the bonding portion (150). In addition, the direction in which the incline of the second side surface (152S) of the second portion (152) of the bonding portion (150) is inclined can be the same as the direction in which the incline of the through electrode (130) provided in the build-up structure (100) is inclined. That is, the direction in which the inclination of the second side surface (152S) of the second portion (152) of the bonding portion (150) is inclined may be the same as the direction in which the inclinations of each of the first to fourth through-electrodes (131, 132, 133, 134) are inclined. Through this, the embodiment can easily control the stress acting on the circuit board (10) by allowing the second side surface (152S) of the second portion (152) of the bonding portion (150) and each of the first to fourth through-electrodes (131, 132, 133, 134) to be inclined in the same direction, and further, the design of the thickness, wiring density, and width of the wiring layer (121) and the through-electrode (130) to prevent the circuit board (10) from being bent in a specific direction can be easily performed.

[0099] At this time, the second part (152) of the bonding portion (150) may have the same slope as described above in the process of etching away a portion of the first protective layer (141) after removing the carrier member and the metal layer in the manufacturing process of the circuit board (10) described above. That is, as the manufacturing process of the circuit board (10) is completed, a process of removing a portion of the first protective layer (141) may be performed so that the thickness (T2) of the first protective layer (141) is smaller than the thickness (T1) of the bonding portion (150), and in this process, a portion of the bonding portion (150) may also be etched together, and accordingly, the bonding portion (150) may include a first part (151) having a first side surface (151S) and a second part (152) having a second side surface (152S) having a predetermined slope with respect to the first side surface (151S).

[0100] In addition, the thickness (T1) of the bonding portion (150) is greater than the thickness (T2) of the first protective layer (141), and accordingly, the bonding portion (150) is provided to protrude above the first protective layer (141). For example, the bonding portion (150) may include a second portion (152), and the second portion (152) may include a protrusion (152a) protruding above the first protective layer (141). At this time, the vertical length (T11) of the first side surface (151S) of the first portion (151) of the bonding portion (150) may be different from the vertical length (T12) of the second side surface (152S) of the second portion (152) of the side surface (150S) of the bonding portion (150). Preferably, the vertical length (T11) of the first side (151S) of the first portion (151) is greater than the vertical length (T12) of the second side (152S) of the second portion (152). In this case, the fact that the vertical length (T11) of the first side (151S) of the first portion (151) is greater than the vertical length (T12) of the second side (152S) of the second portion (152) may mean that the thickness of the area buried in the first protective layer (141) among the entire area of ​​the bonding portion (150) is greater than the thickness of the area protruding above the first protective layer (141). Through this, the embodiment can enable the bonding portion (150) to be stably protected by the first protective layer (141), and improve the adhesion between the bonding portion (150) and the first protective layer (141) and / or the first wiring layer (121). For example, if the vertical length (T11) of the first side (151S) of the first portion (151) is smaller than the vertical length (T12) of the second side (152S) of the second portion (152), stress may be applied to the bonding portion (150) in the process of removing a portion of the first protective layer (141) through a chemical solution and / or dry etching, which may cause the bonding portion (150) to be peeled off from the first wiring layer (121) and / or the first protective layer (141).Accordingly, the embodiment can improve the reliability problem of the bonding portion (150) being peeled off from the first protective layer (141) and / or the first wiring layer (121) by making the vertical length (T11) of the first side (151S) of the first part (151) of the bonding portion (150) greater than the vertical length (T12) of the second side (152S) of the second part (152).

[0101] Furthermore, the vertical length (T11) of the first side (151S) of the first portion (151) may satisfy a range of 1.2 to 3 times the vertical length (T12) of the second side (152S) of the second portion (152). If the vertical length (T11) of the first side (151S) of the first portion (151) is less than 1.2 times the vertical length (T12) of the second side (152S) of the second portion (152), the bonding portion (150) may not be sufficiently protected by the first protective layer (141), and thus the bonding portion (150) may be peeled off from the first protective layer (141) and / or the first wiring layer (121) in the manufacturing process and / or operating environment of the circuit board (10). In addition, if the vertical length (T11) of the first side (151S) of the first portion (151) exceeds three times the vertical length (T12) of the second side (152S) of the second portion (152), the vertical length (T11) of the first side (151S) of the first portion (151) may be excessively large compared to the vertical length (T12) of the second side (152S) of the second portion (152), which may act as a factor in increasing the thickness (T1) of the bonding portion (150), and if the aspect ratio of the bonding portion (150) is not appropriately secured, cracks may occur due to load in the process of bonding the semiconductor element to the bonding portion (150), and it may be difficult to thin the circuit board (10) and / or the semiconductor package.

[0102] In addition, the vertical length (T11) of the first side surface (151S) of the first portion (151) of the bonding portion (150) may be smaller than the thickness (T2) of the first protective layer (141). That is, the uppermost portion of the first side surface (151S) of the first portion (151) of the bonding portion (150) may be positioned lower than the upper surface of the first protective layer (141). This may mean that the lowermost portion of the second side surface (152S) of the second portion (152) of the bonding portion (150) is positioned lower than the upper surface of the first protective layer (141). That is, at least a part of the second side surface (152S) of the second portion (152) of the bonding portion (150) may overlap the first protective layer (141) in the horizontal direction and be spaced apart from the inner surface of the through hole (141H) of the first protective layer (141). For example, a separation space (SS) may be provided between the second side surface (152S) of the second portion (152) of the bonding portion (150) and the inner surface of the first protective layer (141). The separation space (SS) may function as a dam that blocks the flow of the bonding member applied on the bonding portion (150). That is, when the bonding member applied on the bonding portion (150) spreads in the horizontal direction, the separation space (SS) may prevent the bonding member from spreading to a location where another adjacent bonding portion is arranged, thereby further improving the electrical reliability of the circuit board and / or semiconductor package.

[0103] At this time, the difference (TΔ) between the vertical thickness (T2) of the first protective layer (141) and the vertical length (T11) of the first side (151S) of the first part (151) of the bonding portion (150) may be smaller than the vertical length (T11) of the first side (151S) of the first part (151). If the difference (TΔ) between the vertical thickness (T2) of the first protective layer (141) and the vertical length (T11) of the first side (151S) of the first part (151) of the bonding portion (150) is greater than the vertical length (T11) of the first side (151S) of the first part (151), the bonding portion (150) may be excessively removed in the process of removing a portion of the first protective layer (141), and thus the horizontal width of the upper surface (150T) of the bonding portion (150) may become excessively narrow. can be. In addition, the difference (TΔ) between the vertical thickness (T2) of the first protective layer (141) and the vertical length (T11) of the first side (151S) of the first part (151) of the bonding portion (150) may be smaller than the vertical length (T12) of the second side (152S) of the second part (152). When the difference (TΔ) between the vertical thickness (T2) of the first protective layer (141) and the vertical length (T11) of the first side (151S) of the first part (151) of the bonding portion (150) is larger than the vertical length (T12) of the second side (152S) of the second part (152), a problem may occur in which the bonding portion (150) does not protrude above the first protective layer (141), and thus, a semiconductor device may not be stably mounted on the bonding portion (150).

[0104]

[0105] According to the embodiment of FIG. 3a, the upper surface of the first protective layer (141) may be provided with unevenness. That is, the first protective layer (141) of one embodiment may be provided with an insulating material different from the insulating material of the first insulating layer (111), and may be provided with, for example, a solder resist. The first protective layer (141) of another embodiment may be provided with the same insulating material as the first insulating layer (111), and may be provided with, for example, ABF or PID.

[0106] At this time, the first protective layer (141) may be provided with a plurality of fillers (141F). In addition, the upper surface of the first protective layer (141) may be provided with unevenness corresponding to the plurality of fillers (141F). For example, the upper surface of the first protective layer (141) may be provided with a convex portion (141T1). The convex portion (141T1) may correspond to the filler (141F) provided in the first protective layer (141). In addition, the upper surface of the first protective layer (141) may be provided with a concave portion (141T2). In addition, the upper surface of the first protective layer (141) may be provided with a concave portion (141T2) corresponding to the filler (141F) provided in the first protective layer (141). For example, the concave portion (141T2) may be formed by removing at least one filler provided in the first protective layer (141) by etching a portion of the upper surface of the first protective layer (141). That is, the upper surface of the first protective layer (141) may have at least one of a convex portion (141T1) and a concave portion (141T2). In addition, the convex portion (141T1) and the concave portion (141T2) provided on the upper surface of the first protective layer (141) may have a function of increasing a contact area with a molding member that molds a semiconductor element on the first protective layer (141), thereby improving adhesion between the first protective layer (141) and the molding member.

[0107] In addition, the convex portion (141T1) and the concave portion (141T2) provided on the upper surface of the first protective layer (141) can increase the surface area of ​​the upper surface of the first protective layer (141). Through this, the embodiment can prevent cracks from occurring in the bonding portion (150) due to stress caused by a heat cycle. For example, the circuit board may experience stress according to a heat cycle due to thermal expansion and / or thermal contraction in the manufacturing process and / or operating environment, and the stress may be transmitted to the bonding portion (150). In addition, if stress is continuously applied to the bonding portion (150), cracks may occur in the bonding portion (150), which may cause mechanical reliability and / or electrical reliability problems. Furthermore, if the above-described stress acts on a bonding member such as a solder, cracks may occur in the bonding member, which may cause an electrical open problem between the semiconductor element and the bonding portion (150). At this time, the concave portion (141T2) and the convex portion (141T1) provided on the upper surface of the first protective layer (141) function to increase the surface area, thereby increasing the transmission distance of the stress acting along the upper surface of the first protective layer (141), thereby minimizing the magnitude of the stress transmitted to the bonding portion (150). Through this, the embodiment can minimize the stress transmitted to the bonding portion (150), thereby enabling the semiconductor element to be stably attached to the circuit board, and thereby improving the mechanical reliability and electrical reliability between the circuit board and the semiconductor element. Furthermore, the embodiment can enable the semiconductor element to operate stably, thereby improving the operational reliability of electronic products such as servers to which the semiconductor package is applied.

[0108] In addition, at least one filler (141F1) may be exposed on the upper surface of the first protective layer (141). At this time, the exposed filler (141F1) may have a function of preventing horizontal stress from being transmitted to the bonding portion (150), thereby further improving the electrical reliability and / or mechanical reliability of the bonding portion (150). However, the embodiment is not limited thereto, and the exposed filler (141F1) may be removed through an additional etching process, thereby providing a concave portion (141T2).

[0109] In addition, at least one filler may be exposed on the lower surface of the first protective layer (141). That is, as the manufacturing process of the circuit board (10) described above is performed, in addition to the process of removing the upper surface of the first protective layer (141) by etching, the embodiment may perform a process of removing the lower surface of the first protective layer (141) by etching. After performing the process of removing the lower surface of the first protective layer (141) by etching, a grinding process may be additionally performed, through which the lower surface of the first protective layer (141) and the lower surface (150B) of the bonding portion (150) may be positioned on the same plane. At this time, in the process of removing the lower surface of the grinding first protective layer (141) by etching, at least one filler may be exposed to the lower surface of the first protective layer (141), and the filler exposed to the lower surface of the first protective layer (141) may be removed so as to be positioned on the same plane as the lower surface of the bonding portion (150) in the grinding process. At this time, the filler exposed to the lower surface of the first protective layer (141) may remain without being completely removed. Accordingly, at least a portion of the upper surface of the first insulating layer (111) may be in contact with the filler (141F2) exposed to the lower surface of the first protective layer (141). In addition, at least a portion of the upper surface of the first wiring layer (121) may be in contact with the filler (141F3) exposed to the lower surface of the first protective layer (141).

[0110] In the embodiment, as the process of laminating the first protective layer (141) is performed after forming the bonding portion (150), the bonding portion (150) may not come into contact with the filler (141F) provided in the first protective layer (141), but this is not necessarily limited thereto.

[0111] In addition, according to the embodiment of FIG. 3b, unlike the embodiment of FIG. 3a, the grinding process performed after the lower surface of the first protective layer (141) is removed by etching can be omitted. In this case, the lower surface of the first protective layer (141) may be provided with unevenness. And the unevenness provided on the lower surface of the first protective layer (141) may be in contact with the first insulating layer (111) or may be in contact with the first wiring layer (121). In this case, the contact area between the first insulating layer (111) and the first protective layer (141) and / or the contact area between the first protective layer (141) and the first wiring layer (121) can be increased, and thus the bonding strength therebetween can be further improved.

[0112] According to the embodiment of FIG. 4a, the circuit board may further include a barrier layer (160) provided between the bonding portion (150) and the first wiring layer (121). The barrier layer (160) may be disposed on the first barrier layer (160) and may overlap with the first protective layer (141) in the horizontal direction. The bonding portion (150) and the barrier layer (160) may be provided by filling an opening of the dry film. For example, the embodiment may form the bonding portion (150) by filling a portion of the opening of the dry film, and then form the barrier layer (160) by filling the remaining portion of the opening of the dry film. In this case, the horizontal width of the barrier layer (160) may correspond to the horizontal width of the lower surface of the bonding portion (150). The barrier layer (160) can have a barrier function to prevent the bonding material, such as solder, from penetrating into the first wiring layer (121) during the process of applying the bonding material on the bonding portion (150). For example, when a bonding material, such as solder, is placed on the bonding portion (150), the bonding material and the first wiring layer (121) may come into contact with each other due to solder diffusion, thereby forming an intermetallic compound, which may result in deterioration of electrical properties or occurrence of cracks due to brittleness of the intermetallic compound. The barrier layer (160) can prevent the diffusion of the bonding material, such as solder, and thus prevent the bonding material and the first wiring layer (121) from coming into contact with each other due to solder diffusion.

[0113] In addition, cracks may occur at the bottom of the bonding portion (150) in contact with the first wiring layer (121) due to the load generated when bonding the semiconductor element and the circuit board (100) using a micro-bonding method such as thermal compression bonding between the circuit board (100) and the semiconductor element. Therefore, cracks can be prevented by placing a material having a higher elastic modulus than that of the first wiring layer (121) and / or the bonding portion (150) between the bonding portion (150) and the first wiring layer (121). This material may be nickel (Ni), but may also be provided as a copper layer having a low grain density through electroless plating. Furthermore, the barrier layer (160) can solve the problem of cracks that occur when stress due to expansion and / or contraction of the first protective layer (141) by a heat cycle is provided to the joint area between the bonding portion (150) and the first wiring layer (121).

[0114] In addition, according to the embodiment of FIG. 4b, a barrier layer (170) having a width wider than the width of the bonding portion (150) may be disposed between the bonding portion (150) and the first wiring layer (121). At this time, the barrier layer (170) may be disposed on the lower surface of the first protective layer (141) and the lower surface of the bonding portion (150). The barrier layer (170) may be disposed between the bonding portion (150) and the first wiring layer (121) while having a width greater than the width of the lower surface of the bonding portion (150). When the horizontal width of the barrier layer (170) is greater than the horizontal width of the bonding portion (150), the penetration of a bonding material such as solder can be more effectively prevented, and thus the electrical characteristics of the circuit board can be further improved. At this time, in Fig. 4b, the horizontal width of the barrier layer (170) is illustrated as being the same as the horizontal width of the first wiring layer (121), but this is not limited thereto. For example, the horizontal width of the barrier layer (170) may be larger than the horizontal width of the lower surface of the bonding portion (150), and may be larger or smaller than the horizontal width of the first wiring layer (121).

[0115] In addition, the circuit board according to the embodiment of FIG. 5 includes a build-up structure (200) having a first wiring layer (210), a first protective layer (220), and a bonding portion (230). The build-up structure (200) having a first wiring layer (210), the first protective layer (220), and the bonding portion (230) have substantially the same functions as the components having the same names illustrated in FIGS. 1 to 4, and a redundant description thereof will be omitted.

[0116] In addition, the circuit board may have a connecting member (240) embedded within the build-up structure (200). Recently, as the number of signals that semiconductor devices must process increases, the size of semiconductor devices is trending toward larger areas, but this larger area of ​​semiconductor devices is causing problems in lowering the yield of semiconductor devices. Therefore, there is a trend to divide the pattern size or functional part of the semiconductor device, place chiplets on the circuit board, and embed connecting members (240) that have the function of electrically connecting them within the circuit board. However, the connecting members (240) are not limited thereto, and may connect semiconductor devices with other functions, such as memory.

[0117] The connecting member (240) may be disposed within the insulating layer adjacent to the bonding portion (220) in the build-up structure (200). In this case, the signal transmission distance between the plurality of semiconductor elements (260, 270) and the connecting member (240) can be reduced, which is advantageous in preventing signal loss. That is, the connecting member (240) electrically connects between the plurality of semiconductor elements disposed on the circuit board, and thus, reducing the signal transmission distance while being adjacent to the plurality of semiconductor elements can be advantageous in reducing signal transmission loss.

[0118] In addition, the first wiring layer (210) has wiring electrodes that overlap vertically with the connecting member (240). In addition, a first connecting member (250) is arranged on the lower surface of the wiring electrodes that overlap vertically with the connecting member (240). The first connecting member (250) may be solder, but is not limited thereto. The connecting member (240) has a pad portion (245), and the pad portion (245) of the connecting member (240) is electrically connected to the wiring electrodes of the first wiring layer (210) through the first connecting member (250).

[0119] Additionally, a second bonding member (280) may be placed on the bonding portion (220), and a plurality of semiconductor elements (260, 270) may be mounted through the second bonding member (280). Each of the plurality of semiconductor elements (260, 270) may have a terminal (265, 275) and may be electrically connected to the bonding portion (220) through the second bonding member (280).

[0120] Additionally, according to the embodiment of FIG. 6, the circuit board described above can be used as an interposer provided between the semiconductor package substrate and the semiconductor element of the semiconductor package.

[0121] That is, as the terminal density of semiconductor devices increases, the wiring becomes more complex, and accordingly, the thickness of the circuit board increases. However, as the thickness increases, the yield of the circuit board may decrease. Therefore, the circuit board may be divided into an interposer and a semiconductor package substrate (300) and used, and the above-described circuit board may be used not only as a semiconductor package substrate (300) but also as an interposer.

[0122] Semiconductor elements (260, 270) are arranged on the interposer. The semiconductor elements (260, 270) may be provided in multiple numbers on the interposer while being spaced apart from each other in the horizontal direction, but the present invention is not limited thereto. For example, the semiconductor elements (260, 270) may be arranged to be stacked not only horizontally but also vertically on the interposer. A connecting member (240) for electrically connecting the semiconductor elements (260, 270) is arranged on the interposer.

[0123] The connecting member (240) may have a function of electrically connecting between terminals (631, 641) of semiconductor elements (260, 270) disposed on the interposer. In this case, the connecting member (240) may be a bridge die. For example, the connecting member (240) partially overlaps the semiconductor elements (260, 270) disposed on the interposer in a vertical direction. In addition, the connecting member (240) electrically connects a part of the terminal (265) of the first semiconductor element (260) and a part of the terminal (275) of the second semiconductor element (270). The connecting member (240) may be formed of the same material as the semiconductor element, such as silicon, or may be formed of an organic material, such as a photosensitive resin or a thermosetting resin. A plurality of semiconductor devices having different functions, such as a CPU and GPU, a GPU and HBM, or a chiplet unit separated according to function and / or pitch, may be mounted on a circuit board, and a connecting member (240) may function to horizontally electrically connect them.

[0124] The connecting member (240) may be an organic bridge that can smoothly supply power from the bottom to the top while minimizing the loss of the supplied power. In this case, in the case of an inorganic bridge including a silicon substrate, power can be supplied through a TSV (Through Silicon Via), but there is a problem that the process cost for TSV processing increases and the product yield decreases. Therefore, the connecting member (240) of the embodiment is preferably an organic bridge.

[0125] A semiconductor package substrate (300) is placed on the lower surface of the interposer. The semiconductor package substrate (300) can electrically connect the main board of an electronic device and the interposer.

[0126] At this time, a third bonding member (310) may be placed between the interposer and the semiconductor package substrate (300), through which the interposer and the semiconductor package substrate (300) may be electrically bonded.

[0127]

[0128] Hereinafter, a method for manufacturing the circuit board illustrated in Fig. 1 will be described. Figs. 7 to 17 are cross-sectional views showing the manufacturing method of the circuit board illustrated in Fig. 1 in process order.

[0129] Referring to FIG. 7, an embodiment may prepare a carrier member (400), which is a basic material for manufacturing a circuit board (10). The carrier member (400) may include an insulating member (410) and a metal member (420) disposed on at least one surface of the insulating member (410). At this time, the drawing illustrates that the metal member (420) is disposed only on one surface of the insulating member (410), but the present invention is not limited thereto. For example, the metal member (420) may be disposed on both surfaces of the insulating member (410), and thus, the manufacturing process of the circuit board to be described later may be performed simultaneously on both sides of the insulating member (410). At this time, the metal member (420) may be used as a seed layer for electroplating the bonding portion (150) of the embodiment. In one embodiment, the metal member (420) may include the same metal material as the metal material of the bonding portion (150). In another embodiment, the metal member (420) may include a metal material different from the metal material of the bonding portion (150). In this case, in the process of finally removing the metal member (420) by etching, only the metal member (420) can be selectively removed without damaging the bonding portion (150). Thereafter, the embodiment may perform a process of laminating a dry film (430) on the lower surface of the metal member (420). At this time, the dry film (430) may have at least one opening (430H). The opening (430H) may be provided to correspond to an area on the lower surface of the metal member (420) where the bonding portion (150) is to be placed.

[0130] Next, referring to FIG. 8, the embodiment may proceed with a process of forming a bonding portion (150) that fills the opening (430H) of the dry film (430) by electrolytic plating a metal member (420) as a seed layer.

[0131] Next, referring to FIG. 9, the embodiment may proceed with a process of peeling off the dry film (430). Thereafter, the embodiment may proceed with a process of laminating a first protective layer (141) covering the bonding portion (150) on the lower surface of the metal member (420). At this time, the first protective layer (141) may be laminated to entirely cover the side and lower surface of the bonding portion (150).

[0132] Next, referring to FIG. 10, the embodiment may perform a process of etching and removing a portion of the lower surface of the first protective layer (141). For example, the embodiment may remove a portion of the first protective layer (141) so that the lower surface of the first protective layer (141) has a height equal to or higher than the lower surface of the bonding portion (150). Accordingly, the lower surface of the bonding portion (150) may be exposed. At this time, in one embodiment, after performing the process of removing a portion of the first protective layer (141) by etching, a grinding process may be performed so that the lower surface of the first protective layer (141) and the lower surface of the bonding portion (150) are positioned on the same plane. However, the embodiment is not limited thereto, and the grinding process may be omitted. And when the grinding process is performed, the lower surface of the first protective layer (141) may have the structure of FIG. 3, and when the grinding process is omitted, the lower surface of the first protective layer (141) may have the structure of FIG. 4.

[0133] Next, referring to FIG. 11, the embodiment may perform a process of forming a first wiring layer (121) connected to a bonding portion (150) by electrolytic plating a metal member (420) as a seed layer.

[0134] Next, referring to FIG. 12, the embodiment may proceed with a process of laminating a first insulating layer (111) covering a first wiring layer (121) on the lower surface of a first protective layer (141).

[0135] Next, referring to FIG. 13, the embodiment can proceed with a process of laminating a first through-electrode (131) penetrating a first insulating layer (111) and a second wiring layer (122) connected to the first through-electrode (131).

[0136] Next, referring to FIG. 14, the embodiment can proceed with a process of forming a build-up structure (100) including a second insulating layer (112), a third insulating layer (113), a fourth insulating layer (114), a third wiring layer (123), a fourth wiring layer (124), a fifth wiring layer (125), a second through-hole electrode (132), a third through-hole electrode (133), a fourth through-hole electrode (134), and a second protective layer (142) by repeatedly performing the processes of FIGS. 12 and 13.

[0137] Next, referring to FIG. 15, the embodiment can proceed with a process of removing the insulating member (410) of the carrier member (400).

[0138] Next, referring to FIG. 16, the embodiment can proceed with a process of removing a metal member (420) by etching.

[0139] Next, referring to FIG. 17, the embodiment may perform a process of etching and removing a portion of the upper surface of the first protective layer (141) so that the upper surface of the first protective layer (141) is positioned lower than the upper surface of the bonding portion (150). At this time, in the process of etching a portion of the upper surface of the first protective layer (141), a portion of the bonding portion (150) may also be etched and removed together, and through this, the bonding portion (150) includes a first portion (151) and a second portion (152), and the inclination of the first side surface (151S) of the first portion (151) and the inclination of the second side surface (152S) of the second portion (152) may be different from each other.

[0140]

[0141] Meanwhile, when a circuit board having the characteristics of the invention described above is used in IT devices such as smartphones, server computers, TVs, or home appliances, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the characteristics of the invention performs a semiconductor package function, it can safely protect semiconductor chips from external moisture or contaminants, and can solve problems such as leakage current or electrical shorts between terminals, or electrical open circuits in terminals supplying semiconductor chips. Furthermore, when it performs a signal transmission function, it can solve noise problems. Through this, the circuit board having the characteristics of the invention described above can maintain the stable function of IT devices or home appliances, thereby enabling the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability with each other.

[0142] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of the terminal supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0143] The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by a person skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be interpreted as being included within the scope of the embodiments.

[0144] Although the above has been described focusing on embodiments, these are merely examples and are not intended to limit the embodiments. Those skilled in the art to which the embodiments pertain will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the embodiments. For example, each component specifically shown in the embodiments can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

1. Build-up structure including insulation layer and wiring layer; a protective layer disposed on the above build-up structure; and A bonding portion electrically connected to the build-up structure by penetrating the protective layer, A circuit board, wherein the side surface of the bonding portion does not overlap with the protective layer along the horizontal direction and includes a portion having a small inclination angle with respect to the upper surface of the protective layer.

2. In paragraph 1, The side surface of the bonding portion includes a first side surface that overlaps the protective layer in a horizontal direction, and a second side surface that is disposed on the first side surface and corresponds to a portion where the inclination angle decreases. The second side has a predetermined slope with respect to the first side, A circuit board, wherein the vertical length of the first side is greater than the vertical length of the second side.

3. In paragraph 2, A circuit board, wherein the vertical length of the first side is smaller than the vertical thickness of the protective layer.

4. In paragraph 3, The side of the above protective layer includes an inner side forming a through hole and an outer side surrounding the inner side, A circuit board wherein the second side does not contact the inner side of the protective layer.

5. In paragraph 3, A circuit board, wherein the difference between the vertical thickness of the protective layer and the vertical length of the first side is smaller than the vertical length of the first side.

6. In paragraph 3, A circuit board, wherein the difference between the vertical thickness of the protective layer and the vertical length of the first side is smaller than the vertical length of the second side.

7. In paragraph 3, A circuit board, wherein the upper surface of the protective layer has at least one of a convex portion and a concave portion.

8. In paragraph 7, The above protective layer comprises a plurality of fillers, A circuit board, wherein each of the plurality of fillers does not contact the bonding portion.

9. In paragraph 8, A circuit board, wherein at least one of the plurality of fillers is exposed to the upper surface of the protective layer.

10. In paragraph 1, Further comprising a connecting member embedded within the above build-up structure, The circuit board, wherein the above connecting member overlaps the side surface of the above bonding portion along the vertical direction.

Images