Analog-to-digital converter and terminal device

Abstract

An analog-to-digital converter and a terminal device. The analog-to-digital converter comprises: a data weighted average control circuit, a digital-to-analog converter (DAC), a weight acquisition unit, a multiplier, and an accumulator. A decoded signal is inputted to an input end of the data weighted average control circuit, and an output end of the data weighted average control circuit is coupled to the DAC and is suitable for outputting a control signal. The decoded signal is associated with a target analog signal inputted to the analog-to-digital converter, and bits in the control signal are in a one-to-one correspondence with DAC cells in the DAC. The weight acquisition unit stores weights that are in a one-to-one correspondence with the DAC cells. The multiplier is suitable for multiplying the control signal by the weights to obtain digital quantized output correction values that are in a one-to-one correspondence with the DAC cells. The accumulator is suitable for accumulating the digital quantized output correction values corresponding to all of the DAC cells to obtain a target digital signal corresponding to the target analog signal.

Description

Analog-to-digital converters and terminal equipment

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on September 15, 2023, with application number 202311196938.0 and invention name “Analog-to-digital converter and terminal device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of communication technology, and in particular to an analog-to-digital converter and a terminal device. Background Art

[0003] A sigma delta analog-to-digital converter (SD-ADC) uses sigma delta tuning technology and oversampling to achieve a higher Signal-to-Noise Ratio (SNR) using fewer bits. SD-ADCs come in two types: 1-bit and multi-bit.

[0004] Summary of the Invention

[0005] One of the objectives of the present disclosure is to provide a multi-bit SD-ADC having high SNR and accuracy.

[0006] The present disclosure provides an analog-to-digital converter, comprising: a data weighted averaging control circuit, a digital-to-analog converter, a weight acquisition unit, a multiplier, and an accumulator, wherein: the data weighted averaging control circuit has an input terminal inputting a decoding signal, and an output terminal coupled to the digital-to-analog converter, and is suitable for outputting a control signal; the decoding signal is associated with a target analog signal input to the analog-to-digital converter, and bits in the control signal correspond one-to-one to DAC units in the digital-to-analog converter DAC; the weight acquisition unit stores weights corresponding one-to-one to the DAC units; the multiplier is suitable for multiplying the control signal by the weight to obtain a digital quantization output correction value corresponding one-to-one to the DAC unit; and the accumulator is suitable for accumulating the digital quantization output correction values ​​corresponding to all DAC units to obtain a target digital signal corresponding to the target analog signal.

[0007] By presetting weights corresponding to each DAC unit in the DAC, the control signals output by the DWA control circuit are weighted and summed to obtain the target digital signal. The weights corresponding to each DAC unit in the DAC can be determined through pre-testing and can be matched to the analog-to-digital converter, minimizing mismatches between DAC units, thereby improving the signal-to-noise ratio and accuracy of the analog-to-digital converter.

[0008] Optionally, the average value of the weights corresponding one-to-one to the DAC units is 1, and the weights corresponding to some DAC units are not equal.

[0009] Optionally, the weights corresponding to the DAC units are determined in the following manner: a weighted equation corresponding to the i-th DAC unit is obtained, where the i-th weighted equation is: Based on 2 N -1 DAC unit corresponding to the weighted equation, determine the weight x corresponding to the i-th DAC unit i ; Among them, N x is the number of times the i-th DAC unit is selected by the DWA control circuit within Ns sampling periods, N i is the number of times other DAC units are selected by the DWA control circuit within Ns sampling periods; 1≤i≤2 N -1; N is the number of bits of the analog-to-digital converter.

[0010] When the weight acquisition unit acquires the weights corresponding to different DAC units, it acquires 2 N When obtaining the weighted equation corresponding to the i-th DAC unit, the number of times the DWA control circuit selects the i-th DAC unit is not equal to the number of times other DAC units are selected within Ns sampling periods, so the weight corresponding to each DAC unit can be accurately obtained.

[0011] Optional, N x Equal to Ns; or, N x Not equal to Ns, and N x With N i Not waiting.

[0012] Optionally, the analog-to-digital converter also includes: an adder, suitable for performing a subtraction operation on the target analog signal and the feedback signal, and outputting the obtained difference signal; the feedback signal is the output signal of the DAC, and the output signal of the DAC is the sum of the output signals of all DAC units; the output signal of the DAC unit is obtained based on the control signal.

[0013] Optionally, the analog-to-digital converter further includes: a filter, adapted to perform filtering processing on the difference signal to filter out high-frequency components in the difference signal.

[0014] Optionally, the analog-to-digital converter further includes: a quantizer adapted to perform a quantization operation on the difference signal after filtering to obtain a quantized signal with a length of N bits; the number of bits of the quantizer is N.

[0015] Optionally, the analog-to-digital converter further comprises: a decoder adapted to decode the quantized signal into the decoded signal; the bit length of the decoded signal is 2 N -1.

[0016] Optionally, the analog-to-digital converter includes a sigma delta analog-to-digital converter.

[0017] The present disclosure also provides a terminal device, comprising any one of the above-mentioned analog-to-digital converters. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] FIG1 is a schematic structural diagram of an existing sigma delta analog-to-digital converter;

[0019] FIG2 is an application scenario diagram of an existing classic DWA algorithm;

[0020] FIG3 is a schematic diagram of a DAC unit selected by an existing DWA algorithm at different sampling periods;

[0021] FIG4 is a schematic structural diagram of an analog-to-digital converter according to an embodiment of the present disclosure;

[0022] FIG5 is a schematic diagram of a DAC unit selected within Ns sampling periods in an embodiment of the present disclosure;

[0023] FIG6 is a schematic diagram of another DAC unit selected within Ns sampling periods in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] Compared to 1-bit SD-ADCs, multi-bit SD-ADCs offer lower quantization noise, better stability, lower power consumption, and are less sensitive to clock jitter. However, they suffer from poorer linearity. This poor linearity is due to mismatches between the multiple digital-to-analog converter (DAC) units.

[0025] To improve the linearity of multi-bit SD-ADCs, existing technologies often employ dynamic element matching (DEM) algorithms. This dynamic element matching eliminates mismatches between DAC units over a sufficiently long period of time. A commonly used DEM algorithm is the data weighted average (DWA) algorithm, which uses weighted averaging over a sufficiently long period of time to ensure that each DAC unit has an equal probability of occurring, thereby avoiding mismatches between DAC units.

[0026] Referring to Figure 1 , a schematic diagram of the structure of a conventional sigma delta analog-to-digital converter (SD-ADC) is provided. In Figure 1 , the SD-ADC includes an adder 101, a low-pass loop filter 102, an N-bit quantizer 103, a decoder 104, a data weighted average (DWA) control circuit 105, and a digital-to-analog converter (DAC) 106.

[0027] The SD-ADC receives an analog signal, Vin, which is then fed into the first input (the "+" terminal) of adder 101. The analog signal, Vfb, fed back from the digital-to-analog converter, is fed into the second input (the "-" terminal) of adder 101. Adder 101 performs a subtraction operation to generate the difference between Vin and Vfb, Vdff. The Vdff signal is filtered through a low-pass loop filter 102 to remove high-frequency signals, resulting in a Vfltr signal containing only low-frequency components. The Vfltr signal is then quantized by an N-bit quantizer 103 to generate an N-bit digital signal, Dout[N-1:0].

[0028] The N-bit quantizer 103 is essentially a low-precision ADC. Taking N=4 as an example, the 4-bit quantizer 103 can provide a signal-to-noise ratio (SNR) of 25 dB. In the entire loop, an SNR of more than 100 dB can be obtained within a certain bandwidth.

[0029] To improve linearity, an average-weighted DAC cell is used. DAC106 may include 2 N -1 DAC cell. For example, if N=4, the number of DAC cells is 15. The length of the decoder 104 is 2 N -1, the output length is 2 N -1 bit thermometer code, corresponding to 2 N -1 DAC cell. N The outputs of the -1 DAC cells are added together to obtain the feedback voltage signal Vfb.

[0030] In some SD-ADCs, the 2 N -1 bit can directly control 2 N However, since the occurrence probability of each DAC cell is different, there will be mismatch between the DAC cells, which will cause the total harmonic distortion (THD) performance of the SD-ADC to deteriorate significantly.

[0031] To further improve linearity and reduce harmonics, some SD-ADCs include a DWA control circuit 105 that controls the selection of DAC units using a barrel shift mechanism. Figure 2 shows an application scenario for a classic existing DWA algorithm.

[0032] In Figure 2, taking a 4-bit quantizer as an example, the DAC includes 15 DAC units connected end-to-end to form a barrel. Depending on the output data of the 4-bit quantizer, the corresponding number of DAC units is selected during each sampling period T. In a clockwise direction, from the first sampling period T to the fifth sampling period 5T, the output sequence of the 4-bit quantizer is 4, 4, 5, 4, 4.

[0033] Figure 3 shows a schematic diagram of the DAC units selected by an existing DWA algorithm at different sampling periods. In Figure 3, the horizontal direction represents 15 DAC units, while the vertical direction represents different sampling periods. In the first sampling period, DAC units 1 through 4 are selected; in the second sampling period, DAC units 5 through 8 are selected; in the third sampling period, DAC units 9 through 13 are selected; and in the fourth sampling period, DAC units 14 and 15 and DAC units 1 through 2 are selected.

[0034] Figure 3 records a total of 28 sampling cycles, with each DAC unit appearing (and therefore being selected) 8 times, meaning each unit has an equal probability of appearing. Although the output data Dout[3:0] varies within each quantization cycle, each DAC unit is traversed over a sufficiently long period of time, and each unit has an equal probability of appearing. As a result, the DWA algorithm eliminates mismatches between DAC units, eliminating significant harmonics.

[0035] However, while the DWA algorithm reduces harmonics, the harmonic components are dispersed into the noise floor. In other words, while the existing DWA algorithm reduces harmonics, it also raises the noise floor. This increased noise floor reduces the SD-ADC's SNR and results in poor accuracy.

[0036] In the disclosed embodiment, weights are pre-set to correspond to each DAC unit in the DAC, and the control signals output by the DWA control circuit are weighted and summed to obtain the target digital signal. The weights corresponding to each DAC unit in the DAC can be determined through pre-testing and can be matched to the analog-to-digital converter, minimizing mismatches between DAC units, thereby improving the signal-to-noise ratio and accuracy of the analog-to-digital converter.

[0037] In order to make the above-mentioned objectives, features and beneficial effects of the present disclosure more obvious and easy to understand, the specific embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0038] An embodiment of the present disclosure provides an analog-to-digital converter, referring to FIG. 4 .

[0039] In an embodiment of the present disclosure, the analog-to-digital converter may include a DWA control circuit 405 , a DAC 406 , a weight acquisition unit 407 , a multiplier 408 , and an accumulator 409 .

[0040] In a specific implementation, the input end of the DWA control circuit 405 can input a decoding signal, and the output end of the DWA control circuit 405 can be coupled to a digital-to-analog converter and suitable for outputting a control signal; the decoding signal can be associated with the target analog signal input to the analog-to-digital converter, the number of bits in the control signal can be equal to the number of DAC units in DAC406, and the bits in the control signal correspond one-to-one to the DAC cells.

[0041] In a specific implementation, the weight acquisition unit 407 may store weights corresponding to the DAC units. The number of weights stored in the weight acquisition unit 407 may be equal to the number of DAC units, and each DAC unit has a one-to-one corresponding weight.

[0042] For example, there are 7 DAC units, namely DAC unit 1 to DAC unit 7. The weight acquisition unit 407 stores 7 weights, namely weight 1 to weight 7. The weight corresponding to DAC unit 1 is weight 1, the weight corresponding to DAC unit 2 is weight 2, and so on. The weight corresponding to DAC unit 7 is weight 7. The control signal includes 7 bits. The first bit is input to DAC unit 1, the second bit is input to DAC unit 2, and so on. The seventh bit is input to DAC unit 7.

[0043] That is, the number of bits in the control signal, the number of DAC units, and the number of weights stored in the weight acquisition unit 407 are all equal and equal to 2. N -1, N is the number of bits of the analog-to-digital converter.

[0044] For example, if the number of bits of the analog converter N=3, the number of bits in the control signal, the number of DAC units, and the number of weights stored in the weight acquisition unit 407 are all 7.

[0045] For another example, if the number of bits of the analog converter N=4, then the number of bits in the control signal, the number of DAC units, and the number of weights stored in the weight acquisition unit 407 are all 15.

[0046] In a specific implementation, the multiplier 408 may multiply the control signal by the weight to obtain a digital quantization output correction value corresponding to each DAC unit.

[0047] Specifically, the bit value corresponding to the first DAC unit (i.e., the value of the first bit in the control signal) is multiplied by the weight corresponding to the first DAC unit to obtain the digital quantization output correction value corresponding to the first DAC unit; the bit value corresponding to the second DAC unit (i.e., the value of the second bit in the control signal) is multiplied by the weight corresponding to the second DAC unit to obtain the digital quantization output correction value corresponding to the second DAC unit; and so on, the second DAC unit can be obtained. N -Digital quantization output correction value corresponding to 1 DAC unit.

[0048] 2 N The digital quantization output correction value corresponding to -1 DAC unit is input to the accumulator 409, and the accumulator 409 converts 2 N By summing the digital quantization output correction values ​​corresponding to -1 DAC unit, the target digital signal corresponding to the target analog signal can be obtained.

[0049] In a specific implementation, the analog-to-digital converter may further include an adder 401. A target analog signal may be input to a first input terminal of the adder 401, and a feedback signal may be input to a second input terminal of the adder 401. The adder 401 performs a subtraction operation on the target analog signal and the feedback signal to obtain a difference signal. An output terminal of the adder 401 outputs the difference signal.

[0050] In a specific implementation, the analog-to-digital converter may further include a loop filter 402. The input of the loop filter 402 is coupled to the output of the adder 401, and the output of the loop filter 402 outputs the filtered difference signal. By setting the loop filter 402, high-frequency components in the difference signal are filtered out.

[0051] It is understandable that the high-frequency component in the difference signal may refer to a frequency component having a frequency higher than a preset frequency threshold. The specific frequency threshold may be set according to different application scenarios.

[0052] In some embodiments, loop filter 402 may be a low-pass loop filter 402 .

[0053] In a specific implementation, the analog-to-digital converter may further include an N-bit quantizer 403. An input terminal of the N-bit quantizer 403 is coupled to an output terminal of the filter 402, and an output terminal of the N-bit quantizer 403 outputs a quantized signal with a length of N bits.

[0054] In a specific implementation, the analog-to-digital converter may further include a decoder 404. The input end of the decoder 404 is coupled to the output end of the N-bit quantizer 403, and the output end of the decoder 404 is coupled to the input end of the DWA. The decoder 404 decodes the N-bit quantized signal to obtain a 2-bit quantized signal. N -1 bit decoded signal.

[0055] In an embodiment of the present disclosure, the aforementioned analog-to-digital converter may be an SD-ADC.

[0056] The following describes the workflow of the SD-ADC provided in the above embodiments of the present disclosure.

[0057] In a specific implementation, the target analog signal Vin is input to the input end of the SD-ADC, the target analog signal Vin is input to the first input end ("+" end) of the adder, and the feedback signal Vfb output by the digital-to-analog converter (DAC) is input to the second input end ("-" end) of the adder. After the subtraction operation of the adder, the difference signal Vdff between Vin and Vfb is obtained. The difference signal Vdff is filtered out of the high-frequency component by a low-pass loop filter to obtain a Vfltr signal including only low-frequency components. After the Vfltr signal is quantized by an N-bit quantizer, an N-bit digital signal Dout[N-1:0] is obtained. The N-bit digital signal is input to the decoder to obtain 2 N -1-bit thermometer code and input to the DWA control circuit.

[0058] Taking N=4 as an example, the Vfltr signal is quantized by a 4-bit quantizer to generate a 4-bit digital signal. The 4-bit data signal is decoded to generate a 15-bit thermometer code, which is then input and output to the DWA control circuit.

[0059] The DWA control circuit controls the selection of the DAC unit in a barrel shift manner. The output of the DWA control circuit is coupled to the input of the DAC. The DAC includes 2 N - 1 DAC unit, DAC pair 2 N The outputs of the -1 DAC units are accumulated to obtain the feedback signal Vfb.

[0060] The output of the DWA control circuit is also coupled to the first input of the multiplier, the output of the weight acquisition unit is coupled to the second input of the multiplier, and the output of the multiplier is coupled to the input of the accumulator. The output of the accumulator outputs Dout[M:0], which is the target digital signal corresponding to the target analog signal Vin.

[0061] In a specific implementation, the value of M in Dout[M:0] can be determined based on specific application requirements. A larger value of M results in higher SD-ADC accuracy and, correspondingly, greater computing resource requirements. A smaller value of M results in lower SD-ADC accuracy and, correspondingly, lower computing resource requirements. Therefore, the value of M can be determined by balancing SD-ADC accuracy and computing resource requirements.

[0062] In an embodiment of the present disclosure, the weight acquisition unit may pre-store the weights corresponding to each DAC unit. The weights corresponding to each DAC unit may be pre-calculated. When the SD-ADC is operating, the weights corresponding to each DAC unit may be directly obtained from the weight acquisition unit and output to the second input of the multiplier.

[0063] In some embodiments, M is set to 23. Thus, a 24-bit digital signal corresponding to the input analog signal Vin can be obtained.

[0064] Taking a 4-bit quantizer as an example, the DAC includes 15 DAC units. The weights corresponding to each of the 15 DAC units are estimated in advance. The 15 DAC unit weights are multiplied by the data output by the DWA control circuit. The 15 products are then accumulated in an accumulator to obtain Dout[23:0].

[0065] The specific process of the weight obtaining unit 407 obtaining the weight corresponding to each DAC unit is described below.

[0066] For 2 N -1 DAC unit, assuming the number of sampling cycles is Ns:

[0067] Step 1: Select the first DAC unit and set its frequency of occurrence in Ns sampling periods to Nx; for the other two N -2 DAC units, traversed according to the above classic DWA algorithm, the frequency of occurrence in Ns sampling periods is N1;

[0068] Step 2: Select the second DAC unit and set its frequency of occurrence in Ns sampling periods to Nx; for the other two N -2 DAC units, traversed according to the above classic DWA algorithm, the frequency of occurrence in Ns sampling periods is N2;

[0069] Step 3, select the third DAC unit and set its frequency of occurrence in Ns sampling periods to Nx; for the other two N -2 DAC units, traversed according to the above classic DWA algorithm, the frequency of occurrence in Ns sampling periods is N3;

[0070] And so on;

[0071] Step 2 N -1, select 2 N -1 DAC unit, set its frequency of occurrence in Ns sampling periods to Nx; for the other 2 N -2 DAC units, according to the above classic DWA algorithm, the frequency of occurrence in Ns sampling periods is

[0072] Thus, we can get a set of values: Nx.

[0073] Setting 2 N -The weights of 1 DAC unit are 2 N -The average value of the weight of 1 DAC unit is 1. Since Vfb = Vin, the above 2 N The sum of the products of the data obtained in the -1 step and its weight is equal. Based on this, the following equations can be obtained:

[0074] as well as,

[0075] Through the above two equations, we can calculate The sequence is: x1=(Y-(2 N -1)*N1) / (Nx-N1); x2=(Y-(2 N -1)*N2) / (Nx-N2); x3=(Y-(2 N -1)*N3) / (Nx-N3); ...;

[0076] in,

[0077] Thus, we can calculate 2 N -The weight corresponding to 1 DAC unit.

[0078] In some embodiments, the value of Nx may be equal to Ns. In other embodiments, the value of Nx may not be equal to Ns, and the value of Nx may be equal to Are not equal.

[0079] The following takes N=4 as an example to illustrate the calculation process of the weights of the above-mentioned DAC units.

[0080] When N=4, the number of DAC units included in the DAC is 2 N-1=15, which are DAC unit 1 to DAC unit 15. Assume that the number of sampling cycles is Ns, Nx=Ns.

[0081] Step 1: Select the first DAC unit (DAC unit 1) and set its frequency of occurrence within Ns sampling periods to Ns (that is, within Ns sampling periods, the first DAC unit appears in every sampling period); for the other 14 DAC units (DAC unit 2 to DAC unit 15), traverse according to the above classic DWA algorithm, and set their frequency of occurrence within Ns sampling periods to N1;

[0082] 5 shows a schematic diagram of the DAC units selected within Ns sampling periods in step 1. In step 1, DAC unit 1 is assumed to be selected within Ns sampling periods, and DAC units 2 to 15 are traversed according to the classic DWA algorithm, with the frequency of their occurrence within Ns sampling periods being N1.

[0083] Step 2: Select the second DAC unit (DAC unit 2) and set its frequency of occurrence within Ns sampling periods to Ns; for the other 14 DAC units (DAC unit 1, DAC unit 3 to DAC unit 15), traverse according to the above classic DWA algorithm, and set the frequency of occurrence within Ns sampling periods to N2.

[0084] 6 shows a schematic diagram of the DAC units selected within Ns sampling periods in step 2. In step 2, DAC unit 2 is assumed to be selected within Ns sampling periods, and DAC units 1, 3 to 15 are traversed according to the classic DWA algorithm, with the frequency of their occurrence within Ns sampling periods being N2.

[0085] Step 3: Select the third DAC unit (DAC unit 3) and set its frequency of occurrence within Ns sampling periods to Ns. For the other 14 DAC units (DAC unit 1 to DAC unit 2, DAC unit 4 to DAC unit 15), traverse according to the above classic DWA algorithm, and set their frequency of occurrence within Ns sampling periods to N3.

[0086] ...;

[0087] Step 15: Select the 15th DAC unit (DAC unit 15) and set its frequency of occurrence in Ns sampling periods to Ns; for the other 14 DAC units (DAC unit 1 to DAC unit 14), traverse according to the above classic DWA algorithm, and set the frequency of occurrence in Ns sampling periods to Ns. 15 .

[0088] Set the weights of the 15 DAC units to x1, x2, ..., x 15 , the average value of the weights of the 15 DAC units is 1. The following equations are obtained:

[0089] as well as

[0090] Through the above two equations, we can calculate They are: x1=(Y-15*N1) / (Ns-N1); x2=(Y-15*N2) / (Ns-N2); x3=(Y-15*N3) / (Ns-N3); ...; x 15 =(Y-15*N 15 ) / (Ns-N 15 );

[0091] in,

[0092] In a specific implementation, the weight acquisition unit 407 may also be used only to store the weights corresponding to each DAC unit. Specifically, the weights of each DAC unit may be calculated by an external data processing device. For example, the external data processing device calculates the weights of each DAC unit and sends them to the weight acquisition unit 407 for storage.

[0093] In summary, in the embodiments of the present disclosure, by presetting weights corresponding to the DAC units in the DAC, the control signals output by the DWA control circuit are weighted and summed to obtain the target digital signal. The weights corresponding to the DAC units in the DAC can be obtained through pre-testing and can be matched to the analog-to-digital converter, minimizing mismatches between DAC units, thereby improving the signal-to-noise ratio and accuracy of the analog-to-digital converter.

[0094] The analog-to-digital converter provided in the embodiments of the present disclosure does not make any changes to the analog circuit portion, and does not increase the cost and complexity of the analog circuit portion.

[0095] An embodiment of the present disclosure further provides a terminal device, comprising the analog-to-digital converter provided by any of the above embodiments.

[0096] Although the present disclosure is disclosed as above, the present disclosure is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope defined by the claims.

Claims

1. An analog-to-digital converter, characterized in that: include: Data weighted average control circuit, digital-to-analog converter, weight acquisition unit, multiplier, accumulator, wherein: The data weighted average control circuit has an input terminal inputting a decoded signal, and an output terminal coupled to the digital-to-analog converter, adapted to output a control signal; the decoded signal is associated with a target analog signal input to the analog-to-digital converter, and bits in the control signal correspond one-to-one to DAC units in the digital-to-analog converter DAC; The weight acquisition unit stores weights corresponding to the DAC units one by one; The multiplier is adapted to multiply the control signal by the weight to obtain a digital quantization output correction value corresponding to each DAC unit one by one; The accumulator is suitable for accumulating the digital quantization output correction values ​​corresponding to all DAC units to obtain the target digital signal corresponding to the target analog signal.

2. The analog-to-digital converter according to claim 1, wherein: The average value of the weights corresponding one-to-one to the DAC units is 1, and the weights corresponding to some DAC units are not equal.

3. The analog-to-digital converter according to claim 2, wherein: The weights corresponding to the DAC units are determined in the following manner: Obtain a weighted equation corresponding to the i-th DAC unit, wherein the i-th weighted equation is: Based on 2 N -1 weighted equation corresponding to the DAC unit, determine the weight x corresponding to the i-th DAC unit i ; Among them, N x is the number of times the i-th DAC unit is selected by the DWA control circuit within Ns sampling periods, N i is the number of times other DAC units are selected by the DWA control circuit within Ns sampling cycles; 1≤i≤2 N -1; N is the number of bits of the analog-to-digital converter.

4. The analog-to-digital converter according to claim 3, wherein: N x is equal to Ns; or, N x Not equal to Ns, and N x With N i Not waiting.

5. The analog-to-digital converter according to any one of claims 1 to 4, characterized in that: Also includes: An adder is adapted to perform a subtraction operation on the target analog signal and the feedback signal, and output a difference signal; the feedback signal is the output signal of the DAC, and the output signal of the DAC is the sum of the output signals of all DAC units; the output signal of the DAC unit is obtained based on the control signal.

6. The analog-to-digital converter according to claim 5, characterized in that Also includes: The filter is adapted to perform filtering processing on the difference signal to filter out high-frequency components in the difference signal.

7. The analog-to-digital converter according to claim 6, wherein: Also includes: A quantizer, adapted to perform a quantization operation on the difference signal after the filtering process to obtain a quantized signal with a length of N bits; The number of bits of the quantizer is N.

8. The analog-to-digital converter according to claim 7, characterized in that Also includes: A decoder adapted to decode the quantized signal into the decoded signal; the bit length of the decoded signal is 2 N -1.

9. The analog-to-digital converter according to claim 1, wherein: The analog-to-digital converter comprises a sigma delta analog-to-digital converter.

10. A terminal device, characterized in that: It comprises an analog-to-digital converter as claimed in any one of claims 1 to 9.

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