Signal transmission apparatus, electronic device, and vehicle

Abstract

A signal transmission apparatus 400 comprises: an insulation element 435 for performing signal transmission between a primary circuit system 400p and a secondary circuit system 400s while providing insulation therebetween; a self-diagnosis circuit 424 which is provided in the secondary circuit system 400s and performs self-diagnosis of the secondary circuit system 400s; a storage circuit 425 which is provided in the secondary circuit system 400s and in which memory access is permitted after completion of the self-diagnosis; and a transmission circuit 422 which is provided in the secondary circuit system 400s and outputs a transmission pulse signal S1 to the insulation element 435. The transmission circuit 422 generates one pulse or a group of a plurality of pulses in the transmission pulse signal S1 at the completion timing of each of the self-diagnosis and the memory access, and continues generating pulses at the period of a first time T1 in the transmission pulse signal S1 when an abnormality in the memory access is being detected.

Description

Signal transmission devices, electronic devices, vehicles

[0001] The present disclosure relates to a signal transmission device, an electronic device, and a vehicle.

[0002] BACKGROUND ART Signal transmission devices that transmit signals between a primary circuit system and a secondary circuit system while electrically insulating the primary circuit system from the secondary circuit system have been used in various applications (such as power supply devices or motor drive devices).

[0003] An example of the related prior art is Patent Document 1 by the applicant of the present application.

[0004] International Publication No. 2022 / 070944

[0005] [Summary] However, in conventional signal transmission devices, there is room for reducing the number of insulating elements.

[0006] For example, a signal transmission device according to the present disclosure includes an isolation element configured to transmit signals while isolating a primary circuit system from a secondary circuit system, a self-diagnosis circuit provided in the secondary circuit system and configured to perform a self-diagnosis of the secondary circuit system, a memory circuit provided in the secondary circuit system and configured to allow memory access after completion of the self-diagnosis, and a transmission circuit provided in the secondary circuit system and configured to output a transmission pulse signal to the isolation element, wherein the transmission circuit generates one pulse or a group of multiple pulses in the transmission pulse signal at the timing of completion of the self-diagnosis and the memory access, respectively, and continues to generate pulses in the transmission pulse signal at a first time period when an abnormality in the memory access is detected.

[0007] FIG. 1 is a diagram showing the basic configuration of a signal transmission device. FIG. 2 is a diagram showing the basic structure of a transformer chip. FIG. 3 is a perspective view of a semiconductor device used as a two-channel transformer chip. FIG. 4 is a plan view of the semiconductor device shown in FIG. 3. FIG. 5 is a plan view showing a layer in which a low-potential coil is formed in the semiconductor device of FIG. 3. FIG. 6 is a plan view showing a layer in which a high-potential coil is formed in the semiconductor device of FIG. 3. FIG. 7 is a cross-sectional view taken along line VIII-VIII shown in FIG. 6. FIG. 8 is an enlarged view (separation structure) of region XIII shown in FIG. 7. FIG. 9 is a diagram schematically showing an example layout of a transformer chip. FIG. 10 is a diagram showing the detailed configuration of a signal transmission device. FIG. 11 is a diagram showing an example configuration of an electronic device incorporating a signal transmission device. FIG. 12 is a diagram showing operation mode switching control. FIG. 13 is a diagram showing a first embodiment (comparative example) of a signal transmission device. FIG. 14 is a diagram showing a second embodiment (overview) of a signal transmission device. FIG. 15 is a diagram showing a first main part of the second embodiment (first main part) of a signal transmission device. FIG. 16 is a diagram showing a first example of shared insulating elements. Fig. 17 is a diagram showing a second embodiment (second main part) of the signal transmission device, Fig. 18 is a diagram showing a second example of sharing an insulating element, and Fig. 19 is a diagram showing the appearance of a vehicle.

[0008] [Detailed Description] <Signal Transmission Device (Basic Configuration)> Figure 1 shows the basic configuration of a signal transmission device. The signal transmission device 200 of this configuration example is a semiconductor integrated circuit device (a so-called insulated gate driver IC) that transmits a pulse signal from the primary circuit system 200p to the secondary circuit system 200s while isolating the primary circuit system 200p (VCC1-GND1 system) from the secondary circuit system 200s (VCC2-GND2 system) and drives the gate of a switch element (not shown) provided in the secondary circuit system 200s. For example, the signal transmission device 200 is formed by sealing a controller chip 210, a driver chip 220, and a transformer chip 230 in a single package.

[0009] The controller chip 210 is a semiconductor chip that operates by receiving a power supply voltage VCC1 (for example, a maximum of 7 V with respect to GND1). The controller chip 210 has integrated therein, for example, a pulse transmission circuit 211 and buffers 212 and 213.

[0010] The pulse transmitting circuit 211 is a pulse generator that generates transmission pulse signals S11 and S21 in response to the input pulse signal IN. More specifically, when the pulse transmitting circuit 211 notifies that the input pulse signal IN is at a high level, it pulse-drives the transmission pulse signal S11 (outputting a single or multiple transmission pulses), and when it notifies that the input pulse signal IN is at a low level, it pulse-drives the transmission pulse signal S21. In other words, the pulse transmitting circuit 211 pulse-drives either the transmission pulse signal S11 or S21 in response to the logic level of the input pulse signal IN.

[0011] The buffer 212 receives the transmission pulse signal S11 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically, the transformer 231).

[0012] The buffer 213 receives the transmission pulse signal S21 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically, the transformer 232).

[0013] The driver chip 220 is a semiconductor chip that operates by receiving a power supply voltage VCC2 (for example, a maximum of 30 V relative to GND2). The driver chip 220 integrates, for example, buffers 221 and 222, a pulse receiving circuit 223, and a driver 224.

[0014] The buffer 221 shapes the waveform of the received pulse signal S12 induced in the transformer chip 230 (specifically, the transformer 231) and outputs the result to the pulse receiving circuit 223.

[0015] The buffer 222 shapes the waveform of the received pulse signal S22 induced in the transformer chip 230 (specifically, the transformer 232) and outputs the result to the pulse receiving circuit 223.

[0016] The pulse receiving circuit 223 generates the output pulse signal OUT by driving the driver 224 in response to the received pulse signals S12 and S22 input via the buffers 221 and 222. More specifically, the pulse receiving circuit 223 drives the driver 224 so that the output pulse signal OUT rises to a high level in response to the pulse driving of the received pulse signal S12, and the output pulse signal OUT falls to a low level in response to the pulse driving of the received pulse signal S22. In other words, the pulse receiving circuit 223 switches the logic level of the output pulse signal OUT in response to the logic level of the input pulse signal IN. Note that an RS flip-flop, for example, can be suitably used as the pulse receiving circuit 223.

[0017] The driver 224 generates an output pulse signal OUT based on the drive control of the pulse receiving circuit 223 .

[0018] The transformer chip 230 provides DC insulation between the controller chip 210 and the driver chip 220 using transformers 231 and 232, and outputs transmission pulse signals S11 and S21 input from the pulse transmission circuit 211 as reception pulse signals S12 and S22, respectively, to the pulse reception circuit 223. In this specification, "DC-insulated" means that the objects to be insulated are not connected by a conductor.

[0019] More specifically, the transformer 231 outputs a received pulse signal S12 from the secondary coil 231s in response to a transmitted pulse signal S11 input to the primary coil 231p, while the transformer 232 outputs a received pulse signal S22 from the secondary coil 232s in response to a transmitted pulse signal S21 input to the primary coil 232p.

[0020] As described above, due to the characteristics of the spiral coil used for insulated communication, the input pulse signal IN is separated into two transmission pulse signals S11 and S21 (corresponding to a rise signal and a fall signal), and then transmitted from the primary circuit system 200p to the secondary circuit system 200s via two transformers 231 and 232.

[0021] In addition, the signal transmission device 200 of this configuration example has an independent transformer chip 230 equipped with only transformers 231 and 232, separate from the controller chip 210 and driver chip 220, and these three chips are sealed in a single package.

[0022] With this configuration, the controller chip 210 and the driver chip 220 can both be formed using a general low to medium voltage withstand process (withstand voltage of several volts to several tens of volts), eliminating the need to use a dedicated high voltage withstand process (withstand voltage of several kV), thereby making it possible to reduce manufacturing costs.

[0023] The signal transmission device 200 can be suitably used, for example, in a power supply device or a motor drive device for on-board equipment mounted in a vehicle. The above-mentioned vehicles include not only engine vehicles but also electric vehicles (BEVs [battery electric vehicles], HEVs [hybrid electric vehicles], PHEVs / PHVs (plug-in hybrid electric vehicles / plug-in hybrid vehicles), or xEVs such as FCEVs / FCVs (fuel cell electric vehicles / fuel cell vehicles)).

[0024] <Transformer Chip (Basic Structure)> Next, the basic structure of the transformer chip 230 will be described. Fig. 2 is a diagram showing the basic structure of the transformer chip 230. In the transformer chip 230 shown in this figure, the transformer 231 includes a primary coil 231p and a secondary coil 231s that face each other in the vertical direction. The transformer 232 includes a primary coil 232p and a secondary coil 232s that face each other in the vertical direction.

[0025] The primary coils 231p and 232p are both formed on a first wiring layer (lower layer) 230a of the transformer chip 230. The secondary coils 231s and 232s are both formed on a second wiring layer (upper layer in this figure) 230b of the transformer chip 230. The secondary coil 231s is disposed directly above the primary coil 231p and faces the primary coil 231p. The secondary coil 232s is disposed directly above the primary coil 232p and faces the primary coil 232p.

[0026] The primary coil 231p is laid in a spiral shape starting from a first end connected to the internal terminal X21, surrounding the periphery of the internal terminal X21 in a clockwise direction, and its second end corresponding to its end point is connected to the internal terminal X22. On the other hand, the primary coil 232p is laid in a spiral shape starting from a first end connected to the internal terminal X23, surrounding the periphery of the internal terminal X23 in a counterclockwise direction, and its second end corresponding to its end point is connected to the internal terminal X22. The internal terminals X21, X22, and X23 are linearly arranged in the order shown in the figure.

[0027] The internal terminal X21 is connected to the external terminal T21 on the second layer 230b via the conductive wiring Y21 and the via Z21. The internal terminal X22 is connected to the external terminal T22 on the second layer 230b via the conductive wiring Y22 and the via Z22. The internal terminal X23 is connected to the external terminal T23 on the second layer 230b via the conductive wiring Y23 and the via Z23. The external terminals T21 to T23 are arranged in a straight line and are used for wire bonding with the controller chip 210.

[0028] The secondary coil 231s is laid in a spiral shape starting from a first end connected to the external terminal T24, surrounding the periphery of the external terminal T24 in a counterclockwise direction, and its second end corresponding to its end point is connected to the external terminal T25. Meanwhile, the secondary coil 232s is laid in a spiral shape starting from a first end connected to the external terminal T26, surrounding the periphery of the external terminal T26 in a clockwise direction, and its second end corresponding to its end point is connected to the external terminal T25. The external terminals T24, T25, and T26 are arranged linearly in the order shown in the figure, and are used for wire bonding with the driver chip 220.

[0029] The secondary coils 231s and 232s are AC-connected to the primary coils 231p and 232p by magnetic coupling, and are DC-insulated from the primary coils 231p and 232p, respectively. That is, the driver chip 220 is AC-connected to the controller chip 210 via the transformer chip 230, and is DC-insulated from the controller chip 210 by the transformer chip 230.

[0030] <Transformer Chip (Two-Channel Type)> FIG. 3 is a perspective view showing a semiconductor device 5 used as a two-channel transformer chip. FIG. 4 is a plan view of the semiconductor device 5 shown in FIG. 3. FIG. 5 is a plan view showing a layer in which the low-potential coil 22 (corresponding to the primary coil of the transformer) is formed in the semiconductor device 5 shown in FIG. 3. FIG. 6 is a plan view showing a layer in which the high-potential coil 23 (corresponding to the secondary coil of the transformer) is formed in the semiconductor device 5 shown in FIG. 3. FIG. 7 is a cross-sectional view taken along line VIII-VIII shown in FIG. 6. FIG. 8 is an enlarged view of region XIII shown in FIG. 7, showing an isolation structure 130.

[0031] 3 to 7, the semiconductor device 5 includes a rectangular parallelepiped semiconductor chip 41. The semiconductor chip 41 includes at least one of silicon, a wide bandgap semiconductor, and a compound semiconductor.

[0032] The wide bandgap semiconductor is a semiconductor with a bandgap exceeding that of silicon (approximately 1.12 eV). The bandgap of the wide bandgap semiconductor is preferably 2.0 eV or greater. The wide bandgap semiconductor may be silicon carbide (SiC). The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may include at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide).

[0033] In this embodiment, the semiconductor chip 41 includes a silicon semiconductor substrate. The semiconductor chip 41 may be an epitaxial substrate having a layered structure including a silicon semiconductor substrate and a silicon epitaxial layer. The conductivity type of the semiconductor substrate may be n-type or p-type. The epitaxial layer may be n-type or p-type.

[0034] The semiconductor chip 41 has a first main surface 42 on one side, a second main surface 43 on the other side, and chip sidewalls 44A to 44D connecting the first main surface 42 and the second main surface 43. The first main surface 42 and the second main surface 43 are formed in a quadrangular shape (rectangular in this embodiment) in a plan view seen from their normal direction Z (hereinafter simply referred to as "plan view").

[0035] The chip sidewalls 44A to 44D include a first chip sidewall 44A, a second chip sidewall 44B, a third chip sidewall 44C, and a fourth chip sidewall 44D. The first chip sidewall 44A and the second chip sidewall 44B form the long sides of the semiconductor chip 41. The first chip sidewall 44A and the second chip sidewall 44B extend along the first direction X and face the second direction Y. The third chip sidewall 44C and the fourth chip sidewall 44D form the short sides of the semiconductor chip 41. The third chip sidewall 44C and the fourth chip sidewall 44D extend in the second direction Y and face the first direction X. The chip sidewalls 44A to 44D are made of ground surfaces.

[0036] The semiconductor device 5 further includes an insulating layer 51 formed on the first main surface 42 of the semiconductor chip 41. The insulating layer 51 has an insulating main surface 52 and insulating sidewalls 53A to 53D. The insulating main surface 52 is formed in a quadrangular shape (rectangular in this embodiment) that matches the first main surface 42 in a plan view. The insulating main surface 52 extends parallel to the first main surface 42.

[0037] The insulating sidewalls 53A to 53D include a first insulating sidewall 53A, a second insulating sidewall 53B, a third insulating sidewall 53C, and a fourth insulating sidewall 53D. The insulating sidewalls 53A to 53D extend from the periphery of the insulating main surface 52 toward the semiconductor chip 41 and are continuous with the chip sidewalls 44A to 44D. Specifically, the insulating sidewalls 53A to 53D are formed flush with the chip sidewalls 44A to 44D. The insulating sidewalls 53A to 53D form ground surfaces that are flush with the chip sidewalls 44A to 44D.

[0038] The insulating layer 51 has a multilayer insulating laminate structure including a bottom insulating layer 55, a top insulating layer 56, and multiple (11 in this embodiment) interlayer insulating layers 57. The bottom insulating layer 55 is an insulating layer that directly covers the first main surface 42. The top insulating layer 56 is an insulating layer that forms the insulating main surface 52. The multiple interlayer insulating layers 57 are insulating layers interposed between the bottom insulating layer 55 and the top insulating layer 56. In this embodiment, the bottom insulating layer 55 has a single-layer structure containing silicon oxide. In this embodiment, the top insulating layer 56 also has a single-layer structure containing silicon oxide. The thickness of the bottom insulating layer 55 and the top insulating layer 56 may each be 1 μm or more and 3 μm or less (for example, approximately 2 μm).

[0039] Each of the multiple interlayer insulating layers 57 has a stacked structure including a first insulating layer 58 on the side of the bottom insulating layer 55 and a second insulating layer 59 on the side of the top insulating layer 56. The first insulating layer 58 may contain silicon nitride. The first insulating layer 58 is formed as an etching stopper layer for the second insulating layer 59. The thickness of the first insulating layer 58 may be 0.1 μm or more and 1 μm or less (for example, approximately 0.3 μm).

[0040] The second insulating layer 59 is formed on the first insulating layer 58. The second insulating layer 59 contains an insulating material different from that of the first insulating layer 58. The second insulating layer 59 may contain silicon oxide. The thickness of the second insulating layer 59 may be 1 μm or more and 3 μm or less (for example, approximately 2 μm). The thickness of the second insulating layer 59 is preferably greater than the thickness of the first insulating layer 58.

[0041] The total thickness DT of the insulating layers 51 may be 5 μm or more and 50 μm or less. The total thickness DT of the insulating layers 51 and the number of stacked interlayer insulating layers 57 are arbitrary and are adjusted according to the dielectric strength voltage (dielectric breakdown resistance) to be achieved. Furthermore, the insulating materials of the bottom insulating layer 55, the top insulating layer 56, and the interlayer insulating layers 57 are arbitrary and are not limited to a specific insulating material.

[0042] The semiconductor device 5 includes a first functional device 45 formed in an insulating layer 51. The first functional device 45 includes one or more (in this embodiment, multiple) transformers 21 (corresponding to the aforementioned transformers). In other words, the semiconductor device 5 is a multi-channel device including multiple transformers 21. The multiple transformers 21 are formed inward of the insulating layer 51 and spaced apart from the insulating side walls 53A to 53D. The multiple transformers 21 are formed at intervals in the first direction X.

[0043] Specifically, the multiple transformers 21 include a first transformer 21A, a second transformer 21B, a third transformer 21C, and a fourth transformer 21D, which are formed in this order from the insulating side wall 53C side toward the insulating side wall 53D side in a plan view. The multiple transformers 21A to 21D each have a similar structure. The following description will be given using the structure of the first transformer 21A as an example. The description of the structure of the first transformer 21A applies mutatis mutandis to the description of the structures of the second transformer 21B, third transformer 21C, and fourth transformer 21D, and will be omitted.

[0044] 5 to 7 , the first transformer 21A includes a low-potential coil 22 and a high-potential coil 23. The low-potential coil 22 is formed in an insulating layer 51. The high-potential coil 23 is formed in the insulating layer 51 so as to face the low-potential coil 22 in the normal direction Z. In this embodiment, the low-potential coil 22 and the high-potential coil 23 are formed in a region sandwiched between a lowermost insulating layer 55 and an uppermost insulating layer 56 (i.e., multiple interlayer insulating layers 57).

[0045] The low-potential coil 22 is formed on the side of the lowest insulating layer 55 (semiconductor chip 41) within the insulating layer 51, and the high-potential coil 23 is formed on the side of the highest insulating layer 56 (insulating main surface 52) relative to the low-potential coil 22 within the insulating layer 51. In other words, the high-potential coil 23 faces the semiconductor chip 41 with the low-potential coil 22 sandwiched between them. The low-potential coil 22 and the high-potential coil 23 may be disposed in any desired locations. Furthermore, it is sufficient that the high-potential coil 23 faces the low-potential coil 22 with one or more interlayer insulating layers 57 sandwiched between them.

[0046] The distance between the low-potential coil 22 and the high-potential coil 23 (i.e., the number of layers of the interlayer insulating layers 57) is adjusted appropriately depending on the dielectric strength and electric field strength between the low-potential coil 22 and the high-potential coil 23. In this embodiment, the low-potential coil 22 is formed on the third interlayer insulating layer 57 counting from the bottom insulating layer 55 side. In this embodiment, the high-potential coil 23 is formed on the first interlayer insulating layer 57 counting from the top insulating layer 56 side.

[0047] The low-potential coil 22 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The low-potential coil 22 includes a first inner end 24, a first outer end 25, and a first spiral portion 26 that is wound in a spiral shape between the first inner end 24 and the first outer end 25. The first spiral portion 26 is wound in a spiral shape that extends in an elliptical shape (oval shape) in a plan view. The portion that forms the innermost periphery of the first spiral portion 26 defines a first inner region 66 that is elliptical in a plan view.

[0048] The number of turns of the first helical portion 26 may be 5 or more and 30 or less. The width of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. The width of the first helical portion 26 is preferably 1 μm or more and 3 μm or less. The width of the first helical portion 26 is defined by the width in a direction perpendicular to the helical direction. The first winding pitch of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. The first winding pitch is preferably 1 μm or more and 3 μm or less. The first winding pitch is defined by the distance between two adjacent portions of the first helical portion 26 in a direction perpendicular to the helical direction.

[0049] The winding shape of the first spiral portion 26 and the planar shape of the first inner region 66 are arbitrary and are not limited to the form shown in Fig. 5 etc. The first spiral portion 26 may be wound in a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view. The first inner region 66 may be partitioned into a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view, depending on the winding shape of the first spiral portion 26.

[0050] The low-potential coil 22 may include at least one of titanium, titanium nitride, copper, aluminum, and tungsten. The low-potential coil 22 may have a layered structure including a barrier layer and a body layer. The barrier layer defines a recess space in the interlayer insulating layer 57. The barrier layer may include at least one of titanium and titanium nitride. The body layer may include at least one of copper, aluminum, and tungsten.

[0051] The high-potential coil 23 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The high-potential coil 23 includes a second inner end 27, a second outer end 28, and a second spiral portion 29 wound in a spiral shape between the second inner end 27 and the second outer end 28. The second spiral portion 29 is wound in a spiral shape that extends in an elliptical (oval) shape in a plan view. In this embodiment, the portion forming the innermost periphery of the second spiral portion 29 defines a second inner region 67 that is elliptical in a plan view. The second inner region 67 of the second spiral portion 29 faces the first inner region 66 of the first spiral portion 26 in the normal direction Z.

[0052] The number of turns of the second helical portion 29 may be 5 or more and 30 or less. The number of turns of the second helical portion 29 relative to the number of turns of the first helical portion 26 is adjusted according to the voltage value to be boosted. The number of turns of the second helical portion 29 preferably exceeds the number of turns of the first helical portion 26. Of course, the number of turns of the second helical portion 29 may be less than the number of turns of the first helical portion 26 or may be equal to the number of turns of the first helical portion 26.

[0053] The width of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. The width of the second helical portion 29 is preferably 1 μm or more and 3 μm or less. The width of the second helical portion 29 is defined by the width in a direction perpendicular to the helical direction. The width of the second helical portion 29 is preferably equal to the width of the first helical portion 26.

[0054] The second winding pitch of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. The second winding pitch is preferably 1 μm or more and 3 μm or less. The second winding pitch is defined by the distance between two adjacent portions of the second helical portion 29 in a direction perpendicular to the helical direction. The second winding pitch is preferably equal to the first winding pitch of the first helical portion 26.

[0055] The winding shape of the second spiral portion 29 and the planar shape of the second inner region 67 are arbitrary and are not limited to the form shown in Fig. 6 etc. The second spiral portion 29 may be wound in a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view. The second inner region 67 may be partitioned into a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view, depending on the winding shape of the second spiral portion 29.

[0056] The high-potential coil 23 is preferably formed from the same conductive material as the low-potential coil 22. That is, like the low-potential coil 22, the high-potential coil 23 preferably includes a barrier layer and a main body layer.

[0057] 4, the semiconductor device 5 includes a plurality of (12 in this figure) low potential terminals 11 and a plurality of (12 in this figure) high potential terminals 12. The plurality of low potential terminals 11 are electrically connected to the low potential coils 22 of the corresponding transformers 21A to 21D, respectively. The plurality of high potential terminals 12 are electrically connected to the high potential coils 23 of the corresponding transformers 21A to 21D, respectively.

[0058] The plurality of low potential terminals 11 are formed on the insulating main surface 52 of the insulating layer 51. Specifically, the plurality of low potential terminals 11 are formed in an area on the insulating sidewall 53B side at intervals in the second direction Y from the plurality of transformers 21A to 21D, and are arranged at intervals in the first direction X.

[0059] The plurality of low potential terminals 11 include a first low potential terminal 11A, a second low potential terminal 11B, a third low potential terminal 11C, a fourth low potential terminal 11D, a fifth low potential terminal 11E, and a sixth low potential terminal 11F. In this embodiment, two of each of the plurality of low potential terminals 11A to 11F are formed. The number of the plurality of low potential terminals 11A to 11F is arbitrary.

[0060] The first low potential terminal 11A faces the first transformer 21A in the second direction Y in a plan view. The second low potential terminal 11B faces the second transformer 21B in the second direction Y in a plan view. The third low potential terminal 11C faces the third transformer 21C in the second direction Y in a plan view. The fourth low potential terminal 11D faces the fourth transformer 21D in the second direction Y in a plan view. The fifth low potential terminal 11E is formed in a region between the first low potential terminal 11A and the second low potential terminal 11B in a plan view. The sixth low potential terminal 11F is formed in a region between the third low potential terminal 11C and the fourth low potential terminal 11D in a plan view.

[0061] The first low potential terminal 11A is electrically connected to the first inner end 24 of the first transformer 21A (low potential coil 22). The second low potential terminal 11B is electrically connected to the first inner end 24 of the second transformer 21B (low potential coil 22). The third low potential terminal 11C is electrically connected to the first inner end 24 of the third transformer 21C (low potential coil 22). The fourth low potential terminal 11D is electrically connected to the first inner end 24 of the fourth transformer 21D (low potential coil 22).

[0062] The fifth low potential terminal 11E is electrically connected to the first outer end 25 of the first transformer 21A (low potential coil 22) and the first outer end 25 of the second transformer 21B (low potential coil 22). The sixth low potential terminal 11F is electrically connected to the first outer end 25 of the third transformer 21C (low potential coil 22) and the first outer end 25 of the fourth transformer 21D (low potential coil 22).

[0063] The plurality of high potential terminals 12 are formed on the insulating main surface 52 of the insulating layer 51 at intervals from the plurality of low potential terminals 11. Specifically, the plurality of high potential terminals 12 are formed in an area on the insulating sidewall 53A side at intervals from the plurality of low potential terminals 11 in the second direction Y, and are arranged at intervals in the first direction X.

[0064] The multiple high potential terminals 12 are each formed in a region close to the corresponding transformer 21A to 21D in a plan view. The closeness of the high potential terminal 12 to the transformer 21A to 21D means that the distance between the high potential terminal 12 and the transformer 21 in a plan view is less than the distance between the low potential terminal 11 and the high potential terminal 12.

[0065] Specifically, the multiple high potential terminals 12 are formed at intervals along the first direction X so as to face the multiple transformers 21A to 21D along the first direction X in a plan view. More specifically, the multiple high potential terminals 12 are formed at intervals along the first direction X so as to be located in the second inner region 67 of the high potential coil 23 and in a region between adjacent high potential coils 23 in a plan view. As a result, the multiple high potential terminals 12 are arranged in a line with the multiple transformers 21A to 21D in the first direction X in a plan view.

[0066] The plurality of high potential terminals 12 include a first high potential terminal 12A, a second high potential terminal 12B, a third high potential terminal 12C, a fourth high potential terminal 12D, a fifth high potential terminal 12E, and a sixth high potential terminal 12F. In this embodiment, two of each of the plurality of high potential terminals 12A to 12F are formed. The number of the plurality of high potential terminals 12A to 12F is arbitrary.

[0067] The first high potential terminal 12A is formed in the second inner region 67 of the first transformer 21A (high potential coil 23) in a plan view. The second high potential terminal 12B is formed in the second inner region 67 of the second transformer 21B (high potential coil 23) in a plan view. The third high potential terminal 12C is formed in the second inner region 67 of the third transformer 21C (high potential coil 23) in a plan view. The fourth high potential terminal 12D is formed in the second inner region 67 of the fourth transformer 21D (high potential coil 23) in a plan view. The fifth high potential terminal 12E is formed in the region between the first transformer 21A and the second transformer 21B in a plan view. The sixth high potential terminal 12F is formed in the region between the third transformer 21C and the fourth transformer 21D in a plan view.

[0068] The first high potential terminal 12A is electrically connected to the second inner end 27 of the first transformer 21A (high potential coil 23). The second high potential terminal 12B is electrically connected to the second inner end 27 of the second transformer 21B (high potential coil 23). The third high potential terminal 12C is electrically connected to the second inner end 27 of the third transformer 21C (high potential coil 23). The fourth high potential terminal 12D is electrically connected to the second inner end 27 of the fourth transformer 21D (high potential coil 23).

[0069] The fifth high potential terminal 12E is electrically connected to the second outer end 28 of the first transformer 21A (high potential coil 23) and the second outer end 28 of the second transformer 21B (high potential coil 23). The sixth high potential terminal 12F is electrically connected to the second outer end 28 of the third transformer 21C (high potential coil 23) and the second outer end 28 of the fourth transformer 21D (high potential coil 23).

[0070] 5 to 7, the semiconductor device 5 includes a first low potential wiring 31, a second low potential wiring 32, a first high potential wiring 33, and a second high potential wiring 34, each formed in an insulating layer 51. In this embodiment, a plurality of the first low potential wirings 31, a plurality of the second low potential wirings 32, a plurality of the first high potential wirings 33, and a plurality of the second high potential wirings 34 are formed.

[0071] The first low-potential wiring 31 and the second low-potential wiring 32 fix the low-potential coil 22 of the first transformer 21A and the low-potential coil 22 of the second transformer 21B to the same potential. The first low-potential wiring 31 and the second low-potential wiring 32 also fix the low-potential coil 22 of the third transformer 21C and the low-potential coil 22 of the fourth transformer 21D to the same potential. In this embodiment, the first low-potential wiring 31 and the second low-potential wiring 32 fix all of the low-potential coils 22 of the transformers 21A to 21D to the same potential.

[0072] The first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coil 23 of the first transformer 21A and the high-potential coil 23 of the second transformer 21B to the same potential. The first high-potential wiring 33 and the second high-potential wiring 34 also fix the high-potential coil 23 of the third transformer 21C and the high-potential coil 23 of the fourth transformer 21D to the same potential. In this embodiment, the first high-potential wiring 33 and the second high-potential wiring 34 fix all the high-potential coils 23 of the transformers 21A to 21D to the same potential.

[0073] The plurality of first low-potential wirings 31 are electrically connected to the corresponding low-potential terminals 11A to 11D and the first inner ends 24 of the corresponding transformers 21A to 21D (low-potential coils 22), respectively. The plurality of first low-potential wirings 31 have the same structure. In the following, the structure of the first low-potential wiring 31 connected to the first low-potential terminal 11A and the first transformer 21A will be described as an example. The description of the structure of the first low-potential wiring 31 connected to the first transformer 21A applies mutatis mutandis to the description of the structure of the other first low-potential wirings 31, and will be omitted.

[0074] The first low-potential wiring 31 includes a through wiring 71, a low-potential connection wiring 72, a lead-out wiring 73, a first connection plug electrode 74, a second connection plug electrode 75, one or more (multiple in this embodiment) pad plug electrodes 76, and one or more (multiple in this embodiment) substrate plug electrodes 77.

[0075] The through wiring 71, the low-potential connecting wiring 72, the lead-out wiring 73, the first connecting plug electrode 74, the second connecting plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 are preferably formed from the same conductive material as the low-potential coil 22, etc. In other words, the through wiring 71, the low-potential connecting wiring 72, the lead-out wiring 73, the first connecting plug electrode 74, the second connecting plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0076] The through wiring 71 penetrates the multiple interlayer insulating layers 57 in the insulating layer 51 and extends in a columnar shape along the normal direction Z. In this embodiment, the through wiring 71 is formed in the region of the insulating layer 51 between the lowermost insulating layer 55 and the uppermost insulating layer 56. The through wiring 71 has an upper end on the uppermost insulating layer 56 side and a lower end on the lowermost insulating layer 55 side. The upper end of the through wiring 71 is formed in the same interlayer insulating layer 57 as the high-potential coil 23 and is covered by the uppermost insulating layer 56. The lower end of the through wiring 71 is formed in the same interlayer insulating layer 57 as the low-potential coil 22.

[0077] In this embodiment, the through wiring 71 includes a first electrode layer 78, a second electrode layer 79, and a plurality of wiring plug electrodes 80. In the through wiring 71, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 are each formed from the same conductive material as the low-potential coil 22, etc. In other words, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 each include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0078] The first electrode layer 78 forms the upper end of the through wiring 71. The second electrode layer 79 forms the lower end of the through wiring 71. The first electrode layer 78 is formed in an island shape and faces the low potential terminal 11 (first low potential terminal 11A) in the normal direction Z. The second electrode layer 79 is formed in an island shape and faces the first electrode layer 78 in the normal direction Z.

[0079] The plurality of wiring plug electrodes 80 are embedded in the plurality of interlayer insulating layers 57 located in the region between the first electrode layer 78 and the second electrode layer 79. The plurality of wiring plug electrodes 80 are stacked from the lowermost insulating layer 55 toward the uppermost insulating layer 56 so as to be electrically connected to one another, and electrically connect the first electrode layer 78 and the second electrode layer 79. The plurality of wiring plug electrodes 80 each have a planar area that is less than the planar area of ​​the first electrode layer 78 and the planar area of ​​the second electrode layer 79.

[0080] The number of stacked wiring plug electrodes 80 corresponds to the number of stacked interlayer insulating layers 57. In this embodiment, six wiring plug electrodes 80 are embedded in each interlayer insulating layer 57, but the number of wiring plug electrodes 80 embedded in each interlayer insulating layer 57 is arbitrary. Of course, one or more wiring plug electrodes 80 may be formed penetrating the interlayer insulating layers 57.

[0081] The low-potential connecting wiring 72 is formed in the first inner region 66 of the first transformer 21A (low-potential coil 22) in the same interlayer insulating layer 57 as the low-potential coil 22. The low-potential connecting wiring 72 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. The low-potential connecting wiring 72 preferably has a planar area that exceeds the planar area of ​​the wiring plug electrode 80. The low-potential connecting wiring 72 is electrically connected to the first inner end 24 of the low-potential coil 22.

[0082] The lead-out wiring 73 is formed in the interlayer insulating layer 57 in a region between the semiconductor chip 41 and the through wiring 71. In this embodiment, the lead-out wiring 73 is formed in the first interlayer insulating layer 57 counting from the bottom insulating layer 55. The lead-out wiring 73 includes a first end on one side, a second end on the other side, and a wiring portion connecting the first end and the second end. The first end of the lead-out wiring 73 is located in the region between the semiconductor chip 41 and the lower end of the through wiring 71. The second end of the lead-out wiring 73 is located in the region between the semiconductor chip 41 and the low-potential connecting wiring 72. The wiring portion extends along the first main surface 42 of the semiconductor chip 41 and extends in a strip shape in the region between the first end and the second end.

[0083] The first connection plug electrode 74 is formed in the interlayer insulating layer 57 in a region between the through wiring 71 and the lead-out wiring 73, and is electrically connected to first ends of the through wiring 71 and the lead-out wiring 73. The second connection plug electrode 75 is formed in the interlayer insulating layer 57 in a region between the low potential connection wiring 72 and the lead-out wiring 73, and is electrically connected to second ends of the low potential connection wiring 72 and the lead-out wiring 73.

[0084] The plurality of pad plug electrodes 76 are formed in the uppermost insulating layer 56 in a region between the low potential terminal 11 (first low potential terminal 11A) and the through wiring 71, and are electrically connected to the upper ends of the low potential terminal 11 and the through wiring 71, respectively. The plurality of substrate plug electrodes 77 are formed in the lowermost insulating layer 55 in a region between the semiconductor chip 41 and the lead-out wiring 73. In this embodiment, the substrate plug electrodes 77 are formed in a region between the semiconductor chip 41 and the first ends of the lead-out wiring 73, and are electrically connected to the semiconductor chip 41 and the first ends of the lead-out wiring 73, respectively.

[0085] 6 and 7 , the plurality of first high-potential wirings 33 are electrically connected to the corresponding high-potential terminals 12A to 12D and the second inner ends 27 of the corresponding transformers 21A to 21D (high-potential coils 23). The plurality of first high-potential wirings 33 each have a similar structure. The following description will be given taking the structure of the first high-potential wiring 33 connected to the first high-potential terminal 12A and the first transformer 21A as an example. The description of the structure of the first high-potential wiring 33 connected to the first transformer 21A applies mutatis mutandis to the structure of the other first high-potential wirings 33, and will not be repeated here.

[0086] The first high-potential wiring 33 includes a high-potential connection wiring 81 and one or more (in this embodiment, multiple) pad plug electrodes 82. The high-potential connection wiring 81 and the pad plug electrode 82 are preferably formed from the same conductive material as the low-potential coil 22, etc. In other words, the high-potential connection wiring 81 and the pad plug electrode 82 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0087] The high-potential connecting wiring 81 is formed in the second inner region 67 of the high-potential coil 23 within the same interlayer insulating layer 57 as the high-potential coil 23. The high-potential connecting wiring 81 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. The high-potential connecting wiring 81 is electrically connected to the second inner end 27 of the high-potential coil 23. The high-potential connecting wiring 81 is formed spaced apart from the low-potential connecting wiring 72 in a plan view and does not face the low-potential connecting wiring 72 in the normal direction Z. This increases the insulation distance between the low-potential connecting wiring 72 and the high-potential connecting wiring 81, thereby increasing the dielectric strength voltage of the insulating layer 51.

[0088] The plurality of pad plug electrodes 82 are formed in the uppermost insulating layer 56 in a region between the high potential terminal 12 (first high potential terminal 12A) and the high potential connecting wiring 81, and are electrically connected to the high potential terminal 12 and the high potential connecting wiring 81. Each of the plurality of pad plug electrodes 82 has a planar area that is smaller than the planar area of ​​the high potential connecting wiring 81 in a plan view.

[0089] 7, the distance D1 between the low potential terminal 11 and the high potential terminal 12 preferably exceeds the distance D2 between the low potential coil 22 and the high potential coil 23 (D2<D1). The distance D1 preferably exceeds the total thickness DT of the multiple interlayer insulating layers 57 (DT<D1). The ratio D2 / D1 of the distance D2 to the distance D1 may be 0.01 or more and 0.1 or less. The distance D1 is preferably 100 μm or more and 500 μm or less. The distance D2 may be 1 μm or more and 50 μm or less. The distance D2 is preferably 5 μm or more and 25 μm or less. The values ​​of the distance D1 and the distance D2 are arbitrary and are adjusted appropriately depending on the dielectric strength voltage to be achieved.

[0090] 6 and 7, semiconductor device 5 includes dummy patterns 85 embedded in insulating layer 51 so as to be located around transformers 21A to 21D in a plan view.

[0091] The dummy pattern 85 is formed in a pattern (discontinuous pattern) different from the high-potential coil 23 and the low-potential coil 22, and is independent of the transformers 21A to 21D. In other words, the dummy pattern 85 does not function as a part of the transformers 21A to 21D. The dummy pattern 85 is formed as a shielding conductor layer that shields the electric field between the low-potential coil 22 and the high-potential coil 23 in the transformers 21A to 21D and suppresses electric field concentration on the high-potential coil 23. In this form, the dummy pattern 85 is routed with a line density per unit area equal to that of the high-potential coil 23. Having the line density of the dummy pattern 85 equal to that of the high-potential coil 23 means that the line density of the dummy pattern 85 falls within a range of ±20% of the line density of the high-potential coil 23.

[0092] The depth position of the dummy pattern 85 within the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed. The dummy pattern 85 is preferably formed in a region closer to the high-potential coil 23 than to the low-potential coil 22 in the normal direction Z. Note that the dummy pattern 85 being closer to the high-potential coil 23 in the normal direction Z means that the distance between the dummy pattern 85 and the high-potential coil 23 in the normal direction Z is less than the distance between the dummy pattern 85 and the low-potential coil 22.

[0093] In this case, electric field concentration on the high-potential coil 23 can be appropriately suppressed. The smaller the distance between the dummy pattern 85 and the high-potential coil 23 in the normal direction Z, the more electric field concentration on the high-potential coil 23 can be suppressed. The dummy pattern 85 is preferably formed in the same interlayer insulating layer 57 as the high-potential coil 23. In this case, electric field concentration on the high-potential coil 23 can be further appropriately suppressed. The dummy pattern 85 includes multiple dummy patterns with different electrical states. The dummy pattern 85 may include a high-potential dummy pattern.

[0094] The depth position of the high-potential dummy pattern 86 within the insulating layer 51 is arbitrary and is adjusted according to the electric field strength to be relaxed. The high-potential dummy pattern 86 is preferably formed in a region closer to the high-potential coil 23 than to the low-potential coil 22 in the normal direction Z. The high-potential dummy pattern 86 being closer to the high-potential coil 23 in the normal direction Z means that the distance between the high-potential dummy pattern 86 and the high-potential coil 23 in the normal direction Z is less than the distance between the high-potential dummy pattern 86 and the low-potential coil 22.

[0095] The dummy patterns 85 include floating dummy patterns formed in an electrically floating state within the insulating layer 51 so as to be positioned around the transformers 21A to 21D.

[0096] In this embodiment, the floating dummy pattern is routed in a dense line shape so as to partially cover and partially expose the area around the high-potential coil 23 in a plan view. The floating dummy pattern may be formed to have ends or to have no ends.

[0097] The depth position of the floating dummy pattern inside the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed.

[0098] The number of floating lines is arbitrary and can be adjusted depending on the electric field to be relaxed. The floating dummy pattern may be made up of a plurality of floating lines.

[0099] 7, the semiconductor device 5 includes a second functional device 60 formed on the first main surface 42 of the semiconductor chip 41 in a device region 62. The second functional device 60 is formed using a surface layer portion of the first main surface 42 of the semiconductor chip 41 and / or a region above the first main surface 42 of the semiconductor chip 41, and is covered with an insulating layer 51 (lowermost insulating layer 55). In FIG. 7, the second functional device 60 is simply shown by a dashed line drawn on the surface layer portion of the first main surface 42.

[0100] The second functional device 60 is electrically connected to the low-potential terminal 11 via a low-potential wiring, and is electrically connected to the high-potential terminal 12 via a high-potential wiring. The low-potential wiring has a structure similar to that of the first low-potential wiring 31 (second low-potential wiring 32), except that it is routed within the insulating layer 51 so as to be connected to the second functional device 60. The high-potential wiring has a structure similar to that of the first high-potential wiring 33 (second high-potential wiring 34), except that it is routed within the insulating layer 51 so as to be connected to the second functional device 60. A detailed description of the low-potential wiring and high-potential wiring related to the second functional device 60 will be omitted.

[0101] The second functional device 60 may include at least one of a passive device, a semiconductor rectifying device, and a semiconductor switching device. The second functional device 60 may include a circuit network in which any two or more of the passive devices, the semiconductor rectifying device, and the semiconductor switching device are selectively combined. The circuit network may form part or all of an integrated circuit.

[0102] The passive device may include a semiconductor passive device. The passive device may include either or both of a resistor and a capacitor. The semiconductor rectifying device may include at least one of a pn junction diode, a PIN diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The semiconductor switching device may include at least one of a BJT (Bipolar Junction Transistor), a MISFET (Metal Insulator Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Junction Transistor), and a JFET (Junction Field Effect Transistor).

[0103] 5 to 7 , the semiconductor device 5 further includes a seal conductor 61 embedded in the insulating layer 51. The seal conductor 61 is embedded in the insulating layer 51 in a wall shape spaced apart from the insulating side walls 53A to 53D in a plan view, and divides the insulating layer 51 into a device region 62 and an outer region 63. The seal conductor 61 prevents moisture and cracks from entering the device region 62 from the outer region 63.

[0104] The device region 62 is a region that includes the first functional device 45 (plurality of transformers 21), the second functional device 60, the plurality of low potential terminals 11, the plurality of high potential terminals 12, the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85. The outer region 63 is a region outside the device region 62.

[0105] The seal conductor 61 is electrically isolated from the device region 62. Specifically, the seal conductor 61 is electrically isolated from the first functional device 45 (plurality of transformers 21), the second functional device 60, the plurality of low potential terminals 11, the plurality of high potential terminals 12, the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85. More specifically, the seal conductor 61 is fixed in an electrically floating state. The seal conductor 61 does not form a current path leading to the device region 62.

[0106] The seal conductor 61 is formed in a strip shape along the insulating side walls 53 to 53D in plan view. In this embodiment, the seal conductor 61 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in plan view. As a result, the seal conductor 61 defines a quadrangular (specifically, rectangular) device region 62 in plan view. The seal conductor 61 also defines a quadrangular (specifically, rectangular) outer region 63 that surrounds the device region 62 in plan view.

[0107] Specifically, the seal conductor 61 has an upper end on the insulating principal surface 52 side, a lower end on the semiconductor chip 41 side, and a wall extending in a wall shape between the upper and lower ends. In this embodiment, the upper end of the seal conductor 61 is formed at a distance from the insulating principal surface 52 toward the semiconductor chip 41 and is located within the insulating layer 51. In this embodiment, the upper end of the seal conductor 61 is covered by the uppermost insulating layer 56. The upper end of the seal conductor 61 may be covered by one or more interlayer insulating layers 57. The upper end of the seal conductor 61 may be exposed from the uppermost insulating layer 56. The lower end of the seal conductor 61 is formed at a distance from the semiconductor chip 41 toward the upper end.

[0108] Thus, in this embodiment, the seal conductor 61 is embedded in the insulating layer 51 so as to be located on the semiconductor chip 41 side with respect to the plurality of low-potential terminals 11 and the plurality of high-potential terminals 12. Furthermore, within the insulating layer 51, the seal conductor 61 faces the first functional device 45 (plurality of transformers 21), the first low-potential wiring 31, the second low-potential wiring 32, the first high-potential wiring 33, the second high-potential wiring 34, and the dummy pattern 85 in a direction parallel to the insulating principal surface 52. Within the insulating layer 51, the seal conductor 61 may face a part of the second functional device 60 in a direction parallel to the insulating principal surface 52.

[0109] The seal conductor 61 includes a plurality of seal plug conductors 64 and one or more (a plurality in this embodiment) seal via conductors 65. The number of seal via conductors 65 is arbitrary. The uppermost seal plug conductor 64 among the plurality of seal plug conductors 64 forms the upper end of the seal conductor 61. The plurality of seal via conductors 65 each form the lower end of the seal conductor 61. The seal plug conductor 64 and the seal via conductor 65 are preferably formed from the same conductive material as the low-potential coil 22. In other words, the seal plug conductor 64 and the seal via conductor 65 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0110] The multiple seal plug conductors 64 are embedded in the multiple interlayer insulating layers 57, respectively, and are each formed in a quadrangular ring shape (specifically, a rectangular ring shape) surrounding the device region 62 in a plan view. The multiple seal plug conductors 64 are stacked from the lowermost insulating layer 55 to the uppermost insulating layer 56 so as to be connected to each other. The number of stacked multiple seal plug conductors 64 matches the number of stacked multiple interlayer insulating layers 57. Of course, one or more seal plug conductors 64 may be formed penetrating the multiple interlayer insulating layers 57.

[0111] As long as a single annular seal conductor 61 is formed by an assembly of a plurality of seal plug conductors 64, it is not necessary for all of the plurality of seal plug conductors 64 to be formed in an annular shape. For example, at least one of the plurality of seal plug conductors 64 may be formed in an end-shaped form. Also, at least one of the plurality of seal plug conductors 64 may be divided into a plurality of strip-shaped portions with ends. However, in consideration of the risk of moisture and cracks penetrating into the device region 62, it is preferable that the plurality of seal plug conductors 64 be formed in an endless (annular) form.

[0112] The plurality of seal via conductors 65 are respectively formed in the region between the semiconductor chip 41 and the seal plug conductor 64 in the lowermost insulating layer 55. The plurality of seal via conductors 65 are formed spaced apart from the semiconductor chip 41 and connected to the seal plug conductor 64. The plurality of seal via conductors 65 have a planar area smaller than the planar area of ​​the seal plug conductor 64. When a single seal via conductor 65 is formed, the single seal via conductor 65 may have a planar area equal to or larger than the planar area of ​​the seal plug conductor 64.

[0113] The width of the shield conductor 61 may be 0.1 μm or more and 10 μm or less. The width of the shield conductor 61 is preferably 1 μm or more and 5 μm or less. The width of the shield conductor 61 is defined by the width in a direction perpendicular to the direction in which the shield conductor 61 extends.

[0114] 7 and 8 , the semiconductor device 5 further includes an isolation structure 130 interposed between the semiconductor chip 41 and the seal conductor 61 to electrically isolate the seal conductor 61 from the semiconductor chip 41. The isolation structure 130 preferably includes an insulator. In this embodiment, the isolation structure 130 is made of a field insulating film 131 formed on the first main surface 42 of the semiconductor chip 41.

[0115] The field insulating film 131 includes at least one of an oxide film (silicon oxide film) and a nitride film (silicon nitride film). The field insulating film 131 is preferably made of a LOCOS (local oxidation of silicon) film, which is an example of an oxide film formed by oxidizing the first main surface 42 of the semiconductor chip 41. The thickness of the field insulating film 131 is arbitrary as long as it can insulate the semiconductor chip 41 and the seal conductor 61. The thickness of the field insulating film 131 may be 0.1 μm or more and 5 μm or less.

[0116] The isolation structure 130 is formed on the first main surface 42 of the semiconductor chip 41 and extends in a band shape along the seal conductor 61 in a plan view. In this embodiment, the isolation structure 130 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in a plan view. The isolation structure 130 has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 may form an anchor portion where the lower end portion (seal via conductor 65) of the seal conductor 61 is embedded toward the semiconductor chip 41. Of course, the connection portion 132 may be formed flush with the main surface of the isolation structure 130.

[0117] The isolation structure 130 includes an inner end 130A on the device region 62 side, an outer end 130B on the outer region 63 side, and a main body 130C between the inner end 130A and the outer end 130B. The inner end 130A defines the region in which the second functional device 60 is formed (i.e., the device region 62) in a plan view. The inner end 130A may be formed integrally with an insulating film (not shown) formed on the first main surface 42 of the semiconductor chip 41.

[0118] The outer end 130B is exposed from the chip sidewalls 44A to 44D of the semiconductor chip 41 and is continuous with the chip sidewalls 44A to 44D of the semiconductor chip 41. More specifically, the outer end 130B is formed flush with the chip sidewalls 44A to 44D of the semiconductor chip 41. The outer end 130B forms a flush ground surface between the chip sidewalls 44A to 44D of the semiconductor chip 41 and the insulating sidewalls 53A to 53D of the insulating layer 51. Of course, in other embodiments, the outer end 130B may be formed within the first main surface 42 at a distance from the chip sidewalls 44A to 44D.

[0119] The main body 130C has a flat surface extending substantially parallel to the first main surface 42 of the semiconductor chip 41. The main body 130C has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 is formed in a portion of the main body 130C spaced apart from the inner end portion 130A and the outer end portion 130B. The isolation structure 130 can take various forms in addition to the field insulating film 131.

[0120] 7 , the semiconductor device 5 further includes an inorganic insulating layer 140 formed on the insulating principal surface 52 of the insulating layer 51 so as to cover the seal conductor 61. The inorganic insulating layer 140 may also be referred to as a passivation layer. The inorganic insulating layer 140 protects the insulating layer 51 and the semiconductor chip 41 from above the insulating principal surface 52.

[0121] In this embodiment, the inorganic insulating layer 140 has a laminated structure including a first inorganic insulating layer 141 and a second inorganic insulating layer 142. The first inorganic insulating layer 141 may contain silicon oxide. The first inorganic insulating layer 141 preferably contains USG (undoped silicate glass), which is silicon oxide without added impurities. The thickness of the first inorganic insulating layer 141 may be 50 nm or more and 5000 nm or less. The second inorganic insulating layer 142 may contain silicon nitride. The thickness of the second inorganic insulating layer 142 may be 500 nm or more and 5000 nm or less. Increasing the total thickness of the inorganic insulating layer 140 can increase the dielectric strength voltage on the high-potential coil 23.

[0122] When the first inorganic insulating layer 141 is made of USG and the second inorganic insulating layer 142 is made of silicon nitride, the breakdown voltage (V / cm) of USG exceeds the breakdown voltage (V / cm) of silicon nitride. Therefore, when the inorganic insulating layer 140 is thickened, it is preferable that the first inorganic insulating layer 141 be thicker than the second inorganic insulating layer 142.

[0123] The first inorganic insulating layer 141 may contain at least one of BPSG (boron-doped phosphor silicate glass) and PSG (phosphorus silicate glass), which are examples of silicon oxide. However, in this case, since impurities (boron or phosphorus) are contained in the silicon oxide, it is particularly preferable to form the first inorganic insulating layer 141 made of USG in order to increase the dielectric strength voltage on the high-potential coil 23. Of course, the inorganic insulating layer 140 may have a single-layer structure made of either the first inorganic insulating layer 141 or the second inorganic insulating layer 142.

[0124] The inorganic insulating layer 140 covers the entire seal conductor 61, and has a plurality of low potential pad openings 143 and a plurality of high potential pad openings 144 formed in an area outside the seal conductor 61. The plurality of low potential pad openings 143 expose the plurality of low potential terminals 11, respectively. The plurality of high potential pad openings 144 expose the plurality of high potential terminals 12, respectively. The inorganic insulating layer 140 may have an overlapping portion that rides up onto the peripheral edge of the low potential terminal 11. The inorganic insulating layer 140 may have an overlapping portion that rides up onto the peripheral edge of the high potential terminal 12.

[0125] The semiconductor device 5 further includes an organic insulating layer 145 formed on the inorganic insulating layer 140. The organic insulating layer 145 may include a photosensitive resin. The organic insulating layer 145 may include at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the organic insulating layer 145 includes polyimide. The thickness of the organic insulating layer 145 may be 1 μm or more and 50 μm or less.

[0126] The thickness of the organic insulating layer 145 preferably exceeds the total thickness of the inorganic insulating layer 140. Furthermore, the total thickness of the inorganic insulating layer 140 and the organic insulating layer 145 is preferably equal to or greater than the distance D2 between the low-potential coil 22 and the high-potential coil 23. In this case, the total thickness of the inorganic insulating layer 140 is preferably 2 μm or more and 10 μm or less. Furthermore, the thickness of the organic insulating layer 145 is preferably 5 μm or more and 50 μm or less. These structures can prevent the inorganic insulating layer 140 and the organic insulating layer 145 from becoming thicker, and at the same time, the laminated film of the inorganic insulating layer 140 and the organic insulating layer 145 can appropriately increase the dielectric strength voltage on the high-potential coil 23.

[0127] The organic insulating layer 145 includes a first portion 146 covering the low-potential side region and a second portion 147 covering the high-potential side region. The first portion 146 covers the seal conductor 61 with the inorganic insulating layer 140 sandwiched therebetween. The first portion 146 has a plurality of low-potential terminal openings 148 that expose a plurality of low-potential terminals 11 (low-potential pad openings 143) in a region outside the seal conductor 61. The first portion 146 may have an overlapping portion that rises onto the periphery (overlapping portion) of the low-potential pad opening 143.

[0128] The second portion 147 is formed at a distance from the first portion 146, exposing the inorganic insulating layer 140 between the second portion 147 and the first portion 146. The second portion 147 has a plurality of high-potential terminal openings 149 that expose the plurality of high-potential terminals 12 (high-potential pad openings 144), respectively. The second portion 147 may have an overlapping portion that rises onto the periphery (overlapping portion) of the high-potential pad opening 144.

[0129] The second portion 147 collectively covers the transformers 21A to 21D and the dummy pattern 85. Specifically, the second portion 147 collectively covers the plurality of high-potential coils 23, the plurality of high-potential terminals 12, the first high-potential dummy pattern 87, the second high-potential dummy pattern 88, and the floating dummy pattern 121.

[0130] The embodiments of the present disclosure can be implemented in other forms. In the above-described embodiment, an example in which the first functional device 45 and the second functional device 60 are formed has been described. However, a form in which only the second functional device 60 is provided without the first functional device 45 may also be adopted. In this case, the dummy pattern 85 may be removed. According to this structure, the second functional device 60 can achieve the same effects as those described in the first embodiment (excluding the effects related to the dummy pattern 85).

[0131] That is, when a voltage is applied to the second functional device 60 via the low potential terminal 11 and the high potential terminal 12, it is possible to suppress undesired conduction between the high potential terminal 12 and the seal conductor 61. Furthermore, when a voltage is applied to the second functional device 60 via the low potential terminal 11 and the high potential terminal 12, it is possible to suppress undesired conduction between the low potential terminal 11 and the seal conductor 61.

[0132] In the above embodiment, an example has been described in which the second functional device 60 is formed. However, the second functional device 60 is not necessarily required and may be removed.

[0133] In the above embodiment, the dummy pattern 85 is formed. However, the dummy pattern 85 is not necessarily required and may be removed.

[0134] In the above-described embodiment, an example has been described in which the first functional device 45 is a multi-channel type that includes a plurality of transformers 21. However, a first functional device 45 that is a single-channel type that includes a single transformer 21 may also be employed.

[0135] 9 is a plan view (top view) schematically showing an example of a transformer arrangement in a two-channel transformer chip 300 (corresponding to the aforementioned semiconductor device 5). The transformer chip 300 in this figure has a first transformer 301, a second transformer 302, a third transformer 303, a fourth transformer 304, a first guard ring 305, a second guard ring 306, pads a1 to a8, pads b1 to b8, pads c1 to c4, and pads d1 to d4.

[0136] In the transformer chip 300, pads a1 and b1 are connected to one end of a secondary coil L1s forming a first transformer 301, and pads c1 and d1 are connected to the other end of the secondary coil L1s. Pads a2 and b2 are connected to one end of a secondary coil L2s forming a second transformer 302, and pads c1 and d1 are connected to the other end of the secondary coil L2s.

[0137] Furthermore, pads a3 and b3 are connected to one end of a secondary coil L3s that forms the third transformer 303, and pads c2 and d2 are connected to the other end of the secondary coil L3s. Pads a4 and b4 are connected to one end of a secondary coil L4s that forms the fourth transformer 304, and pads c2 and d2 are connected to the other end of the secondary coil L4s.

[0138] Note that the primary coils forming the first transformer 301, the primary coils forming the second transformer 302, the primary coils forming the third transformer 303, and the primary coils forming the fourth transformer 304 are not shown in this figure. However, the primary coils basically have the same configuration as the secondary coils L1s to L4s, and are arranged directly below the secondary coils L1s to L4s, respectively, so as to face the secondary coils L1s to L4s.

[0139] That is, pads a5 and b5 are connected to one end of the primary coil forming the first transformer 301, and pads c3 and d3 are connected to the other end of the primary coil. Also, pads a6 and b6 are connected to one end of the primary coil forming the second transformer 302, and pads c3 and d3 are connected to the other end of the primary coil.

[0140] Pads a7 and b7 are connected to one end of the primary coil forming the third transformer 303, and pads c4 and d4 are connected to the other end of the primary coil. Pads a8 and b8 are connected to one end of the primary coil forming the fourth transformer 304, and pads c4 and d4 are connected to the other end of the primary coil.

[0141] However, the pads a5 to a8, pads b5 to b8, pads c3 and c4, and pads d3 and d4 are drawn out from the inside of the transformer chip 300 to the surface through vias (not shown).

[0142] Of the multiple pads, pads a1 to a8 correspond to first current supply pads, pads b1 to b8 correspond to first voltage measurement pads, pads c1 to c4 correspond to second current supply pads, and pads d1 to d4 correspond to second voltage measurement pads.

[0143] Therefore, with the transformer chip 300 of this configuration example, the series resistance component of each coil can be accurately measured during the defective product inspection. Therefore, it is possible to not only reject defective products in which a break has occurred in each coil, but also to appropriately reject defective products in which an abnormal resistance value has occurred in each coil (for example, a short circuit between coils), thereby making it possible to prevent defective products from being released onto the market.

[0144] For the transformer chip 300 that has passed the above-mentioned defective product inspection, the above-mentioned plurality of pads may be used as a means for connecting the primary chip and the secondary chip (for example, the above-mentioned controller chip 210 and driver chip 220).

[0145] Specifically, pads a1 and b1, pads a2 and b2, pads a3 and b3, and pads a4 and b4 may be connected to the signal input or output terminals of the secondary chip, respectively, and pads c1 and d1, and pads c2 and d2 may be connected to the common voltage application terminal (GND2) of the secondary chip, respectively.

[0146] On the other hand, pads a5 and b5, pads a6 and b6, pads a7 and b7, and pads a8 and b8 may be connected to the signal input or output terminals of the primary chip, respectively, and pads c3 and d3, and pads c4 and d4 may be connected to the common voltage application terminal (GND1) of the primary chip, respectively.

[0147] 9, the first transformer 301 to the fourth transformer 304 are arranged in a coupled arrangement according to the respective signal transmission directions. Referring to this figure, for example, the first transformer 301 and the second transformer 302, which transmit signals from the primary chip to the secondary chip, are formed into a first pair by a first guard ring 305. Furthermore, for example, the third transformer 303 and the fourth transformer 304, which transmit signals from the secondary chip to the primary chip, are formed into a second pair by a second guard ring 306.

[0148] The reason for such coupling is to ensure a withstand voltage between the primary coil and the secondary coil when the primary coil and the secondary coil that respectively form the first transformer 301 to the fourth transformer 304 are stacked in the vertical direction of the substrate of the transformer chip 300. However, the first guard ring 305 and the second guard ring 306 are not necessarily essential components.

[0149] The first guard ring 305 and the second guard ring 306 may be connected to a low impedance wiring such as a ground terminal via pads e1 and e2, respectively.

[0150] In the transformer chip 300, pads c1 and d1 are shared between the secondary coil L1s and secondary coil L2s. Pads c2 and d2 are shared between the secondary coil L3s and secondary coil L4s. Pads c3 and d3 are shared between the primary coil L1p and primary coil L2p. Pads c4 and d4 are shared between the corresponding primary coils. This configuration reduces the number of pads, making it possible to miniaturize the transformer chip 300.

[0151] 9, it is desirable that the primary coil and secondary coil forming each of the first transformer 301 to the fourth transformer 304 are wound so as to form a rectangular shape (or a track shape with rounded corners) in a plan view of the transformer chip 300. By using such a configuration, the area where the primary coil and the secondary coil overlap each other becomes larger, which makes it possible to improve the transmission efficiency of the transformer.

[0152] Of course, the transformer arrangement in this figure is merely an example, and the number, shape, and arrangement of the coils, as well as the arrangement of the pads, are arbitrary. Furthermore, the chip structure and transformer arrangement described so far can be applied to all semiconductor devices in which coils are integrated on a semiconductor chip.

[0153] <Signal Transmission Device (Detailed Configuration)> Fig. 10 is a diagram showing the detailed configuration of a signal transmission device. As shown in this diagram, a signal transmission device 400 of this configuration example can be mounted in electronic equipment A together with various discrete components (such as the switch element TR1 to be driven). The signal transmission device 400 is formed by sealing a first die 410, a second die 420, and a third die 430 in a single package.

[0154] Like the signal transmission device 200 (FIG. 1) described above, the signal transmission device 400 may be a semiconductor integrated circuit device (a so-called insulated gate driver IC) that generates an output pulse signal OUT in response to an input pulse signal IN to drive the switch element TR1 while insulating the primary circuit system 400p from the secondary circuit system 400s.

[0155] Furthermore, the signal transmission device 400 can be widely applied to general applications (such as motor drivers, DC / DC converters, AC / DC converters or inverters that handle high voltages) that require signal transmission between the primary circuit system 400p and the secondary circuit system 400s while isolating them from each other.

[0156] The first die 410 is provided in the primary circuit system 400p. The first die 410 corresponds to the controller chip 210 (=first chip) described above. Referring to this figure, the first die 410 includes logic 411, a transmitting circuit 412, a receiving circuit 413, a self-diagnosis circuit 414, and a memory circuit 415.

[0157] The logic 411 (corresponding to a signal processing circuit) performs bidirectional insulated communication with the second die 420 via a transmitting circuit 412 and a receiving circuit 413. The logic 411 also controls self-diagnosis of the first die 410 by a self-diagnosis circuit 414 and memory access (read or write) to the memory circuit 415.

[0158] The transmitting circuit 412 drives an insulating element (not shown) of the third die 430 in response to an instruction from the logic 411 to transmit a pulse signal to the second die 420 .

[0159] The receiving circuit 413 receives the pulse signal transmitted from the second die 420 via the third die 430 and transmits it to the logic 411 .

[0160] The self-diagnosis circuit 414 performs a self-diagnosis (so-called BIST [built-in self test]) to determine whether each component of the first die 410 is in a state where it can operate correctly. The self-diagnosis may include a comparator for detecting various abnormal conditions. For example, during the self-diagnosis, a pseudo abnormal signal may be injected into the comparator to be diagnosed, and it may be determined whether the abnormal condition is correctly detected.

[0161] The memory circuit 415 stores various data processed by the logic 411. The memory circuit 415 may include a non-volatile memory such as an OTPROM (one-time programmable read only memory) or an MTPROM (multiple-time PROM). The memory circuit 415 may also include a volatile memory such as a register.

[0162] The second die 420 is provided in the secondary circuit system 400s. The second die 420 corresponds to the driver chip 220 (=second chip) described above. Referring to this figure, the second die 420 includes logic 421, a transmitting circuit 422, a receiving circuit 423, a self-diagnosis circuit 424, and a memory circuit 425.

[0163] The logic 421 performs bidirectional insulated communication with the first die 410 via a transmitting circuit 422 and a receiving circuit 423. The logic 421 also controls self-diagnosis of the second die 420 by a self-diagnosis circuit 424 and memory access to a memory circuit 425.

[0164] The transmitting circuit 422 drives an insulating element (not shown) of the third die 430 in response to an instruction from the logic 421 to transmit a pulse signal to the first die 410 .

[0165] The receiving circuit 423 receives a pulse signal transmitted from the first die 410 through an insulating element (not shown) of the third die 430 and transmits it to the logic 421 .

[0166] The self-diagnosis circuit 424 performs a self-diagnosis (so-called BIST) to determine whether each component of the second die 420 is in a state where it can operate correctly. The self-diagnosis may include a comparator for detecting various abnormal conditions. For example, during the self-diagnosis, a pseudo-abnormal signal may be injected into the comparator to be diagnosed, and a determination may be made as to whether the abnormal condition is correctly detected.

[0167] The memory circuit 425 stores various data to be processed by the logic 421. The memory circuit 425 may include a nonvolatile memory such as an OTPROM or an MTPROM. The memory circuit 425 may also include a volatile memory such as a register.

[0168] The third die 430 is a semiconductor chip that integrates an isolation element (not shown) for bidirectional signal transmission while insulating the first die 410 and the second die 420. For example, the isolation element may be a transformer. That is, the third die 430 corresponds to the aforementioned transformer chip 230 (=third chip).

[0169] When a signal is transmitted from the first die 410 to the second die 420, a first signal transmission path is formed from the logic 411 through the transmitting circuit 412 and the receiving circuit 423 to the logic 421. When a signal is transmitted from the second die 420 to the first die 410, a second signal transmission path is formed from the logic 421 through the transmitting circuit 422 and the receiving circuit 413 to the logic 411.

[0170] Note that the signal transmission device 400 of this configuration example includes an independent third die 430 that mounts only an insulating element, separate from the first die 410 and the second die 420. With this configuration, the first die 410 and the second die 420 can both be formed using a general low- to medium-voltage withstand process (withstand voltage of several volts to several tens of volts), eliminating the need to use a dedicated high-voltage process (withstand voltage of several kV), and making it possible to reduce manufacturing costs.

[0171] Furthermore, both the first die 410 and the second die 420 can be manufactured using existing processes with proven results, and there is no need to conduct new reliability tests, which can contribute to shortening development time and reducing development costs.

[0172] The switch element TR1 may be, for example, an upper switch element and a lower switch element of a half-bridge output stage or a full-bridge output stage. The half-bridge output stage or the full-bridge output stage may be used as a load driving means such as a motor driver, or as a power conversion means such as an inverter. As shown in this figure, the switch element TR1 may be an IGBT. Alternatively, the switch element TR1 may be replaced with a MOSFET (metal oxide semiconductor field effect transistor) or the like.

[0173] 11 is a diagram showing an example of the configuration of an electronic device equipped with a signal transmission device 400. Electronic device A of this example configuration has an upper gate driver IC1H(u / v / w), a lower gate driver IC1L(u / v / w), upper power transistors 2H(u / v / w), lower power transistors 2L(u / v / w), an ECU [electronic control unit] 3, and a motor 4.

[0174] The upper gate driver IC1H(u / v / w) drives the upper power transistor 2H(u / v / w) by generating an upper gate drive signal in response to an upper gate control signal input from the ECU 3 while insulating the ECU 3 from the upper power transistor 2H(u / v / w).

[0175] The lower gate drivers IC1L(u / v / w) drive the lower power transistors 2L(u / v / w) by generating lower gate drive signals in response to lower gate control signals input from the ECU 3 while insulating the ECU 3 from the lower power transistors 2L(u / v / w).

[0176] The signal transmission device 400 described above can be suitably used as the upper gate driver IC1H(u / v / w) and the lower gate driver IC1L(u / v / w).

[0177] The upper power transistors 2H (u / v / w) serve as upper switches forming a three-phase (U-phase / V-phase / W-phase) half-bridge output stage, and are connected between the power system power supply end (= the application end of the load power supply voltage PVDD) and each phase input end of the motor 4.

[0178] The lower power transistors 2L (u / v / w) are connected between each phase input terminal of the motor 4 and the power system ground terminal as lower switches that form a three-phase (U phase / V phase / W phase) half-bridge output stage.

[0179] In this figure, an IGBT (insulated gate bipolar transistor) is used as each of the upper power transistor 2H (u / v / w) and the lower power transistor 2L (u / v / w), but it is also possible to use, for example, a MOSFET instead of the IGBT.

[0180] The ECU 3 drives the upper power transistors 2H (u / v / w) and the lower power transistors 2L (u / v / w) via the upper gate driver IC1H (u / v / w) and the lower gate driver IC1L (u / v / w), respectively, thereby controlling the rotational driving of the motor 4. The ECU 3 also has a function of monitoring the abnormality detection status and self-diagnosis results of each of the upper gate driver IC1H (u / v / w) and the lower gate driver IC1L (u / v / w).

[0181] The motor 4 is a three-phase motor that is rotationally driven in response to three-phase drive voltages U / V / W input from three-phase (U-phase / V-phase / W-phase) half-bridge output stages.

[0182] <PWM Mode and SPI Communication Mode> Fig. 12 is a diagram showing the operation mode switching control. More specifically, in this diagram, in the signal transmission device 400, isolation elements 431 to 434 integrated on the third die 430 are shared by both the PWM (pulse width modulation) mode and the SPI (serial peripheral interface) communication mode. The isolation elements 431 to 434 may be transformers.

[0183] In the PWM mode, the first die 410 generates a first rise signal INH and a first fall signal INL from an externally input pulse signal IN. For example, the first rise signal INH is pulse-driven in response to a rising edge of the input pulse signal IN. Meanwhile, the first fall signal INL is pulse-driven in response to a falling edge of the input pulse signal IN. The first rise signal INH and the first fall signal INL are transmitted from the first die 410 to the second die 420 via insulating elements 431 and 432, respectively.

[0184] The second die 420 generates an output pulse signal OUT from the first rise signal INH and the first fall signal INL to drive a switch element TR1 (not shown). The second die 420 also generates a second rise signal OSFBH and a second fall signal OSFBL in response to the on / off state of the switch element TR1. For example, the second rise signal OSFBH is pulse-driven in response to the on transition of the switch element TR1. Meanwhile, the second fall signal OSFBL is pulse-driven in response to the off transition of the switch element TR1. The second rise signal OSFBH and the second fall signal OSFBL are transmitted from the second die 420 to the first die 410 via insulating elements 433 and 434, respectively.

[0185] The first die 410 generates a switch state signal OSFB from the second rise signal OSFBH and the second fall signal OSFBL and outputs the generated signal to the outside. That is, the switch state signal OSFB is a pulse signal corresponding to the on / off state of the switch element TR1 driven by the output pulse signal OUT.

[0186] In addition, a microcomputer (e.g., an ECU) provided outside the signal transmission device 400 can monitor the switch state signal OSFB to check whether the switch element TR1 is turned on / off as intended in response to the input pulse signal IN.

[0187] As described above, in the PWM mode, the input pulse signal IN is externally input and the output pulse signal OUT is externally output. Also, in the PWM mode, a switch state signal OSFB corresponding to the on / off state of the switch element TR1 driven by the output pulse signal OUT is externally output. Note that in the PWM mode, the first rise signal INH, the first fall signal INL, the second rise signal OSFBH, and the second fall signal OSFBL are transmitted bidirectionally between the first die 410 and the second die 420 via the third die 430. The PWM mode can be understood as, for example, a first operation mode used during normal driving of the switch element TR1.

[0188] The first die 410 also has a function of serial communication with the microcomputer. For example, the first die 410 transmits and receives a chip select signal CSB, an input data signal MOSI, an output data signal MISO, and a clock signal SCLK in accordance with the SPI protocol.

[0189] Therefore, in the SPI communication mode, the first data signal DATA12, the first clock signal CLK12, the second data signal DATA21, and the second clock signal CLK21 are transmitted bidirectionally between the first die 410 and the second die 420 via the third die 430. The SPI communication mode can be understood as, for example, a second operation mode used when setting the drive parameters of the switch element TR1.

[0190] The PWM mode and the SPI communication mode are switched exclusively between each other. That is, the PWM mode and the SPI communication mode are not used simultaneously. Therefore, in the signal transmission device 400, the isolation elements 431 to 434 integrated on the third die 430 are shared by both the PWM mode and the SPI communication mode.

[0191] Referring to this figure, the isolation element 431 is used as a transmission means for the first rise signal INH and the first data signal DATA12. The isolation element 432 is used as a transmission means for the first fall signal INL and the first clock signal CLK12. The isolation element 433 is used as a transmission means for the second rise signal OSFBH and the second data signal DATA21. The isolation element 434 is used as a transmission means for the second fall signal OSFBL and the second clock signal CLK21.

[0192] In this way, if the isolation elements 431 to 434 are shared between both the PWM mode and the SPI communication mode, it is possible to reduce the number of isolation elements integrated on the third die 430. For example, if an isolation element is provided in a one-to-one correspondence as a transmission means for each of the eight signals (INH, INL, OSFBH, OSFBL, DATA12, CLK12, DATA21, and CLK21), eight isolation elements are required. In contrast, with the configuration shown in the figure, four isolation elements 431 to 434 are sufficient.

[0193] The signal transmission device 400 may be in the PWM mode when the chip select signal CSB, which is externally input to select the communication target of the microcomputer, is at a high level (=the logic level when the chip is not selected).

[0194] <Signal Transmission Device (First Embodiment)> Fig. 13 is a diagram showing a first embodiment of a signal transmission device 400 (corresponding to a comparative example to be compared with the second embodiment described later). The signal transmission device 400 of this embodiment includes a first die 410, a second die 420, and a third die 430, similar to the first die 410 shown in Fig. 10 above. The second die 420 also includes a self-diagnosis circuit 424 and a memory circuit 425.

[0195] The second die 420 generates a self-test completion signal BIST_END, a memory access signal MEM_ACCS, and a memory fault signal MEM_FLT.

[0196] The self-diagnosis completion signal BIST_END is a signal indicating whether or not the self-diagnosis has been completed by the self-diagnosis circuit 424. The above self-diagnosis is performed only once when the signal transmission device 400 is started up.

[0197] The memory access signal MEM_ACCS is a signal indicating whether or not a memory access is being executed to the memory circuit 425. The memory access can be executed as many times as desired by the user.

[0198] The memory abnormality signal MEM_FLT is a signal indicating whether or not there is an abnormality in the memory access to the memory circuit 425. Whether or not the memory access is abnormal may be determined every time a memory access is performed.

[0199] The self-diagnosis completion signal BIST_END, the memory access signal MEM_ACCS, and the memory abnormality signal MEM_FLT are transmitted from the second die 420 to the first die 410 via the third die 430. The self-diagnosis completion signal BIST_END, the memory access signal MEM_ACCS, and the memory abnormality signal MEM_FLT may also be output from the first die 410 to an external device such as a microcomputer (not shown).

[0200] If an isolation element is provided as a one-to-one connection for each of the three signals (BIST_END, MEM_ACCS, and MEM_FLT), three isolation elements are required, which may result in an increase in the size of the third die 430 and, ultimately, an increase in the cost of the signal transmission device 400.

[0201] In the following, in view of the above considerations, a second embodiment is proposed that can reduce the number of insulating elements integrated on the third die 430.

[0202] 14 is a diagram showing a second embodiment (overview) of the signal transmission device 400. In the signal transmission device 400 of this embodiment, a single insulating element 435 is shared as a means for transmitting the self-diagnosis completion signal BIST_END, the memory access signal MEM_ACCS, and the memory error signal MEM_FLT. With this configuration, the third die 430 can be made smaller, and the cost of the signal transmission device 400 can be reduced.

[0203] However, when a single isolation element 435 is shared as a means for transmitting the above three signals (BIST_END, MEM_ACCS, and MEM_FLT), the first die 410 must be able to determine which signal is transmitted through the single isolation element 435. A signal discrimination method in the first die 410 will be described in detail below.

[0204] 15 is a diagram showing a second embodiment (particularly the first main part) of the signal transmission device 400. In this figure, means for transmitting the self-diagnosis completion signal BIST_END and the memory access signal MEM_ACCS are depicted as the first main part of the signal transmission device 400. Note that the same reference numerals as in FIG. 10 are used to denote the same components as in FIG.

[0205] The transmission circuit 422 generates one pulse or a group of multiple pulses in the transmission pulse signal S1 at the timing when the self-diagnosis by the self-diagnosis circuit 424 and the memory access to the storage circuit 425 are completed.

[0206] The insulating element 435 transmits the transmission pulse signal S1 output from the transmission circuit 422 of the second die 420 to the reception circuit 413 of the first die 410 as a reception pulse signal S2.

[0207] The receiving circuit 413 performs waveform shaping and noise removal on the received pulse signal S2 input via the insulating element 435, and then outputs the signal to the logic 411 as a received pulse signal S3.

[0208] The logic 411 (corresponding to a signal processing circuit) identifies, from the received pulse signal S3, the completion timing of the self-diagnosis by the self-diagnosis circuit 424 and the completion timing of the memory access to the storage circuit 425. Referring to this figure, the logic 411 includes a latch 411a, an AND gate 411b, and a latch 411c.

[0209] The latch 411a (corresponding to the first latch) is reset when the power-on reset signal S5 is at a low level. In the reset state, the latch 411a fixes the self-diagnosis completion signal S4 to a low level without depending on the received pulse signal S3. The self-diagnosis completion signal S4 corresponds to the self-diagnosis completion signal BIST_END mentioned above.

[0210] The latch 411a is in a reset release state when the power-on reset signal S5 is at a high level. In the reset release state, the latch 411a latches the received pulse signal S3 and generates a self-diagnosis completion signal S4. For example, in the reset release state, the latch 411a raises the self-diagnosis completion signal S4 to a high level when one pulse or a group of multiple pulses is generated in the received pulse signal S3.

[0211] The power-on reset signal S5 is at a low level (=a logic level at the time of reset) until the signal transmission device 400 is started up. Moreover, the power-on reset signal S5 is at a high level (=a logic level at the time of reset release) when the signal transmission device 400 is started up.

[0212] In this way, the latch 411a fixes the self-diagnosis completion signal S4 at a low level until the signal transmission device 400 is started up. The latch 411a also sets the self-diagnosis completion signal S4 to a high level when one pulse or a group of multiple pulses is generated in the received pulse signal S3 for the first time after the signal transmission device 400 is started up. Therefore, the timing at which the self-diagnosis by the self-diagnosis circuit 424 has completed can be identified from the rising timing of the self-diagnosis completion signal S4.

[0213] The AND gate 411b generates a logical product signal S6 of the received pulse signal S3 and the self-diagnosis completion signal S4. The logical product signal S6 is low when at least one of the received pulse signal S3 and the self-diagnosis completion signal S4 is low. The logical product signal S6 is high when both the received pulse signal S3 and the self-diagnosis completion signal S4 are high. In other words, when the self-diagnosis completion signal S4 is low, the AND gate 411b sets the logical product signal S6 to low regardless of the received pulse signal S3. On the other hand, when the self-diagnosis completion signal S4 is high, the AND gate 411b simply passes the received pulse signal S3 through as the logical product signal S6.

[0214] The latch 411c (corresponding to the second latch) is reset when the memory access start signal S8 is at a high level. In the reset state, the latch 411c fixes the memory access signal S7 at a low level regardless of the logical product signal S6. The memory access signal S7 corresponds to the memory access signal MEM_ACCS mentioned above.

[0215] The latch 411c is in a reset release state when the memory access start signal S8 is at a low level. In the reset release state, the latch 411c latches the logical product signal S6 to generate the memory access signal S7. For example, in the reset release state, the latch 411c raises the memory access signal S7 to a high level when one pulse or a group of multiple pulses is generated in the logical product signal S6.

[0216] In addition, a high-level one-shot pulse is generated in the memory access start signal S8 at the start timing of memory access to the memory circuit 425. The start timing of memory access may be, for example, the timing when a read command or a write command for memory access to the memory circuit 425 is written to the memory circuit 415 (such as a register) of the first die 410.

[0217] In this way, the latch 411c sets the memory access signal S7 to low level when memory access to the storage circuit 425 is initiated. The latch 411c also sets the memory access signal S7 to high level when one pulse or a group of multiple pulses is generated in the received pulse signal S3 while the self-diagnosis completion signal S4 is high level. Therefore, the completion timing of memory access to the storage circuit 425 can be identified from the rising timing of the memory access signal S7.

[0218] 16 is a diagram showing a first example of sharing the isolation element 435 realized by the first main part (FIG. 15) described above. From top to bottom, the diagram depicts a power-on reset signal S5, a transmission pulse signal S1, a self-diagnosis completion signal S4, a memory access signal S7, and a memory access start signal S8. The transmission pulse signal S1 may also be understood as the reception pulse signal S2 or S3.

[0219] At time t11, when the signal transmission device 400 is started up, the power-on reset signal S5 rises from low level to high level.

[0220] At time t12, when the self-diagnosis by the self-diagnosis circuit 424 is completed, one pulse or a group of multiple pulses is generated in the transmission pulse signal S1. As the group of multiple pulses, for example, three pulses may be generated intensively at 10 MHz (pulse period T0 = 0.1 μs).

[0221] In this way, when one pulse or a group of multiple pulses is generated in the transmission pulse signal S1 (and therefore the reception pulse signal S3), the self-diagnosis completion signal S4 rises to a high level. Therefore, the timing at which the self-diagnosis by the self-diagnosis circuit 424 completes can be identified from the rising timing of the self-diagnosis completion signal S4. Note that when the self-diagnosis completion signal S4 rises to a high level, memory access to the storage circuit 425 becomes possible.

[0222] At time t13, when memory access to the storage circuit 425 is started, a high-level one-shot pulse is generated in the memory access start signal S8, which resets the memory access signal S7 to a low level.

[0223] At time t14, when memory access to the memory circuit 425 is completed, one pulse or a group of multiple pulses is generated in the transmission pulse signal S1. As the group of multiple pulses, three pulses may be generated intensively at 10 MHz (pulse period T0 = 0.1 μs), as described above.

[0224] At time t14, the self-diagnosis completion signal S4 is at a high level. Therefore, the received pulse signal S3 is output as is as the logical product signal S6. As a result, when a single pulse or a group of multiple pulses is generated in the transmitted pulse signal S1 (and thus the received pulse signal S3), the memory access signal S7 rises to a high level. Therefore, the timing of completion of memory access to the memory circuit 425 can be identified from the rising timing of the memory access signal S7. The low level period of the memory access signal S7 (from time t13 to t14) indicates that memory access to the memory circuit 425 is currently being performed.

[0225] Thereafter, the same signal transmission process as above is repeated every time a memory access is made to the storage circuit 425 (see times t15 and t16).

[0226] 17 is a diagram showing a second embodiment (particularly a second main part) of the signal transmission device 400. In this figure, a transmission means for the memory fault signal MEM_FLT is depicted as the second main part of the signal transmission device 400. Note that the same reference numerals as in FIG. 10 are used to denote the same components as in FIG.

[0227] When an abnormality in memory access to the memory circuit 425 is detected, the transmission circuit 422 continues to generate pulses in the transmission pulse signal S1 at a period of the first time T1. However, the pulse generation operation associated with the detection of the abnormality in memory access is disabled until the self-diagnosis circuits 414 and 424 have completed their respective self-diagnoses. The pulse generation operation is also disabled in the SPI communication mode. The first time T1 is preferably set to a value (e.g., T1 = 5 μs) that is sufficiently longer than the pulse period T0.

[0228] The insulating element 435 transmits the transmission pulse signal S1 output from the transmission circuit 422 of the second die 420 to the reception circuit 413 of the first die 410 as a reception pulse signal S2.

[0229] The receiving circuit 413 performs waveform shaping and noise removal on the received pulse signal S2 input via the insulating element 435, and then outputs the signal to the logic 411 as a received pulse signal S3.

[0230] The logic 411 (corresponding to a signal processing circuit) determines from the received pulse signal S3 whether there is an abnormality in memory access to the memory circuit 425. Referring to this figure, the logic 411 includes a timer 411d, an AND gate 411e, and a counter 411f.

[0231] The timer 411d sets the timer signal S9 to high level when a pulse is generated in the received pulse signal S3, and sets the timer signal S9 to low level when no pulse is generated in the received pulse signal S3 for a second time T2 (e.g., T2=8 μs) longer than the first time T1.

[0232] The AND gate 411e generates a logical product signal SB of the timer signal S9 and the UVLO (under voltage locked out) signal SA. The logical product signal SB is low when at least one of the timer signal S9 and the UVLO signal SA is low. The logical product signal SB is high when both the timer signal S9 and the UVLO signal SA are high. That is, when the UVLO signal SA is low (= the logical level when UVLO is detected), the AND gate 411e sets the logical product signal SB to low regardless of the timer signal S9. On the other hand, when the UVLO signal SA is high (= the logical level when UVLO is released), the AND gate 411e simply outputs the timer signal S9 as the logical product signal SB.

[0233] The counter 411f is in a reset-released state when the logical product signal SB (corresponding to the timer signal S9 in the UVLO-released state, the same applies below) is at a high level. In the reset-released state, the counter 411f counts the number of pulses of the internal clock signal CLK. The internal clock signal CLK may be, for example, a pulse signal of 10 MHz (pulse period 1 μs).

[0234] The counter 411f sets the memory abnormality signal SC to low level when the pulse count value has not reached a predetermined value (e.g., 10 pulses). On the other hand, the counter 411f sets the memory abnormality signal SC to high level (reference voltage VREF in this figure) when the pulse count value has reached the predetermined value (e.g., 10 pulses). The memory abnormality signal SC corresponds to the memory abnormality signal MEM_FLT mentioned above.

[0235] The counter 411f is reset when the logical product signal SB is at a low level. In the reset state, the counter 411f resets the memory error signal SC to a low level. In addition, the counter 411f in the reset state resets the pulse count value of the internal clock signal CLK to an initial value (zero).

[0236] In this way, the counter 411f sets the memory abnormality signal SC to a high level when the timer signal S9 is at a high level for a third time T3 (e.g., T3 = 10 μs) that is longer than the second time T2. The counter 411f also sets the memory abnormality signal SC to a low level when the logical product signal SB is at a low level. Therefore, the presence or absence of an abnormality in memory access to the memory circuit 425 can be identified from the logical level of the memory abnormality signal SC.

[0237] FIG. 18 is a diagram showing a second example of the use of the isolation element 435 realized by the second main part (FIG. 17). From top to bottom, the diagram depicts a transmission pulse signal S1, a timer signal S9, and a memory error signal SC. The transmission pulse signal S1 may also be understood as the reception pulse signal S2 or S3. The timer signal S9 may also be understood as the logical product signal SB in the UVLO release state (SA=H).

[0238] At time t21, one pulse or a group of multiple pulses is generated in the transmission pulse signal S1. As described above, this pulse or group of pulses can be generated at the completion timing of the self-diagnosis by the self-diagnosis circuit 424 and the memory access to the memory circuit 425 (see FIG. 16 ). It is also possible that one pulse or a group of multiple pulses is generated in the transmission pulse signal S1 due to noise superposition. When a pulse is generated in the transmission pulse signal S1 in this way, the timer signal S9 rises to a high level.

[0239] However, only three pulses are generated intensively at 10 MHz (pulse period T0=0.1 μs) at the completion timings of the self-diagnosis by the self-diagnosis circuit 424 and the memory access to the storage circuit 425. In other words, no subsequent pulses are generated after time t21.

[0240] Therefore, after a pulse or a group of pulses is generated in the transmission pulse signal S1 at time t21, if a second time T2 (e.g., T2 = 8 μs) passes without a subsequent pulse being generated, the timer signal S9 falls to low level at time t22, and the memory abnormality signal SC is maintained at low level.

[0241] Then, at time t23, an abnormality occurs in memory access to the memory circuit 425. In this case, from time t24 onwards, pulses are continuously generated in the transmission pulse signal S1 at a period of a first time T1 (for example, T1 = 5 μs). When pulses are generated in the transmission pulse signal S1 in this way, the timer signal S9 rises to a high level.

[0242] Then, when the timer signal S9 is maintained at a high level for a third time T3 (for example, T3=10 μs) from time t24, the memory abnormality signal SC rises to a high level at time t25. Therefore, the presence or absence of an abnormality in memory access to the memory circuit 425 can be identified from the logic level of the memory abnormality signal SC.

[0243] In this manner, according to the signal transmission device 400 of this embodiment, the single insulating element 435 is shared as a means for transmitting the aforementioned self-diagnosis completion signal BIST_END, the memory access signal MEM_ACCS, and the memory error signal MEM_FLT, respectively, which can reduce the size of the third die 430 and ultimately the cost of the signal transmission device 400.

[0244] For convenience, the present disclosure describes the first main part ( FIG. 15 ) and the second main part ( FIG. 17 ) of the signal transmission device 400 separately. However, the actual signal transmission device 400 (particularly the logic 411) may be implemented with a combination of the first main part ( FIG. 15 ) and the second main part ( FIG. 17 ).

[0245] <Application to Vehicles> Fig. 19 is a diagram showing the appearance of a vehicle B. Vehicle B of this configuration example is equipped with various electronic devices that operate with power supplied from a battery.

[0246] Vehicle B includes not only engine vehicles but also electric vehicles (battery electric vehicles (BEVs), hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs / PHVs), or xEVs such as fuel cell electric vehicles (FCEVs / FCVs)).

[0247] The signal transmission device 200 or 400 described above can be incorporated into any of the electronic devices installed in the vehicle B.

[0248] <Additional Notes> The following are additional notes regarding the present disclosure: According to the present disclosure, the number of insulating elements can be reduced.

[0249] [Supplementary Note 1] A signal transmission device (400) comprising: an isolation element (435) configured to transmit signals while isolating a primary circuit system (400p) from a secondary circuit system (400s); a self-diagnosis circuit (424) provided in the secondary circuit system (400s) and configured to perform a self-diagnosis of the secondary circuit system (400s); a memory circuit (425) provided in the secondary circuit system (400s) and configured to permit memory access after completion of the self-diagnosis; and a transmission circuit (422) provided in the secondary circuit system (400s) and configured to output a transmission pulse signal (S1) to the isolation element (435), wherein the transmission circuit (422) generates one pulse or a group of multiple pulses in the transmission pulse signal (S1) at the timings of completion of the self-diagnosis and the memory access, respectively, and continues to generate pulses in the transmission pulse signal (S1) at a period of a first time (T1) when an abnormality in the memory access is detected.

[0250] [Supplementary Note 2] The signal transmission device (400) according to Supplementary Note 1 further comprises a signal processing circuit (411) provided in the primary circuit system (400p) and configured to identify the completion timing of each of the self-diagnosis and the memory access and the presence or absence of an abnormality in the memory access from a received pulse signal (S3) input via the insulating element (435).

[0251] [Supplementary Note 3] The signal processing circuit (411) includes: a first latch (411a) configured to fix a self-diagnosis completion signal (S4) to a first logic level until the signal transmission device (400) is started up, and to set the self-diagnosis completion signal (S4) to a second logic level when one pulse or a group of multiple pulses is generated in the received pulse signal (S3) for the first time since the signal transmission device (400) is started up; and a second latch (411c) configured to set a memory access signal (S7) to a third logic level when the memory access is started, and to set the memory access signal (S7) to a fourth logic level when one pulse or a group of multiple pulses is generated in the received pulse signal (S3) while the self-diagnosis completion signal (S4) is at the second logic level.

[0252] [Supplementary Note 4] The signal processing circuit (411) includes: a timer (411d) configured to set a timer signal (S9) to a fifth logic level when a pulse is generated in the received pulse signal (S3), and to set the timer signal (S9) to a sixth logic level when no pulse is generated in the received pulse signal (S3) for a second time (T2) longer than the first time (T1); and a counter (411f) configured to set a memory abnormality signal (SC) to a seventh logic level when the timer signal (S9) is at the fifth logic level for a third time (T3) longer than the second time (T2), and to set the memory abnormality signal (SC) to an eighth logic level when the timer signal (S9) is at the sixth logic level.

[0253] [Supplementary Note 5] The signal transmission device (400) according to any one of Supplementary Notes 1 to 4, wherein the isolation element (435) is a transformer.

[0254] [Supplementary Note 6] The signal transmission device (400) according to any one of Supplementary Notes 1 to 5, further comprising a first isolation element (431) and a second isolation element (432) configured to transmit signals while isolating the primary circuit system (400p) and the secondary circuit system (400s), wherein in a first operation mode, a rising edge and a falling edge of an input pulse signal (IN) are transmitted from the primary circuit system (400p) to the secondary circuit system (400s) via the first isolation element (431) and the second isolation element (432), and in a second operation mode, a data signal (DATA12) and a clock signal (CLK12) are transmitted from the primary circuit system (400p) to the secondary circuit system (400s) via the first isolation element (431) and the second isolation element (432).

[0255] [Supplementary Note 7] The signal transmission device (400) according to any one of Supplementary Notes 1 to 6, comprising: a first die (410) on which circuit elements of the primary circuit system (400p) are integrated; a second die (420) on which circuit elements of the secondary circuit system (400s) are integrated; and a third die (430) on which the insulating element (435) is integrated.

[0256] [Supplementary Note 8] The signal transmission device (400) according to Supplementary Note 7, wherein the first die (410), the second die (420), and the third die (430) are sealed in a single package.

[0257] [Supplementary Note 9] An electronic device (A) comprising: a power transistor (2); and an insulated gate driver IC (1) configured to drive a gate of the power transistor (2), wherein the insulated gate driver IC (1) is the signal transmission device (400) according to any one of Supplementary Notes 1 to 8.

[0258] [Supplementary Note 10] A vehicle (B) including the electronic device (A) according to Supplementary Note 9.

[0259] <Others> In addition to the above-described embodiments, various technical features of the present disclosure can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects. Furthermore, the technical scope of the present disclosure is defined by the claims, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0260] 1H (u / v / w) Upper gate driver IC 1L (u / v / w) Lower gate driver IC 2H (u / v / w) Upper power transistor 2L (u / v / w) Lower power transistor 3 ECU 4 Motor 5 Semiconductor device 11, 11A to 11F Low potential terminal 12, 12A to 12F High potential terminal 21, 21A to 21D Transformer 22 Low potential coil (primary coil) 23 High potential coil (secondary coil) 24 First inner end 25 First outer end 26 First spiral portion 27 Second inner end 28 Second outer end 29 Second spiral portion 31 First low potential wiring 32 Second low potential wiring 33 First high potential wiring 34 Second high potential wiring 41 Semiconductor chip 42 First main surface 43 Second main surface 44A to 44D Chip side wall 45 First functional device 51 Insulating layer 52 Insulating principal surface 53A to 53D Insulating side wall 55 Bottom insulating layer 56 Top insulating layer 57 Interlayer insulating layer 58 First insulating layer 59 Second insulating layer 60 Second functional device 61 Seal conductor 62 Device region 63 Outer region 64 Seal plug conductor 65 Seal via conductor 66 First inner region 67 Second inner region 71 Through wiring 72 Low-potential connecting wiring 73 Lead-out wiring 74 First connecting plug electrode 75 Second connecting plug electrode 76 Pad plug electrode 77 Substrate plug electrode 78 First electrode layer 79 Second electrode layer 80 Wiring plug electrode 81 High-potential connecting wiring 82 Pad plug electrode 85 Dummy pattern 86 High-potential dummy pattern 87 First high-potential dummy pattern 88 Second high potential dummy pattern 89 First region 90 Second region 91 Third region 92 First connection portion 93 First pattern94 Second pattern 95 Third pattern 96 First outer peripheral line 97 Second outer peripheral line 98 First intermediate line 99 First connecting line 100 Slit 130 Isolation structure 140 Inorganic insulating layer 141 First inorganic insulating layer 142 Second inorganic insulating layer 143 Low potential pad opening 144 High potential pad opening 145 Organic insulating layer 146 First portion 147 Second portion 148 Low potential terminal opening 149 High potential terminal opening 200 Signal transmission device 200p Primary circuit system 200s Secondary circuit system 210 Controller chip (first chip) 211 Pulse transmitting circuit (pulse generator) 212, 213 Buffer 220 Driver chip (second chip) 221, 222 Buffer 223 Pulse receiving circuit (RS flip-flop) 224 Driver 230 Transformer chip (third chip) 230a First wiring layer (lower layer) 230b Second wiring layer (upper layer) 231, 232 Transformer 231p, 232p Primary coil 231s, 232s Secondary coil 300 Transformer chip 301 First transformer 302 Second transformer 303 Third transformer 304 Fourth transformer 305 First guard ring 306 Second guard ring 400 Signal transmission device 400p Primary circuit system 400s Secondary circuit system 410 First die 411 Logic (signal processing circuit) 411a Latch 411b AND gate 411c Latch 411d Timer 411e AND gate 411f Counter 412 Transmission circuit 413 Reception circuit 414 Self-diagnosis circuit 415 Memory circuit 420 Second die 421 Logic 422 Transmitting circuit 423 Receiving circuit 424 Self-diagnosis circuit 425 Memory circuit 430 Third die431 to 434 Isolation element (transformer) a1 to a8 Pads (corresponding to first current supply pads) b1 to b8 Pads (corresponding to first voltage measurement pads) c1 to c4 Pads (corresponding to second current supply pads) d1 to d4 Pads (corresponding to second voltage measurement pads) e1, e2 Pads A Electronic device B Vehicle L1p, L2p Primary coil L1s, L2s, L3s, L4s Secondary coil T21, T22, T23, T24, T25, T26 External terminal TR1 Switch element X First direction X21, X22, X23 Internal terminal Y Second direction Y21, Y22, Y23 Wiring Z Normal direction Z21, Z22, Z23 Via

Claims

1. A signal transmission device comprising: an isolation element configured to transmit signals while isolating a primary circuit system from a secondary circuit system; a self-diagnosis circuit provided in the secondary circuit system and configured to perform a self-diagnosis of the secondary circuit system; a memory circuit provided in the secondary circuit system and configured to permit memory access after completion of the self-diagnosis; and a transmission circuit provided in the secondary circuit system and configured to output a transmission pulse signal to the isolation element, wherein the transmission circuit generates one pulse or a group of multiple pulses in the transmission pulse signal at the timings of completion of the self-diagnosis and the memory access, and continues to generate pulses in the transmission pulse signal at a first time period when an abnormality in the memory access is detected.

2. The signal transmission device according to claim 1, further comprising a signal processing circuit provided in said primary circuit system and configured to identify the completion timing of said self-diagnosis and said memory access, and the presence or absence of an abnormality in said memory access, from a received pulse signal input via said insulating element.

3. The signal transmission device according to claim 2, wherein the signal processing circuit includes: a first latch configured to fix a self-diagnosis completion signal at a first logic level until the signal transmission device is started up, and to set the self-diagnosis completion signal to a second logic level when one pulse or a group of multiple pulses is generated in the received pulse signal for the first time since the signal transmission device is started up; and a second latch configured to set a memory access signal to a third logic level when the memory access is started, and to set the memory access signal to a fourth logic level when one pulse or a group of multiple pulses is generated in the received pulse signal with the self-diagnosis completion signal at the second logic level.

4. A signal transmission device as described in claim 2 or 3, wherein the signal processing circuit includes: a timer configured to set a timer signal to a fifth logic level when a pulse is generated in the received pulse signal, and to set the timer signal to a sixth logic level when no pulse is generated in the received pulse signal for a second time period longer than the first time; and a counter configured to set a memory abnormality signal to a seventh logic level when the timer signal is at the fifth logic level for a third time period longer than the second time, and to set the memory abnormality signal to an eighth logic level when the timer signal is at the sixth logic level.

5. A signal transmission device according to any one of claims 1 to 4, wherein the isolation element is a transformer.

6. A signal transmission device according to any one of claims 1 to 5, further comprising a first insulating element and a second insulating element configured to transmit signals while isolating said primary circuit system and said secondary circuit system, wherein in a first operation mode, a rising edge and a falling edge of an input pulse signal are transmitted from said primary circuit system to said secondary circuit system via said first insulating element and said second insulating element, and wherein in a second operation mode, a data signal and a clock signal are transmitted from said primary circuit system to said secondary circuit system via said first insulating element and said second insulating element.

7. A signal transmission device according to any one of claims 1 to 6, comprising: a first die on which circuit elements of the primary circuit system are integrated; a second die on which circuit elements of the secondary circuit system are integrated; and a third die on which the insulating element is integrated.

8. The signal transmission device of claim 7, wherein the first die, the second die and the third die are sealed in a single package.

9. An electronic device comprising: a power transistor; and an insulated gate driver IC configured to drive a gate of the power transistor, the insulated gate driver IC being a signal transmission device according to any one of claims 1 to 8.

10. A vehicle comprising the electronic device according to claim 9.

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