Ternary logic circuit using Anti-ambipolar transistor, and method for designing ternary logic circuit

Abstract

The present invention relates to a ternary logic circuit and, more particularly, to a ternary logic circuit using an anti-ambipolar transistor (AAT), and a method for designing a ternary logic circuit. The present invention relates to a ternary logic circuit and a method for designing a ternary logic circuit in which a more efficient ternary logic circuit can be implemented by outputting three states by using three transistors respectively connected to three different voltage sources, and a leakage current can be greatly reduced by using an AAT.

Description

Ternary logic circuit using a semi-bipolar transistor and a method for designing a ternary logic circuit

[0001] The present invention relates to a ternary logic circuit, and more particularly, to a ternary logic circuit using anti-ambipolar transistors (AAT) and a method for designing a ternary logic circuit.

[0002]

[0003] With the advancement of Fourth Industrial Revolution technologies like artificial intelligence, the amount of data to be processed is increasing exponentially. Consequently, the demand for devices capable of processing more data in a single period of time has grown. To meet this demand, smaller devices have been developed to accommodate more devices within the same footprint, thereby improving speed.

[0004] However, as current binary-based systems approach the nanometer scale, uniform component fabrication and further integration are becoming impossible. Furthermore, because current binary-based systems process data in two representations, an astronomical number of components is required to handle the current high data volumes.

[0005] To solve these problems, the development of a ternary system is required.

[0006] The ternary system offers the advantage of handling more data than the binary system by processing data in three representations (-1, 0, 1, or 0, 1, 2). However, the existing ternary system suffers from the problem of large leakage current when implementing intermediate states.

[0007]

[0008] The technical problem of the present invention is proposed to solve such problems, and the purpose of the present invention is to provide a ternary logic circuit capable of implementing three states using three voltage sources.

[0009] In particular, the present invention aims to provide a ternary logic circuit and a ternary logic circuit design method using a semi-bipolar transistor capable of reducing leakage current when implementing an intermediate state.

[0010] However, the purpose of the present invention is not limited to the above purpose, and other purposes not mentioned can be clearly understood from the description below.

[0011]

[0012] In order to achieve the above-described object, according to an embodiment of the present invention, a ternary logic circuit using an anti-ambipolar transistor comprises: a first type transistor including a first type channel; a second type transistor including a second type channel arranged in series with the first type transistor and operating complementarily with the first type channel; and an anti-ambipolar transistor arranged in parallel with the first type transistor and the second type transistor, wherein the first type transistor, the second type transistor, and the anti-ambipolar transistor are each connected to different voltage sources, and switching operations of the first type transistor, the second type transistor, and the anti-ambipolar transistor are controlled according to an input voltage so that different voltage sources can be output.

[0013] At this time, if the first type channel is a P type channel, the second type channel may be an N type channel.

[0014] At this time, if the input voltage is a low level voltage, the first type transistor connected to a high level voltage source is switched on to output the voltage of the high level voltage source, if the input voltage is a high level voltage, the second type transistor connected to a low level voltage source is switched on to output the voltage of the low level voltage source, and if the input voltage is a ground voltage, the semi-bipolar transistor connected to a ground electrode is switched on to output the ground voltage.

[0015] In addition, the semi-bipolar transistor includes an N-type channel and a P-type channel, and the N-type channel may be made of indium oxide (InO), and the P-type channel may be made of a single-wall carbon nanotube (SWCNT).

[0016] At this time, the P-type channel may be a three-layer single-walled carbon nanotube.

[0017] Additionally, depending on the voltage source connection direction of the N-type channel and the P-type channel, the semi-bipolar transistor can operate as a positive network or a negative network.

[0018] In addition, a ternary logic circuit using a semi-bipolar transistor of the present invention may further include at least one other semi-bipolar transistor connected in series with the semi-bipolar transistor.

[0019] In order to achieve the above-described object, a method for designing a ternary logic circuit using an anti-ambipolar transistor according to an embodiment of the present invention may include a step of setting switching conditions for output states of a high level voltage source, a low level voltage source, and a ground voltage source corresponding to three input voltages; and a step of controlling, according to the switching conditions, a switching operation of a first type transistor including a first type channel, a second type transistor including a second type channel arranged in series with the first type transistor and operating complementarily with the first type channel, and an anti-ambipolar transistor arranged in parallel with the first type transistor and the second type transistor.

[0020]

[0021] According to the ternary logic circuit and ternary logic circuit design method using the semi-bipolar transistor of the present invention, by using three transistors each connected to three different voltage sources, leakage current can be significantly reduced compared to the conventional method using two voltage sources.

[0022] In addition, according to the present invention, by further utilizing a semi-bipolar transistor capable of reducing leakage current when implementing an intermediate state, the leakage current generated during a switching operation can be significantly reduced.

[0023] In addition, various effects other than the above-described effects may be disclosed directly or implicitly in the detailed description according to the embodiments of the present invention to be described later.

[0024]

[0025] Figure 1 is an exemplary diagram illustrating a semi-bipolar transistor of the present invention.

[0026] Figures 2 to 4 are graphs for explaining the characteristics of a semi-bipolar transistor.

[0027] Figure 5 is a circuit diagram for explaining a ternary logic circuit using a semi-bipolar transistor of the present invention.

[0028] Figures 6 to 8 are circuit diagrams for explaining the operation of the ternary logic circuit of the present invention.

[0029] Figure 9 is a graph for explaining the operating characteristics of the ternary logic circuit of the present invention.

[0030] Figure 10 is an exemplary diagram for explaining a process for controlling the on / off switching operation of the semi-bipolar transistor of the present invention.

[0031] Figure 11 is a graph for explaining the operation of the semi-bipolar transistor of the present invention according to the channel direction.

[0032] FIG. 12 is a circuit diagram for explaining a ternary logic circuit using a stacked semi-bipolar transistor according to another embodiment of the present invention.

[0033] FIGS. 13 and 14 are graphs illustrating performance improvement when using a stacked semi-bipolar transistor according to another embodiment of the present invention.

[0034] FIG. 15 is a flowchart illustrating a method for designing a ternary logic circuit using a semi-bipolar transistor according to an embodiment of the present invention.

[0035]

[0036] <Description of drawing symbols>

[0037] 10: Type 1 transistor

[0038] 20: Type 2 transistor

[0039] 30: Semi-bipolar transistor

[0040] 100: Ternary logic circuit

[0041]

[0042] In order to more clearly explain the features and advantages of the problem-solving means of the present invention, the present invention will be described in more detail with reference to specific embodiments of the present invention illustrated in the attached drawings.

[0043] However, detailed descriptions of known functions or components that may obscure the gist of the present invention in the following description and attached drawings are omitted. It should also be noted that, where possible, identical components are indicated with identical reference numerals throughout the drawings.

[0044] The terms and words used in the following description and drawings should not be interpreted as limited to their conventional or dictionary meanings, but should be interpreted with meanings and concepts that conform to the technical idea of ​​the present invention based on the principle that the inventor can appropriately define the concept of the term to best describe his or her invention. Therefore, the embodiments described in this specification and the configurations illustrated in the drawings are merely the most preferred embodiments of the present invention and do not represent all of the technical idea of ​​the present invention. Therefore, it should be understood that there may be various equivalents and modified examples that can replace them at the time of filing this application.

[0045] Additionally, terms containing ordinal numbers, such as "first," "second," etc., are used to describe various components, and are only used to distinguish one component from another, not to limit said components. For example, without departing from the scope of the present invention, a second component could be referred to as a "first component," and similarly, a first component could also be referred to as a "second component."

[0046] Additionally, when a component is referred to as being "connected" or "connected" to another component, this means that the component can be connected or connected logically or physically. In other words, while a component may be directly connected or connected to another component, it should be understood that other components may exist in between, and that the component may be connected or connected indirectly.

[0047] In addition, the terminology used in this specification is only used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In addition, it should be understood that the terms "comprises" or "has" described in this specification are intended to specify the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0048] Hereinafter, a ternary logic circuit using an anti-ambipolar transistor according to an embodiment of the present invention will be described.

[0049] FIG. 1 is an exemplary diagram for explaining a semi-bipolar transistor of the present invention, and FIGS. 2 to 4 are graphs for explaining the characteristics of the semi-bipolar transistor.

[0050] First, referring to FIG. 1, a semi-bipolar transistor (30) according to an embodiment of the present invention will be described. The semi-bipolar transistor (30) according to an embodiment of the present invention may be configured to include a substrate (310), an insulating film (320), a channel (330), and an electrode (340).

[0051] The substrate (310) may include a semiconductor substrate such as doped silicon (Si) and may serve as a gate electrode (G, 311).

[0052] And, an insulating film (320) is formed on the substrate (310). Here, the insulating film (320) may use, for example, hafnium oxide (HfO2), and the insulating film (320) may include a structure that completely covers one surface of the substrate (310).

[0053] The electrode (340) includes a source electrode (S, 341) and a drain electrode (D, 342), and may be made of, for example, an Ag material. In addition, when an input voltage is applied from the gate electrode (S, 311), the source electrode (341) and the drain electrode (342) are connected to each other to form a channel (330).

[0054] More specifically, the channel (330) of the semi-bipolar transistor (30) of the present invention is configured to include two types of channels.

[0055] That is, the semi-bipolar transistor (30) of the present invention can exhibit two current characteristics at once, namely, the N-type channel (331) characteristic and the P-type channel (332) characteristic, by using two types of N-type channels (331) and P-type channels (332).

[0056] The current resistance characteristics of these N-type channels (331) and P-type channels (332) are shown in Fig. 2, where the N-type channel (331) has a low V GS It transmits a very small current with high resistance, and the P type channel (332) has a high V GS In this way, V transmits a very small current with high resistance. GSAs the voltage increases, the anti-ambipolarity increases until it reaches a peak and then decreases, showing an inverted V-shaped curve. In the present invention, a ternary logic circuit capable of representing an intermediate state can be implemented by utilizing the current characteristics of this anti-ambipolar transistor (30).

[0057] In general, the channel (330) can be configured to include materials such as MoS2, MoSe2, WS2, WSe2, MoTe2, and ReS2, but in the case of a transistor including such materials, the problem of increased manufacturing cost may arise.

[0058] Therefore, in order to solve this problem in the embodiment of the present invention, the N-type channel (331) may use indium oxide (InO), and the P-type channel (332) may use a single-wall carbon nanotube (SWCNT).

[0059] Here, the thickness of the SWCNT can affect the magnitude of the maximum current, and in a preferred embodiment of the present invention, a three-layer SWCNT can be applied.

[0060] That is, as shown in (a) of FIG. 3, a semi-bipolar transistor (AAT with 3-layers of P-ch) including 3-layer SWCNTs exhibits symmetrical N-type channel-off (N-ch OFF) and P-type channel-off (P-ch OFF) characteristics, whereas a semi-bipolar transistor (AAT with 4-layers of P-ch) including 4-layer SWCNTs illustrated in (b) of FIG. 3 exhibits a larger maximum current, thereby forming an asymmetrical channel-off characteristic, i.e., a P-type channel-off (P-ch OFF) current level that is greater than an N-type channel-off (N-ch OFF) current level. Since the P-type channel-off operation may be somewhat unstable in the case of such 4-layer SWCNTs, a 3-layer SWCNT is used in the present preferred embodiment.

[0061] In this way, the semi-bipolar transistor (30) according to the embodiment of the present invention does not flow current because the channel is not connected (N-ch OFF, P-ch OFF) at high level input voltage and low level input voltage, and the maximum current (V) is input when the specified input voltage, i.e., ground voltage (GND, 0 V) ​​is input. PEAK ), it exhibits characteristics that are different from those of a typical CMOS transistor that operates at high-level input voltage and low-level input voltage.

[0062] By utilizing the current characteristics of such a semi-bipolar transistor (30), as shown in Fig. 4, it is possible to implement a ternary logic circuit capable of expressing three types of data by outputting different output voltages according to the level of the input voltage using three transistors that perform independent operations, each connected to a different voltage source.

[0063] Hereinafter, a ternary logic circuit using a semi-bipolar transistor according to an embodiment of the present invention will be described in more detail.

[0064] FIG. 5 is a circuit diagram for explaining a ternary logic circuit using a semi-bipolar transistor of the present invention, FIGS. 6 to 8 are circuit diagrams for explaining the operation of the ternary logic circuit of the present invention, and FIG. 9 is a graph for explaining the operating characteristics of the ternary logic circuit of the present invention.

[0065] First, referring to FIG. 5, a ternary logic circuit (100) using a semi-bipolar transistor according to an embodiment of the present invention may mean an inverter circuit (NOT gate).

[0066] The ternary logic circuit (100) of the present invention is configured to include different independent transistors connected to different voltage sources.

[0067] That is, the ternary logic circuit (100) of the present invention may be configured to include a first type transistor (10) including a first type channel, a second type transistor (20) including a second type channel that is arranged in series with the first type transistor (10) and operates complementarily with the first type channel, and a semi-bipolar transistor (30) that is arranged in parallel with the first type transistor (10) and the second type transistor (20).

[0068] A first type transistor (10) including a first type channel and a second type transistor (20) including a second type channel are CMOS (Complementary Metal-Oxide Semiconductor) transistors that operate complementarily to each other, and if the first type channel is a P type channel, the second type channel may be an N type channel.

[0069] The gates of the first type transistor (10), the second type transistor (20), and the semi-bipolar transistor (30) are commonly connected to an input voltage (A) at point P1, the drains of the first type transistor (10) and the second type transistor (20) are connected at point P2, and the drain of the semi-bipolar transistor (30) is connected at point P3 so that it can be output as an output voltage (Y).

[0070] Each transistor (10, 20, 30) constituting the ternary logic circuit (100) according to an embodiment of the present invention has its source connected to a different voltage source. That is, the source of the first type transistor (10) is connected to a high level voltage source (V DD ) is connected to the second type transistor (20), and the source of the second type transistor (20) is a low level voltage source (V SS ) is connected to the ground voltage (GND, 0V), and the anti-polar transistor (30) is connected to the ground voltage (GND, 0V).

[0071] The ternary logic circuit (100) according to this embodiment of the present invention uses different independent transistors each connected to different independent voltage sources, thereby outputting voltages of different voltage sources as output voltages (Y) according to the voltage level of the input voltage (A), thereby enabling output of multiple logic states.

[0072] Referring to FIGS. 6 to 8, in the embodiment of the present invention, the state of the input voltage (A) can be used as a high level voltage, a low level voltage, and an intermediate voltage between the high level voltage and the low level voltage. For example, the voltage of the input voltage (A) can be 1 V, 0 V, or -1 V.

[0073] At this time, as shown in Fig. 6, if the input voltage (A) is a low level voltage (-1 V), the first type transistor (10) is turned on, the second type transistor (20) and the anti-polar transistor (30) are turned off, and the high level voltage source (V) connected to the first type transistor (10) DD ) is output as the output voltage (Y).

[0074] And as shown in Fig. 7, when the input voltage (A) is a high level voltage (1 V), the first type transistor (10) is turned off, the second type transistor (20) is turned on, and the semi-bipolar transistor (30) is turned off. Therefore, the source and drain of the second type transistor (20) are connected to the low level voltage source V SS A voltage of (-1V) is output through the drain as the output voltage (Y).

[0075] And as shown in FIG. 8, when the threshold voltage of the input voltage (A) is the intermediate voltage, i.e., the ground voltage (0 V), both the first type transistor (10) and the second type transistor (20) are turned off, and as described with reference to FIG. 4 described above, the first type transistor (10) and the second type transistor (20) are turned off, i.e., the semi-bipolar transistor (30) is turned on according to the characteristics of the semi-bipolar transistor that turns on when the input voltage is the ground voltage, so that the voltage of the voltage source (GND, 0 V) ​​is output as the output voltage (Y).

[0076] In this way, the ternary logic circuit (100) of the present invention uses three different transistors each connected to a different independent voltage source, thereby generating different input voltages (V) as shown in FIG. 9. A ) are input, different output voltages (V Y ) can be output, which can express three different operating states.

[0077] In addition, the ternary logic circuit (100) of the present invention can operate at low power by using a semi-bipolar transistor (30), and can stably implement ternary operation without loss of leakage current.

[0078] As described above, a semi-bipolar transistor (30) according to an embodiment of the present invention includes two channels, an N-type channel and a P-type channel, simultaneously. In one embodiment of the present invention, the N-type channel is connected to a ground voltage source (GND, 0 V) ​​as a source electrode, and the P-type channel is connected to a drain electrode. When the two channels are connected to each other, they operate as a positive network that outputs the ground voltage connected to the source electrode as an output voltage. However, depending on the implementation method, the semi-bipolar transistor (30) may also operate as a negative network in which the directions of the channels are opposite, which will be described with reference to FIG. 10.

[0079] FIG. 10 is an exemplary diagram for explaining a process for controlling the on / off switching operation of the semi-bipolar transistor of the present invention, and FIG. 11 is a graph for explaining the operation according to the channel direction of the semi-bipolar transistor of the present invention.

[0080] First, (a) of Fig. 10 illustrates that the on / off switching operation can vary depending on the channel direction of the semi-bipolar transistor (30), i.e., whether it is a positive network or a negative network.

[0081] In other words, the semi-bipolar transistor (30) according to the embodiment of the present invention described above is a positive network (AAT) P ) as input voltage (V IN ) is 0V, the connected voltage source ground voltage (0V) is output.

[0082] However, the semi-bipolar transistor (30) of the present invention has a negative network (AAT) N) is operated as a drain electrode, that is, when the P-type channel is connected to the ground voltage and the N-type channel operates as a drain electrode, the input voltage (V IN ) can be switched on and operate even at low level voltages, such as negative voltages.

[0083] That is, the semi-bipolar transistor according to the embodiment of the present invention is input from the gate to the source with an input voltage (V) as shown in FIG. 11. GS ) can operate not only at 0 V but also at -1 V, and by controlling the switching operation in the channel direction, more diverse switching operation control is possible.

[0084] The ternary logic circuit using a semi-bipolar transistor according to an embodiment of the present invention has been described above.

[0085] A ternary logic circuit using a semi-bipolar transistor according to an embodiment of the present invention may be configured to include a first type transistor including a first type channel, a second type transistor including a second type channel arranged in series with the first type transistor and operating complementarily with the first type channel, and one semi-bipolar transistor arranged in parallel with the first type transistor and the second type transistor, but a ternary logic circuit according to another embodiment of the present invention may also be implemented by stacking two semi-bipolar transistors.

[0086] This will be explained with reference to Figure 12.

[0087] FIG. 12 is a circuit diagram for explaining a ternary logic circuit using a stacked semi-bipolar transistor according to another embodiment of the present invention, and FIGS. 13 and 14 are graphs for explaining performance improvement when using a stacked semi-bipolar transistor according to another embodiment of the present invention.

[0088] First, referring to FIG. 12, a ternary logic circuit (200) using a stacked semi-bipolar transistor according to another embodiment of the present invention may include a first type transistor (10) including a first type channel and a second type transistor (20) including a second type channel that is arranged in series with the first type transistor (10) and operates complementarily with the first type channel.

[0089] Here, the first type transistor (10) and the second type transistor (20) are substantially the same as the configuration described with reference to FIG. 5, so a detailed description thereof will be omitted.

[0090] In addition, the ternary logic circuit (200) using the stacked semi-bipolar transistor of the present invention can be configured to include a second semi-bipolar transistor (40) that is stacked and connected in series to a first semi-bipolar transistor (30).

[0091] Each gate of the first type transistor (10) and the second type transistor (20) is connected to a common input voltage (A) branched at point P1, and the branched input voltage (A) is branched at point P4 and transmitted to the stacked first semi-bipolar transistor (30) and second semi-bipolar transistor (40).

[0092] And, the drains of the first type transistor (10) and the second type transistor (20) are connected at point P2 and output as an output voltage (Y) through point P3, the source electrode of the second semi-bipolar transistor (40) is connected to the ground electrode (GND, 0 V) ​​and the drain electrode is connected to the source electrode of the first semi-bipolar transistor (30), and when a channel is formed, the ground voltage flows from the source electrode of the second semi-bipolar transistor (40) to the drain electrode, and the ground voltage output from the second semi-bipolar transistor (40) is output as an output voltage (Y) through the source electrode of the first semi-bipolar transistor (30) through point P3.

[0093] In this way, by configuring the first semi-bipolar transistor (30) and the second semi-bipolar transistor (40) in a stacked type (N1), the current path of the semi-bipolar transistors (30, 40) can be suppressed, thereby exhibiting a more improved output state. In this case, as illustrated in FIG. 13, when only one semi-bipolar transistor is used (see Original STI), the transfer characteristics of the N-type transistor when the input voltage is 1 V appear to be somewhat narrow, but when a stacked semi-bipolar transistor is used (see Suppressed leaky AAT), by suppressing the current path of the semi-bipolar transistor, the narrow transfer characteristics of the N-type transistor when the input voltage is 1 V are improved, thereby ensuring a more efficient switching operation of the N-type transistor.

[0094] In addition, as shown in (b) of Fig. 14, when using a stacked semi-bipolar transistor, a more optimized equal distribution of noise margin can be achieved, and thus, better performance can be exhibited than the ternary logic circuit using the semi-bipolar transistor shown in (a).

[0095] In addition, the ternary logic circuit according to an embodiment of the present invention may be implemented using an inkjet printing method, but is not limited thereto, and the ternary logic circuit according to an embodiment of the present invention may be implemented using other methods.

[0096] The ternary logic circuit using the semi-bipolar transistor of the present invention has been described above.

[0097] Hereinafter, a design method of a ternary logic circuit using a semi-bipolar transistor of the present invention will be described.

[0098] FIG. 15 is a flowchart illustrating a method for designing a ternary logic circuit using a semi-bipolar transistor according to an embodiment of the present invention.

[0099] Referring to Fig. 15, the ternary logic circuit of the present invention sets switching conditions for the output states of three voltage sources corresponding to three input voltages (S100). Here, the three voltage sources include a high-level voltage source, a low-level voltage source, and a ground voltage source, and, as shown in the table in Fig. 10, sets on-off switching operation conditions according to the input voltage.

[0100] And, the ternary logic circuit of the present invention controls the switching operation of three transistors according to the set switching conditions (S200). The ternary logic circuit of the present invention controls the switching operation of three transistors, that is, a first type transistor including a first type channel, a second type transistor including a second type channel that is arranged in series with the first type transistor and operates complementarily with the first type channel, and an anti-ambipolar transistor that is arranged in parallel with the first type transistor and the second type transistor. According to this switching operation, different output voltages corresponding to the input voltage are output, so that the ternary logic circuit of the present invention can represent three states.

[0101] Thus, a ternary logic circuit and a ternary logic circuit design method using a semi-bipolar transistor according to an embodiment of the present invention have been described.

[0102] While the present invention has been described with reference to the embodiments illustrated in the drawings, these are merely exemplary, and those skilled in the art will understand that various modifications and equivalent embodiments are possible. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the patent claims.

[0103]

[0104] The present invention relates to a ternary logic circuit, and more particularly, to a ternary logic circuit using anti-ambipolar transistors (AAT) and a method for designing a ternary logic circuit.

[0105] According to the present invention, a more efficient ternary logic circuit can be implemented by outputting three states using three transistors each connected to three different voltage sources, and by using a semi-bipolar transistor, leakage current can be significantly reduced, contributing to the popularization of ternary systems, and thus has sufficient potential for industrial use.

Claims

1. A first type transistor comprising a first type channel; A second type transistor including a second type channel arranged in series with the first type transistor and operating complementarily with the first type channel; An anti-ambipolar transistor arranged in parallel with the first type transistor and the second type transistor; Includes, The first type transistor, the second type transistor and the semi-bipolar transistor are each connected to different voltage sources, A ternary logic circuit using an anti-ambipolar transistor, characterized in that different voltage sources are output by controlling the switching operations of each of the first type transistor, the second type transistor, and the anti-ambipolar transistor according to an input voltage.

2. In paragraph 1, If the above first type channel is a P type channel, A ternary logic circuit using a semi-bipolar transistor, characterized in that the second type channel is an N type channel.

3. In paragraph 1, When the input voltage is a low level voltage, the first type transistor connected to a high level voltage source is switched on to output the voltage of the high level voltage source, When the input voltage is a high level voltage, the second type transistor connected to the low level voltage source is switched on to output the voltage of the low level voltage source, A ternary logic circuit using a semi-bipolar transistor, characterized in that when the input voltage is a ground voltage, the semi-bipolar transistor connected to the ground electrode is switched on and outputs a ground voltage.

4. In paragraph 1, The above semi-bipolar transistor Includes N-type channels and P-type channels, A ternary logic circuit using a semi-bipolar transistor, characterized in that the N-type channel is made of indium oxide (InO) and the P-type channel is made of single-wall carbon nanotube (SWCNT).

5. In paragraph 4, A ternary logic circuit using a semi-bipolar transistor, wherein the above P-type channel is a three-layer single-walled carbon nanotube.

6. In paragraph 4, A ternary logic circuit using a bipolar transistor, characterized in that the bipolar transistor operates as a positive network or a negative network depending on the voltage source connection direction of the N-type channel and the P-type channel.

7. In paragraph 1, A ternary logic circuit using a semi-bipolar transistor, characterized in that it further includes at least one other semi-bipolar transistor connected in series with the above semi-bipolar transistor. 8.3 Step of setting switching conditions for the output states of the corresponding high level voltage source, low level voltage source, and ground voltage source according to the input voltage; and A step of controlling the switching operation of a first type transistor including a first type channel, a second type transistor including a second type channel arranged in series with the first type transistor and operating complementarily with the first type channel, and an anti-ambipolar transistor arranged in parallel with the first type transistor and the second type transistor, according to the above switching conditions; A method for designing a ternary logic circuit using an anti-ambipolar transistor, characterized by including:

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