Optical module, and method for preparing hybrid inp / si optical chip

Abstract

The present disclosure provides an optical module, and a method for preparing a hybrid InP / Si optical chip. The optical module comprises: a circuit board; and a hybrid InP / Si optical chip, which is electrically connected to the circuit board and is configured to modulate and generate an optical signal. The hybrid InP / Si optical chip comprises: a Si platform, which is integrated with a silicon optical circuit, wherein an InP region is formed inside the Si platform, the InP region has no pad, a radio frequency pad and a direct-current bias pad are provided at the top of the Si platform, the radio frequency pad is located on one side of the InP region, and the direct-current bias pad is located on the other side of the InP region; an InP phase modulator, which is located in the InP region and comprises an InP waveguide and a coupling electrode, wherein the coupling electrode is arranged above the InP waveguide, and the InP waveguide is electrically connected to the direct-current bias pad; and a radio frequency traveling waveguide, one end of which is connected to the radio frequency pad, and the other end of which extends over the InP waveguide and extends to the other side of the InP region, wherein the radio frequency traveling waveguide is electrically connected to the coupling electrode. Thus, the modulation rate of a phase modulator is increased, thereby meeting the requirements of a high-rate optical module.

Description

Optical module and preparation method of hybrid InP / Si optical chip

[0001] This application claims the priority of application number 202311270743.6 filed with the China Patent Office on September 28, 2023; the priority of application number 202410135176.1 filed with the China Patent Office on January 31, 2024; and the priority of application number 202410135674.6 filed with the China Patent Office on January 31, 2024; all of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of optical fiber communication technology, and in particular to a method for preparing an optical module and a hybrid InP / Si optical chip. Background Art

[0003] With the development of new services and applications such as cloud computing, mobile internet, and video, advances in optical communication technology are becoming increasingly important. As a key component in optical communication equipment, optical modules enable photoelectric signal conversion. As optical communication technology evolves, the data transmission rate of these modules continues to increase.

[0004] Summary of the Invention

[0005] The present disclosure provides an optical module and a method for preparing a hybrid InP / Si optical chip, which meet the requirements of high-speed optical modules.

[0006] In a first aspect, the present disclosure provides an optical module, comprising:

[0007] circuit boards;

[0008] A hybrid InP / Si optical chip, electrically connected to the circuit board, for modulating and generating optical signals;

[0009] Among them, hybrid InP / Si optical chips include:

[0010] A Si platform is formed with an InP region inside, and the top of the InP region has no pad; a radio frequency pad and a DC bias pad are set on the top of the Si platform, the radio frequency pad is located on one side of the InP region, and the DC bias pad is located on the other side of the InP region;

[0011] An InP phase modulator is located in the InP region; the InP phase modulator includes an InP waveguide and an electrode, the coupling electrode is arranged above the InP waveguide, and the InP waveguide is electrically connected to a DC bias pad;

[0012] A radio frequency traveling waveguide has one end connected to the radio frequency pad and the other end extending over the InP waveguide and to the other side of the InP region; the radio frequency traveling waveguide is electrically connected to the coupling electrode.

[0013] In a second aspect, the present disclosure provides a method for preparing a hybrid InP / Si optical chip, wherein the hybrid InP / Si optical chip is used to modulate and generate an optical signal, the preparation method comprising:

[0014] forming a first substrate, wherein the first substrate comprises a substrate layer and a BOX layer, wherein the BOX layer is located above the substrate layer;

[0015] forming a Si waveguide layer above the BOX layer, and etching the Si waveguide layer to form an input Si waveguide and an output Si waveguide, with a gap between the input Si waveguide and the output Si waveguide;

[0016] forming a first SiO2 layer around the etched Si waveguide layer, wherein the first SiO2 layer fills the etched area of ​​the Si waveguide layer;

[0017] An InP bare chip is arranged above the first SiO2 layer, wherein the InP bare chip comprises, from bottom to top, an n-InP layer, a first i-InP layer, a quantum hydrazine layer, a second i-InP layer, a p-InP layer, and a second substrate;

[0018] Etching the InP bare chip to form an InP waveguide, wherein a first n-InP protrusion and a second n-InP protrusion are formed on the top of the n-InP layer at the bottom of the InP waveguide, a gap is formed between the first n-InP protrusion and the second n-InP protrusion, and the top of the first n-InP protrusion and the top of the second n-InP protrusion respectively support the first i-InP layer, the quantum hydrazine layer, the second i-InP layer, and the p-InP layer;

[0019] forming a second SiO2 layer on a side of the InP waveguide, wherein the first SiO2 layer and the second SiO2 layer form a SiO2 layer;

[0020] An RF pad, a DC bias pad, an RF traveling waveguide and a coupling electrode are formed on the top of the second SiO2 layer; wherein: the RF pad is located on the side of one end of the InP waveguide, the RF traveling waveguide is located on the side of the top edge of the InP waveguide, and one end of the RF traveling waveguide is electrically connected to the RF pad; the DC bias pad is located on the side of the other end of the InP waveguide, and the DC bias pad is electrically connected to the InP waveguide; the coupling electrode is located above the InP waveguide, and the coupling electrode is electrically connected to the RF traveling waveguide. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0022] FIG1 is a partial architecture diagram of an optical communication system according to some embodiments of the present disclosure;

[0023] FIG2 is a partial structural diagram of a host computer provided according to some embodiments of the present disclosure;

[0024] FIG3 is a structural diagram of an optical module provided according to some embodiments of the present disclosure;

[0025] FIG4 is an exploded view of an optical module according to some embodiments of the present disclosure;

[0026] FIG5 is a schematic diagram of the internal structure of an optical module according to some embodiments of the present disclosure;

[0027] FIG6 is a schematic diagram of a layout of a silicon photonic chip according to some embodiments of the present disclosure;

[0028] FIG7 is a schematic diagram of the layout of a hybrid InP / Si optical chip according to some embodiments of the present disclosure;

[0029] FIG8 is a schematic diagram of a partial structure of a hybrid InP / Si optical chip according to some embodiments of the present disclosure;

[0030] FIG9 is a second schematic diagram of a partial structure of a hybrid InP / Si optical chip provided according to some embodiments of the present disclosure;

[0031] FIG10 is a schematic structural diagram of a first radio frequency electrode provided according to some embodiments of the present disclosure;

[0032] FIG11 is an enlarged cross-sectional view of a hybrid InP / Si optical chip according to some embodiments of the present disclosure;

[0033] FIG12 is a second enlarged cross-sectional view of a hybrid InP / Si optical chip according to some embodiments of the present disclosure;

[0034] FIG13 is a third enlarged cross-sectional view of a hybrid InP / Si optical chip according to some embodiments of the present disclosure;

[0035] FIG14 is a fourth enlarged cross-sectional view of a hybrid InP / Si optical chip according to some embodiments of the present disclosure;

[0036] FIG15 is an equivalent circuit diagram of a hybrid InP / Si optical chip according to some embodiments of the present disclosure;

[0037] FIG16 is a first structural diagram of a hybrid InP / Si optical chip assembly according to some embodiments of the present disclosure;

[0038] FIG17 is a second structural diagram of a hybrid InP / Si optical chip assembly according to some embodiments of the present disclosure;

[0039] FIG18 is a schematic flow chart of a method for preparing a hybrid InP / Si optical chip according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0040] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0041] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0042] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0043] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0044] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0045] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0046] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0047] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0048] In optical communication technology, to establish information transmission between information processing devices, it is necessary to load the information onto light and use the propagation of light to achieve information transmission. Here, the light loaded with information is an optical signal. When transmitting optical signals within information transmission equipment, they can reduce optical power loss, thereby enabling high-speed, long-distance, and low-cost information transmission. The signals that information processing equipment can recognize and process are electrical signals. Information processing equipment typically includes optical network units (ONUs), gateways, routers, switches, mobile phones, computers, servers, tablets, televisions, etc., and information transmission equipment typically includes optical fibers and optical waveguides.

[0049] Optical modules can convert optical signals into electrical signals between information processing devices and information transmission devices. For example, at least one of the optical signal input or output ends of an optical module is connected to an optical fiber, and at least one of the electrical signal input or output ends of the optical module is connected to an optical network terminal. A first optical signal from the optical fiber is transmitted to the optical module, which converts the first optical signal into a first electrical signal and transmits the first electrical signal to the optical network terminal. A second electrical signal from the optical network terminal is transmitted to the optical module, which converts the second electrical signal into a second optical signal and transmits the second optical signal to the optical fiber. Because multiple information processing devices can transmit information via electrical signals, at least one of the multiple information processing devices needs to be directly connected to the optical module, rather than all of them. Here, the information processing device directly connected to the optical module is referred to as the optical module's host computer. Furthermore, the optical signal input or output end of the optical module can be referred to as an optical port, and the electrical signal input or output end of the optical module can be referred to as an electrical port.

[0050] Figure 1 is a partial structural diagram of an optical communication system provided according to some embodiments of the present disclosure. As shown in Figure 1, the optical communication system mainly includes a remote information processing device 1000, a local information processing device 2000, a host computer 100, an optical module 200, an optical fiber 101, and a network cable 103.

[0051] One end of optical fiber 101 extends toward remote information processing device 1000, and the other end of optical fiber 101 is connected to optical module 200 through the optical port of optical module 200. Optical signals can be totally reflected in optical fiber 101, and the propagation of the optical signal in the direction of total reflection can almost maintain the original optical power. The optical signal undergoes multiple total reflections in optical fiber 101 to transmit the optical signal from remote information processing device 1000 to optical module 200, and vice versa, thereby achieving long-distance, low-power information transmission.

[0052] The optical communication system may include one or more optical fibers 101, and the optical fibers 101 may be detachably connected or fixedly connected to the optical module 200. The host computer 100 is configured to provide data signals to the optical module 200, receive data signals from the optical module 200, or monitor or control the operating status of the optical module 200.

[0053] The host computer 100 includes a substantially rectangular housing and an optical module interface 102 disposed on the housing. The optical module interface 102 is configured to connect to the optical module 200 to establish a unidirectional or bidirectional electrical signal connection between the host computer 100 and the optical module 200.

[0054] The host computer 100 also includes an external electrical interface that can access an electrical signal network. For example, the external electrical interface includes a Universal Serial Bus (USB) interface or a network cable interface 104. The network cable interface 104 is configured to access a network cable 103 so that the host computer 100 establishes a unidirectional or bidirectional electrical signal connection with the network cable 103. One end of the network cable 103 is connected to the local information processing device 2000, and the other end of the network cable 103 is connected to the host computer 100, so that an electrical signal connection is established between the local information processing device 2000 and the host computer 100 via the network cable 103. For example, a third electrical signal emitted by the local information processing device 2000 is transmitted to the host computer 100 via the network cable 103. The host computer 100 generates a second electrical signal based on the third electrical signal. The second electrical signal from the host computer 100 is transmitted to the optical module 200. The optical module 200 converts the second electrical signal into a second optical signal and transmits the second optical signal to the optical fiber 101. The second optical signal is then transmitted to the remote information processing device 1000 via the optical fiber 101. For example, a first optical signal from the remote information processing device 1000 is transmitted through the optical fiber 101. The first optical signal from the optical fiber 101 is transmitted to the optical module 200. The optical module 200 converts the first optical signal into a first electrical signal. The optical module 200 transmits the first electrical signal to the host computer 100. The host computer 100 generates a fourth electrical signal based on the first electrical signal and transmits the fourth electrical signal to the local information processing device 2000. It should be noted that optical modules are tools for converting optical signals into electrical signals. During this conversion process, the information does not change, but the encoding and decoding methods of the information can change.

[0055] In addition to the optical network terminal, the host computer 100 also includes an optical line terminal (OLT), an optical network device (ONT), or a data center server.

[0056] FIG2 is a partial structural diagram of a host computer provided according to some embodiments of the present disclosure. In order to clearly show the connection relationship between the optical module 200 and the host computer 100, FIG2 only shows the structure of the host computer 100 related to the optical module 200. As shown in FIG2, the host computer 100 also includes a PCB circuit board 105 disposed in the housing, a cage 106 disposed on the surface of the PCB circuit board 105, a heat sink 107 disposed on the cage 106, and an electrical connector disposed inside the cage 106. The electrical connector is configured to connect to the electrical port of the optical module 200; the heat sink 107 has a protruding structure such as fins that increase the heat dissipation area.

[0057] The optical module 200 is inserted into the cage 106 of the host computer 100. The cage 106 secures the optical module 200. Heat generated by the optical module 200 is transferred to the cage 106 and then dissipated through the heat sink 107. After the optical module 200 is inserted into the cage 106, the electrical port of the optical module 200 connects with the electrical connector inside the cage 106, thereby establishing a bidirectional electrical signal connection between the optical module 200 and the host computer 100. Furthermore, the optical port of the optical module 200 connects to the optical fiber 101, thereby establishing a bidirectional optical signal connection between the optical module 200 and the optical fiber 101.

[0058] FIG3 is a structural diagram of an optical module provided according to some embodiments of the present disclosure, and FIG4 is an exploded view of an optical module provided according to some embodiments of the present disclosure. As shown in FIG3 and FIG4, the optical module 200 includes a housing (shell), a circuit board 300 disposed within the housing, an optical chip 400, and a light source 500. Exemplarily, the optical chip 400 and the light source 500 are electrically connected to the circuit board 300, respectively, and the light output end of the light source 500 is optically coupled to the optical chip 400. In some embodiments, the light output end of the light source 500 is connected to the optical chip 400 via an optical fiber coupling.

[0059] The housing includes an upper housing 201 and a lower housing 202 . The upper housing 201 covers the lower housing 202 to form the housing having two openings 204 and 205 . The outer contour of the housing is generally a square.

[0060] In some embodiments, the lower shell 202 includes a base plate 2021 and two lower side plates 2022 located on both sides of the base plate 2021 and arranged perpendicular to the base plate 2021; the upper shell 201 includes a cover plate 2011, and the cover plate 2011 covers the two lower side plates 2022 of the lower shell 202 to form the above-mentioned shell.

[0061] In some embodiments, the lower shell 202 includes a base plate 2021 and two lower side plates 2022 located on both sides of the base plate 2021 and arranged perpendicularly to the base plate 2021; the upper shell 201 includes a cover plate 2011 and two upper side plates located on both sides of the cover plate 2011 and arranged perpendicularly to the cover plate 2011. The two upper side plates are combined with the two lower side plates 2022 to achieve the upper shell 201 covering the lower shell 202.

[0062] The direction of the line connecting the two openings 204 and 205 can be consistent with the length direction of the optical module 200, or it can be inconsistent with the length direction of the optical module 200. For example, opening 204 is located at the end of the optical module 200 (the left end in Figure 3), and opening 205 is also located at the end of the optical module 200 (the right end in Figure 3). Alternatively, opening 204 is located at the end of the optical module 200, while opening 205 is located on the side of the optical module 200. Opening 204 is an electrical port, and the gold finger 301 of the circuit board 300 extends from opening 204 and is inserted into the electrical connector of the host computer 100. Opening 205 is an optical port, configured to receive an external optical fiber 101, so that the optical fiber 101 can connect to the optical chip 400 in the optical module 200.

[0063] The combined assembly of the upper housing 201 and the lower housing 202 facilitates installation of the circuit board 300, optical modulation chip 900, and light source 1100 within the housing. The upper housing 201 and the lower housing 202 provide encapsulation and protection for these components. Furthermore, during assembly of the circuit board 300, optical chip 400, and light source 500, positioning components, heat dissipation components, and electromagnetic shielding components are easily positioned, facilitating automated production.

[0064] In some embodiments, the upper shell 201 and the lower shell 202 are made of metal materials, which facilitates electromagnetic shielding and heat dissipation.

[0065] In some embodiments, the optical module 200 further includes an unlocking component 600 located outside its housing. The unlocking component 600 is configured to achieve a fixed connection between the optical module 200 and the host computer, or to release the fixed connection between the optical module 200 and the host computer.

[0066] For example, the unlocking component 600 is located on the outside of the two lower side panels 2022 of the lower housing 202 and includes a snap-fit ​​component that mates with the cage 106 of the host computer 100. When the optical module 200 is inserted into the cage 106, the snap-fit ​​component of the unlocking component 600 secures the optical module 200 in the cage 106. When the unlocking component 600 is pulled, the snap-fit ​​component of the unlocking component 600 moves accordingly, thereby changing the connection between the snap-fit ​​component and the host computer, thereby releasing the optical module 200 from the cage 106 and allowing the optical module 200 to be removed from the cage 106.

[0067] The circuit board 300 includes circuit traces, electronic components, and chips. The electronic components and chips are connected according to the circuit design through the circuit traces to achieve functions such as power supply, electrical signal transmission, and grounding. Electronic components may include, for example, capacitors, resistors, transistors, and metal-oxide-semiconductor field-effect transistors (MOSFETs). Chips may include, for example, microcontroller units (MCUs), laser driver chips, transimpedance amplifiers (TIAs), limiting amplifiers (LAs), clock and data recovery chips (CDRs), power management chips, and digital signal processing (DSP) chips.

[0068] The circuit board 300 is generally a rigid circuit board. Due to its relatively hard material, the rigid circuit board can also realize the load-bearing function. For example, the rigid circuit board can stably carry the above-mentioned electronic components and chips; the rigid circuit board can also be inserted into the electrical connector in the cage 106 of the host computer 100.

[0069] The circuit board 300 also includes a gold finger 301 formed on its end surface, and the gold finger 301 is composed of a plurality of independent pins. The circuit board 300 is inserted into the cage 106, and the gold finger 301 is connected to the electrical connector in the cage 106. The gold finger 301 can be set only on the surface of one side of the circuit board 300 (for example, the upper surface shown in Figure 4), or it can be set on the upper and lower surfaces of the circuit board 300 to provide a larger number of pins, thereby adapting to occasions where a large number of pins are required. The gold finger 301 is configured to establish an electrical connection with the host computer to achieve power supply, grounding, two-wire synchronous serial (Inter-Integrated Circuit, I2C) signal transmission, data signal transmission, etc. Of course, flexible circuit boards are also used in some optical modules. Flexible circuit boards are generally used in conjunction with rigid circuit boards to supplement rigid circuit boards.

[0070] Figure 5 is a schematic diagram of the internal structure of an optical module provided according to some embodiments of the present disclosure. As shown in Figure 5, in some embodiments, a light source 500 is disposed on the side of the optical chip 400. Light from the light source 500 is emitted from the side and coupled into the optical chip 400. The light source 500 serves as an external light source for the optical chip 400, and the light emitted by the light source 500 enters the optical chip 400. The light source 500 can optionally be a laser box, which encapsulates a laser. The laser generates a laser beam, and the light source 500 is used to transmit laser light to the optical chip 400. Lasers, due to their excellent single-wavelength characteristics and wavelength tuning properties, are the preferred light source for optical modules and even optical fiber transmission. Other types of light, such as LEDs, are generally not used in common optical communication systems. Even if such light sources are used in specific optical communication systems, their light source characteristics and chip components differ significantly from those of lasers. This results in significant technical differences between optical modules using lasers and those using other light sources. Those skilled in the art generally do not consider these two types of optical modules to be technically instructive for each other.

[0071] The light emitted by the light source 500 is light that does not carry data. This light that does not carry data is the light to be modulated. The light to be modulated enters the optical chip 400, and the optical chip 400 performs phase modulation on it to load the electrical signal into the light to obtain light carrying data, that is, to generate an optical transmission signal, thereby realizing the transmission of the optical signal; similarly, external light enters the optical chip 400, and the optical chip 400 demodulates it, thereby realizing the reception of the optical signal.

[0072] In some embodiments, the optical chip 400 is a silicon photonic chip, i.e., the optical chip 400 is formed by encapsulating silicon materials. The silicon photonic chip includes a Mach-Zehnder modulator (MZM), which integrates a silicon photonic phase modulator (SiPM) for optical signal modulation and demodulation. Because SiPM chips are easily etched, other functional components such as optical splitters, combiners, mixers, and photodetectors can be integrated within them, thereby achieving more functionality.

[0073] Figure 6 is a schematic diagram of the layout of a silicon photonic chip provided according to some embodiments of the present disclosure. As shown in Figure 6, the silicon photonic chip integrates multiple channels, each of which includes a silicon photonic phase modulator 410, a thermal phase adjuster 420, etc., each of which is formed by encapsulating silicon materials and is connected to each other via silicon waveguides.

[0074] However, the fundamental properties of silicon materials lead to drawbacks in optical modulator implementation, such as relatively low modulation efficiency, high capacitance, limited bandwidth, and high optical loss. Consequently, because silicon photonic phase modulators operate based on carriers, current long-haul 400G optical modules can only achieve transmission rates of 50-60Gbaud per channel. However, in next-generation optical modules for 1.6-3.2T PAM short-haul transmission and 800G-3.2T coherent long-haul transmission, transmission rates per channel within the module will need to exceed 100Gbaud, necessitating a silicon photonic phase modulator with a modulation rate exceeding 100Gbaud. However, when the modulation rate of a silicon photonic phase modulator approaches 100Gbaud, the driver's output voltage swing will be high, resulting in increased driver power consumption.

[0075] In some embodiments, the optical chip 400 is a hybrid InP / Si optical chip, that is, the optical chip 400 is formed by hybrid packaging of silicon material and InP material. Figure 7 is a schematic layout diagram of a hybrid InP / Si optical chip provided according to some embodiments of the present disclosure. As shown in Figure 7, the hybrid InP / Si optical chip includes multiple channels, each channel includes an InP phase modulator 430, a thermal phase regulator 420, etc., the InP phase modulator 430 is formed by packaging InP material, and the thermal phase regulator 420, etc. are formed by packaging silicon material. The InP phase modulator 430, the thermal phase regulator 420, etc. are connected to each other through silicon waveguides to form a high-traveling-wave MZM. The hybrid InP / Si optical chip provided in the embodiment of the present disclosure realizes the hybrid integration of Si material and InP material, so as to utilize InP material to provide high-speed modulation and Si material to provide highly integrated silicon optical circuits, so that the optical chip 400 can have the high-speed modulation characteristics of InP material, so that the optical chip 400 can meet the needs of high baud rate modulation.

[0076] In some embodiments, hybrid InP / Si optical chips are fabricated by bonding an InP platform formed of InP material to a Si platform formed of Si material. An InP phase modulator is then formed on the bonded InP platform, and a silicon optical circuit is then formed on the bonded Si platform. However, a large coefficient of thermal expansion (CTE) mismatch easily exists between the InP and Si platforms, resulting in concentrated thermal stress. Furthermore, InP-based materials are brittle, and any mechanical and thermal stresses can cause reliability issues in terms of temperature and aging, hindering the use of hybrid InP / Si optical chips.

[0077] Figure 8 is a schematic diagram (I) of a partial structure of a hybrid InP / Si optical chip provided according to some embodiments of the present disclosure, and Figure 9 is a schematic diagram (II) of a partial structure of a hybrid InP / Si optical chip provided according to some embodiments of the present disclosure. Figures 8 and 9 illustrate the structure of an InP phase modulator 430 in a hybrid InP / Si optical chip. As shown in Figures 8 and 9, the hybrid InP / Si optical chip includes an InP region 431 and a Si platform 460. The InP region 431 is located within the Si platform 460 such that the Si platform 460 surrounds the InP region 431 from the front, back, left, right, and bottom. An InP waveguide 432 is disposed within the InP region 431, extending from one end of the InP region 431 to the other end. An RF pad 440 is disposed on one side of the InP region 431 and is located on top of the Si platform 460, i.e., the RF pad 440 is located outside the InP region 431. The RF pad 440 is used to electrically connect to a driver to input a RF electrical signal.

[0078] In some embodiments, when a hybrid InP / Si optical chip includes multiple channels, the InP / Si optical chip will have multiple pairs of InP phase modulators 430 having the structural shapes shown in Figures 8 and 9. Exemplarily, the multiple pairs of InP phase modulators 430 are arranged side by side.

[0079] In some embodiments, RF pad 440 includes a first RF pad 441 and a second RF pad 442. Both first RF pad 441 and second RF pad 442 are located outside InP region 431. First RF pad 441 and second RF pad 442 are insulated from each other and spaced apart. For example, first RF pad 441 and second RF pad 442 are disposed side by side on one side of InP region 431.

[0080] A radio frequency traveling waveguide 450 is disposed on top of the hybrid InP / Si optical chip. One end of the radio frequency traveling waveguide 450 is connected to the radio frequency pad 440. The radio frequency traveling waveguide 450 extends above the InP waveguide 432 and across the InP region 431 to the other side of the InP region 431. The radio frequency traveling waveguide 450 is used to transmit radio frequency electrical signals, thereby transmitting the radio frequency electrical signals input through the radio frequency pad 440 to the top of the InP waveguide 432. Exemplarily, the width of the radio frequency traveling waveguide 450 is smaller than the width of the radio frequency pad 440.

[0081] In some embodiments, the RF traveling waveguide 450 includes a first RF electrode 450a and a second RF electrode 450b. The first RF electrode 450a extends across the InP region 431 along one side of the top of the InP waveguide 432, and the second RF electrode 450b extends across the InP region 431 along the other side of the top of the InP waveguide 432. The first RF electrode 450a extends from one side outside the InP region 431 to the other side outside the InP region 431, and one end of the first RF electrode 450a is connected to the first RF pad 441. The second RF electrode 450b extends from one side outside the InP region 431 to the other side outside the InP region 431, and one end of the second RF electrode 450b is connected to the second RF pad 442.

[0082] In some embodiments, a middle portion of the first RF electrode 450 a is located on one side of a top edge of the InP waveguide 432 , and a middle portion of the second RF electrode 450 b is located on the other side of the top edge of the InP waveguide 432 .

[0083] In some embodiments, coupling electrodes 433 are disposed above the InP waveguide 432. The coupling electrodes 433 appear in pairs and are electrically connected to the RF traveling waveguide 450. The paired coupling electrodes 433 are used to couple the RF electrical signal transmitted from the RF traveling waveguide 450 to the top of the InP waveguide 432 into the InP waveguide 432. Exemplarily, multiple pairs of coupling electrodes 433 are disposed above the InP waveguide 432 and arranged from one end to the other of the InP waveguide 432. Each pair of coupling electrodes 433 is respectively connected to the RF traveling waveguide 450, and adjacent pairs of coupling electrodes 433 are spaced apart.

[0084] In some embodiments, each pair of coupling electrodes 433 is located between the first RF electrode 450a and the second RF electrode 450b, one electrode in each pair of coupling electrodes 433 is electrically connected to the first RF electrode 450a, and the other electrode is electrically connected to the second RF electrode 450b, and there is a gap between the two electrodes in each pair of coupling electrodes 433.

[0085] In some embodiments, each pair of coupling electrodes 433 includes a first electrode 4331 and a second electrode 4332, each of which is a "T"-shaped electrode. The first electrode 4331 and the second electrode 4332 are positioned above the InP waveguide 432. The top of the first electrode 4331 and the top of the second electrode 4332 are positioned opposite each other with a gap therebetween. The bottom of the first electrode 4331 is electrically connected to the first RF electrode 450a, and the bottom of the second electrode 4332 is electrically connected to the second RF electrode 450b. The "T"-shaped electrode pair, including the first electrode 4331 and the second electrode 4332, is positioned above the InP waveguide 432 to slow down the microwaves of the RF electrical signal, facilitating coupling of the RF electrical signal into the InP waveguide 432.

[0086] In the InP phase modulator 430, an InP-MQW optical waveguide can have high-speed modulation efficiency with good quantum basis effect, realize high bandwidth of the InP-based traveling waveguide MZM, and thus meet the high-speed requirements of the optical module.

[0087] A DC bias pad 461 is also provided outside the InP region 431. This DC bias pad 461 is located on the Si platform 460 and is electrically connected to the InP waveguide 432 for providing a bias current to the PN junction in the InP waveguide 432. Exemplarily, a connecting waveguide 434 and a bias input electrode 462 are provided on the other side of the InP waveguide 432. The bias input electrode 462 is located outside the InP region 431. The connecting waveguide 434 is made of InP material, with a portion located in the InP region 431 and a portion located outside the InP region 431. One end of the connecting waveguide 434 is connected to the InP waveguide 432, and the other end of the connecting waveguide 434 is connected to one end of the bias input electrode 462. The other end of the bias input electrode 462 is connected to the DC bias pad 461. Bias input electrode 462 is narrower than DC bias pad 461 and serves to bridge the gap between DC bias pad 461 and connecting waveguide 434. Bias input electrode 462 couples the bias current input via DC bias pad 461 to connecting waveguide 434, which then loads the bias current onto InP waveguide 432 via connecting waveguide 434. Input electrode 462 is located on Si platform 460, and connecting waveguide 434 extends from InP region 431 to Si platform 460.

[0088] In some embodiments, the connecting waveguide 434 first extends along the length of the InP waveguide 432 to the Si platform 460, and then extends within the Si platform 460 toward the DC bias pad 461. Of course, to properly arrange the components on the Si platform 460, the DC bias pad 461 can be positioned perpendicular to the length of the InP waveguide 432. After extending to the position on the Si platform 460 corresponding to the DC bias pad 461, the connecting waveguide 434 can turn 90 degrees and extend until it connects to the input electrode 462.

[0089] In some embodiments, an end pad 463 is disposed outside the InP region 431 and connected to the other end of the RF traveling waveguide 450. In some embodiments, the end pad 463 connects the first RF electrode 450a and the second RF electrode 450b, forming a closed loop.

[0090] In the embodiment of the present disclosure, the InP area 431 is a prohibited area in the hybrid circuit layout of the hybrid InP / Si optical chip. No devices requiring bonding, such as pads, are provided in the InP area 431 to avoid any bonding, mechanical and thermal stresses and eliminate problems caused by temperature and aging.

[0091] FIG10 is a schematic diagram of the structure of a first RF electrode provided according to some embodiments of the present disclosure, and FIG10 illustrates the structural form of a first RF electrode. As shown in FIG10 , the first RF electrode 450a includes a parallel section 452. The parallel section 452 is disposed on one side of the upper edge of the InP waveguide 432. The side of the parallel section 452 is connected to the bottom of the coupling electrode 433. The parallel section 452 facilitates coupling and transmitting RF electrical signals to each coupling electrode 433, so as to passively couple the RF electrical signals to the InP waveguide 432 through each coupling electrode 433. Exemplarily, the width of the parallel section 452 is smaller than the width of the first RF pad 441, and the parallel section 452 is a straight, thin strip-shaped structure.

[0092] In some embodiments, the first RF electrode 450a includes a first connecting segment 451 and a second connecting segment 453. One end of the parallel segment 452 is connected to the first connecting segment 451, and the other end of the parallel segment 452 is connected to the second connecting segment 453. One end of the first connecting segment 451 is connected to the first RF pad 441, and the other end of the first connecting segment 451 is connected to one end of the parallel segment 452. The first connecting segment 451 is used to achieve a transition from the first RF pad 441 to the RF traveling waveguide of the parallel segment 452. One end of the second connecting segment 453 is connected to the other end of the parallel segment 452, and the other end of the second connecting segment 453 is connected to the end pad 463. The second connecting segment 453 is used to achieve a transition from the parallel segment 452 to the end of the first RF electrode 450a. The first RF electrode 450a is designed to accommodate the difference in dielectric constant between InP and SiO2 in the Si platform 460, ensuring signal integrity at transmission rates exceeding 100 Gbaud.

[0093] In some embodiments, the first connecting segment 451 includes a first transition region 4512, wherein the width of one end of the first transition region 4512 is greater than the width of the other end. The first transition region 4512 is used to adjust the width of one end of the first RF electrode 450a. The first transition region 4512 facilitates the coupling and transmission of RF electrical signals from the RF pad to the RF traveling waveguide. Exemplarily, the width of the first transition region 4512 gradually decreases from one end to the other. In other words, the width of the first transition region 4512 at the end facing the first RF pad 441 is greater than the width of the first transition region 4512 at the end facing the parallel segment 452.

[0094] In some embodiments, the first connecting section 451 includes a second transition region 4514, where the width of one end of the second transition region 4514 is greater than the width of the other end. The second transition region 4514 is used to achieve a transition from the width of the first RF electrode 450a to the parallel section 452. The second transition region 4514 facilitates the coupling and transmission of RF electrical signals from the RF pad to the RF traveling waveguide. Exemplarily, the width of the second transition region 4514 gradually decreases from one end to the other; in other words, the width of the second transition region 4514 on the end facing the first RF pad 441 is greater than the width of the second transition region 4514 on the end facing the parallel section 452.

[0095] In some embodiments, the first connecting section 451 includes a first connecting area 4511 , one end of the first connecting area 4511 is connected to the first RF pad 441 , and the other end of the first connecting area 4511 is connected to one end of the first transition area 4512 . The first connecting area 4511 is used to facilitate the connection of the first transition area 4512 to the first RF pad 441 .

[0096] In some embodiments, the first connecting section 451 includes a second connecting area 4513 , which is connected to one end of the second transition area 4514 . The second connecting area 4513 is used to facilitate the connection of the second transition area 4514 to the first transition area 4512 .

[0097] In some embodiments, the first connecting section 451 includes a first connecting region 4511, a first transition region 4512, a second connecting region 4513, and a second transition region 4514. One end of the first connecting region 4511 is connected to the first RF pad 441, the other end of the first connecting region 4511 is connected to one end of the first transition region 4512, the other end of the first transition region 4512 is connected to one end of the second connecting region 4513, the other end of the second connecting region 4513 is connected to one end of the second transition region 4514, and one end of the second transition region 4514 is connected to one end of the parallel section 452. The width of one end of the first transition region 4512 is greater than the width of the other end of the first transition region 4512, and the width of the first transition region 4512 gradually changes from one end to the other. The width of one end of the second transition region 4514 is greater than the width of the other end of the second transition region 4514, and the width of the second transition region 4514 gradually changes from one end to the other. The first connection region 4511 is located above the Si platform 460 ; one end of the first transition region 4512 is located above the Si platform 460 and the other end is located above the InP region 431 ; the second connection region 4513 and the second transition region 4514 are located above the InP region 431 .

[0098] In some embodiments, the second connecting segment 453 includes a third transition region 4531. The width of one end of the third transition region 4531 is smaller than the width of the other end. One end of the third transition region 4531 connects to the other end of the parallel segment 452. The third transition region 4531 is used to adjust the width from the parallel segment 452 to the other end of the first RF electrode 450a, thereby facilitating adjustment of the width of the other end of the first RF electrode 450a and ensuring the coupling and transmission performance of the RF electrical signal to the RF traveling waveguide. Exemplarily, the width of the third transition region 4531 gradually increases from one end to the other.

[0099] In some embodiments, the second connecting section 453 includes a fourth transition region 4533. The width of one end of the fourth transition region 4533 is smaller than the width of the other end of the fourth transition region 4533. The fourth transition region 45331 is used to adjust the width from the parallel section 452 to the other end of the first RF electrode 450a, thereby facilitating adjustment of the width of the other end of the first RF electrode 450a and ensuring the coupling and transmission performance of the RF electrical signal to the RF traveling waveguide. Exemplarily, the width of the fourth transition region 4533 gradually increases from one end to the other.

[0100] In some embodiments, the second connecting segment 453 includes a third transition region 4531, a third connecting region 4532, and a fourth transition region 4533. One end of the third transition region 4531 connects to the other end of the parallel segment 452, and the other end of the third transition region 4531 connects to one end of the third connecting region 4532. The other end of the third connecting region 4532 connects to one end of the fourth transition region 4533. The width of one end of the third transition region 4531 is smaller than the width of the other end of the third transition region 4531, and the width of the third transition region 4531 gradually changes from one end to the other. The width of one end of the fourth transition region 4533 is smaller than the width of the other end of the fourth transition region 4533, and the width of the fourth transition region 4533 gradually changes from one end to the other. The third transition region 4531 and the third connecting region 4532 are located above the InP region 431. One end of the fourth transition region 4533 is located above the InP region 431, and the other end of the fourth transition region 4533 is located above the Si platform 460.

[0101] In some embodiments, the second RF electrode 450b has the same or similar structural morphology as the first RF electrode 450a. For example, the second RF electrode 450b is symmetrically positioned with the first RF electrode 450a at the edge above the InP waveguide 432. The portions of the first and second RF electrodes 450a, 450b extending from the Si platform 460 to the InP region 431, gradually change in morphology to accommodate both InP waveguides 432 with and without PN junctions, which is crucial for ensuring the modulation rate of the phase modulator.

[0102] In some embodiments, the hybrid InP / Si optical chip further includes a first resistor 464, which is located outside the InP region 431. One end of the first resistor 464 is electrically connected to the other end of the first RF electrode 450a, and the other end of the first resistor 464 is electrically connected to the terminal pad 463. The first resistor 464 is used to match the impedance of the transmission circuit of the first RF electrode 450a. Exemplarily, the first resistor 464 is an on-chip resistor.

[0103] In some embodiments, the hybrid InP / Si optical chip further includes a second resistor 465 located outside the InP region 431. One end of the second resistor 465 is electrically connected to the second RF electrode 450b, and the other end of the second resistor 465 is electrically connected to the terminal pad 463. The second resistor 465 is used to match the impedance of the transmission circuit of the second RF electrode 450b. Exemplarily, the second resistor 465 is an on-chip resistor.

[0104] In some embodiments, the hybrid InP / Si optical chip further includes a first resistor 464, a second resistor 465, and a capacitor 466. The first resistor 464 and the second resistor 465 are on-chip resistors, and the capacitor 466 is an on-chip capacitor. One end of the first resistor 464 is electrically connected to the other end of the first RF electrode 450a, and the other end of the first resistor 464 is electrically connected to the terminal pad 463. One end of the second resistor 465 is electrically connected to the second RF electrode 450b, and the other end of the second resistor 465 is electrically connected to the terminal pad 463. One end of the capacitor 466 is connected between the other end of the first resistor 464 and the other end of the second resistor 465, and the other end of the capacitor 466 is grounded. The first resistor 464, the second resistor 465, and the capacitor 466 form a matching circuit for matching the transmission circuits of the first RF electrode 450a and the second RF electrode 450b, ensuring the performance of coupling RF electrical signals from the first RF electrode 450a and the second RF electrode 450b to the InP waveguide 432. The first resistor 464 , the second resistor 465 and the capacitor 466 are located outside the InP region 431 , which can effectively reduce the adverse effects of mechanical stress, thermal stress, etc. generated by the first resistor 464 , the second resistor 465 and the capacitor 466 on the InP waveguide 432 .

[0105] In some embodiments, the first resistor 464 and the second resistor 465 are disposed between the other end of the first RF electrode 450a and the other end of the second RF electrode 450b. The distance between the other end of the first RF electrode 450a and the other end of the second RF electrode 450b is greater than the distance between one end of the first RF electrode 450a and one end of the second RF electrode 450b, thereby facilitating the placement of the first resistor 464 and the second resistor 465.

[0106] Figure 11 is an enlarged cross-sectional view 1 of a hybrid InP / Si optical chip provided according to some embodiments of the present disclosure, Figure 12 is an enlarged cross-sectional view 2 of a hybrid InP / Si optical chip provided according to some embodiments of the present disclosure, Figure 13 is an enlarged cross-sectional view 3 of a hybrid InP / Si optical chip provided according to some embodiments of the present disclosure, and Figure 14 is an enlarged cross-sectional view 4 of a hybrid InP / Si optical chip provided according to some embodiments of the present disclosure; Figure 11 shows the cross-sectional structure at A in Figure 8, Figure 12 shows the interface structure at B in Figure 8, Figure 13 shows the cross-sectional structure at C in Figure 8, and Figure 14 shows the cross-sectional structure at D in Figure 8. Among them: Figure 11 shows the cross-sectional structure of a hybrid InP / Si optical chip outside the InP area, and the cross section does not intercept the InP area; Figure 12 shows the cross-sectional structure of a hybrid InP / Si optical chip at the edge of one end of the InP waveguide, and the cross section intercepts the InP area but does not intercept the InP waveguide; Figure 13 shows the cross-sectional structure of a hybrid InP / Si optical chip on the InP waveguide, and the cross section intercepts the InP waveguide; Figure 14 shows the structure of a hybrid InP / Si optical chip outside the other end of the InP waveguide, and the cross section does not intercept the InP waveguide; Figures 11-13 show in detail the main cross-sectional structure of an InP phase modulator 430.

[0107] As shown in Figure 11, Si platform 460 includes a substrate layer 4601, a BOX layer 4602 located above substrate layer 4601, and a Si waveguide layer 4603 and a SiO2 layer 4604 located above BOX layer 4602. SiO2 layer 4604 wraps around Si waveguide layer 4603, which includes a strip-shaped Si waveguide. The top of SiO2 layer 4604 supports a first RF electrode 450a and a second RF electrode 450b. The Si waveguides in Si waveguide layer 4603 include a light input Si waveguide for inputting light. Exemplarily, substrate layer 4601 is epitaxially grown using Si material, and BOX layer 4602 is epitaxially grown using SiO2 material.

[0108] In some embodiments, the cross-section of the light input Si waveguide is a "convex" structure, that is, the size of the top of the light input Si waveguide is smaller than the size of the bottom of the light input Si waveguide, which facilitates coupling the light input through the light input Si waveguide to the InP waveguide 432.

[0109] As shown in FIG12 , the InP waveguide 432 is embedded in the SiO 2 layer 4604 , and the Si waveguide in the Si waveguide layer 4603 extends below one end of the InP waveguide 432 . The Si waveguide layer 4603 is used to transmit light to one end of the InP waveguide 432 and couple light into the InP waveguide 432 .

[0110] As shown in Figures 12 and 13, the InP waveguide 432 includes an n-InP layer 4321, and a first n-InP protrusion 4321a and a second n-InP protrusion 4321b are arranged on the top of the n-InP layer 4321, with a gap set between the first n-InP protrusion 4321a and the second n-InP protrusion 4321b. A first i-InP layer 4322, a quantum well (QW) layer 4323, a second i-InP layer 4324 and a p-InP layer 4325 are arranged above the first n-InP protrusion 4321a, and a first i-InP layer 4322, a quantum well (QW) layer 4323, a second i-InP layer 4324 and a p-InP layer 4325 are arranged above the second n-InP protrusion 4321b. A coupling electrode 433 is arranged above the p-InP layer 4325. Illustratively, a first electrode 4331 is disposed on the p-InP layer 4325 above the first n-InP protrusion 4321a, and a second electrode 4332 is disposed on the p-InP layer 4325 above the second n-InP protrusion 4321b. The spaces between the first i-InP layer 4322, the quantum well (QW) layer 4323, the second i-InP layer 4324, and the p-InP layer 4325 above the first n-InP protrusion 4321a and the second n-InP protrusion 4321b are filled with SiO2 material. Consequently, the InP waveguide 432 is wrapped by the SiO2 layer 4604, forming two long strips of waveguide structure.

[0111] In some embodiments, the first RF electrode 450a is located on a side of the first electrode 4331 away from the second electrode 4332, and the second RF electrode 450b is located on a side of the second electrode 4332 away from the first electrode 4331; the first RF electrode 450a is connected to the first electrode 4331, and the second RF electrode 450b is connected to the second electrode 4332.

[0112] In some embodiments, the RF electrical signal transmitted through the first RF electrode 450a and the second RF electrode 450b is coupled into the InP waveguide 432 through the first electrode 4331 and the second electrode 4332, and the InP waveguide 432 forms a PN junction. Under the action of the electric field formed by the RF electrical signal, the carrier phase of the PN junction changes, causing the refractive index of the light wave transmitted through the Si waveguide coupling to the InP waveguide 432 to change, thereby changing the phase of the light wave and realizing modulation of the light wave.

[0113] As shown in Figure 14, a Si waveguide layer 4603 is disposed below the other end of InP waveguide 432. Si waveguide layer 4603 includes a strip-shaped Si waveguide. The Si waveguides in Si waveguide layer 4603 include a light output Si waveguide, which extends from below the other end of InP waveguide 432 and away from InP waveguide 432. Lightwaves modulated by InP waveguide 432 are coupled into the Si waveguides of Si waveguide layer 4603 for transmission through the Si waveguides.

[0114] In some embodiments, the cross-section of the light output Si waveguide in the Si waveguide layer 4603 is a "convex" structure, that is, the size of the top of the light output Si waveguide is smaller than the size of the bottom of the light output Si waveguide, which facilitates coupling the light modulated by the InP waveguide 432 into the light output Si waveguide.

[0115] In some embodiments of the present application, when preparing a hybrid InP / Si optical chip, a Si platform 460 is prepared and a groove is formed on the Si platform 460; an InP material including an n-InP layer 4321, a first i-InP layer 4322, a quantum hydrazine layer 4323, a second i-InP layer 4324 and a p-InP layer 4325 is set in the groove, and the InP material is processed to form an InP waveguide 432; SiO2 material is filled around the InP waveguide 432 so that a continuous SiO2 layer 4604 is wrapped around the InP waveguide 432; a coupling electrode 433 is formed on the top of the InP waveguide 432, and a first RF electrode 450a and a second RF electrode 450b are formed on the SiO2 layer 4604.

[0116] Figure 15 is an equivalent circuit diagram of a hybrid InP / Si optical chip according to some embodiments of the present disclosure. As shown in Figure 15 , each pair of coupling electrodes 433 and the InP waveguide 432 below it form a pair of diodes with opposing cathodes. In some embodiments, the cathodes of the diode pairs are connected to a bias voltage.

[0117] As shown in FIG15 , in the hybrid InP / Si optical chip provided by the embodiment of the present disclosure, no structures such as bonding pads are provided in the InP region 431, so that there is a relatively sufficient distance between the bonding pads and other structures and the InP waveguide 432. The RF traveling waveguide 450 is used to couple the RF electrical signal to the InP waveguide 432, which can effectively prevent the stress generated by the bonding pad from affecting the InP waveguide 432 in the InP region 431. This enables the use of InP material in the Si platform, thereby improving the modulation rate and reliability of the phase modulator. Moreover, in the hybrid InP / Si optical chip, in the InP phase modulator formed by the InP material, a traveling waveguide with a T-shaped guide rail structure is used for high-speed and efficient modulation with phase and impedance matching.

[0118] FIG16 is a first schematic diagram of the structure of a hybrid InP / Si optical chip assembly according to some embodiments of the present disclosure, and FIG17 is a second schematic diagram of the structure of a hybrid InP / Si optical chip assembly according to some embodiments of the present disclosure. FIG16 and FIG17 illustrate the external structure of a hybrid InP / Si optical chip assembly. As shown in FIG16 and FIG17 , a hybrid InP / Si optical chip assembly 700 includes a substrate 710, a driver 720 and a hybrid InP / Si optical chip 730 are disposed above the substrate 710, and an optical fiber assembly 740 is connected to the side of the hybrid InP / Si optical chip 730. The driver 720 and the hybrid InP / Si optical chip 730 are respectively connected to the substrate 710 by welding, and the driver 720 is electrically connected to the hybrid InP / Si optical chip 730 via a high-frequency transmission line on the substrate 710. The hybrid InP / Si optical chip 730 is the hybrid InP / Si optical chip provided in the above-mentioned embodiments, and InP material is disposed within the Si platform to form an InP phase modulator. Exemplarily, the driver 720 and the hybrid InP / Si optical chip 730 are connected to the substrate via solder balls respectively. One end of the high-frequency transmission line on the substrate 710 is connected to the driver 720 and the other end is connected to the RF pad on the hybrid InP / Si optical chip.

[0119] In the hybrid InP / Si optical chip assembly provided in the disclosed embodiments, the bonding and termination of the hybrid InP / Si optical chip are both located outside the InP phase modulator, helping to reduce the effects of mechanical and thermal stress on the InP phase modulator. The optical fiber assembly 740 is also located outside the InP phase modulator, eliminating stress generated by the connection to the optical fiber assembly 740 and thereby reducing the effects of the connection to the InP phase modulator. The hybrid InP / Si optical chip assembly can be used in optical modules.

[0120] In some embodiments, other devices made of InP materials, such as lasers, semiconductor optical amplifiers (SOAs), etc., can also be provided in the hybrid InP / Si optical chip assembly. Lasers, SOAs, etc. made of InP materials can be integrated into the InP region where the InP phase modulator is located or the InP region outside the InP phase modulator integrated in the Si platform. The specific settings can refer to the settings of the InP phase modulator in the Si platform, which helps to reduce the influence of thermal stress and mechanical stress on the corresponding InP region, and facilitates the integration of lasers, SOAs, etc. made of InP materials into the platform.

[0121] Based on the hybrid InP / Si optical chip provided in the embodiment of the present disclosure, a method for preparing a hybrid InP / Si optical chip is also provided in the embodiment of the present disclosure. The method for preparing a hybrid InP / Si optical chip provided in the embodiment of the present disclosure is used to facilitate the preparation of the hybrid InP / Si optical chip provided in the above embodiment. Figure 18 is a flow chart of a method for preparing a hybrid InP / Si optical chip provided in accordance with some embodiments of the present disclosure. Figure 18 shows the cross-sectional structure of the hybrid InP / Si optical chip formed in each step. As shown in Figure 18, the method for preparing a hybrid InP / Si optical chip provided in the embodiment of the present disclosure includes:

[0122] S100: forming a first substrate, wherein the first substrate comprises a substrate layer and a BOX layer, wherein the BOX layer is located above the substrate layer.

[0123] A substrate layer 4601 is epitaxially grown, and a BOX layer 4602 is grown on the substrate layer 4601. The substrate layer 4601 is epitaxially grown using Si material, and the BOX layer 4602 is epitaxially grown using SiO2 material.

[0124] S200: forming a Si waveguide layer above the BOX layer, and etching the Si waveguide layer to form an input Si waveguide and an output Si waveguide, with a gap between the input Si waveguide and the output Si waveguide.

[0125] A Si waveguide layer 4603 is epitaxially grown on the BOX layer 4602. A mask is then used to form a Si waveguide pattern on the Si waveguide layer 4603. Etching then forms the input and output Si waveguides. A gap is provided between the input and output Si waveguides, and an InP waveguide 432 is positioned above the gap. The input Si waveguide is used to input light and transmit it to the InP waveguide 432. The output Si waveguide is used to output light and transmit the light output from the InP waveguide 432.

[0126] In some embodiments, the cross-section of the input Si waveguide and the output Si waveguide is a "convex" structure, where the size of the top is smaller than that of the bottom, and can be formed by secondary etching.

[0127] S300: forming a first SiO2 layer around the etched Si waveguide layer, wherein the first SiO2 layer fills the etched area of ​​the Si waveguide layer.

[0128] A first SiO2 layer 4604a is epitaxially grown so that the first SiO2 layer 4604a wraps around the side of the Si waveguide layer 4603 and the top of the Si waveguide layer 4603 is exposed.

[0129] S400: Disposing an InP bare chip above the first SiO2 layer, the InP bare chip including, from bottom to top, an n-InP layer, a first i-InP layer, a quantum hydrazine layer, a second i-InP layer, a p-InP layer, and a second substrate.

[0130] An InP die 432a is disposed on the first SiO2 layer 4604a. The InP die covers the space between the input Si waveguide and the output Si waveguide, and the ends of the input Si waveguide and the output Si waveguide are located below the ends of the InP die 432a.

[0131] The InP die 432a includes a second substrate 4320, on which are sequentially arranged a p-InP layer 4325, a second i-InP layer 4324, a quantum dot layer 4323, a first i-InP layer 4322, and an n-InP layer 4321. The InP die 432a is inverted onto the first SiO2 layer 4604a, with the n-InP layer contacting the top surface of the first SiO2 layer 4604a.

[0132] In some embodiments, the InP die 432 a may be formed by sequentially growing a p-InP layer 4325 , a second i-InP layer 4324 , a quantum dot layer 4323 , a first i-InP layer 4322 , and an n-InP layer 4321 on a second substrate 4320 .

[0133] S500: Etching the InP bare chip to form an InP waveguide, the bottom of the InP waveguide forms a first n-InP protrusion and a second n-InP protrusion on the top of the n-InP layer, a gap is formed between the first n-InP protrusion and the second n-InP protrusion, and the top of the first n-InP protrusion and the top of the second n-InP protrusion respectively support the first i-InP layer, the quantum hydrazine layer, the second i-InP layer and the p-InP layer.

[0134] The second substrate 4320 is first etched away, and then the InP waveguide 432 is formed. In some embodiments, the InP bare chip 432a can be etched to form a single InP waveguide 432, or multiple InP waveguides 432 can be formed. When etching the InP bare chip 432a to form a single InP waveguide 432, the etching depth reaches the n-InP layer 4321 but does not reach the first SiO2 layer 4604a, so that the n-InP layer 4321 forms a first n-InP protrusion 4321a and a second n-InP protrusion 4321b, with a gap between the first n-InP protrusion 4321a and the second n-InP protrusion 4321b. The first i-InP layer 4322, quantum hydrazine layer 4323, second i-InP layer 4324, and p-InP layer 4325 above the spacer are etched away to form a trench in the InP die 432a that reaches as deep as the n-InP layer 4321. The first i-InP layer 4322, quantum hydrazine layer 4323, second i-InP layer 4324, and p-InP layer 4325 above the side of the first n-InP protrusion 4321a and above the side of the second n-InP protrusion 4321b away from the spacer are also etched away, leaving only the first i-InP layer 4322, quantum hydrazine layer 4323, second i-InP layer 4324, and p-InP layer 4325 supported above the first n-InP protrusion 4321a and the second n-InP protrusion 4321b. When etching the InP bare chip 432 a to form a plurality of InP waveguides 432 , the etching is performed to the first SiO 2 layer 4604 a between adjacent InP waveguides 432 , so that the adjacent InP waveguides 432 are not connected.

[0135] S600: forming a second SiO2 layer on a side of the InP waveguide, wherein the first SiO2 layer and the second SiO2 layer form a SiO2 layer.

[0136] A second SiO2 layer 4604b is epitaxially grown, extending from the sides of InP waveguide 432 and filling the first n-InP protrusion 4321a and the second n-InP protrusion 4321b. First SiO2 layer 4604a and second SiO2 layer 4604b are joined to form SiO2 layer 4604, wrapping around InP waveguide 432 from below and along its sides.

[0137] In some embodiments, a top surface of the second SiO 2 layer 4604 b is flush with a top surface of the p-InP layer 4325 .

[0138] In some embodiments, before forming the second SiO2 layer, the p-InP layer 4325 is further etched to make the top of the p-InP layer 4325 larger than the bottom of the p-InP layer 4325. Exemplarily, inclined surfaces are formed on both sides of the p-InP layer 4325.

[0139] S700: Forming a radio frequency pad, a DC bias pad, a radio frequency traveling waveguide and an electrode on the top of the second SiO2 layer; wherein: the radio frequency pad is located on the side of one end of the InP waveguide, the radio frequency traveling waveguide is located on the side of the top edge of the InP waveguide, and one end of the radio frequency traveling waveguide is electrically connected to the radio frequency pad; the DC bias pad is located on the side of the other end of the InP waveguide, and the DC bias pad is electrically connected to the InP waveguide; the coupling electrode is located above the InP waveguide, and the coupling electrode is electrically connected to the radio frequency traveling waveguide.

[0140] The RF pad 440, DC bias pad 461, RF traveling waveguide 450 and coupling electrode 433 on the top of the second SiO2 layer 4604 are formed by electroplating. The coupling electrode 433 is located above the p-InP layer 4325, and the RF traveling waveguide 450 is located on the side above the p-InP layer 4325.

[0141] In some embodiments, a first resistor 464, a second resistor 465, a capacitor 466, and a terminal pad 463 are further formed on top of the second SiO2 layer 4604. The first resistor 464, the second resistor 465, the capacitor 466, and the terminal pad 463 can be formed by electroplating.

[0142] The specific form of the hybrid InP / Si optical chip prepared by the method for preparing the hybrid InP / Si optical chip provided in the embodiment of the present disclosure can refer to the structure of the hybrid InP / Si optical chip provided in the above embodiment of the present disclosure.

[0143] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. An optical module, comprising: Circuit boards; A hybrid InP / Si optical chip, electrically connected to the circuit board, configured to modulate and generate an optical signal; Among them, the hybrid InP / Si optical chip includes: A Si platform is integrated with a silicon photonic circuit; an InP region is formed inside the Si platform, and the InP region has no pad; a radio frequency pad and a direct current bias pad are arranged on the top of the Si platform, the radio frequency pad is located on one side of the InP region, and the direct current bias pad is located on the other side of the InP region; An InP phase modulator is located in the InP region; the InP phase modulator comprises an InP waveguide and a coupling electrode, the coupling electrode is arranged above the InP waveguide, and the InP waveguide is electrically connected to a DC bias pad; A radio frequency traveling waveguide has one end connected to the radio frequency pad and the other end extending through the top of the InP waveguide and extending to the other side of the InP region; the radio frequency traveling waveguide is electrically connected to the coupling electrode.

2. The optical module according to claim 1, wherein: The RF pad includes a first RF pad and a second RF pad, and the RF traveling waveguide includes a first RF electrode and a second RF electrode; one end of the first RF electrode is connected to the first RF pad, and one end of the second RF electrode is connected to the second RF pad; The middle of the first RF electrode is located above one edge of the InP waveguide, the middle of the second RF electrode is located above the other edge of the InP waveguide, and the first RF electrode and the second RF electrode correspond to electrodes connected to the top of the InP waveguide respectively.

3. The optical module according to claim 2, wherein: The first RF electrode includes a first connecting section, a parallel section, and a second connecting section, wherein the parallel section is located above an edge of one side of the InP waveguide; one end of the first connecting section is connected to the first RF pad, the other end of the first connecting section is connected to one end of the parallel section, the other end of the parallel section is connected to one end of the second connecting section, and the other end of the second connecting section is located outside the InP region; the first connecting section is configured as a transition connection from the first RF pad to the parallel section, and the second connecting section is configured as a transition connection from the parallel section to the end of the first RF electrode.

4. The optical module according to claim 1, wherein: The InP waveguide includes an n-InP layer, the n-InP layer includes a first n-InP protrusion and a second n-InP protrusion, and a gap is formed between the first n-InP protrusion and the second n-InP protrusion; A first i-InP layer, a quantum hydrazine layer, a second i-InP layer and a p-InP layer are respectively arranged on the top of the first n-InP protrusion and the second n-InP protrusion in sequence; the coupling electrode includes a first electrode and a second electrode; the first electrode is arranged on the p-InP layer above the first n-InP protrusion, and the second electrode is arranged on the p-InP layer above the second n-InP protrusion.

5. The optical module according to claim 3, wherein: The first connecting section includes a first connecting area, a first transition area, a second connecting area, and a second transition area; One end of the first connection region is connected to the first RF pad, the other end of the first connection region is connected to one end of the first transition region, the other end of the first transition region is connected to one end of the second connection region, the other end of the second connection region is connected to one end of the second transition region, and the other end of the second transition region is connected to one end of the parallel section; The first connection zone is located outside the InP region, one end of the first transition zone is located outside the InP region and the other end is located within the InP region, and the second connection zone and the second transition zone are located outside the InP region; the width of one end of the first transition zone is greater than the width of the other end of the first transition zone, and the width of one end of the second transition zone is greater than the width of the other end of the second transition zone.

6. The optical module according to claim 3, wherein: The second connecting section includes a third transition zone, a third connecting zone and a fourth transition zone; One end of the third transition zone is connected to the other end of the parallel section, the other end of the third transition zone is connected to one end of the third connection zone, the other end of the third connection zone is connected to one end of the fourth transition zone, and the other end of the fourth transition zone is connected to the end of the first RF electrode; The third transition zone and the third connection zone are located in the InP region, one end of the fourth transition zone is located in the InP region and the other end is located outside the InP region; the width of one end of the third transition zone is smaller than the width of the other end of the third transition zone, and the width of one end of the fourth transition zone is smaller than the width of the other end of the fourth transition zone.

7. The optical module according to claim 2, wherein: The hybrid InP / Si optical chip further includes a first resistor, a second resistor, a capacitor and an end pad located outside the InP region; One end of the first resistor is electrically connected to the other end of the first RF electrode, and the other end of the first resistor is electrically connected to the terminal pad; one end of the second resistor is electrically connected to the second RF electrode, and the other end of the second resistor is electrically connected to the terminal pad; one end of the capacitor is connected between the other end of the first resistor and the other end of the second resistor, and the other end of the capacitor is grounded.

8. The optical module according to claim 2, wherein: A Si waveguide is arranged in the Si platform, and the Si waveguide includes a light input Si waveguide and a light output Si waveguide; One end of the light input Si waveguide is located outside the InP region and extends below the InP waveguide, and the other end of the light input Si waveguide is located below one end of the InP waveguide, so that the light input Si waveguide couples unmodulated light to the InP waveguide; One end of the light output Si waveguide is located below the other end of the InP waveguide and extends in a direction away from the InP waveguide, so that the light modulated by the InP waveguide is coupled to the light output Si waveguide and output through the light output Si waveguide.

9. The optical module according to claim 1, wherein: The optical module also includes a hybrid InP / Si optical chip assembly, and the hybrid InP / Si optical chip assembly includes: A substrate, on which a high frequency transmission line is arranged; A driver, disposed on the substrate and connected to one end of the high-frequency transmission line; The hybrid InP / Si optical chip is arranged on the substrate and connected to the other end of the high-frequency transmission line.

10. An optical module, wherein: include: Circuit boards; a light source, electrically connected to the circuit board and configured to emit light that does not carry a signal; a hybrid InP / Si optical chip, electrically connected to the circuit board, configured to modulate light not carrying a signal to generate an optical signal; The hybrid InP / Si optical chip includes a Si platform; InP material is arranged in the Si platform, and the InP material forms an InP waveguide; a radio frequency pad, a DC bias pad, a radio frequency traveling waveguide and a coupling electrode are arranged on the top of the Si platform; the coupling electrode is located above the InP material, the middle of the radio frequency traveling waveguide is located at the edge of the top of the InP waveguide, and the coupling electrode is electrically connected to the radio frequency traveling waveguide; the radio frequency pad and the DC bias pad are located outside the InP waveguide and away from the top of the InP waveguide; the radio frequency pad is connected to one end of the radio frequency traveling waveguide, and the DC bias pad is coupled to the InP waveguide.

11. A method for preparing a hybrid InP / Si optical chip, wherein the hybrid InP / Si optical chip is used for modulating and generating an optical signal, the method comprising: forming a first substrate, wherein the first substrate comprises a substrate layer and a BOX layer, wherein the BOX layer is located above the substrate layer; A Si waveguide layer is formed above the BOX layer, and the Si waveguide layer is etched to form an input Si waveguide and an output Si waveguide. There is a gap between the input Si waveguide and the output Si waveguide; forming a first SiO2 layer around the etched Si waveguide layer, wherein the first SiO2 layer fills the etched area in the Si waveguide layer; An InP bare chip is arranged above the first SiO2 layer, wherein the InP bare chip comprises, from bottom to top, an n-InP layer, a first i-InP layer, a quantum hydrazine layer, a second i-InP layer, a p-InP layer, and a second substrate; Etching the InP bare chip to form an InP waveguide, wherein the bottom of the InP waveguide forms a first n-InP protrusion and a second n-InP protrusion on the top of the n-InP layer, a gap is formed between the first n-InP protrusion and the second n-InP protrusion, and the top of the first n-InP protrusion and the top of the second n-InP protrusion respectively support the first i-InP layer, the quantum hydrazine layer, the second i-InP layer and the p-InP layer; forming a second SiO2 layer on the side of the InP waveguide, wherein the first SiO2 layer and the second SiO2 layer form a SiO2 layer; A radio frequency pad, a DC bias pad, a radio frequency waveguide and a coupling electrode are formed on the top of the second SiO2 layer; wherein: the radio frequency pad is located on the side of one end of the InP waveguide, the radio frequency waveguide is located on the side of the top edge of the InP waveguide, and one end of the radio frequency waveguide is electrically connected to the radio frequency pad; the DC bias pad is located on the side of the other end of the InP waveguide, and the DC bias pad is electrically connected to the InP waveguide; the coupling electrode is located above the InP waveguide, and the coupling electrode is electrically connected to the radio frequency waveguide.

12. The preparation method according to claim 11, wherein The preparation method further comprises: A p-InP layer, a second i-InP layer, a quantum dot layer, a first i-InP layer and an n-InP layer are sequentially grown on the second substrate to form an InP bare chip.

13. The preparation method according to claim 11, wherein The RF pad includes a first RF pad and a second RF pad, and the RF traveling waveguide includes a first RF electrode and a second RF electrode; one end of the first RF electrode is connected to the first RF pad, and one end of the second RF electrode is connected to the second RF pad; The middle of the first RF electrode is located above one edge of the InP waveguide, the middle of the second RF electrode is located above the other edge of the InP waveguide, and the first RF electrode and the second RF electrode correspond to electrodes connected to the top of the InP waveguide respectively.

14. The preparation method according to claim 13, wherein: The preparation method further comprises: forming a first resistor, a second resistor, a capacitor and an end pad on the top of the second SiO2 layer, wherein the first resistor, the second resistor, the capacitor and the end pad are located on the side of the top of the InP waveguide; One end of the first resistor is electrically connected to the other end of the first RF electrode, and the other end of the first resistor is electrically connected to the terminal pad; one end of the second resistor is electrically connected to the second RF electrode, and the other end of the second resistor is electrically connected to the terminal pad; one end of the capacitor is connected between the other end of the first resistor and the other end of the second resistor, and the other end of the capacitor is grounded.

15. The preparation method according to claim 11, wherein The input Si waveguide extends from the edge of one end of the BOX layer to the edge of one end of the bottom of the n-InP layer; The output Si waveguide extends from the edge of the other end of the bottom of the n-InP layer to the edge of the other end of the BOX layer; The coupling electrode is a "T"-shaped electrode, and the bottom of the coupling electrode is connected to the radio frequency traveling waveguide.

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