Semiconductor light receiving element, optical line terminating device, multi-value intensity modulation transmitting / receiving device, digital coherent receiving device, radio-over-fiber system, spad sensor system, and lidar device

Abstract

A semiconductor light receiving element (100) according to the present disclosure comprises: an n-type InP substrate (1); an n-type semiconductor layer (2) formed on the n-type InP substrate (1); a multiplication layer (3) formed on the n-type semiconductor layer (2) and having an InAlAs digital alloy structure in which InAs layers having a layer thickness of 40-170 nm and AlAs layers are alternately laminated; a p-type field relaxation layer (4) formed on the multiplication layer (3) and composed of InP or InAlAs; and an InGaAs light absorption layer (5) formed on the p-type field relaxation layer (4).

Description

Semiconductor photodetectors, optical line terminals, multilevel intensity modulation transmitters and receivers, digital coherent receivers, radio-over-fiber systems, SPAD sensor systems, and lidar devices

[0001] The present disclosure relates to a semiconductor photodetector, an optical line terminal, a multilevel intensity modulation transceiver, a digital coherent receiver, an optical fiber radio system, a SPAD sensor system, and a lidar device.

[0002] Along with the progress of digital transformation that utilizes digital information, there has been remarkable development of communication networks that mutually communicate digital information and data centers that store and process data. Optical communication is used for communication networks and communication within data centers. Optical communication has made remarkable progress in recent years in increasing speed and capacity. With the progress of optical communication, avalanche photodiodes (APDs), which can provide high receiving sensitivity, are used as optical communication receivers.

[0003] Passive Optical Networks (PONs) are the primary method used in access networks connecting optical communication subscribers. PON systems began with G(E)-PON systems that transmit signals at 1-2 Gbps, and are expected to see an increase in 10G-EPON and XG-PON systems that transmit signals at 10 Gbps. Furthermore, the International Telecommunication Union Telecommunication Standardization Sector (ITU-T) is considering the 50G-PON system, a next-generation high-speed PON system, and it is expected that 50 Gbps-class transmissions will be put into practical use in access networks in the future.

[0004] APDs, which are semiconductor photodetectors used in PON systems, have a device structure consisting of a light absorption layer (InGaAs), an electric field buffer layer (InP or InAlAs), and a multiplication layer (InP or InAlAs). A high electric field of about 800 kV / cm is applied to the multiplication layer to multiply, or ionize, the electrons and holes generated in the light absorption layer. The electric field buffer layer functions to weaken the electric field so that the high electric field of the multiplication layer is not applied to the light absorption layer. Incidentally, the ionization rate of electrons is expressed as α, and the ionization rate of holes as β.

[0005] In an APD, the larger the ratio of the ionization rates of electrons and holes, the smaller the excess noise generated during multiplication and the higher the receiver sensitivity.Furthermore, the larger the ratio of the ionization rates of electrons and holes, the shorter the multiplication time in the multiplication layer, resulting in a wider bandwidth.

[0006] The ionization rate ratio k of electrons and holes is defined as k = β / α. When electrons are injected into the multiplication layer, the smaller the ionization rate ratio k, the better the performance of the APD. The multiplication layer of an APD for optical communication uses a compound semiconductor material such as InAlAs or InP.

[0007] When InAlAs is selected as the material for the multiplication layer, the difference between the ionization rates of electrons and holes is greater than when InP is used. In InP, the ionization rate of holes is greater than that of electrons, and the ionization rate of holes is approximately twice that of electrons. On the other hand, when InAlAs is selected as the material for the multiplication layer, the ionization rate of electrons is greater than that of holes, and the ionization rate of electrons is approximately five times that of holes. Therefore, since the receiver sensitivity is higher when InAlAs is used as the multiplication layer, InAlAs is more suitable than InP as the material for the multiplication layer of an APD.

[0008] As mentioned above, PON systems require APDs, which are semiconductor light-receiving elements, to have a wide response bandwidth and high receiving sensitivity. However, unlike PDs, APDs have a problem in that the time required for multiplication, i.e., the multiplication time, increases as the multiplication factor increases, resulting in a decrease in bandwidth at high multiplication factors. APDs with a multiplication layer made of InAlAs, which are used in optical communications, have a wider bandwidth than APDs made of other semiconductor materials, but at multiplication factors of 6 or more, the bandwidth remains at around 20 GHz. In other words, there is a problem in that it is difficult to achieve the bandwidth of around 37.5 GHz or more required for 50G-PON systems when using conventional APDs.

[0009] US Patent Application Publication No. 2022 / 0099813

[0010] Jiyuan Zheng et. al, “Digital Alloy InAlAs Avalanche Photodiodes”, JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 36, NO. 17, SEPTEMBER 1, pp. 3580-3585, 2018

[0011] In a 50G-PON system, the response bandwidth of the semiconductor light-emitting element and the semiconductor light-receiving element, the optical output of the semiconductor light-emitting element, and the receiving sensitivity of the semiconductor light-receiving element are insufficient. For this reason, it is being considered to provide a digital bandwidth compensation circuit using a digital signal processor (DSP) after the APD in the optical network unit (ONU), i.e., the receiving device on the subscriber side.

[0012] In addition, in the optical line terminal (OLT), i.e., the receiving device on the central office side, a semiconductor optical amplifier (SOA) is required to compensate for the insufficient receiving sensitivity of the semiconductor photodetector, or an SOA must be integrated into the electro-absorption modulated laser diode (EML) on the transmitting side of the ONU to increase the optical output. However, DSPs and SOAs consume very large amounts of power, which increases costs, and there are concerns that the replacement of existing PON systems with 50G-PON systems will not progress.

[0013] In addition, in existing PON systems other than the next-generation high-speed PON system, increasing the number of branches of the optical signal output from the OLT is being considered to reduce costs. However, even in this case, it is necessary to integrate an SOA in the EML on the transmitting side of the OLT or ONU to increase the optical output, which causes problems such as increased power consumption of the transmitter and increased costs.

[0014] As described above, in order to compensate for the limitations of the receiving sensitivity and response bandwidth of semiconductor photodetectors, transceivers have been designed that incorporate expensive and power-hungry DSPs and SOAs into the ONU or OLT, but this results in problems such as increased power consumption and increased costs.

[0015] The present disclosure has been made to solve the above-mentioned problems, and has as its object to provide a semiconductor light-receiving element that has high receiving sensitivity, a wide response band, and operates with low power consumption.

[0016] The semiconductor light receiving element according to the present disclosure includes an InP substrate, an n-type semiconductor layer formed on the InP substrate, a multiplication layer formed on the n-type semiconductor layer and having a digital alloy structure with a layer thickness of 40 nm or more and 170 nm or less, a p-type electric field buffer layer formed on the multiplication layer, and an InGaAs light absorption layer formed on the p-type electric field buffer layer.

[0017] The optical line terminal device according to the present disclosure comprises the above-mentioned semiconductor photodetector; an optical multiplexer / demultiplexer that inputs an optical signal to the semiconductor photodetector; an amplifier circuit that amplifies an electrical signal output from the semiconductor photodetector; a clock and data recovery circuit connected to the amplifier circuit that recovers clock data from the amplified electrical signal; and a forward error correction circuit connected to the clock and data recovery circuit that corrects errors in the clock data.

[0018] The multilevel intensity modulation transceiver according to the present disclosure includes the above-described semiconductor photodetector that receives an optical signal that has been intensity-modulated into multiple levels; an amplifier circuit that amplifies an electrical signal output from the semiconductor photodetector; an analog-to-digital conversion circuit that is connected to the amplifier circuit and converts the amplified electrical signal into a digital signal; and a digital signal processing circuit that is connected to the analog-to-digital conversion circuit and processes the digital signal.

[0019] The radio-on-fiber system according to the present disclosure includes: a light source that emits an analog-modulated optical signal; the above-described semiconductor photodetector that receives the analog-modulated optical signal; a transmission path that transmits the analog electrical signal output from the semiconductor photodetector to an antenna; and an antenna that is connected to the transmission path and emits the analog electrical signal as a radio wave signal.

[0020] The digital coherent receiving device according to the present disclosure comprises the semiconductor photodetector described above, a polarization separator that separates the polarizations of a polarization multiplexed optical signal whose intensity and phase are modulated, a 90-degree hybrid that splits and combines the optical signal output from the polarization separator, and a digital signal processing circuit that is connected to the 90-degree hybrid and processes digital signals.

[0021] The SPAD sensor system according to the present disclosure includes a SPAD sensor configured with the semiconductor light-receiving element described above; a quenching circuit that repeatedly applies a voltage equal to or greater than a breakdown voltage and a voltage less than the breakdown voltage to the SPAD sensor; and an optoelectronic measurement circuit that measures an electrical signal output from the SPAD sensor.

[0022] The LIDAR device according to the present disclosure comprises a light source that emits light in pulses, the above-mentioned semiconductor light receiving element that receives light that is emitted from the light source and reflected by an object, an amplifier circuit that amplifies the electrical signal output from the semiconductor light receiving element, and a ranging circuit that calculates the distance based on the electrical signal amplified by the amplifier circuit.

[0023] According to the semiconductor photodetector of the present disclosure, the multiplication layer is constructed with a digital alloy structure, and the thickness of the multiplication layer is set to be within a predetermined range, thereby achieving the effect of obtaining a semiconductor photodetector with high reception sensitivity and a wide response band.

[0024] According to the optical line terminal device, multi-level intensity modulation transceiver device, digital coherent receiver device, optical fiber radio system, SPAD sensor system, and LIDAR device of the present disclosure, the semiconductor photodetector element of the present disclosure is used as the semiconductor photodetector element, thereby achieving the effect of obtaining each device, each system, etc. with excellent performance.

[0025] FIG. 6 is a cross-sectional view showing the element structure of a front-illuminated APD, which is an example of a semiconductor light-receiving element according to the first embodiment. FIG. 7 is a cross-sectional view showing the element structure of an edge-illuminated APD, which is an example of a semiconductor light-receiving element according to the first embodiment. FIG. 8 is a diagram showing the electric field dependence of the electron dead space in an InAlAs multiplication layer. FIG. 4A to FIG. 4C are diagrams showing the ionization rates of electrons and holes. FIG. 9 is a diagram showing the dependence of the ionization rate ratio and the tunnel current on the thickness of the multiplication layer. FIG. 10 is a diagram showing the ionization rates in the multiplication layer and the electric field relaxation layer, where FIG. 10A shows the ionization rates for a random alloy structure multiplication layer, FIG. 10B shows the ionization rates for a digital alloy structure multiplication layer, FIG. 10C shows the ionization rates for a partially disordered digital alloy structure multiplication layer, and FIG. 10D shows the ionization rates when a thick electric field relaxation layer and a digital alloy structure multiplication layer are combined. FIG. 11 is a diagram showing the configuration of a comparative example of optical line terminals (ONU and OLT) for a 50G-PON system. FIG. 1 is a diagram illustrating the configuration of an ONU in a 50G-PON system using a semiconductor photodetector according to a first embodiment. FIG. 2 is a diagram illustrating the configuration of an OLT in a 50G-PON system using a semiconductor photodetector according to the first embodiment. FIG. 3 is a diagram illustrating the configuration of a 50G-PON system and an OLT / ONU as a comparative example. FIG. 4 is a diagram illustrating the configuration of a multi-branch 50G-PON system and an OLT / ONU according to the first embodiment. FIG. 5 is a diagram illustrating the configuration of a 50G-PON system and an OLT / ONU according to the first embodiment. FIG. 6 is a cross-sectional view illustrating the element structure of a front-illuminated APD as an example of a semiconductor photodetector according to a second embodiment. FIG. 7 is a cross-sectional view illustrating the element structure of a front-illuminated APD as an example of a semiconductor photodetector according to the second embodiment. FIG. 8 is a cross-sectional view illustrating the element structure of a front-illuminated APD as an example of a semiconductor photodetector according to a third embodiment. FIG. 9 is a cross-sectional view illustrating the element structure of a back-illuminated APD as an example of a semiconductor photodetector according to a fourth embodiment. FIG. 10 is a cross-sectional view illustrating the element structure of a front-illuminated APD as an example of a semiconductor photodetector according to a fifth embodiment. 10A and 10B are cross-sectional views showing another element structure of a front-illuminated APD which is an example of a semiconductor light-receiving element according to embodiment 5. FIG. 10C are cross-sectional views showing an element structure of a front-illuminated APD which is an example of a semiconductor light-receiving element according to embodiment 6. FIG. 10D are cross-sectional views showing an element structure of a back-illuminated APD which is an example of a semiconductor light-receiving element according to embodiment 7.10 is a cross-sectional view showing the element structure of a back-illuminated APD, which is an example of a semiconductor light-receiving element according to an eighth embodiment. FIG. 23A is a diagram showing the configuration of a multilevel intensity-modulated transceiver according to a ninth embodiment. FIGS. 23A and 23B are diagrams showing received waveforms of the multilevel intensity-modulated transceiver according to the ninth embodiment. FIGS. 24A and 24B are diagrams explaining the operation of a PD at high optical input. FIGS. 24A and 24B are diagrams explaining the operation of an APD at high optical input. FIGS. 24B and 24C are diagrams showing the residence times of electrons and holes for each material constituting the multiplication layer. FIG. 24A is a diagram showing the configuration of a radio-on-fiber system according to a tenth embodiment. FIG. 24B is a diagram showing the configuration of a radio-on-fiber system as a comparative example. FIG. 24B is a diagram showing the configuration of a digital coherent receiving device according to an eleventh embodiment. FIG. 30A is a diagram showing waveforms of a digital coherent receiving device as a comparative example, and FIG. 30B is a diagram showing waveforms of the digital coherent receiving device according to the eleventh embodiment. FIG. 32A is a diagram showing waveforms of a SAPD sensor system as a comparative example, and FIG. 32B is a diagram showing waveforms of the SAPD sensor system according to the twelfth embodiment. 35A is a diagram showing the calculation of the difference between the quenching electric field and the Geiger mode electric field for each configuration of the multiplication layer. 35B is a diagram showing the configuration of a LIDAR device according to embodiment 13. 35A is a diagram showing the received waveform of the APD of a LIDAR device that is a comparative example, and 35B is a diagram showing the received waveform of the APD of the LIDAR device according to embodiment 13.

[0026] Embodiment 1. <Element Structure of Semiconductor Photodetector According to Embodiment 1> Fig. 1 is a cross-sectional view showing the element structure of a front-illuminated APD, which is an example of a semiconductor photodetector 100 according to embodiment 1. Fig. 2 is a cross-sectional view showing the element structure of an edge-illuminated APD, which is an example of a semiconductor photodetector 110 according to embodiment 1.

[0027] <Element Structure of Semiconductor Photodetector According to First Embodiment> The semiconductor photodetector 100 according to the first embodiment includes an n-type InP substrate 1 and a semiconductor layer having a carrier concentration of 1 to 5×10 18 cm -3and a layer thickness of 0.1 to 1.0 μm; an InAlAs multiplication layer 3 (hereinafter referred to as an InAlAs digital alloy structure multiplication layer 3; it may also be abbreviated as a DA multiplication layer) having a digital alloy structure in which an i-type AlAs layer (for example, a layer thickness of two atomic layers, about 0.6 nm) and an i-type InAs layer (for example, a layer thickness of two atomic layers, about 0.6 nm) are alternately stacked multiple times; and an n-type InAlAs buffer layer 2 having a carrier concentration of 0.1 to 1.0 μm. 17 cm -3 The n-type InP substrate 1 includes a p-type InP field relaxation layer 4 having a thickness of 10 to 70 nm, an i-type InGaAs light absorption layer 5 having a thickness of 0.1 to 2.0 μm, an i-type InAlGaAs / InAlAs graded layer 6, a p-type InP window layer 7 having a thickness of 0.1 to 3.0 μm, a p-type InGaAs contact layer 8, an n-type electrode 31 formed on the back surface side of the n-type InP substrate 1, and a p-type electrode 32 formed on the p-type InGaAs contact layer 8. The n-type InAlAs buffer layer 2 is also referred to as an n-type semiconductor layer.

[0028] The semiconductor light-receiving element 110 according to the first embodiment has a layer structure similar to that of the semiconductor light-receiving element 100, but further includes an Fe-doped semi-insulating InP buried layer 20 formed at least on the end surface onto which the incident light 90 is incident.

[0029] The n-type InAlAs buffer layer 2 may have either a random alloy structure or a digital alloy structure. Silicon (Si) is optimal as the n-type dopant for the n-type InAlAs buffer layer 2. This is to prevent n-type impurities from diffusing from the n-type InAlAs buffer layer 2 to the i-type InAlAs digital alloy structure multiplication layer 3, causing disorder in the digital alloy structure. Here, disorder refers to the phenomenon in which the compositions of the layers in the digital alloy structure intermingle, resulting in a random alloy structure with an average composition.

[0030] As described above, the InAlAs digital alloy structure multiplication layer 3 is configured of semiconductor layers in which AlAs layers (layer thickness: 2 atomic layers, approximately 0.6 nm) and InAs layers (layer thickness: 2 atomic layers, approximately 0.6 nm) are alternately stacked in this order. However, it is sufficient that the thicknesses of the AlAs layers and InAs layers are each in the range of 2 to 6 atomic layers. The reason for specifying 6 atomic layers or less is that it is desirable for the stacked structure of the AlAs layers and InAs layers not to function as a quantum well structure.

[0031] Furthermore, the number of atomic layers in each layer of the InAlAs digital alloy structure multiplication layer 3 is preferably 2 to 4, and optimally 2. The reason for this is that the thinner the atomic layer thickness of each layer, the greater the effect of the digital alloy structure in reducing the ionization rate ratio k.

[0032] Considering the affinity with InAlAs constituting the n-type InAlAs buffer layer 2, it is preferable to make the thickness of only the first AlAs layer of the InAlAs digital alloy structure multiplication layer 3 three atomic layers or more. Alternatively, the InAlAs digital alloy structure multiplication layer 3 may be formed by alternately stacking InAs layers and AlAs layers in this order.

[0033] The conductivity type of the InAlAs digital alloy structure multiplication layer 3 is i-type, and the carrier concentration is 1×10 17 cm -3 However, as the conductivity type of the InAlAs digital alloy structure multiplication layer 3, the carrier concentration is 5×10 18 cm -3 It may be p-type or n-type as follows.

[0034] In order to increase the dead space effect in the InAlAs digital alloy structure multiplication layer 3, the thickness of the InAlAs digital alloy structure multiplication layer 3 is preferably in the range of 40 nm to 170 nm. However, considering a typical degree of variation of 20% in layer thickness during fabrication of the semiconductor light receiving element 100, the thickness of the InAlAs digital alloy structure multiplication layer 3 is preferably in the range of 50 nm to 140 nm.

[0035] In addition to the multiplication layer having an InAlAs digital alloy structure, an InAlGaAs digital alloy structure in which InAlyGa(1-y)As (layer thickness of 2 to 6 atomic layers, Al composition ratio Y) and InAlzGa(1-z)As (layer thickness of 2 to 6 atomic layers, Al composition ratio Z) are alternately stacked can also be used as the multiplication layer of the present disclosure. Furthermore, a digital alloy structure made of InAlAsSb, which is a material system containing antimony (Sb), can also be used as the multiplication layer of the present disclosure.

[0036] As described above, the p-type InP field relaxation layer 4 has a carrier concentration of 0.1 to 50×10 17 cm -3 The thickness of the p-type InP field buffer layer 4 is preferably in the range of 10 nm to 70 nm. Examples of p-type dopants for the p-type InP field buffer layer 4 include beryllium (Be), zinc (Zn), and carbon (C).

[0037] The field buffer layer does not necessarily have to be made of p-type InP. That is, the field buffer layer may have a p-type InAlAs digital alloy structure or a p-type InAlAs random alloy structure. However, if the dopants contained in the p-type InP field buffer layer 4 diffuse into the adjacent InAlAs digital alloy structure multiplication layer 3, the digital alloy structure may become disordered and may change to an InAlAs random alloy structure. As mentioned above, the InAlAs digital alloy structure multiplication layer 3 has a thin layer thickness of approximately 100 nm, and therefore may be significantly affected by disordering due to dopant diffusion. Therefore, in the case of the p-type InP field buffer layer 4, Be, which is less likely to diffuse, is optimal as the p-type dopant. On the other hand, when p-type InAlAs is used as the constituent material of the field buffer layer, Zn is optimal as the p-type dopant.

[0038] By providing a layer of InAlGaAs or InGaAsP or the like having a band gap intermediate between the p-type InP field buffer layer 4 and the i-type InGaAs light absorption layer 5 and having a thickness of 0.1 μm or less, it is possible to prevent accumulation of electrons and holes at the heterojunction interface. The conductivity type of the InGaAs light absorption layer may be either n-type or p-type.

[0039] For the same purpose, a layer of InAlGaAs or InGaAsP having a band gap intermediate between the i-type InGaAs light absorption layer 5 and the p-type InAlAs layer may be provided between them, with a thickness of 0.1 μm or less. The p-type InGaAs contact layer 8 has a peripheral portion formed so as to have a smaller area than the multiplication layer.

[0040] 1 , an example of the device structure of the semiconductor photodetector 100 includes an InAlGaAs / InAlAs graded layer 6 formed by alternately stacking two types of i-type InAlGaAs layers with different compositions multiple times on an i-type InGaAs light absorption layer 5. The conductivity type of the InAlGaAs / InAlAs graded layer 6 may be p-type or n-type. Furthermore, a p-type InAlAs window layer may be used instead of the p-type InP window layer 7.

[0041] <Operation Principle of Semiconductor Photodetector According to First Embodiment> The operation principle of the semiconductor photodetector 100 according to the first embodiment is described below. If a wideband APD of about 37.5 GHz or more can be realized, a next-generation high-speed PON system can be realized without using a DSP or SOA. In the case of a PD, which is relatively easy to widen, the response bandwidth is limited by: (1) the RC time constant (R is the element resistance, C is the element capacitance) and (2) the carrier transit time (the time it takes for electrons or holes to transit through the depletion layer). In the case of an APD, the response bandwidth is further limited by: (3) the multiplication time (the time it takes for electrons and holes to multiply in a chain reaction within the multiplication layer, which increases in proportion to the multiplication factor).

[0042] While a PD can achieve the above-mentioned 37.5 GHz bandwidth, an APD requires a multiplication time, making it difficult to achieve the desired bandwidth if the multiplication factor is increased. The multiplication time TM is expressed by the following equations (1) to (3): Multiplication time TM = multiplication factor M / GB product (1) GB product = 1 / (2πNkτav) (2) In other words, the multiplication time TM = 2πNkMτav (3)

[0043] Here, GB product is the product of the multiplication factor and the bandwidth, k is the ionization rate ratio, N is a coefficient that is loosely dependent on the ionization rate ratio k, and τav is the average time it takes for electrons and holes to travel through the multiplication layer. Therefore, by reducing the ionization rate ratio k, it is possible to shorten the multiplication time TM. In particular, to realize a high-speed PON system, it is necessary to make the multiplication time TM approach zero, that is, to make the ionization rate ratio k approach zero.

[0044] In order to make the ionization rate ratio k zero, various compound semiconductors have been proposed as materials for the multiplication layer. In addition, in order to reduce the ionization rate ratio k, a digital alloy structure (also called ALSL: Atomic Layer Super Lattice) has been proposed in which semiconductor layers of different compositions are alternately stacked at a period of about 1 to 6 atomic layers. However, even in the digital alloy structure, it has been difficult to make the ionization rate ratio k zero unless the structure is optimized. The digital alloy structure is described in Non-Patent Document 1.

[0045] Therefore, in order to reduce the ionization rate ratio k of the digital alloy structure, the inventors fabricated an APD with a digital alloy structure multiplication layer using a multiplication layer formed by alternately stacking two-atom InAs layers and two-atom AlAs layers, and analyzed the multiplication characteristics. As a result, they discovered that the distance that carriers travel through the multiplication layer to become ionized is longer than that of an APD with an InAlAs multiplication layer made of a normal bulk crystal, i.e., an InAlAs random alloy structure multiplication layer. The distance that carriers travel through the multiplication layer to become ionized is called the dead space.

[0046] Because the length of the dead space (hereinafter referred to as the dead space length) is longer for holes than for electrons, in the case of an InAlAs random alloy structure made of a typical bulk crystal, thinning the multiplication layer to about several tens of nanometers results in a decrease in the ionization rate ratio k because holes cannot be ionized. However, when the multiplication layer is thinned to about several tens of nanometers, a new problem arises: a higher electric field must be applied to the multiplication layer to obtain the desired multiplication factor, which increases leakage currents such as tunnel currents. In other words, an increase in tunnel current increases noise generated in the APD. On the other hand, the inventors' analysis discovered that, because the dead space is unusually large in the digital alloy structure compared to the random alloy structure, the ionization rate ratio k = 0 even for a multiplication layer with a thickness of 100 nm or more.

[0047] In other words, the inventors have discovered for the first time that by constructing the multiplication layer of an APD with a digital alloy structure, it is possible to achieve an ionization rate ratio k = 0 while suppressing the tunneling current. Specifically, they have found that in a multiplication layer having the digital alloy structure of the present disclosure, the ionization rate ratio k drops sharply at a layer thickness of 170 nm or less, and that the dead space effect is dramatically improved particularly when the multiplication layer thickness is in the range of 60 to 130 nm. In other words, the inventors have demonstrated that the ionization rate ratio k = 0, which was impossible to achieve with a multiplication layer having a random alloy structure or a multiplication layer having a thick digital alloy structure, can be achieved by applying a multiplication layer having the digital alloy structure of the present disclosure. At present, no research institute has reported that thinning the multiplication layer of an APD having a digital alloy structure multiplication layer is more effective in reducing the ionization rate ratio k than thinning the multiplication layer of an APD made of conventional materials.

[0048] <Method for Manufacturing Semiconductor Photodetector According to First Embodiment> A front-illuminated APD, which is an example of the semiconductor photodetector 100 according to the first embodiment, can be realized by using metal organic vapor phase epitaxy (MOVPE) or molecular beam epitaxy (MBE) on an n-type InP substrate 1. A method for manufacturing the semiconductor photodetector 100 according to the first embodiment will be described below.

[0049] By using MOVPE or MBE, a layer having a thickness of 0.1 to 1 μm and a carrier concentration of 1 to 5×10 18 cm -3 The n-type InAlAs buffer layer 2 is grown by crystal growth.

[0050] The InAlAs digital alloy structure multiplication layer 3 is grown by crystal growth on the n-type InAlAs buffer layer 2. That is, the InAlAs digital alloy structure multiplication layer 3 is formed by alternately growing crystals of an AlAs layer (having a thickness of two atomic layers, approximately 0.6 nm) and an InAs layer (having a thickness of two atomic layers, approximately 0.6 nm) in this order from the n-type InAlAs buffer layer 2.

[0051] On the InAlAs digital alloy structure multiplication layer 3, a layer having a thickness of 10 nm or more and 70 nm or less and a carrier concentration of 0.1 to 50×10 17 cm -3 The p-type InP field buffer layer 4 is grown by crystal growth.

[0052] An i-type InGaAs light absorption layer 5 having a thickness of 0.1 μm to 2 μm, an i-type InAlGaAs / InAlAs graded layer 6, a p-type InP window layer 7 having a thickness of 0.1 μm to 3 μm, and a p-type InGaAs contact layer 8 are successively grown by crystal growth on the p-type InP field relaxation layer 4. The InAlGaAs / InAlAs graded layer may be either n-type or p-type. A p-type InAlAs window layer may be used instead of the p-type InP window layer 7.

[0053] After the crystal growth is completed, a p-type electrode 32 is formed on the surface of the p-type InGaAs contact layer 8, and an n-type electrode 31 is formed on the back surface of the n-type InP substrate 1, respectively.

[0054] 1, incident light 90 is incident perpendicularly to the i-type InGaAs light absorption layer 5. The diameter of the light-receiving area of ​​the APD is in the range of 5 μm to 1 mm if the light-receiving area is circular, or the length of the long side of the light-receiving area of ​​the APD is in the range of 5 μm to 1 mm if the light-receiving area is rectangular. An anti-reflective coating (not shown) is applied to the incident surface of the APD.

[0055] In the edge-illuminated APD shown in Figure 2, incident light 90 is incident parallel to the i-type InGaAs light absorption layer 5. From the viewpoint of reliability, the edge portions are covered with an insulating film, an organic film, or a semiconductor layer. In the edge-illuminated APD shown in Figure 2, an Fe-doped semi-insulating InP burying layer 20 is formed on the edge. The thickness of the Fe-doped semi-insulating InP burying layer 20 is in the range of 100 nm to 5 μm in the incident direction.

[0056] In the APD according to the first embodiment, Ti and Au are used as the electrode materials for the p-type electrode 32. In the APD according to the first embodiment, the amount of electric field relaxation is adjusted so that tunnel breakdown does not occur at a voltage lower than avalanche breakdown. In the APD according to the first embodiment, the operating voltage is 15 V to 90 V, and the electric field in the multiplication layer during APD operation is 500 kV / cm to 900 kV / cm. In addition, in the APD according to the first embodiment, the electric field in the i-type InGaAs light absorption layer 5 is set to 300 kV / cm or less. In the APD according to the first embodiment, the multiplication factor is used in the range of 3 to 30, but is 100 or more when operating in Geiger mode.

[0057] <Function of Semiconductor Photodetector of First Embodiment> The function of the APD according to the first embodiment shown in Figures 1 and 2 will be described below. The inventors have found that using a digital alloy structure multiplication layer, as in the APD according to the first embodiment, enhances the dead space effect, i.e., the effect of reducing the ionization rate ratio k. Figure 3 is a graph showing the electric field dependence of the electron dead space in an InAlAs multiplication layer. The inventors analyzed the electron multiplication characteristics of the digital alloy structure multiplication layer and found that, as shown in the graph in Figure 3, the InAlAs digital alloy structure multiplication layer of the present disclosure has a longer dead space than the conventional InAlAs random alloy structure multiplication layer.

[0058] 4A to 4C are graphs showing the ionization rates of electrons and holes, respectively. 4A shows the case of electron ionization, 4B shows the case of hole ionization, and 4C shows the ionization rate when the multiplication layer is thinned. In a conventional InAlAs random alloy multiplication layer, as shown in the graph of FIG. 3, the dead space length is about 45 nm, so the thickness of the multiplication layer needs to be thinned to about 1.5 times the dead space (about 70 nm). However, thinning the multiplication layer to 70 nm increases the electric field in the multiplication layer, which leads to a rapid increase in tunnel current and increased noise, making it difficult to obtain an APD with good receiver sensitivity.

[0059] On the other hand, in the InAlAs digital alloy structure multiplication layer 3 of the APD according to the first embodiment, as shown in the graph of FIG. 3, the reciprocal of the applied electric field is 1.47×10 -6 In the case of a voltage of 1.0 V / cm / V, the dead space length is about 85 nm, and therefore the ionization rate ratio k can be made close to zero even if the thickness of the multiplication layer is about 1.5 times the dead space (about 130 nm). Therefore, the effect of the tunnel current is small in the APD according to the first embodiment.

[0060] In addition, in the InAlAs digital alloy structure multiplication layer, the dead space is highly dependent on the applied electric field, and the reciprocal of the applied electric field is 1.27 × 10 -6In the case of a multiplication layer having a dead space length of about 50 nm, the thickness of the multiplication layer must be reduced to 75 nm, as shown in the graph of Fig. 3. In other words, the thickness of the InAlAs digital alloy structure multiplication layer can be made thicker than that of the InAlAs random alloy structure multiplication layer.

[0061] 5 is a graph showing the layer thickness dependence of the ionization rate ratio and the tunnel current on the multiplication layer. The inventors fabricated APDs having an InAlAs digital alloy structure multiplication layer and an InAlAs random alloy structure multiplication layer, respectively, and measured the ionization rate ratio k. Furthermore, the results were plotted in FIG. 5 together with the measurement results from References 1 and 2 described in FIG. 5. References 1 and 2 in FIG. 5 are as follows: (1) Reference 1: Yuan Yuan, et al., "Temperature dependence of the ionization coefficients of InAlAs and AlGaAs digital alloys," pp. 794, Vol. 6, No. 10, 2003. 8 / August 2018 / Photonics Research (2) Reference 2 Wenyang Wang, et al “Characteristics of thin InAlAs digital alloy avalanche photodiodes” pp. 3841, Vol. 46, No. 16 / 15 August 2021 / Optics Letters

[0062] As shown in Figure 5, in an InAlAs random alloy multiplication layer, the effect of reducing the ionization rate ratio k due to dead space cannot be achieved unless the multiplication layer thickness is 80 nm or less. On the other hand, if the multiplication layer thickness is thinner than 80 nm, the tunneling current increases sharply, resulting in tunnel breakdown. When the multiplication layer thickness is around 60 nm, both the reduction in the ionization rate ratio k and the limitation of the tunneling current are barely achieved, but the thickness margin is only a few nanometers, making it extremely difficult to reliably manufacture APDs. Furthermore, the ionization rate ratio k is also large, at 0.12. In other words, with a conventional InAlAs random alloy multiplication layer, it is difficult to apply the effect of reducing the ionization rate ratio k by thinning the layer to APDs.

[0063] On the other hand, in the InAlAs digital alloy structure multiplication layer of the present disclosure, as discovered by the inventors, the dead space is large, and therefore, as the multiplication layer is made thinner, the ionization rate ratio k starts to decrease to 0.1 or less at a layer thickness of 170 nm, as shown in Figure 5. Here, the ionization rate ratio k is determined from the measured value of the multiplication noise, and is the minimum value of the ionization rate ratio in the multiplication factor range of 1 to 10. For the same ionization rate ratio k, the layer thickness of the InAlAs digital alloy structure multiplication layer is more than twice as large as that of the InAlAs random alloy structure multiplication layer.

[0064] As shown in the graph of FIG. 5, if the lower limit of the thickness of the multiplication layer for which the tunnel current becomes 1 μA in an APD with a pn junction diameter of 20 μm is 40 nm, the layer thickness range of 40 nm to 170 nm is the optimum range for an InAlAs digital alloy structure multiplication layer, and layer thicknesses within this range can be fabricated with sufficient reproducibility.

[0065] The thickness of the InAlAs digital alloy structure multiplication layer, which can sufficiently reduce the ionization rate ratio k due to the dead space effect, is 1.47×10 -6 In the case of a thickness of 170 nm, the upper limit of the thickness of the InAlAs digital alloy structure multiplication layer is preferably about twice the dead space length, considering that the dead space length is 85 nm as shown in FIG. 3 .

[0066] Furthermore, in order to control the ionization rate ratio k to 0.05 or less in an InAlAs digital alloy structure multiplication layer, the thickness of the multiplication layer is preferably 150 nm or less, as shown in the graph of Figure 5. Furthermore, in order to achieve a tunnel current of 1 μA or less and an ionization rate ratio k of approximately zero, the thickness of the multiplication layer is optimally in the range of 60 nm to 130 nm. If a margin of 10 nm is set during the fabrication of an APD, the thickness of the multiplication layer is preferably set in the range of 70 nm to 120 nm.

[0067] Furthermore, as shown in FIG. 3, the length of the dead space is preferably 50 nm to 90 nm. The ratio of the length of the dead space to the thickness of the multiplication layer is preferably 29% or more, calculated by dividing the minimum dead space length of 50 nm by the maximum multiplication layer thickness of 170 nm. As the ratio increases, the ionization rate ratio k decreases, but it cannot exceed 100%. This is because multiplication no longer occurs when the ionization rate ratio k exceeds 100%. Therefore, the ratio of the dead space length to the thickness of the multiplication layer is preferably 29% or more but less than 100%. Furthermore, when an example of a DA-APD according to the present disclosure having a multiplication layer thickness of 120 nm was fabricated, the optimum range of the ratio of the dead space length to the thickness of the multiplication layer was experimentally confirmed to be 42% (= 50 nm / 120 nm) to 75% (= 90 nm / 120 nm).

[0068] The inventors have considered why the ionization rate ratio k=0 could not be achieved with a conventional InAlAs random alloy structure multiplication layer, but the InAlAs digital alloy structure multiplication layer of the present disclosure can achieve it. If the electron dead space length is De and the hole dead space length is Dh, the conditions under which the ionization rate ratio k=0 can be achieved are expressed by the following equations (4) and (5). Note that equation (4) represents the condition for the difference in dead space length, and equation (5) represents the condition for the tunnel current. Dhe=Dh-De>0 (4) Dh>Tmin (5)

[0069] Here, Dhe is the difference between the dead space lengths of holes and electrons. Tmin is the minimum thickness of the multiplication layer at which the tunnel current becomes small enough to not affect noise, and the thicker the multiplication layer, the more the tunnel current decreases. As shown in Figure 4C, when the thickness of the multiplication layer is equal to or less than the dead space length of holes, holes are no longer multiplied and the ionization rate ratio k = 0, so the condition for the difference in dead space length is set as shown in Equation (5) above.

[0070] 3 and 5, in the case of an InAlAs random alloy structure multiplication layer, the ionization rate ratio k starts to decrease when the multiplication layer is made thinner at values ​​De ~ 40 nm and Dh ~ 80 nm. When the pn junction diameter is 20 μm and the tunnel current is set to 100 nA or less, the minimum layer thickness Tmin = 90 nm. Therefore, the InAlAs random alloy structure does not satisfy the tunnel current condition, and it is impossible to achieve an ionization rate ratio k = 0.

[0071] On the other hand, in the case of an InAlAs digital alloy structure multiplication layer, the ionization rate ratio k starts to decrease as the multiplication layer is made thinner at values ​​De ~ 80 nm and Dh ~ 170 nm, and when the pn junction diameter is 20 μm and the tunnel current is 100 nA or less, the minimum layer thickness Tmin = 90 nm, so there is a multiplication layer thickness that satisfies the condition of ionization rate ratio k = 0. Note that the minimum layer thickness Tmin is the same for the InAlAs digital alloy structure multiplication layer and the InAlAs random alloy structure multiplication layer because the band gaps of both are the same.

[0072] Specifically, in the case of a random alloy structure, De is about 40 nm and Dh is about 80 nm, whereas in the case of a digital alloy structure, the inventors found that De is about 80 nm and Dh is about 170 nm.

[0073] In the InAlAs digital alloy structure multiplication layer, the difference in lattice constant between the InAs (lattice constant = 0.606 nm) and AlAs (lattice constant = 0.566 nm) that make up the superlattice is very large at 6.55%. Therefore, during the fabrication process, dopants in the field relaxation layer, i.e., impurities, may diffuse into the InAlAs digital alloy structure multiplication layer, causing disorder within the multiplication layer.

[0074] 6A to 6D are diagrams showing the ionization rates in the multiplication layer and the electric field buffer layer, with Fig. 6A showing the ionization rates in the case of an InAlAs random alloy structure multiplication layer, Fig. 6B showing the ionization rates in the case of an InAlAs digital alloy structure multiplication layer, Fig. 6C showing the ionization rates in the case of a partially disordered InAlAs digital alloy structure multiplication layer, and Fig. 6D showing the ionization rates in the case of a combination of a thick electric field buffer layer and an InAlAs digital alloy structure multiplication layer. Compared to the InAlAs random alloy structure multiplication layer shown in Fig. 6A, the InAlAs digital alloy structure multiplication layer shown in Fig. 6B has a longer dead space length, but due to dopant diffusion from the electric field buffer layer, the partially disordered InAlAs digital alloy structure multiplication layer has a shorter dead space length, as shown in Fig. 6C.

[0075] In order to avoid the influence of disorder in the InAlAs digital alloy structure multiplication layer, the selection of the material and dopant of the field relaxation layer and the doping concentration are important. The impurity diffusion equation is expressed by the following equation (6): dN / dt=D(d 2 N / d 2 x)-F (6)

[0076] In equation (6), N is the impurity concentration, t is time, D is the diffusion constant, x is position, and F is the external force acting on the diffusion. Examples of materials for the field buffer layer include InP, an InAlAs random alloy structure, and an InAlAs digital alloy structure. Examples of p-type dopants for the field buffer layer include Be and Zn. Considering the p-type dopant, a combination of a Be-doped p-type InP field buffer layer and an InAlAs digital alloy structure multiplication layer is preferable. This is because Be has a small diffusion constant D and also forms a potential barrier between it and the InAlAs digital alloy structure multiplication layer. The potential barrier corresponds to F in equation (6).

[0077] When the thickness of the electric field relaxation layer varies, the carrier concentration of the electric field relaxation layer is set to 2×10 so that the variation in the amount of electric field relaxation, that is, the variation in the product of the layer thickness and the carrier concentration, does not increase. 18 cm -3When InAlAs is used as the material for the field relaxation layer, Zn doping is optimal, and the carrier concentration is 2×10 18 cm -3 The optimum is 2 × 10 18 cm -3 When the impurity concentration is higher than 5×10, the inactive impurities increase and diffusion becomes more likely. 18 cm -3 The following is required:

[0078] The electric field relaxation amount ΔE is expressed by the following equation (7): ΔE=W q N / ε (7) When the electric field relaxation amount ΔE is constant, if the carrier concentration of the electric field relaxation layer is increased, the thickness of the electric field relaxation layer must be reduced in inverse proportion to the carrier concentration, where W is the layer thickness of the electric field relaxation layer, q is the elementary charge, N is the carrier concentration of the electric field relaxation layer, and ε is the dielectric constant.

[0079] The carrier concentration N of the electric field relaxation layer is 5×10 18 cm -3 In order to prevent the dead space length from being shortened due to impurity diffusion into the multiplication layer, the carrier concentration of the field relaxation layer is set to 5×10 18 cm -3 The electric field relaxation layer must have a thickness of 10 nm or more.

[0080] On the other hand, as shown in Figure 6D, if the thickness of the electric field buffer layer becomes 1.5 times or more the dead space length of the electric field buffer layer, multiplication occurs in the electric field buffer layer. As shown in Figure 3, in the random alloy structure, the dead space length is 45 nm or less, so the layer thickness of the random alloy electric field buffer layer must be 70 nm or less. On the other hand, in the InAlAs digital alloy structure, the dead space length is 85 nm or less, so the layer thickness of the digital alloy electric field buffer layer must be 130 nm or less.

[0081] The lengths of the dead spaces shown in FIGS. 6A to 6D have the following relationship: dead space (FIG. 6A)<dead space (FIG. 6D)<dead space (FIG. 6C)<dead space (FIG. 6B).

[0082] <Effects of the Semiconductor Photodetector According to the First Embodiment> First, a first effect of the semiconductor photodetector according to the first embodiment will be quantitatively described below. The 3 dB bandwidth fc of a conventional APD is expressed by the following equation (8), where frc is the bandwidth limit due to the RC time constant, ftr is the bandwidth limited by the carrier transit time, and fm is the bandwidth limit due to the multiplication time. fc=1 / ((1 / frc) 2 +(1 / ftr) 2 +(1 / fm) 2 ) 0.5 (8)

[0083] On the other hand, the 3 dB bandwidth fc of the APD having the InAlAs digital alloy structure multiplication layer according to the first embodiment is limited only by the RC time constant and the carrier transit time according to equations (1), (2), and (3) because the ionization rate ratio k is close to zero, and therefore can be expressed by the following equation (9): fc=1 / ((1 / frc) 2 +(1 / ftr) 2 ) 0.5 (9) In equation (9), the transit time ftr of the carriers includes the time it takes to transit through the light absorption layer plus the time it takes to transit through the multiplication layer.

[0084] The RC time constant is inversely proportional to the sum of the thickness of the light absorption layer and the thickness of the multiplication layer, while the transit time is directly proportional, so Equation (9) has a maximum value. That is, the maximum bandwidth occurs when frc = ftr. Substituting frc = ftr, Equation (9) is expressed by the following Equation (10): fc = ftr / √2 (10) Furthermore, the 3 dB bandwidth ftr determined by the transit time is expressed by the following Equation (11): ftr = 3.5Vav / (2πWt) (11)

[0085] In equation (11), Vav is the average saturated transit velocity of electrons and holes, and Wt is the total thickness of the light absorption layer and the multiplication layer. For example, in the case of InGaAs, Vav is 5.35×10 6 Furthermore, if the thickness of the multiplication layer is 100 nm and the thickness of the light absorption layer is 400 nm, then Wt=500 nm.

[0086] Vav=5.35×106 When cm / s and Wt=500 nm are substituted into equation (11), ftr=59.6 GHz is obtained. Furthermore, when substituted into equation (10), the 3 dB bandwidth of the APD having the InAlAs digital alloy structure multiplication layer according to the first embodiment is 42.2 GHz. Therefore, it is clear from the above considerations that the APD having the InAlAs digital alloy structure multiplication layer 3 according to the first embodiment can satisfy the bandwidth of 37.5 GHz required for a 50G-PON system. In the following description of devices, systems, etc., an APD having an InAlAs digital alloy structure multiplication layer according to the present disclosure will be referred to as the DA-APD of the present disclosure.

[0087] 7 is a configuration diagram showing an optical line terminal (OLT) 250 of a 50G-PON system as a comparative example. The optical line terminal 250 as a comparative example includes a forward error correction (FEC) circuit (FEC) 251, a driver amplifier 252, a light source 253, a wavelength division multiplexing (WDM) circuit (WDM) 254, a digital signal processing circuit (DSP) 255, an analog-to-digital converter (ADC) 256, an analog-to-digital conversion circuit (ADC), a burst TIA 257, and a conventional APD 258.

[0088] 8 is a configuration diagram illustrating an optical line terminal (OLT) 260 of a 50G-PON system according to embodiment 1. The optical line terminal 260 includes an FEC 261, a driver amplifier 262, a light source 263, a WDM 264, a clock data recovery (CDR) 265 that is a clock and data recovery circuit, a limiting amplifier 266, a burst TIA 267, and a DA-APD 268 of the present disclosure.

[0089] 9 is a configuration diagram illustrating an optical network unit (ONU) 270 of a 50G-PON system according to embodiment 1. The optical network unit 270 includes a WDM 271, a light source 272, a driver amplifier 273, an FEC 274, a DA-APD 275 of the present disclosure, a TIA 276, a limiting amplifier 277, and a CDR 278.

[0090] As shown in the optical line terminal (OLT) 250 of the 50G-PON system of the comparative example shown in Figure 7, the 50G-PON system of the comparative example required digital bandwidth compensation, i.e., a DSP 255. On the other hand, in the 50G-PON system using the DA-APD of the present disclosure, digital bandwidth compensation is not required. As a result, the DSP in each configuration of the optical line terminal 260 shown in Figure 8 and the optical line terminal 270 shown in Figure 9 can be omitted, thereby enabling reductions in power consumption and costs.

[0091] Next, a second effect of the semiconductor photodetector according to the first embodiment will be described. In order to increase the number of branches in a PON system and to omit the SOA, it is necessary to improve the S / N ratio of the receiver and increase the receiving sensitivity. For example, if one optical demultiplexer is added to increase the number of branches from the current level, the amount of light will be halved, so it is necessary to improve the S / N ratio by at least 3 dB. The S / N ratio of a receiver using an APD is expressed by the following equation (12): S / N ratio = Iph 2 ・M 2 / (2q(Iph+Id)M 2 ・F・B +4Kb・T・Ft・B / Rt) (12)

[0092] In equation (12), I is the photocurrent of the APD, M is the multiplication factor, q is the unit charge, I is the dark current to be multiplied, F is the excess noise factor of the APD, B is the bandwidth, K is the Boltzmann constant, T is the absolute temperature, F is the noise figure of the amplifier, and R is the input resistance. The left term of the denominator represents the shot noise of the APD, and the right term of the denominator represents the thermal noise of the amplifier.

[0093] To simplify equation (12), we assume that Id is sufficiently smaller than Iph, and that the APD shot noise term and the amplifier thermal noise term are equal when the multiplication factor is set to maximize the S / N ratio. If we replace the amplifier thermal noise term with the APD shot noise term, the S / N ratio can be expressed by the following equation (13): S / N ratio=Iph / (4q F B) (13)

[0094] The excess noise factor F is given by the following equation (14): F = M(1-(1-k) x ((M-1) 2 / M 2 ))) (14)

[0095] In the case of a conventional InAlAs random alloy multiplication layer, as mentioned above, it is difficult to thin the layer (to 70 nm) enough to cause the dead space effect due to the influence of tunnel current, so there are no examples of its application to APDs. For this reason, systems are designed with the ionization rate ratio k set to 0.2 for an unthinned InAlAs multiplication layer. When the ionization rate ratio k = 0.2 and the multiplication factor is 12, the excess noise factor F = 3.9.

[0096] On the other hand, in the 50G-PON system according to the first embodiment, an APD with an InAlAs digital alloy structure as a multiplication layer, i.e., the DA-APD of the present disclosure, is used as the semiconductor light-receiving element. In the case of the InAlAs digital alloy structure multiplication layer of the present disclosure, the dead space effect functions even with a layer thickness of 100 nm or more, making it possible to apply it to an APD. In this case, the ionization rate ratio k = 0, and when the multiplication factor is 12 times, the excess noise factor F = 1.9. Therefore, the excess noise is approximately half that of a conventional APD. As a result, the DA-APD of the present disclosure can improve the S / N ratio by 3 dB.

[0097] Generally, in a 50G-PON system, inserting one stage of a 2-stage demultiplexer to increase the number of branches increases the loss by 3 dB. Therefore, by applying the DA-APD of the present disclosure as a semiconductor photodetector, it becomes possible to insert one more stage of demultiplexer into the 50G-PON system.

[0098] 10 is a diagram showing the configuration of a 50G-PON system 280 and an OLT / ONU as a comparative example. The OLT of the 50G-PON system 280 includes an FEC 251, a driver amplifier 252, a light source 253, a WDM 254, a DSP 255, an ADC 256, a burst TIA 257, and a conventional APD 258. The ONU of the 50G-PON system 280 includes an FEC 251, a driver amplifier 252, a light source 253, a WDM 254, a DSP 255, an ADC 256, a TIA 257a, and a conventional APD 258.

[0099] 11 is a diagram showing the configuration of a 50G-PON system 282 and an OLT / ONU according to embodiment 1. The OLT of the 50G-PON system 282 includes an FEC 261, a driver amplifier 262, a light source 263, a WDM 264, a DSP 265a, an ADC 266a, a burst TIA 267, and a DA-APD 268 of the present disclosure. The OLT of the 50G-PON system 282 includes an FEC 261, a driver amplifier 262, a light source 263, a WDM 264, a DSP 265a, an ADC 266a, a TIA 267a, and a DA-APD 268 of the present disclosure.

[0100] By applying the DA-APD of the present disclosure, the number of branches, which is 32 in the 50G-PON system 280 shown in Fig. 10 as a comparative example, can be doubled to 64 branches as in the 50G-PON system 282 according to the first embodiment shown in Fig. 11, thereby enabling a dramatic improvement. Furthermore, since it is possible to double the number of branches in PON systems other than the 50G-PON system 282, it is also possible to reduce the driving current of the laser in the transmitter.

[0101] 12 is a diagram showing the configuration of a 50G-PON system 284 and an OLT / ONU according to the first embodiment. The OLT of the 50G-PON system 284 includes a WDM 271, a light source 272, a driver amplifier 273, an FEC 274, a DA-APD 275 of the present disclosure, a burst TIA 276, a limiting amplifier 277, and a CDR 278. The ONU of the 50G-PON system 284 includes a WDM 271, a light source 272, a driver amplifier 273, an FEC 274, a DA-APD 275 of the present disclosure, a TIA 276a, a limiting amplifier 277, and a CDR 278.

[0102] In the comparative example, 50G-PON system 280, the use of SOAs in the optical line terminals ONU and OLT is being considered to compensate for the lack of sensitivity, but it is possible to configure the ONU and OLT without using SOAs, as in the 50G-PON system 284 according to embodiment 1 shown in Figure 12.

[0103] The effects of the semiconductor photodetector according to the present disclosure will now be further explained. The DA-APD according to the present disclosure has an InAlAs digital alloy structure multiplication layer, and by controlling the layer thickness of the multiplication layer within a predetermined range to set the ionization rate ratio k to zero, the multiplication time in equation (1) becomes nearly zero. As a result, the response bandwidth of the APD does not deteriorate even when the multiplication factor is increased. In other words, with the DA-APD according to the present disclosure, the bandwidth is limited only by the RC time constant and the carrier transit time, just like with conventional PDs. Therefore, the wide bandwidth required for 50G-PON systems is possible, and reception becomes possible without digital bandwidth compensation by a DSP.

[0104] Furthermore, when the ionization rate ratio k approaches zero, excess noise that deteriorates receiver sensitivity is suppressed, eliminating the need for optical signal amplification by an SOA. Furthermore, even in PON systems other than 50G-PON systems, it becomes possible to achieve higher branching than before. As a result, PON systems can be made lower cost and more energy-efficient.

[0105] <Effects of First Embodiment> As described above, the semiconductor photodetector according to the first embodiment has a digital alloy structure multiplication layer whose layer thickness is controlled within a predetermined range, and therefore has the effect of providing a semiconductor photodetector that is highly reliable and has excellent wideband and low-noise characteristics.

[0106] Embodiment 2 Fig. 13 is a cross-sectional view showing the device structure of a front-illuminated APD, which is an example of a semiconductor light-receiving element 120 according to embodiment 2. Fig. 14 is a cross-sectional view showing the device structure of an edge-illuminated APD, which is an example of a semiconductor light-receiving element 130 according to embodiment 2.

[0107] <Element Structure of Semiconductor Photodetector According to Second Embodiment> The semiconductor photodetector 120 according to the second embodiment includes an n-type InP substrate 1 and a semiconductor layer having a carrier concentration of 1 to 5×10 18 cm -3 and a layer thickness of 0.1 to 1.0 μm; an InAlAs digital alloy structure multiplication layer 3 in which an i-type AlAs layer (for example, a layer thickness of two atomic layers, about 0.6 nm) and an i-type InAs layer (for example, a layer thickness of two atomic layers, about 0.6 nm) are alternately stacked multiple times; and a carrier concentration of 0.1 to 50×10 17 cm -3 and a p-type InP field relaxation layer 4 having a layer thickness of 10 to 70 nm, an i-type InGaAs light absorption layer 5 having a layer thickness of 0.1 to 2.0 μm, an i-type InAlGaAs / InAlAs graded layer 6, and an i-type InAlGaAs / InAlAs layer 7 having a layer thickness of 0.1 to 3.0 μm and a carrier concentration of 5×10 17 cm -3 The n-type InAlAs buffer layer 2 is composed of an n-type InP window layer 11, a p-type diffusion region 15 provided in the n-type InP window layer 11, a p-type InGaAs contact layer 8 provided on the p-type diffusion region 15, an n-type electrode 31 formed on the back surface of the n-type InP substrate 1, and a p-type electrode 32 formed on the p-type InGaAs contact layer 8. The n-type InAlAs buffer layer 2 is also called an n-type semiconductor layer.

[0108] The semiconductor light-receiving element 130 according to the second embodiment shown in FIG. 14 includes an Fe-doped semi-insulating InP substrate 1a, an n-type InP conductive layer 2a formed in this order on the Fe-doped semi-insulating InP substrate 1a, and an n-type InP conductive layer 2b having a carrier concentration of 1 to 5×10 18 cm -3 and a layer thickness of 0.1 to 1.0 μm; an InAlAs digital alloy structure multiplication layer 3 in which an i-type AlAs layer (for example, a layer thickness of two atomic layers, about 0.6 nm) and an i-type InAs layer (for example, a layer thickness of two atomic layers, about 0.6 nm) are alternately stacked multiple times; and a carrier concentration of 0.1 to 50×10 17 cm -3 and a p-type InP field relaxation layer 4 having a layer thickness of 10 to 70 nm, an i-type InGaAs light absorption layer 5 having a layer thickness of 0.1 to 2.0 μm, an i-type InAlGaAs / InAlAs graded layer 6, and an i-type InAlGaAs / InAlAs layer 7 having a layer thickness of 0.1 to 3.0 μm and a carrier concentration of 5×10 17 cm -3 The n-type InP window layer 11 includes a p-type diffusion region 15 provided in the n-type InP window layer 11, a p-type InGaAs contact layer 8 provided on the p-type diffusion region 15, an n-type electrode 31a formed on the surface side of the n-type InP conductive layer 2a, and a p-type electrode 32 formed on the p-type InGaAs contact layer 8. The n-type InAlAs buffer layer 2 and the n-type InP conductive layer 2a are also referred to as n-type semiconductor layers.

[0109] The semiconductor photodetectors 120 and 130 according to the second embodiment differ from the semiconductor photodetectors 100 and 110 according to the first embodiment in that the n-type InP constituting the n-type InP window layer 11 is undoped (i-type) or has a low carrier concentration, and that a p-type diffusion region 15 is provided in the n-type InP window layer 11. The thickness of the n-type InP window layer 11 of the semiconductor photodetectors 120 and 130 is 0.1 μm or more and 3 μm or less, and the carrier concentration is 5×10 17 cm -3 The n-type InP window layer 11 may be made of InAlAs instead of InP, or may have a laminated structure of InP and InAlAs.

[0110] The p-type diffusion region 15 is formed by partially selectively diffusing a p-type dopant such as Zn in a solid or vapor phase. The carrier concentration of the p-type diffusion region 15 is 5×10 17 cm -3 That is all. The tip of the p-type diffusion region 15 may be located at a depth that reaches partway through the n-type InP window layer 11, a depth that reaches the i-type InAlGaAs / InAlAs graded layer 6, or a depth that reaches the i-type InGaAs light absorption layer 5. In the device structures shown in Figures 13 and 14, the p-type diffusion region 15 has a depth that reaches the i-type InAlGaAs / InAlAs graded layer 6. A p-type InGaAs contact layer 8 is provided on the p-type diffusion region 15.

[0111] In a front-illuminated APD, which is an example of a semiconductor photodetector 120 shown in FIG. 13, an n-type electrode 31 is provided on the back surface. On the other hand, in a front-illuminated APD, which is an example of a semiconductor photodetector 130 shown in FIG. 14, an n-type electrode 31a is provided on the front surface. That is, in the semiconductor photodetector 130, an n-type InP conductive layer 2a is provided on an Fe-doped semi-insulating InP substrate 1a. After crystal growth, the semiconductor layers above the n-type InP conductive layer 2a are partially removed, and then the n-type electrode 31a is formed on the n-type InP conductive layer 2a. In the semiconductor photodetector 130, a p-type InP substrate or an n-type InP substrate may be used instead of the Fe-doped semi-insulating InP substrate 1a.

[0112] <Function of the Semiconductor Photodetector According to the Second Embodiment> In a mesa structure such as a front-illuminated APD, which is an example of the semiconductor photodetector 100 according to the first embodiment shown in Figure 1, the side portion of the multiplication layer to which an electric field is applied is exposed to the outside and is therefore prone to deterioration. In particular, when the InAlAs digital alloy structure multiplication layer 3 is used as the multiplication layer, high strain is applied to each layer of the InAlAs digital alloy structure multiplication layer 3, so dislocation defects and disorder are likely to occur from the exposed portion toward the interior, which may result in a problem such as a shortened dead space length.

[0113] Furthermore, in the case of a multiplication layer in which an InAlAs digital alloy structure is thinned, as in the semiconductor photodetectors 100 and 110 according to the first embodiment, the electric field is several tens of percent higher than in the conventional InAlAs random alloy structure, and therefore, there is a risk that the life of the semiconductor photodetector will be shortened due to the influence of the side portions.

[0114] On the other hand, when a p-type diffusion region 15 is provided as in the semiconductor light-receiving element 120 shown in FIG. 13, the portion of the InAlAs digital alloy structure multiplication layer 3 to which an electric field is applied, i.e., the portion directly below the p-type diffusion region 15, is not exposed to the outside of the crystal layer, which has the effect of preventing deterioration of the dead space length in the InAlAs digital alloy structure multiplication layer 3 in which each layer is highly strained.

[0115] 13 , when the p-type diffusion region 15 is formed by thermal diffusion, the heat treatment temperature in the diffusion step reaches a high temperature of 400° C. or more, which makes it easy for disorder to occur in the InAlAs digital alloy structure multiplication layer 3. Furthermore, when Zn is diffused into the n-type InP window layer 11, components with a high diffusion rate and vacancies generated by the Zn diffusion reach the InAlAs digital alloy structure multiplication layer 3, causing disorder. In particular, if interdiffusion occurs with the p-type dopant in the p-type InP field buffer layer 4, disordering of the InAlAs digital alloy structure multiplication layer 3 may be accelerated.

[0116] Therefore, in the semiconductor light-receiving elements 120 and 130 according to the second embodiment, Be-doped p-type InP is used for the p-type InP electric field relaxation layer 4, thereby suppressing the diffusion of Be into the InAlAs digital alloy structure multiplication layer 3 and preventing the intrusion of Zn and vacancies into the InAlAs digital alloy structure multiplication layer 3 due to interdiffusion, thereby achieving the effect of preventing disordering of the InAlAs digital alloy structure multiplication layer 3.

[0117] Therefore, in the semiconductor light-receiving elements 120 and 130 according to the second embodiment, even if a high-temperature heat treatment is performed to diffuse Zn in the diffusion step of forming the p-type diffusion region 15, disordering of the InAlAs digital alloy structure multiplication layer 3 can be prevented, and the dead space length can be maintained long as shown in Fig. 6B without shortening as shown in Fig. 6C, for example. As a result, in the semiconductor light-receiving elements 120 and 130 according to the second embodiment, the ionization rate ratio k can be maintained at approximately zero despite the Zn diffusion performed to form the p-type diffusion region 15.

[0118] <Effects of Second Embodiment> As described above, according to the semiconductor photodetector of the second embodiment, even though Zn diffusion is performed to form a p-type diffusion region during device structure formation, disordering of the InAlAs digital alloy structure multiplication layer can be prevented, and the ionization rate ratio k can be maintained at approximately zero, thereby achieving the effect of providing a semiconductor photodetector that is highly reliable and has excellent wideband and low-noise characteristics.

[0119] Third Embodiment Fig. 15 is a cross-sectional view showing the device structure of a front-illuminated APD, which is an example of a semiconductor light-receiving device 140 according to a third embodiment.

[0120] <Element Structure of Semiconductor Photodetector According to Third Embodiment> The front-illuminated APD, which is an example of semiconductor photodetector 140 according to the third embodiment, is characterized in that, in addition to the element structure of the front-illuminated APD, which is an example of semiconductor photodetector 120 according to the second embodiment, an isolation groove 17 is provided along the outer periphery of p-type diffusion region 15 formed in n-type InP window layer 11.

[0121] The depth of the separation groove 17 is preferably in the range of 2 μm to 5 μm. The opening width of the separation groove 17 is preferably in the range of 0.5 μm to 100 μm. The bottom of the separation groove 17 reaches at least the InAlAs digital alloy structure multiplication layer 3. FIG. 15 shows an example in which the bottom of the separation groove 17 reaches partway through the n-type InAlAs buffer layer 2. The separation groove 17 may be formed by either dry etching or wet etching. However, it is preferable to perform dry etching, which has excellent depth control, followed by wet etching to remove any damaged layers caused by the dry etching.

[0122] The inside of the isolation groove 17 and the surface of the n-type InP window layer 11 are protected by a surface protective film 18, which is an insulating film made of an oxide such as SiN or SiO. The surface protective film 18 also serves as an anti-reflective coating for the light receiving section. The thickness of the surface protective film 18 is preferably in the range of 50 nm to 5000 nm. Alternatively, the surface protective film 18 may be an organic film such as benzocyclobutene (BCB).

[0123] <Function of the Semiconductor Photodetector According to the Third Embodiment> When an InAlAs digital alloy structure is used as a multiplication layer, each layer of the InAlAs digital alloy structure is highly strained, and external stress can easily cause disordering of the InAlAs digital alloy structure. Therefore, by providing a separation groove 17 along the outer periphery of the p-type diffusion region 15, as in the semiconductor photodetector 140 according to the third embodiment, stress across the entire wafer during the manufacturing process can be alleviated. Furthermore, even when the semiconductor photodetector 140 is in the individual state, the presence of the separation groove 17 alleviates stress, thereby alleviating stress concentration in the central light-receiving portion of the semiconductor photodetector 140. Furthermore, because the InAlAs digital alloy structure multiplication layer 3 is exposed in the separation groove 17, it is desirable that the surface of the separation groove 17 be covered with the above-described surface protection film 18. Note that a high electric field is not applied to the separation groove 17, and therefore it does not become a starting point for degradation.

[0124] As described above, in the semiconductor light-receiving element 140 of the third embodiment, even if a high-temperature heat treatment is performed to diffuse Zn in the diffusion step of forming the p-type diffusion region 15, disordering of the InAlAs digital alloy structure multiplication layer 3 can be prevented, and therefore, the dead space length does not become shorter as shown in Fig. 6C, for example, and it is possible to maintain a long dead space length as shown in Fig. 6B. As a result, it is possible to maintain the ionization rate ratio k at approximately zero despite the Zn diffusion being performed in the manufacturing process.

[0125] Furthermore, since stress is alleviated by the separation groove 17 even during operation of the semiconductor light-receiving element 140, no disorder occurs even when the semiconductor light-receiving element 140 is used for a long period of time. In other words, the semiconductor light-receiving element 140 of the third embodiment can achieve high reliability, in that it is possible to maintain a wide bandwidth and low noise for a long period of time.

[0126] <Effects of Third Embodiment> As described above, according to the semiconductor photodetector of the third embodiment, even though Zn diffusion is performed to form the p-type diffusion region 15 during device structure formation, disordering of the InAlAs digital alloy structure multiplication layer can be prevented, and therefore the ionization rate ratio k can be maintained at approximately zero. In addition, the presence of the separation groove can alleviate stress, resulting in an effect of providing a semiconductor photodetector that is highly reliable and has excellent wideband and low-noise characteristics.

[0127] Fourth Embodiment Fig. 16 is a cross-sectional view showing the device structure of a back-illuminated APD, which is an example of a semiconductor light-receiving device 150 according to a fourth embodiment.

[0128] <Element Structure of Semiconductor Photodetector According to Fourth Embodiment> While a front-illuminated APD, which is an example of semiconductor photodetector 140 according to the third embodiment, receives light from the front side, a back-illuminated APD, which is an example of semiconductor photodetector 150 according to the fourth embodiment, is characterized in that it has an element structure in which a part of n-type electrode 31b on the back side is removed to provide opening 33, and light is incident on n-type InP substrate 1 exposed in opening 33. In other words, opening 33, which is an incident region for incident light 90, is provided on the back side of n-type InP substrate 1 opposite p-type electrode 32.

[0129] The back-illuminated APD, which is an example of the semiconductor photodetector 150 according to the fourth embodiment, can prevent the InAlAs digital alloy structure multiplication layer 3 from becoming disordered even when a high-temperature heat treatment is performed to diffuse Zn in the diffusion step of forming the p-type diffusion region 15, similar to the semiconductor photodetector 140 according to the third embodiment. Therefore, the dead space length does not become shorter as shown in FIG. 6C, and it is possible to maintain a long dead space length as shown in FIG. 6B.

[0130] Furthermore, because the area of ​​the p-type diffusion region 15 can be made smaller in a back-illuminated APD such as the semiconductor photodetector 150 than in a front-illuminated APD such as the semiconductor photodetector 120, it is possible to further reduce the stress generated during p-type diffusion, thereby further preventing disordering of the InAlAs digital alloy structure multiplication layer 3. As a result, even though Zn diffusion is performed during device structure formation, disordering of the InAlAs digital alloy structure multiplication layer 3 can be prevented, making it possible to maintain the ionization rate ratio k at approximately zero and further reducing the stress, resulting in a semiconductor photodetector that is highly reliable and has excellent wideband and low-noise characteristics.

[0131] <Effects of Fourth Embodiment> As described above, according to the semiconductor light-receiving element of the fourth embodiment, the element structure is a back-illuminated APD, and therefore the area of ​​the p-type diffusion region can be made smaller than that of a front-illuminated APD. This makes it possible to maintain the ionization rate ratio k at almost zero, and further alleviate stress, thereby achieving the effect of providing a semiconductor light-receiving element that is highly reliable and has excellent wide-band and low-noise characteristics.

[0132] Fifth Embodiment Fig. 17 is a cross-sectional view showing the device structure of a front-illuminated APD, which is an example of a semiconductor light-receiving element 160 according to the fifth embodiment. Fig. 18 is a cross-sectional view showing another device structure of a front-illuminated APD, which is an example of a semiconductor light-receiving element 170 according to the fifth embodiment.

[0133] <Element Structure of Semiconductor Photodetector According to Fifth Embodiment> The semiconductor photodetector 160 according to the fifth embodiment includes an n-type InP substrate 1 and a semiconductor layer having a carrier concentration of 1 to 5×1018 cm -3 and a layer thickness of 0.1 to 1.0 μm; an InAlAs digital alloy structure multiplication layer 3 in which an i-type AlAs layer (for example, a layer thickness of two atomic layers, about 0.6 nm) and an i-type InAs layer (for example, a layer thickness of two atomic layers, about 0.6 nm) are alternately stacked multiple times; and a carrier concentration of 0.1 to 50×10 17 cm -3 The n-type InP substrate 1 includes a p-type InAlAs field relaxation layer 4 having a thickness of 10 to 70 nm, an i-type InGaAs light absorption layer 5 having a thickness of 0.1 to 2.0 μm, an i-type InAlGaAs / InAlAs graded layer 6, an n-type InP window layer 11 having a thickness of 0.1 to 3.0 μm, a p-type InAlAs conductive layer 25, a p-type InGaAs contact layer 8, an n-type electrode 31 formed on the back surface of the n-type InP substrate 1, and a p-type electrode 32 formed on the p-type InGaAs contact layer 8. The n-type InAlAs buffer layer 2 is also called an n-type semiconductor layer.

[0134] The semiconductor photodetector 160 according to the fifth embodiment differs from the semiconductor photodetector 100 according to the first embodiment in that the p-type InAlAs conductive layer 25 formed on the n-type InP window layer 11 is formed in a mesa shape, and a p-type InGaAs contact layer 8 and a p-type electrode 32 are provided on the p-type InAlAs conductive layer 25. The n-type InP window layer 11 may have a thickness of 50 nm or more, but a thickness of 200 nm or less is preferable in order to prevent the carrier transit time from becoming long. The conductivity type of the n-type InP window layer 11 may be undoped instead of n-type. In the case of n-type, the carrier concentration is 5.0×10 17 cm -3 The following is desirable:

[0135] The method for manufacturing the semiconductor light-receiving element 160 according to the fifth embodiment is characterized in that the p-type InAlAs conductive layer 25 is crystal-grown on the n-type InP window layer 11 by MOCVD or the like, and then the p-type InGaAs contact layer 8 is crystal-grown, and thereafter the p-type InAlAs conductive layer 25 is removed while leaving the light-receiving portion.

[0136] The thickness of the p-type InAlAs conductive layer 25 is preferably 100 nm or more and 3000 nm or less. The carrier concentration of the p-type InAlAs conductive layer 25 is preferably high, that is, 5.0×10 17 cm -3 The p-type InAlAs conductive layer 25 may be a laminated structure of p-type InP, p-type InGaAs, p-type InGaAsP, or p-type InAlGaAs instead of p-type InAlAs.

[0137] 17 has an n-type electrode 31 on the back surface side, whereas the semiconductor light-receiving element 160 shown in FIG. 18 has an n-type electrode 31a on the front surface side. That is, in the semiconductor light-receiving element 170, an n-type InP conductive layer 2a is provided on an Fe-doped semi-insulating InP substrate 1a, and after crystal growth, the layers above the n-type InP conductive layer 2a are partially removed, and then the n-type electrode 31a is formed on the n-type InP conductive layer 2a. A p-type InP substrate or an n-type InP substrate may be used instead of the Fe-doped semi-insulating InP substrate 1a.

[0138] <Function of Semiconductor Photodetector According to Fifth Embodiment> The function of the semiconductor photodetectors 160 and 170 according to the fifth embodiment will be described below. When forming the p-type InAlAs conductive layer 25 to which a voltage is applied, the p-type diffusion process involving heat treatment at a high temperature of 400° C. or higher is not performed, as in the semiconductor photodetector 120 according to the second embodiment shown in FIG. 14 . This prevents the InAlAs digital alloy structure multiplication layer 3 from becoming disordered. Therefore, for example, the dead space length does not become shorter as shown in FIG. 6C , but rather it is possible to maintain a long dead space length as shown in FIG. 6B . As a result, it is possible to maintain the ionization rate ratio k at approximately zero.

[0139] As described above, according to the semiconductor photodetector of the fifth embodiment, similarly to the semiconductor photodetector of the second embodiment, the region of the multiplication layer directly below the photodetector to which a high electric field is applied is located away from the side surface of the device, thereby achieving high reliability. As a result, a semiconductor photodetector having high reliability and excellent broadband and low noise characteristics can be obtained.

[0140] Sixth Embodiment Fig. 19 is a cross-sectional view showing the device structure of a front-illuminated APD, which is an example of a semiconductor light-receiving device 180 according to a sixth embodiment.

[0141] <Element Structure of Semiconductor Photodetector According to Sixth Embodiment> A front-illuminated APD, which is an example of the semiconductor photodetector 180 according to the sixth embodiment, is characterized in that a separation groove 17 is further provided along the outer periphery of the p-type InAlAs conductive layer 25 in addition to the element structure of the front-illuminated APD, which is an example of the semiconductor photodetector 160 according to the fifth embodiment.

[0142] The depth of the separation groove 17 is preferably in the range of 2 μm to 5 μm. The opening width of the separation groove 17 is preferably in the range of 0.5 μm to 100 μm. The bottom of the separation groove 17 reaches at least the InAlAs digital alloy structure multiplication layer 3. Note that FIG. 19 shows an example in which the bottom of the separation groove 17 reaches partway through the n-type InAlAs buffer layer 2. The separation groove 17 may be formed by either dry etching or wet etching. However, it is preferable to perform dry etching, which has excellent depth control, followed by wet etching to remove damaged layers caused by the dry etching.

[0143] The inside of the separation groove 17 and the surface of the n-type InP window layer 11 are protected by a surface protective film 18, which is an insulating film made of an oxide film such as SiN or SiO. The surface protective film 18 also serves as an anti-reflective coating for the light receiving section. The thickness of the surface protective film 18 is preferably in the range of 50 nm to 5000 nm. Alternatively, the surface protective film 18 may be an organic film such as BCB.

[0144] <Function of the Semiconductor Photodetector According to Sixth Embodiment> When an InAlAs digital alloy structure is used as a multiplication layer, each layer of the InAlAs digital alloy structure is highly strained, and therefore, when external stress is applied, disordering is likely to occur. Therefore, by providing a separation groove 17 along the outer periphery of the p-type InAlAs conductive layer 25, as in the semiconductor photodetector 180 according to the sixth embodiment, stress across the entire wafer during the manufacturing process can be alleviated. Furthermore, even when the semiconductor photodetector 180 is in the individual state, the presence of the separation groove 17 alleviates stress, thereby alleviating stress concentration in the central light-receiving portion of the semiconductor photodetector 180. Furthermore, because the InAlAs digital alloy structure multiplication layer 3 is exposed in the separation groove 17, it is desirable that the surface of the separation groove 17 be covered with the above-described surface protection film 18. Furthermore, because a high electric field is not applied to the separation groove 17, it does not become a starting point for degradation.

[0145] <Effects of Sixth Embodiment> As described above, according to the semiconductor photodetector of the sixth embodiment, the separation groove can relieve stress due to heat treatment and the like in the manufacturing process, and therefore disordering of the digital alloy structure multiplication layer can be prevented, so that it is possible to maintain the ionization rate ratio k at almost zero, and an effect is achieved in that a semiconductor photodetector is obtained that is highly reliable and has excellent wideband and low-noise characteristics.

[0146] Seventh Embodiment Fig. 20 is a cross-sectional view showing the device structure of a back-illuminated APD, which is an example of a semiconductor light-receiving device 190 according to a seventh embodiment.

[0147] <Element Structure of Semiconductor Photodetector According to Seventh Embodiment> While a front-illuminated APD, which is an example of semiconductor photodetector 180 according to the sixth embodiment, receives light from the front side as shown in Fig. 19 , a back-illuminated APD, which is an example of semiconductor photodetector 190 according to the seventh embodiment, is characterized in that it has an element structure in which a part of n-type electrode 31b on the back side is removed to provide opening 33, and light is incident on n-type InP substrate 1 exposed in opening 33, as shown in Fig. 20 . In other words, opening 33, which is an incident region for incident light 90, is provided on the back side of n-type InP substrate 1 opposite p-type electrode 32.

[0148] In the back-illuminated APD, which is an example of the semiconductor photodetector 190 according to the seventh embodiment, similarly to the semiconductor photodetector 180 according to the sixth embodiment, the separation grooves can relieve stress due to heat treatment or the like in the manufacturing process, and therefore disordering of the InAlAs digital alloy structure multiplication layer 3 can be prevented. As a result, the dead space length does not become shorter as shown in FIG. 6C, but rather it is possible to maintain a long dead space length as shown in FIG. 6B.

[0149] Furthermore, because the area of ​​the p-type InAlAs conductive layer 25 can be made smaller in a back-illuminated APD such as the semiconductor photodetector 190 than in a front-illuminated APD, stress due to heat treatment and the like in the manufacturing process can be further reduced, thereby further preventing disordering of the InAlAs digital alloy structure multiplication layer 3. As a result, even though a heat treatment process is performed during device structure formation, disordering of the InAlAs digital alloy structure multiplication layer 3 can be prevented, making it possible to maintain the ionization rate ratio k at approximately zero and further reducing stress, resulting in the advantageous effect of providing a semiconductor photodetector that is highly reliable and has excellent wideband and low-noise characteristics.

[0150] Furthermore, in a back-illuminated APD such as the semiconductor photodetector 190, the area of ​​the mesa-shaped p-type InAlAs conductive layer 25 can be reduced compared to that of a front-illuminated APD, and therefore the influence of stress from the mesa portion of the p-type InAlAs conductive layer 25 is reduced, preventing disordering of the InAlAs digital alloy structure multiplication layer 3. Furthermore, since stress is relaxed even during operation of the semiconductor photodetector 190, no disordering of the InAlAs digital alloy structure multiplication layer occurs even after a long period of time. In other words, the semiconductor photodetector 190 according to the seventh embodiment can maintain a wide bandwidth and low noise for a long period of time.

[0151] <Effects of Seventh Embodiment> As described above, according to the semiconductor light-receiving element of the seventh embodiment, the area of ​​the p-type conductive layer can be made small, and therefore the stress generated in the heat treatment process can be further reduced. This further prevents the InAlAs digital alloy structure multiplication layer 3 from becoming disordered, making it possible to maintain the ionization rate ratio k at almost zero, and further reducing the stress. This has the effect of providing a semiconductor light-receiving element that is highly reliable and has excellent wide-band and low-noise characteristics.

[0152] Eighth Embodiment Fig. 21 is a cross-sectional view showing the device structure of a back-illuminated APD, which is an example of a semiconductor light-receiving device 200 according to an eighth embodiment.

[0153] <Element Structure of Semiconductor Photodetector According to Eighth Embodiment> The semiconductor photodetector 200 according to the eighth embodiment includes an Fe-doped semi-insulating InP substrate 1a and an Fe-doped semi-insulating InP layer having a carrier concentration of 1 to 5×10 18 cm -3 and a p-type InGaAlAs contact layer 40 having a thickness of 0.1 to 1 μm and a carrier concentration of 1 to 5×10 18 cm -3 and a p-type InP conductive layer 41 having a layer thickness of 0.1 to 1 μm, and a p-type or low carrier concentration (5×10 17 cm -3 an n-type or i-type InAlGaAs / InAlAs graded layer 42 having a thickness of 0.1 to 2.0 μm; an i-type InGaAs light absorption layer 43 having a thickness of 10 to 100 nm and a carrier concentration of 1 to 50×10 17 cm -3 a p-type InP field relaxation layer 44 having a thickness of 2 atomic layers, approximately 0.6 nm; an InAlAs digital alloy structure multiplication layer 45 having a digital alloy structure in which an i-type AlAs layer (for example, a layer thickness of 2 atomic layers, approximately 0.6 nm) and an i-type InAs layer (for example, a layer thickness of 2 atomic layers, approximately 0.6 nm) are alternately stacked multiple times; an n-type InAlAs field adjustment layer 46 having a thickness of 10 to 50 nm; an n-type InP window layer 47 having a thickness of 0.1 to 2 μm; and an n-type InAlAs window layer 48 having a thickness of 0.1 to 2 μm and a carrier concentration of 5×10 17 ~8 x 10 18 cm -3and an n-type InAlAs conductive layer 48 having a thickness of 0.1 to 2 μm and a carrier concentration of 5×10 17 ~8 x 10 18 cm -3 the p-type InGaAlAs contact layer 40; an n-type electrode 50 formed on the n-type InGaAs contact layer 49; a p-type electrode 51 formed on the p-type InGaAlAs contact layer 40; and a metal film 53 formed on the back surface of the Fe-doped semi-insulating InP substrate 1a. The p-type InP conductive layer 41 is also called a p-type semiconductor layer.

[0154] <Method for Manufacturing a Semiconductor Photodetector According to the Eighth Embodiment> A method for manufacturing a semiconductor photodetector 200 according to the eighth embodiment will be described below. An Fe-doped semi-insulating InP substrate 1a is doped with a GaN layer having a carrier concentration of 1 to 5×10 by MOVPE or MBE. 18 cm -3 The p-type InGaAlAs contact layer 40 is crystal-grown to a thickness of 0.1 to 1 μm. An n-type InP substrate may be used instead of the Fe-doped semi-insulating InP substrate 1a. The p-type InGaAs contact layer 40 may be made of p-type InP, p-type InGaAsP, or p-type InGaAs instead of p-type InGaAlAs.

[0155] On the p-type InGaAlAs contact layer 40, a carrier concentration of 1 to 5×10 18 cm -3 The p-type InP conductive layer 41 is grown to a thickness of 0.1 to 1 μm. The p-type InP conductive layer 41 may be made of p-type InGaAsP or p-type InAlGaAs instead of p-type InP.

[0156] Next, an i-type, n-type, or p-type InAlAs layer having a small barrier to holes may be formed on the p-type InP conductive layer 41. Furthermore, a p-type or low carrier concentration (5×10 17 cm -3 After growing the n-type or i-type InAlGaAs / InAlAs graded layer 42 having a carrier concentration of 5×10 or less, the i-type InGaAs light absorbing layer 43 is grown to a thickness of 0.1 to 2 μm. 17 cm -3Here, either the p-type InP conductive layer 41 or the n-type InAlGaAs / InAlAs graded layer 42, or both, are not necessarily required.

[0157] Next, the carrier concentration is 1 to 50×10 17 cm -3 The p-type InP field buffer layer 44 is crystal-grown to a thickness of 10 to 100 nm. Examples of p-type dopants for the p-type InP field buffer layer 44 include Be, Zn, and C. The p-type InP field buffer layer 44 does not necessarily have to be p-type InP, and may also have a p-type InAlAs or p-type InAlAs digital alloy structure.

[0158] If the dopants in the p-type InP field buffer layer 44 diffuse into the adjacent InAlAs digital alloy structure multiplication layer 45, the InAlAs digital alloy structure becomes disordered and changes to an InAlAs random alloy structure. In particular, since the InAlAs digital alloy structure multiplication layer 45 is thin, at approximately 100 nm, the influence of disorder caused by dopant diffusion is significant. Therefore, Be, which is less likely to diffuse, is optimal as the p-type dopant for the p-type InP field buffer layer 44. On the other hand, when a p-type InAlAs field buffer layer is used, Zn is optimal as the p-type dopant.

[0159] Furthermore, an InAlGaAs / InAlAs graded layer having a thickness of 10 to 100 nm and an intermediate band gap value, such as InAlGaAs or InGaAsP, may be provided between the i-type InGaAs light absorption layer 43 and the p-type InP field relaxation layer 44.

[0160] An InAlAs digital alloy structure multiplication layer 45 is grown as a multiplication layer on the p-type InP field buffer layer 44. The InAlAs digital alloy structure multiplication layer 45 is composed of semiconductor layers in which an AlAs layer (having a thickness of two atomic layers, approximately 0.6 nm) and an InAs layer (having a thickness of two atomic layers, approximately 0.6 nm) are alternately stacked in this order from the Fe-doped semi-insulating InP substrate 1a side. The InAlAs digital alloy structure multiplication layer 45 may alternatively be formed in the order of an InAs layer and an AlAs layer.

[0161] The number of atomic layers in each layer of the InAlAs digital alloy structure multiplication layer 45 is preferably 2 to 4, and is optimally 2. The reason for this is that the thinner the atomic layer thickness of each layer, the greater the effect of the digital alloy structure in reducing the ionization rate ratio k.

[0162] The conductivity type of the InAlAs digital alloy structure multiplication layer 45 is i-type, and the carrier concentration is 1×10 17 cm -3 However, the carrier concentration is 5×10 18 cm -3 It may be p-type or n-type as follows.

[0163] The thickness of the InAlAs digital alloy structure multiplication layer 45 is preferably in the range of 40 nm to 170 nm in order to increase the dead space effect in the InAlAs digital alloy structure multiplication layer 45. However, considering a typical variation of 20% in layer thickness during fabrication of the semiconductor light receiving element 190, the thickness of the InAlAs digital alloy structure multiplication layer 45 is preferably in the range of 50 nm to 140 nm inclusive.

[0164] Next, an n-type InAlAs field adjustment layer 46 is grown by crystal growth to a thickness of 10 to 50 nm, and then an n-type InP window layer 47 is grown by crystal growth to a thickness of 0.1 to 2 μm. Here, the n-type InP window layer 47 also functions as a field adjustment layer and an electron transit layer, but is not necessarily required. The n-type InAlAs field adjustment layer 46 and the n-type InP window layer 47 are layers for adjusting the electric field on the outermost surface, and have a carrier concentration of 1 to 500×10 16 cm -3 The range of is preferable. By weakening the electric field on the outermost surface, local breakdown is suppressed and reliability is improved.

[0165] An n-type InAlAs conductive layer 48 is grown as an n-type conductive layer on the n-type InP window layer 47, and an n-type InGaAs contact layer 49 is grown as an n-type contact layer. The thickness of the n-type InAlAs conductive layer 48 and the n-type InGaAs contact layer 49 is 0.1 to 2 μm, and the carrier concentration is 5×10 17 cm -3 ~8 x 10 18 cm-3 is.

[0166] After crystal growth of the n-type InGaAs contact layer 49, the n-type InAlAs conductive layer 48 and the n-type InGaAs contact layer 49 are etched into a mesa shape to form a first mesa. Then, a second mesa is formed by etching the outer side of the first mesa to include the first mesa and reach the p-type InGaAs contact layer 40. The second mesa does not need to reach the p-type InGaAs contact layer 40 as long as it can electrically isolate the i-type InGaAs light absorption layer 43. The distance between the first and second mesas is preferably 1 μm or more. Alternatively, the first mesa may be formed after the second mesa is formed.

[0167] The p-type electrode 51 is formed on the p-type InGaAs contact layer 40, and the n-type electrode 50 is formed on the n-type InGaAs contact layer 49. Note that, in the case of an n-type semiconductor, the ohmic resistance is one order of magnitude smaller than that of a p-type semiconductor, so it is not necessarily necessary to use the n-type InGaAs contact layer 49, which has a small band gap; n-type InP, n-type InGaAlAs, or n-type InGaAsP may also be used. Alternatively, a direct contact may be made with the n-type InAlAs conductive layer 48. Through the above steps, the semiconductor light-receiving element 200 according to the eighth embodiment is completed.

[0168] <Functions and Effects of Semiconductor Photodetector According to Eighth Embodiment> The semiconductor photodetector 200 according to the eighth embodiment is characterized in that the conductivity types of the semiconductor photodetector 180 according to the seventh embodiment are inverted from n-type to p-type and from p-type to n-type, respectively, and the conductivity type of the upper surface side is made n-type.

[0169] The first function and effect of the semiconductor photodetector 200 according to the eighth embodiment will be described below. The InAlAs digital alloy structure multiplication layer 45 may become disordered and assume an InAlAs random alloy structure if maintained at high temperatures for a long period of time during epitaxial crystal growth. In the semiconductor photodetector 200 according to the eighth embodiment, the total thickness of the semiconductor layers above the InAlAs digital alloy structure multiplication layer 45 is approximately one-third that of the semiconductor photodetector 190 according to the seventh embodiment. That is, in the semiconductor photodetector 200 according to the eighth embodiment, the crystal growth time required for epitaxially growing the remaining semiconductor layers after the crystal growth of the InAlAs digital alloy structure multiplication layer 45 is approximately one-third that of the semiconductor photodetector 190 according to the seventh embodiment. Therefore, the InAlAs digital alloy structure multiplication layer 45 is less likely to become disordered. As a result, the dead space length is increased, and a state in which the ionization rate ratio k is zero can be more reliably achieved.

[0170] A second function and effect of the semiconductor light-receiving element 200 according to the eighth embodiment will be described below. The upper electrode of the semiconductor light-receiving element, i.e., the electrode on the front surface side, is a p-type electrode 32 in the back-illuminated APD shown in FIG. 20 and an n-type electrode 50 in the back-illuminated APD shown in FIG. 21. To increase the speed, it is necessary to further reduce the electrode area of ​​the front surface side electrode to reduce the capacitance. However, reducing the electrode area of ​​the upper electrode increases the contact resistance between the electrode and the semiconductor layer, which causes a problem of an increased RC time constant and a narrower response band.

[0171] In the semiconductor photodetector 200 according to the eighth embodiment, the upper electrode, i.e., the n-type electrode 50, is in contact with an n-type semiconductor, thereby reducing the ohmic resistance to one-tenth of that of a contact with a p-type semiconductor. This allows the area of ​​the n-type electrode 50 to be reduced, thereby reducing stress from the electrode and making disorder less likely to occur in the InAlAs digital alloy structure multiplication layer 45. As a result, the semiconductor photodetector 200 according to the eighth embodiment can more easily achieve a state in which the ionization rate ratio k is zero, thereby achieving the following effects in a PON system: reducing the number of bandwidth compensation circuits, doubling the number of branches, omitting an SOA, and reducing the operating current of the transmitter laser.

[0172] Effect of Eighth Embodiment As described above, according to the semiconductor photodetector of the eighth embodiment, the crystal growth time required for epitaxially growing the remaining semiconductor layers after the InAlAs digital alloy structure multiplication layer has been crystal grown is about one-third of that in the semiconductor photodetector of the seventh embodiment, and therefore disordering of the InAlAs digital alloy structure multiplication layer is even less likely to occur. This makes it possible to more reliably achieve a state in which the dead space length is increased and the ionization rate ratio k is zero, and also makes it possible to further reduce stress, thereby achieving the effect of providing a semiconductor photodetector that is highly reliable and has excellent wideband and low-noise characteristics.

[0173] Ninth embodiment Fig. 22 is a diagram showing the configuration of a multi-level intensity modulation transmitting / receiving apparatus 300 according to a ninth embodiment. Also, Fig. 23A and Fig. 23B are diagrams showing received waveforms of the multi-level intensity modulation transmitting / receiving apparatus 300 according to the ninth embodiment.

[0174] The multilevel intensity modulation transmitting / receiving device 300 is a multilevel intensity modulation transmitting / receiving device that uses PAM (Pulse Amplitude Modulation), which is a multilevel intensity modulation method. In the transmitting section, a digital signal generated by a DSP 301 is converted to an analog signal by a DAC 302a, amplified by a driver amplifier 303, and driven by a light source 304 consisting of a DFB laser or EML to emit an optical signal to an optical fiber cable 310.

[0175] Meanwhile, in the receiving section, the light passes through the optical fiber cable 310 and the optical system and enters the DA-APD 305, which is the semiconductor light receiving element of the present disclosure, where the light signal is converted into a current and multiplied. After being amplified in the Linear-TIA 306, the light is converted into a digital signal in the ADC 302b and signal processing is performed by the DSP 301.

[0176] <Functions and Effects of the Multilevel Intensity Modulation Transmitter / Receiver According to the Ninth Embodiment> The PAM-based multilevel intensity modulation transmitter / receiver 300 is required to receive not only binary signals of 1 and 0 such as NRZ (None Return to Zero) and RZ (Return to Zero), but also four values ​​of different optical signal intensities, for example, in PAM4 (Pulse Amplitude Modulation-4). An example of a PAM4 received waveform is shown in FIG. 23A. To determine whether the received waveform in PAM4 is good or bad, an index called TDECQ (Transmitter Dispersion and Eye Closure Quaternary) is used. TDECQ is calculated using the following equation (15). TDECQ (dB) = 10log (OMA / (6・Qt・R)) (15)

[0177] In equation (15), the optical modulation amplitude (OMA) is the total amplitude from level 0 to level 3, Qt is a value dependent on the SER (Symbol Error Rate) defined by the IEEE (Institute of Electrical and Electronics Engineers), and R is the additional noise value required to achieve the SER value. TDECQ (dB) is defined as, for example, 3 dB or less. To reduce TDECQ (dB), the following are required: (1) the eye opening at each level is uniform, and (2) the noise at each level is low.

[0178] In order to ensure uniform eye openings at each of the four levels of optical signal intensity, the semiconductor photodetector must have excellent linearity. Here, good linearity of a semiconductor photodetector means that the photocurrent Iph increases in proportion to the optical input power Pin. In other words, even if the optical input power Pin changes, the semiconductor photodetector has good linearity if Iph / Pin is constant.

[0179] Furthermore, PAM requires a good dynamic range because it must receive signals ranging from low to high intensity. In other words, even if the optical input power Pin increases, a good dynamic range can be achieved if the decrease in Iph / Pin is small. As shown in the received waveform in Figure 23B, if the linearity and dynamic range deteriorate, the eye opening formed between level 2 and level 3 deteriorates.

[0180] In the case of an APD, the linearity deteriorates because, as the photocurrent increases with increasing optical input, the number of holes and electrons traveling in the multiplication layer and the light absorption layer increases, causing a change in the electric field distribution in the multiplication layer and the light absorption layer. This phenomenon is called the space charge effect.

[0181] The inventors have studied a model for the degradation of APD linearity. Figures 24A and 24B are diagrams for explaining the operation of a PD when a high optical input is applied. As shown in Figure 24A, when the optical input increases and the photocurrent increases, a space charge effect occurs, as if a voltage drop occurs due to series resistance, preventing voltage from being applied to the pn junction. This voltage drop reduces the multiplication factor. This is because the generated electrons and holes affect the electric field distribution, as shown in Figure 24B. The series resistance Rli that degrades the linearity of an APD is expressed by the following equation (16): Rli = Rsc + Rd + Rlo (16)

[0182] In equation (16), Rsc is the resistance due to the space charge effect, Rd is the element resistance, and Rlo is the load resistance. Rd and the load resistance are usually several tens of Ω, but Rsc can be several hundreds of Ω or more.

[0183] When the time it takes for electrons and holes generated by light absorption to pass through the depletion layer is Td, it was found that Rsc can be expressed by the following equation (17): Rsc=W·Td / (2εS) (17) In equation (17), W is the thickness of the depletion layer, ε is the dielectric constant, and S is the pn junction area.

[0184] Next, the operation of an APD at high light input will be described. FIG. 25 is a diagram illustrating the operation of an APD at high light input. When a large number of electrons and holes are generated in the multiplication layer, the electric field in the multiplication layer of the APD changes, that is, the so-called space charge effect occurs. This space charge effect reduces the multiplication factor of the APD and deteriorates its linearity. As described above, the deterioration of the linearity of the APD is caused by the series resistance Rsc, so it is necessary to reduce the residence time Td of electrons and holes in the depletion layer. In particular, as the multiplication factor increases, the residence time Tdm in the multiplication layer increases. Tdm is the same as the so-called multiplication time, and is expressed by the following equation (18): Residence time Tdm = multiplication time = 2π N k M τav (18)

[0185] In equation (18), N is the Emmons coefficient (which is gradually dependent on the ionization rate ratio k), M is the multiplication factor, and τav is the time it takes for a carrier to travel through the multiplication layer. The residence time Tdm excludes the one-way transit time it takes for a carrier to cross the multiplication layer. The multiplication factor N is 0.55, 0.83, 1.1, and 2.0 when the ionization rate ratio k=0.5 (InP), 0.2 (InAlAs), 0.1 (Si), and 0 to 0.001 (InAlAs digital alloy structure), respectively.

[0186] Figure 26 shows the residence time Tdm of electrons and holes for each material constituting the multiplication layer. In the InAlAs digital alloy structure multiplication layer, the residence time Tdm within the multiplication layer is dramatically reduced. In other words, electrons and holes are quickly discharged from the multiplication layer, suppressing the space charge effect in the multiplication layer, resulting in improved linearity and dynamic range in the InAlAs digital alloy structure multiplication layer.

[0187] As a result, while the eye opening of PAM4 was non-uniform with a conventional APD as shown in Fig. 23B, the eye opening is uniform with the DA-APD of the present disclosure as shown in Fig. 23A, making it possible for TDECQ to satisfy the specified value. Therefore, the DA-APD of the present disclosure allows the APD to be used in a PAM transceiver, which makes it possible to increase the transmission distance of optical signals and reduce the drive current of the transmitting laser.

[0188] <Effects of Ninth Embodiment> As described above, the multi-level intensity modulation transmitting / receiving device according to the ninth embodiment uses the DA-APD of the present disclosure as the semiconductor light-receiving element, and therefore has the effect of providing a multi-level intensity modulation transmitting / receiving device that can increase the transmission distance of optical signals and reduce power consumption.

[0189] Tenth Embodiment Fig. 27 is a schematic diagram showing the configuration of a radio-on-fiber (RoF) system 400 according to a tenth embodiment. Fig. 28 is a schematic diagram showing the configuration of a radio-on-fiber system 450, which is a comparative example. The radio-on-fiber system 400 includes a light source 401, a transmission path 402 such as an optical fiber cable, a DA-APD 403 according to the present disclosure, and an antenna 404.

[0190] In a radio-on-fiber system 400 according to the tenth embodiment, an analog electrical amplitude signal is input to a light source 401 such as an LD and converted into an optical amplitude signal. The converted optical amplitude signal is transmitted through an optical fiber cable, i.e., a transmission path 402. The transmitted optical amplitude signal is multiplied and converted into an electrical amplitude signal using a DA-APD 403 according to the present disclosure. The converted electrical amplitude signal is transmitted to an antenna 404 and radiated as a radio wave signal.

[0191] The radio-on-fiber system 400 according to the tenth embodiment can efficiently supply signals to an antenna 404 that is located at a distance from an electrical signal source. Furthermore, since no analog-to-digital or digital-to-analog conversion is performed during transmission, the system has the advantages of a simple configuration and low power consumption.

[0192] <Functions and Effects of Radio-on-Fiber System According to Tenth Embodiment> In the radio-on-fiber system 450 of the comparative example shown in FIG. 28, if the signal is attenuated during transmission through the optical fiber cable, the signal cannot be amplified by the PD 406, and therefore there is a problem that a sufficient radio signal cannot be emitted from the antenna.

[0193] Furthermore, when a conventional APD is used, as shown in Figures 24A and 24B, an increase in the number of electrons and holes in the multiplication layer changes the electric field distribution, causing the multiplication factor to saturate and making it impossible to ensure the dynamic range. This not only results in an insufficient amplitude of the electrical signal, but also in distortion of the analog signal. As a result, it is difficult to apply a conventional APD to a radio-on-fiber system 450 such as the comparative example.

[0194] On the other hand, in the DA-APD 403 of the present disclosure used in the radio-on-fiber system 400 according to the tenth embodiment, as shown in Fig. 26, the residence time Tdm of electrons and holes in the multiplication layer is short, thereby suppressing changes in the electric field distribution in the multiplication layer. As a result, a response with excellent linearity can be obtained over a wide dynamic range. In other words, since the DA-APD 403 of the present disclosure multiplies the signal, the original signal can be reproduced and a large current amplitude can be obtained.

[0195] The DA-APD403 of the present disclosure can be used with a multiplication factor in the range of 1.2 to 10. However, since a larger multiplication factor causes signal distortion, it is desirable to use a multiplication factor in the range of 1.2 to 5. Furthermore, considering the loss of the optical fiber and the fact that the quantum efficiency of the APD is not 100% but about 80%, it is optimal to use a multiplication factor of 2 to 3 to compensate for such loss.

[0196] Effect of Tenth Embodiment As described above, according to the radio-on-fiber system of the tenth embodiment, the DA-APD of the present disclosure is used to configure the radio-on-fiber system, which has the effect of enabling a strong radio signal to be output even if the optical transmission distance is long.

[0197] 29 is a schematic diagram illustrating a configuration of a digital coherent receiving apparatus 500 according to embodiment 11. The digital coherent receiving apparatus 500 according to embodiment 11 is characterized in that it uses a DA-APD 505a according to the present disclosure.

[0198] In digital coherent communications, optical signals modulated in both phase and intensity are polarization-multiplexed and transmitted through optical fibers. In a digital coherent receiving device 500, an optical signal input from an optical fiber cable 501 is first polarization-separated by a polarization separator 502. After polarization separation, each polarized signal light is input to a 90-degree hybrid device 503a and a 90-degree hybrid device 503b, respectively. Meanwhile, a laser light locally emitted from a semiconductor laser 504 is separated into two signals with a phase shift of 90 degrees from each other.

[0199] The signal light and laser light are multiplexed, and the signal light is further separated into orthogonal components (I, Q) and output. The four optical signals, i.e., the orthogonal I and Q components for each polarization, total four optical signals, are incident on four balanced detectors 505 arranged in 90-degree hybrid devices 503a, 503b, each of which is formed by connecting two DA-APDs 505a of the present disclosure in series. The electrical signals output from the balanced detectors 505 are input to the DSP 506. The digital coherent receiving device 500 according to the eleventh embodiment has the above configuration.

[0200] <Operation of the Digital Coherent Receiving Apparatus According to the Eleventh Embodiment> FIG. 30A is a diagram showing waveforms of a digital coherent receiving apparatus as a comparative example, and FIG. 30B is a diagram showing waveforms of a digital coherent receiving apparatus according to the eleventh embodiment.

[0201] Conventional balanced detectors use PDs as semiconductor light-receiving elements for receiving signal light. On the other hand, the DA-APD 505a disclosed herein can multiply signals, thereby enabling the local oscillation to be suppressed. Furthermore, when a conventional APD is used, as shown in FIG. 25 , an increase in the number of electrons and holes in the multiplication layer changes the electric field distribution, resulting in saturation of the multiplication factor and an inability to ensure a sufficient dynamic range. This not only results in insufficient electrical signal amplitude, but also in distortion of the analog signal. As a result, as shown in FIG. 30A , in the comparative example, the interval between waveforms A1 and B1 becomes narrow, distorting the intensity signal of the constellation waveform, making it difficult to apply an APD.

[0202] On the other hand, in the DA-APD 505a of the present disclosure, as shown in Fig. 26, the residence time Tdm of electrons and holes in the multiplication layer is short, so changes in the electric field distribution in the multiplication layer are suppressed. As a result, as shown in Fig. 30B, when the DA-APD 505a of the present disclosure is used, the interval between waveform A and waveform B is widened, and a constellation waveform with excellent linearity over a wide dynamic range is obtained. In other words, even if a signal is multiplied by an APD, the original signal can be reproduced, and a large current amplitude can be obtained.

[0203] The multiplication factor of the DA-APD 505a of the present disclosure can be used within a range of 1.2 to 10. However, as the multiplication factor increases, the signal becomes distorted, so it is desirable to use a multiplication factor within a range of 1.2 to 5.

[0204] <Effects of Eleventh Embodiment> As described above, according to the digital coherent receiving device of the eleventh embodiment, the DA-APD of the present disclosure is applied as a semiconductor photodetector that receives an optical signal, and therefore, it is possible to reduce the drive current of the local light (laser), that is, to reduce the power consumption of the digital coherent receiving device.

[0205] 31 is a schematic diagram showing the configuration of a SPAD sensor (Single Photon Avalanche Diode) system according to embodiment 12. The SPAD sensor system 600 includes a photoelectron measurement circuit 601, a SPAD sensor 602 including a DA-APD according to the present disclosure, and a quenching circuit 603.

[0206] The SPAD sensor system 600 uses the DA-APD of the present disclosure. Photons incident on the SPAD sensor system 600 are absorbed in a light absorption layer of a SPAD sensor 602 made of the DA-APD of the present disclosure, generating electron-hole pairs, and the electrons flow into a multiplication layer. An electric field about 10% higher than the avalanche breakdown electric field is applied to the multiplication layer.

[0207] This state is called the Geiger mode. In the Geiger mode, electrons are 6 The generated electrons flow as a current and are passed through the photoelectron measurement circuit 601. If the current generated by one photon is known in advance, it is possible to count the number of photons incident on the SPAD sensor system 600.

[0208] FIG. 32A shows waveforms of a SAPD sensor system according to a comparative example, and FIG. 32B shows waveforms of a SAPD sensor system according to embodiment 12. Continuous application of an electric field equal to or greater than the avalanche breakdown electric field to the multiplication layer causes excessive current to flow. Therefore, after photons are detected, the voltage applied to the SPAD sensor 602 is quickly reduced to weaken the electric field in the multiplication layer. This is called quenching. As shown in the comparison of the multiplication characteristics of the SPAD sensor in FIGS. 32A and 32B , the voltage is reduced from B: Geiger-mode voltage to A: quenching voltage to stop chain multiplication. Then, the voltage is increased again from A: quenching voltage to B: Geiger-mode voltage, enabling high-sensitivity reception of incident photons.

[0209] The quenching circuit 603 that controls the voltage is classified into a passive circuit and an active circuit. In a passive circuit, when a current flows due to photons incident on the SPAD sensor 602, a voltage drop occurs in a resistor connected in series to the SPAD sensor 602, resulting in a decrease in the voltage applied to the SPAD sensor 602. In other words, the quenching circuit 603 operates to repeatedly apply a voltage equal to or greater than the breakdown voltage and a voltage less than the breakdown voltage to the SPAD sensor 602.

[0210] <Functions and Effects of the SPAD Sensor System According to Embodiment 12> The SPAD sensor system 600 according to embodiment 12 can be used not only to count the number of photons but also as a highly sensitive semiconductor light-receiving element. However, it is necessary to constantly repeat the process from B: Geiger-mode voltage to A: quenching voltage. The repetition period is on the order of nanoseconds to microseconds. If the difference between A: quenching voltage and B: Geiger-mode voltage can be reduced, the repetition period can be shortened and the response speed of the SPAD sensor system 600 can be increased.

[0211] The passive quenching circuit 603 makes it possible to reduce the resistance value connected in series to the SPAD sensor 602, thereby increasing the response speed of the SPAD sensor 602. Furthermore, the active quenching circuit 603 reduces the voltage amplitude, making it possible to simplify the drive circuit and save power, and also to widen the response band.

[0212] The effect of using the InAlAs digital alloy structure of the present disclosure as a multiplication layer will be described below. In the InAlAs digital alloy structure multiplication layer of the present disclosure, as shown in FIGS. 4A and 6B , the dead space length is long, so multiplication does not occur at low electric fields. However, as the electric field increases, the dead space length shortens, causing a rapid increase in the multiplication factor, leading to breakdown. In APDs with InAlAs random alloy multiplication layers and APDs with thick digital alloy InAlAs multiplication layers, if the breakdown voltage is defined as the voltage at which the dark current exceeds 10 μA, the multiplication factor at 90% of the breakdown voltage exceeds 10 times. On the other hand, in the InAlAs digital alloy structure multiplication layer of the present disclosure, the multiplication factor at 90% of the breakdown voltage is 10 times or less.

[0213] The voltage required for breakdown depends on the device structure, such as the thickness of the light absorption layer and the carrier concentration of the electric field buffer layer, so here we verify the effect using the quantifiable electric field of the multiplication layer. Note that above the reach-through voltage (up to 12 V), the voltage applied to the SPAD sensor 602 and the electric field of the multiplication layer are proportional.

[0214] 33 is a diagram showing the calculated difference between the quenching electric field and the Geiger mode electric field for each material constituting the multiplication layer. It can be seen that in the InAlAs digital alloy structure multiplication layer of the present disclosure, the difference between the quenching electric field and the Geiger mode electric field of each multiplication layer is 170 kV / cm, which is exceptionally low. The electric field is 120 kV / cm lower than that of an InAlAs digital alloy structure multiplication layer having a superlattice structure similar to the InAlAs digital alloy structure multiplication layer of the present disclosure but a layer thickness of 200 nm or more that has not been thinned.

[0215] <Effects of Twelfth Embodiment> As described above, according to the SPAD sensor system of the twelfth embodiment, the DA-APD of the present disclosure is used in the SPAD sensor, and therefore the difference between the quenching electric field and the Geiger mode electric field, that is, the applied voltage difference, can be reduced, thereby achieving the effect of obtaining a SPAD sensor system that enables an improvement in the response band, simplification of the quenching circuit, and power saving.

[0216] Embodiment 13. Fig. 34 is a diagram showing the configuration of a LIDAR (Light Detection and Ranging: LiDAR) device according to embodiment 13. Fig. 35A is a diagram showing the received waveform of the APD of a LIDAR device that is a comparative example, and Fig. 35B is a diagram showing the received waveform of the APD of the LIDAR device according to embodiment 13.

[0217] The LIDAR device 700 includes a light source 701, a DA-APD 702 of the present disclosure, a TIA 703, and a ranging circuit 704.

[0218] The LIDAR device 700 calculates the distance to the object 705 by measuring the time it takes for pulsed light emitted from a light source to hit the object 705 and return to the semiconductor light-receiving element. An LD or the like is used as the light source 701. To measure long distances, the light output of the LD needs to be increased, but an upper limit is set for the amount of light emitted from the LD for eye safety reasons. Therefore, it is necessary to increase the sensitivity of the semiconductor light-receiving element. Therefore, the LIDAR device 700 according to embodiment 13 uses the DA-APD 702 of the present disclosure with high amplification as the semiconductor light-receiving element.

[0219] The detected optical pulse is multiplied by the DA-APD 702 of the present disclosure and converted into a current pulse. It is then amplified by the TIA 703 and input to the distance measurement circuit 704, and the time when the intensity of the pulse signal exceeds a preset discrimination line is determined to be the arrival time, as shown in Figures 35A and 35B. The timing at which the optical pulse is emitted from the light source 701 is input as a signal to the distance measurement circuit 704, and the distance to the object 705 can be calculated by multiplying the time difference between them by the speed of light and dividing the result by 2.

[0220] <Functions and Effects of the LIDAR Device According to Embodiment 13> The reflectivity of the object 705 is not necessarily high, and the reflection direction varies, so it is necessary to detect weak light using an APD. With a conventional APD, as shown in Figure 35A, when a voltage is set to achieve high multiplication, the multiplication time becomes long and the current pulse width output from the APD becomes wide. In addition, the tunnel current increases, making it difficult to distinguish the light pulses.

[0221] On the other hand, in the multiplication layer of the DA-APD 702 of the present disclosure, even at high multiplication rates of 20 times or more, as described in the explanation of the operation of embodiment 1, the tunnel current does not increase, making it easy to identify weak light. Furthermore, as shown in FIG. 26 , the residence time in the multiplication layer is short, and therefore, as shown in FIG. 35B , a current pulse with a high peak intensity is obtained, resulting in high identification sensitivity. As a result, not only is it possible to measure the distance to a distant object, but the optical output of the light source can be reduced, thereby saving power and further improving safety for the eyes.

[0222] <Effects of Embodiment 13> As described above, according to the LIDAR device of embodiment 13, the DA-APD disclosed herein receives reflected light from an object, and therefore, it is possible to measure the distance to a distant object, it is possible to reduce the power consumption of the light source, and it is possible to obtain a LIDAR device that is also highly safe for the eyes.

[0223] Although the present disclosure describes various exemplary embodiments and examples, the various features, aspects, and functions described in one or more embodiments are not limited to application to a particular embodiment, but may be applied to the embodiments alone or in various combinations.

[0224] Therefore, countless variations not illustrated are conceivable within the scope of the technology of the present disclosure, including, for example, cases where at least one component is modified, added, or omitted, and even cases where at least one component is extracted and combined with a component of another embodiment.

[0225] 1 n-type InP substrate, 1a Fe-doped semi-insulating InP substrate, 2 n-type InAlAs buffer layer, 2a n-type InP conductive layer, 3, 45 InAlAs digital alloy structure multiplication layer, 4, 44 p-type InP field relaxation layer, 5, 43 i-type InGaAs light absorption layer, 6 i-type InAlGaAs / InAlAs graded layer, 7 p-type InP window layer, 8 p-type InGaAs contact layer, 11, 47 n-type InP window layer, 15 p-type diffusion region, 17 isolation groove, 18 surface protection film, 20 Fe-doped semi-insulating InP buried layer, 25 p-type InAlAs conductive layer, 31, 31a, 31b, 50 n-type electrode, 32, 51 p-type electrode, 33 opening, 40 p-type InGaAlAs contact layer, 41 p-type InP conductive layer, 42 n-type InAlGaAs / InAlAs graded layer, 46 n-type InAlAs field adjustment layer, 48 n-type InAlAs conductive layer, 49 n-type InGaAs contact layer, 53 metal film, 90 incident light, 100, 110, 120, 130, 140, 150, 160, 170, 180, 190, 200 semiconductor light receiving element, 250, 260, 270 optical line terminal, 251, 261, 274 FEC, 252, 262, 273, 303 driver amplifier, 253, 263, 272, 304, 401, 701 light source, 254, 264, 271 WDM, 255, 265a, 301, 506 DSP, 256, 266a, 302b ADC, 258 APD, 257, 267, 276 Burst TIA, 265, 278 CDR, 266, 277 Limiting amplifier, 257a, 267a, 276a, 703 TIA, 268, 275, 305, 403, 505a, 702 DA-APD, 280, 282, 284 50G-PON system, 302a DAC, 310, 501 Optical fiber cable, 306 Linear-TIA, 400, 450 Radio-on-fiber system, 402 Transmission path, 404 Antenna, 406 PD, 300 Multilevel intensity modulation transmitting / receiving device, 500 Digital coherent receiving device, 501 Optical fiber cable, 502 Polarization separator, 503a, 503b 90-degree hybrid, 504 semiconductor laser, 505 balanced detector, 600 SPAD sensor system, 601 optoelectronic measurement circuit, 602 SPAD sensor, 603 quenching circuit, 700 lidar device,704 Ranging Circuit, 705 Object,

Claims

1. A semiconductor photodetector comprising: an InP substrate; an n-type semiconductor layer formed on the InP substrate; a multiplication layer formed on the n-type semiconductor layer and consisting of a digital alloy structure having a layer thickness of 40 nm or more and 170 nm or less; a p-type electric field relaxation layer formed on the multiplication layer; and an InGaAs light absorption layer formed on the p-type electric field relaxation layer.

2. A semiconductor light receiving element comprising: an InP substrate; a p-type semiconductor layer formed on the InP substrate; an InGaAs light absorbing layer formed on the p-type semiconductor layer; a p-type electric field relaxation layer formed on the InGaAs light absorbing layer; and a multiplication layer formed on the p-type electric field relaxation layer and having a digital alloy structure with a layer thickness of 40 nm or more and 170 nm or less.

3. The semiconductor light-receiving element according to claim 1 or 2, wherein the multiplication layer has a digital alloy structure in which InAl layers and AlAs layers are alternately laminated.

4. The semiconductor light-receiving element according to any one of claims 1 to 3, wherein the thickness of said multiplication layer is 60 nm or more and 130 nm or less.

5. A semiconductor light-receiving element according to any one of claims 1 to 4, characterized in that the p-type electric field relaxation layer has a random alloy structure with a layer thickness of 10 nm or more and 70 nm or less.

6. The semiconductor light-receiving element according to claim 5, wherein said p-type electric field relaxation layer is made of InP or InAlAs.

7. A semiconductor light-receiving element according to any one of claims 1 to 4, characterized in that the p-type electric field relaxation layer has a digital alloy structure with a layer thickness of 10 nm or more and 130 nm or less.

8. The semiconductor light-receiving element according to claim 7, wherein the p-type electric field buffer layer has an InAlAs digital alloy structure in which InAs layers and AlAs layers are alternately laminated.

9. The semiconductor light-receiving element according to any one of claims 1 to 8, wherein the p-type electric field buffer layer is doped with beryllium or zinc as a p-type impurity.

10. The semiconductor light-receiving element according to claim 1, wherein said n-type semiconductor layer is doped with silicon as an n-type impurity.

11. The semiconductor light-receiving element according to claim 1, characterized in that an i-type or n-type window layer is formed on the InGaAs light absorption layer, a p-type impurity diffusion region is formed in the window layer, and a p-type electrode is provided on the p-type impurity diffusion region.

12. The semiconductor light-receiving element according to claim 11, characterized in that the n-type semiconductor layer is an n-type conductive layer, and an n-type electrode is provided on a partially exposed portion of the n-type conductive layer formed on the InP substrate.

13. The semiconductor light-receiving element according to claim 12, wherein an isolation groove is provided on the outer periphery of said p-type impurity diffusion region, the isolation groove reaching said n-type conductive layer.

14. The semiconductor light-receiving element according to claim 11, further comprising a light incidence region provided on the rear surface of said InP substrate opposite said p-type electrode.

15. The semiconductor light-receiving element according to claim 1, characterized in that a p-type contact layer having an outer periphery with an area smaller than that of the multiplication layer is formed on the InGaAs light absorption layer, and a p-type electrode is provided on the p-type contact layer.

16. The semiconductor light-receiving element according to any one of claims 1 to 15, characterized in that the length of the dead space is 50 nm or more and 90 nm or less.

17. A semiconductor light-receiving element according to any one of claims 1 to 15, characterized in that the ratio of the length of the dead space to the thickness of the multiplication layer is 29% or more and less than 100%.

18. The semiconductor light-receiving element according to any one of claims 1 to 15, characterized in that the ionization rate ratio k is 0.1 or less.

19. A semiconductor light-receiving element according to any one of claims 1 to 15, characterized in that the multiplication factor at a voltage that is 90% of the breakdown voltage is 10 times or less.

20. An optical line termination device comprising: a semiconductor photodetector according to any one of claims 1 to 19; an optical multiplexer / demultiplexer for inputting an optical signal into said semiconductor photodetector; an amplifier circuit for amplifying an electrical signal output from said semiconductor photodetector; a clock and data recovery circuit connected to said amplifier circuit for recovering clock data from the amplified electrical signal; and a forward error correction circuit connected to said clock and data recovery circuit for correcting errors in the clock data.

21. An optical line termination device comprising: a semiconductor photodetector according to any one of claims 1 to 19; an optical multiplexer / demultiplexer for inputting an optical signal into the semiconductor photodetector; an amplifier circuit for amplifying an electrical signal output from the semiconductor photodetector; an analog / digital conversion circuit connected to the amplifier circuit for converting the amplified electrical signal into a digital signal; a digital signal processing circuit connected to the analog / digital conversion circuit for processing the digital signal; and a forward error correction circuit connected to the digital signal processing circuit for correcting errors in the digital signal.

22. A radio-on-fiber system comprising: a light source that emits an analog-modulated optical signal; a semiconductor photodetector according to any one of claims 1 to 19 that receives the analog-modulated optical signal; a transmission path that transmits an analog electrical signal output from the semiconductor photodetector to an antenna; and an antenna connected to the transmission path that radiates the analog electrical signal as a radio wave signal.

23. A multi-level intensity modulation transmitting / receiving device comprising: a semiconductor photodetector according to any one of claims 1 to 19 for receiving a multi-level intensity modulated optical signal; an amplifier circuit for amplifying an electrical signal output from the semiconductor photodetector; an analog / digital conversion circuit connected to the amplifier circuit for converting the amplified electrical signal into a digital signal; and a digital signal processing circuit connected to the analog / digital conversion circuit for processing the digital signal.

24. A digital coherent receiving device comprising: a semiconductor photodetector according to any one of claims 1 to 19; a polarization separator which separates the polarization of an intensity- and phase-modulated polarization multiplexed optical signal; a 90-degree hybrid which splits and combines the optical signal output from the polarization separator; and a digital signal processing circuit connected to the 90-degree hybrid which processes digital signals.

25. A SPAD sensor system comprising: a SPAD sensor constituted by a semiconductor light receiving element according to any one of claims 1 to 19; a quenching circuit which repeatedly applies a voltage equal to or greater than the breakdown voltage and a voltage less than the breakdown voltage to the SPAD sensor; and an optoelectronic measurement circuit which measures an electrical signal output from the SPAD sensor.

26. A LIDAR device comprising: a light source that emits light in a pulsed manner; a semiconductor light receiving element described in any one of claims 1 to 19 that receives light emitted from the light source that has been reflected by an object and returned; an amplifier circuit that amplifies an electrical signal output from the semiconductor light receiving element; and a distance measuring circuit that calculates a distance based on the electrical signal amplified by the amplifier circuit.

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