Array substrate and display panel

Abstract

An array substrate and a display panel, comprising an active definition part (BS), a junction of a connection surface (Sc) of the active definition part (BS) and a first top surface (Su) of the active definition part (BS) being a first edge (L1). An active layer (202) is arranged on a substrate (201) and the active definition part (BS); a single crystal starting point (gr) of the active layer (202) corresponds to the first edge (L1); the area on two sides of the single crystal starting point (gr) where two rows of single crystal grains parallel to the first edge (L1) are located is a single crystal area (ga); a channel part (pl) is located in the single crystal area (ga); and in the direction perpendicular to the substrate, a gate electrode (GE) only covers one of the two rows of single crystal grains.

Description

Array substrate and display panel Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] Integrating sub-pixels, gate driver circuits, demultiplexing circuits, source driver chips, timing controllers, and other driver circuits on a glass substrate (system on glass (SOG)) can significantly improve the integration of display panels, reduce dependence on driver chips, and lower costs. To achieve SOG, it is necessary to increase transistor integration, maximum operating frequency, and current density. In turn, increasing the integration, maximum operating frequency, and current density of thin-film transistors requires transistors with shorter channel lengths, higher mobility, and smaller size. SUMMARY OF THE INVENTION

[0003] The embodiments of the present application provide an array substrate and a display panel, which are conducive to achieving a short channel, high mobility and small volume design for semiconductor devices on the array substrate.

[0004] An embodiment of the present application provides an array substrate, comprising a substrate and a plurality of semiconductor devices located on the substrate, wherein the substrate has an active definition portion, wherein the active definition portion comprises a first bottom surface in contact with the top surface of the substrate, a first top surface parallel to the first bottom surface, and a connecting surface connected between the first top surface and the first bottom surface and arranged at an angle, wherein the junction between the connecting surface and the first top surface is a first edge, and the junction between the connecting surface and the first bottom surface is a second edge. The semiconductor devices comprise an active layer and a gate layer. The active layer is disposed on the substrate and the active definition portion, and comprises a first doped portion, a second doped portion, and a channel portion located between the first doped portion and the second doped portion; the gate layer comprises a gate disposed corresponding to the channel portion, and a gate insulating layer is disposed between the gate layer and the active layer. In which, the active layer includes a single crystal starting point, and the grains of the active layer diffuse and grow horizontally on the substrate and the active definition part in a direction perpendicular to the single crystal starting point, and the single crystal starting point corresponds to the first edge; the area where the two rows of single crystal grains on both sides of the single crystal starting point are parallel to the first edge is the single crystal area, the channel part is located in the single crystal area, and the gate has and only covers one of the two rows of single crystal grains in the direction perpendicular to the substrate.

[0005] Optionally, in some embodiments of the present application, the first bottom surface and the connecting surface have an acute angle, and the acute angle is less than 45°.

[0006] Optionally, in some embodiments of the present application, the acute angle is greater than or equal to 15° and less than or equal to 30°.

[0007] Optionally, in some embodiments of the present application, the gate covers a row of the single grains located on the first top surface in a direction perpendicular to the substrate; wherein the first doped portion is located on the first top surface, and the second doped portion is located on the substrate and the connecting surface.

[0008] Optionally, in some embodiments of the present application, the gate covers a row of the single grains located on the connection surface in a direction perpendicular to the substrate; wherein the first doped portion is located on the first top surface, and the second doped portion is located on the substrate.

[0009] Optionally, in some embodiments of the present application, the single crystal region includes a first single crystal region and a second single crystal region, the first single crystal region includes a row of the single crystal grains located on the first top surface, and the second single crystal region includes a row of the single crystal grains covering the connecting surface; wherein, on the connecting surface, the grain size of the single crystal grains in the row of the single crystal grains in the second single crystal region is greater than the distance between the first edge and the second edge.

[0010] Optionally, in some embodiments of the present application, in a direction from the first edge to the second edge, the length of the gate is less than or equal to the length of a corresponding row of the single crystal grains.

[0011] Optionally, in some embodiments of the present application, an insulating pad layer is provided on a side of the active layer close to the substrate, and the insulating pad layer is provided on the substrate and the active definition portion; wherein the material of the insulating pad layer includes silicon oxide.

[0012] Optionally, in some embodiments of the present application, the array substrate further includes a source / drain layer, the source / drain layer being located on the active layer, the source / drain layer including a first electrode electrically connected to the first doped portion and a second electrode electrically connected to the second doped portion. The semiconductor device further includes a light shielding layer, the light shielding layer being located within the substrate, the light shielding layer including a light shielding portion provided corresponding to the channel portion.

[0013] An embodiment of the present application further provides a display panel, which includes any of the above-mentioned array substrates. Beneficial effects

[0014] Compared to the prior art, the embodiments of the present application provide an array substrate and a display panel, comprising a substrate and a plurality of semiconductor devices located on the substrate, wherein the substrate has an active definition portion, the active definition portion comprising a first bottom surface in contact with the top surface of the substrate, a first top surface parallel to the first bottom surface, and a connecting surface connected between the first top surface and the first bottom surface and arranged at an angle. The junction of the connecting surface and the first top surface is a first edge, and the junction of the connecting surface and the first bottom surface is a second edge. The semiconductor device comprises an active layer and a gate layer. The active layer is arranged on the substrate and the active definition portion, the active layer comprising a first doping portion, a second doping portion, and a channel portion located between the first doping portion and the second doping portion; the gate layer comprises a gate arranged corresponding to the channel portion, and a gate insulating layer is arranged between the gate layer and the active layer. The active layer comprises a single crystal starting point, and the single crystal starting point corresponds to the first edge. The grains of the active layer diffuse and grow horizontally on the substrate and the active definition portion in a direction perpendicular to the single crystal starting point; the area where the two rows of single crystal grains on both sides of the single crystal starting point are parallel to the first edge is the single crystal area, the channel part is located in the single crystal area, and the gate has and only covers one row of the two rows of single crystal grains in the direction perpendicular to the substrate, so that the channel length of the semiconductor device is determined by the size of the row of single crystal grains corresponding to the gate, and the gate no longer corresponds to the grain boundary, which is beneficial to improving the mobility of the semiconductor device and is beneficial to enabling the semiconductor device to achieve a short channel and small volume design. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] FIG1 is a schematic structural diagram of an array substrate in the prior art;

[0016] FIG2A is a schematic diagram of a first structure of an array substrate provided in an embodiment of the present application;

[0017] FIG2B is a first cross-sectional schematic diagram taken along line AA' shown in FIG2A;

[0018] FIG2C is a first cross-sectional schematic diagram taken along line BB' shown in FIG2A;

[0019] FIG2D is a second cross-sectional schematic diagram taken along line AA' shown in FIG2A;

[0020] FIG2E is a second cross-sectional schematic diagram taken along line BB' shown in FIG2A;

[0021] FIG2F is a third cross-sectional schematic diagram taken along line BB' shown in FIG2A;

[0022] FIG2G is a schematic diagram of a second structure of an array substrate provided in an embodiment of the present application;

[0023] FIG2H is a first cross-sectional schematic diagram taken along line AA' shown in FIG2G;

[0024] FIG2I is a first cross-sectional schematic diagram taken along line BB' shown in FIG2G;

[0025] FIG2J is a second cross-sectional schematic diagram taken along line AA' shown in FIG2G;

[0026] FIG2K is a second cross-sectional schematic diagram taken along line BB' shown in FIG2G;

[0027] FIG2L is a third cross-sectional schematic diagram taken along line BB' shown in FIG2G;

[0028] FIG3 is a schematic diagram showing the relationship between the single crystal grain size and the connection surface length provided in an embodiment of the present application;

[0029] 4A to 4F are flowcharts of a preparation process of an array substrate according to an embodiment of the present application;

[0030] FIG5A is a top view of an active layer measured by a scanning electron microscope according to an embodiment of the present application;

[0031] 5B to 5C are cross-sectional views of a semiconductor device measured using a scanning electron microscope according to an embodiment of the present application;

[0032] FIG6 is a schematic diagram of a characteristic curve of a semiconductor device provided in an embodiment of the present application;

[0033] 7 is a cross-sectional view of a semiconductor device including an insulating pad layer measured by a scanning electron microscope according to an embodiment of the present application;

[0034] FIG8 is a schematic structural diagram of a display panel provided in an embodiment of the present application. Modes for Carrying Out the Invention

[0035] To make the purpose, technical solutions and effects of this application clearer and more specific, the following further describes this application in detail with reference to the accompanying drawings and examples. It should be understood that the specific examples described herein are only used to explain this application and are not intended to limit this application.

[0036] Specifically, Figure 1 is a schematic diagram of the structure of a conventional array substrate. Currently, the active layer 101 of a semiconductor device is disposed on the same horizontal plane, the gate 102 is located on the active layer 101, and the source-drain layer 103 includes a source electrode and a drain electrode electrically connected to the active layer 101. However, due to limitations in exposure and etching processes, the channel length of a semiconductor device is generally greater than 2 microns, occupying a large planar area. Furthermore, the presence of numerous grain boundaries within the channel results in low mobility and a large device size.

[0037] The embodiments of the present application provide an array substrate and a display panel, which are conducive to achieving a short channel, high mobility, and small volume design for the semiconductor devices included in the array substrate. As shown in Figure 2A, a first structural schematic diagram of the array substrate provided in the embodiment of the present application, Figure 2B is a first cross-sectional schematic diagram cut along A-A' shown in Figure 2A, and Figure 2C is a first cross-sectional schematic diagram cut along B-B' shown in Figure 2A; the embodiments of the present application provide an array substrate, including a substrate 201 and a plurality of semiconductor devices Tr located on the substrate 201. Optionally, the substrate 201 includes a base 2011. The base 2011 includes two types: a flexible base and a rigid base. Therefore, the base 2011 can be a flexible substrate, a rigid base, or a combination of a flexible base and a rigid base. Optionally, the base 2011 includes one or a combination of glass, polyimide, etc.

[0038] The substrate 201 has an active definition portion BS. The active definition portion BS includes a first bottom surface Sd in contact with the top surface of the substrate 201, a first top surface Su parallel to the first bottom surface Sd, and a connecting surface Sc connected between the first top surface Su and the first bottom surface Sd and arranged at an angle. The junction of the connecting surface Sc and the first top surface Su is a first edge L1, and the junction of the connecting surface Sc and the first bottom surface Sd is a second edge L2.

[0039] The active defining portion BS refers to a three-dimensional structure with a height difference and an inclined surface at a connection point, and may be in a truncated cone shape, a prism shape, or the like.

[0040] Optionally, the active defining portion BS is made of a material including silicon oxide, silicon nitride, and the like.

[0041] Optionally, the substrate 201 further includes a buffer layer 2012 , which is located on the base 2011 to provide a better planarization basis for the active definition portion BS and to block or prevent impurities and moisture from penetrating from the substrate 201 toward the active layer 202 .

[0042] Optionally, the buffer layer 2012 includes one or more inorganic insulating layers.

[0043] Optionally, the active defining portion BS may be provided in the same layer as the buffer layer 2012 in the substrate 201 (ie, a whole layer of the buffer layer 2012 is prepared, and then the buffer layer 2012 is etched to form the active defining portion BS).

[0044] 2A to 2C , the semiconductor device Tr includes an active layer 202 and a gate layer 203. The active layer 202 is located on the substrate 201 and the active defining portion BS, and includes a first doped portion Np1, a second doped portion Np2, and a channel portion p1 located between the first doped portion Np1 and the second doped portion Np2.

[0045] The gate layer 203 includes a gate GE disposed corresponding to the channel portion.

[0046] Optionally, the gate layer 203 is located on the active layer 202 , as shown in FIG. 2A to FIG. 2C .

[0047] Optionally, the gate layer 203 is located below the active layer 202 , so that the semiconductor device has a bottom-gate structure.

[0048] In which, the active layer 202 includes a single crystal starting point gr, and the grains of the active layer 202 diffuse and grow horizontally on the substrate 201 and the active definition part BS in a direction perpendicular to the single crystal starting point gr (as shown by the dotted arrow a in Figures 2A and 2C), and the single crystal starting point gr corresponds to the first edge L1; the area where the two rows of single crystal grains on both sides of the single crystal starting point gr are parallel to the first edge L1 is the single crystal area ga, the channel part pl is located in the single crystal area ga, and the gate GE has and only covers one of the two rows of single crystal grains in the direction perpendicular to the substrate.

[0049] It should be noted that the gate GE covers only one row of the two rows of single grains in the direction perpendicular to the substrate, including: the orthographic projection of the gate GE on the substrate 201 coincides with the orthographic projection of the corresponding row of single grains on the substrate 201; and the orthographic projection of the gate GE on the substrate 201 is located within the orthographic projection of the corresponding row of single grains on the substrate 201.

[0050] By making the gate GE correspond to the channel portion pl, and the gate GE is arranged corresponding to one of the two rows of single crystal grains, the channel portion pl is arranged corresponding to a row of single crystal grains, and the starting point of the row of single crystal grains corresponding to the channel portion pl is located at the first edge L1, so that the gate GE does not correspond to the grain boundary, and the channel length of the semiconductor is determined by the size of the row of single crystal grains corresponding to the gate GE, thereby reducing the channel length of the semiconductor device, which is beneficial to improving the electrical properties of the semiconductor device such as mobility and on-state current, and is beneficial to enabling the semiconductor device to achieve a short channel and high mobility design.

[0051] In addition, compared with the design of the prior art shown in Figure 1 in which the active layers are arranged on the same horizontal plane, the present application can reduce the projected area of ​​the active layer 202 on the substrate 201 by arranging at least part of the active layer 202 on the active definition portion BS, so that the active layer 202 can meet the design performance requirements while helping to reduce the volume of the semiconductor device.

[0052] Optionally, the active defining portion BS is truncated cone-shaped, and a connecting surface Sc is provided between the first top surface Su and the first bottom surface Sd, wherein the active layer 202 may cover the entire connecting surface Sc or may partially cover the connecting surface Sc.

[0053] Optionally, the active layer 202 covers the entire connection surface Sc, so that the channel width of the semiconductor device is equal to the perimeter of the connection surface Sc, thereby increasing the channel width of the semiconductor device and improving the on-state current of the semiconductor device.

[0054] Optionally, the active layer 202 partially covers the connection surface Sc, so as to reduce the area occupied by the active layer 202 while the active layer 202 meets the performance requirements.

[0055] Optionally, when the active defining portion BS is in a prism shape, a plurality of connecting surfaces Sc are correspondingly provided between the first top surface Su and the first bottom surface Sd, and the active layer 202 may be provided corresponding to a partial area of ​​at least one of the connecting surfaces Sc.

[0056] Optionally, when the channel portion p1 covers a portion of the active definition portion BS, the size of the active definition portion BS in a first direction (the same direction as the cross-sectional direction along A-A' in FIG. 2A ) is greater than or equal to the size of the active layer 202, so that the active definition portion BS has a sufficiently large area for the active layer 202 to be properly formed on the active definition portion BS. The direction from the first edge L1 to the second edge L2 is a second direction (the same direction as the cross-sectional direction along BB' in FIG. 2A and FIG. 2G ), and the second direction may be perpendicular to the first direction.

[0057] Please continue to refer to Figures 2A to 2C. In order to make the single crystal starting point gr correspond to the first edge L1 (that is, the starting point of a row of single crystal grains corresponding to the channel portion pl can be located at the junction of the first top surface Su and the connecting surface Sc) and to reduce the length of the connecting surface Sc, the first bottom surface Sd and the connecting surface Sc can have an acute angle α, and the acute angle α is less than or equal to 45°.

[0058] Optionally, the acute angle α is equal to 44°, 43°, 42°, 41°, 40°, 36°, 35°, 34°, 32°, 31°, 30°, 26°, 25°, 24°, 20°, 16°, 15°, 14°, 10°, 8°, 15° or 1°.

[0059] Optionally, to avoid the acute angle α being too small, the first edge L1 cannot be used as the starting point of a row of single grains corresponding to the channel portion pl, so that the first edge L1 cannot play a positioning role, and the acute angle α may be greater than or equal to 15°.

[0060] Optionally, in order to improve the problem of cracks occurring at the junction of the first top surface Su and the connecting surface Sc and at the junction of the second bottom surface and the connecting surface Sc during the preparation process of the active layer 202, causing problems such as disconnection and film breakage in the active layer 202, so that when the active layer 202 is formed into grains using the existing excimer laser annealing (ELA) process, the active layer 202 can still have a good crystallization effect, and the acute angle α can be less than or equal to 30°.

[0061] Therefore, to balance the crystallization effect of the active layer 202 and the positioning effect of the first edge L1, the acute angle α is greater than or equal to 15° and less than or equal to 30°. Optionally, the acute angle α is greater than or equal to 15° and less than or equal to 30°.

[0062] As shown in Figure 2D, which is a second cross-sectional schematic diagram cut along A-A' shown in Figure 2A, and Figure 2E, which is a second cross-sectional schematic diagram cut along B-B' shown in Figure 2A, the array substrate includes an insulating pad layer 204, which is located on a side of the active layer 202 close to the substrate 201. The insulating pad layer 204 is arranged on the substrate 201 and the active definition portion BS. The preparation material of the insulating pad layer 204 includes silicon oxide, so that when preparing the active layer 202, the insulating pad layer 204 and the active layer 202 are continuously formed into films (that is, the insulating pad layer 204 is prepared under the active layer 202) to reduce the back channel defects of the active layer 202 (that is, the crystal defect states existing on the surface of the active layer 202 close to the substrate 201) and improve the electrical performance of the transistor.

[0063] Since, in actual fabrication, a long time passes between the preparation of the substrate 201 and the active definition portion BS and the preparation of the active layer 202, the surfaces of the substrate 201 and the active definition portion BS may be contaminated, causing the prepared active layer 202 to be affected by the contaminants. This results in crystal defects existing on the surface of the active layer 202 in contact with the substrate 201 and the first top surface Su of the active definition portion BS, thus affecting the performance of the active layer 202. However, by providing the insulating pad layer 204 under the active layer 202 and forming the insulating pad layer 204 and the active layer 202 continuously during the preparation of the active layer 202, the time and probability of contamination of the surface of the active layer 202 in contact with the insulating pad layer 204 can be reduced, thereby reducing back-channel defects in the active layer 202 and improving the electrical performance of the transistor.

[0064] Optionally, the insulating pad layer 204 may be provided only corresponding to the channel portion p1. Optionally, after etching the active layer 202, the insulating pad layer 204 may be etched with hydrofluoric acid so that the insulating pad layer 204 is provided only corresponding to the channel portion p1.

[0065] Optionally, since the insulating pad layer 204 under the active layer 202 cannot be completely patterned when etching the active layer 202, the insulating pad layer 204 can be set not only corresponding to the channel portion pl, but also corresponding to the first doping portion Np1, the second doping portion Np2, etc.

[0066] Optionally, please continue to refer to Figures 2A to 2E. At least one of the active definition part BS and the insulating pad layer 204 can also be reused as a barrier layer to block or prevent impurities and moisture from penetrating from the substrate 201 toward the active layer 202, thereby reducing the volume of the semiconductor device.

[0067] Optionally, the active defining portion BS includes a boss, as shown in FIG. 2C and FIG. 2E .

[0068] As shown in Figure 2F, which is a third cross-sectional schematic diagram cut along BB' shown in Figure 2A, the active definition portion BS correspondingly includes a groove, the inclined surface of the groove forms the connecting surface Sc of the active definition portion BS, the portion connected to the inclined surface of the groove and in contact with the substrate 201 forms the first bottom surface Sd of the active definition portion BS, and the portion connected to the inclined surface of the groove and parallel to the first bottom surface Sd forms the first top surface Su of the active definition portion BS.

[0069] 2A to 2F, the semiconductor device further includes a light shielding layer 205, which is located within the substrate 201. The light shielding layer 205 includes a light shielding portion corresponding to the channel portion p1 to reduce the impact of light on the semiconductor device.

[0070] Optionally, the light shielding layer 205 is located between the buffer layer 2012 and the substrate 2011 .

[0071] Optionally, because the single crystal starting point gr corresponds to the first edge L1, the grains included in the active layer 202 diffuse and grow horizontally in a direction perpendicular to the single crystal starting point gr. Therefore, the grains can grow from the single crystal starting point gr toward the first top surface Su and the connecting surface Sc, so that a row of single crystal grains is located on the first top surface Su, and another row of single crystal grains is located on the connecting surface Sc. As the grains grow toward the first top surface Su and the connecting surface Sc, the grain boundaries between the grains are located correspondingly at the first edge L1.

[0072] Accordingly, a row of the single crystal grains corresponding to the channel portion pl may be located on the first top surface Su, as shown in FIG. 2A to FIG. 2C .

[0073] Alternatively, a row of single crystal grains corresponding to the channel portion p1 may be located on the connection surface Sc. Specifically, FIG2G is a schematic diagram of a second structural embodiment of the array substrate provided in an embodiment of the present application; FIG2H is a schematic diagram of a first cross-sectional view taken along line AA' shown in FIG2G; and FIG2I is a schematic diagram of a first cross-sectional view taken along line BB' shown in FIG2G.

[0074] Optionally, the single crystal region ga includes a first single crystal region ga1 (as shown in Figures 2C, 2E, and 2F). The first single crystal region ga1 includes a row of single crystal grains located on the first top surface Su. The single crystal region ga includes a second single crystal region ga2 (as shown in Figures 2I, 2K, and 2L). The second single crystal region ga2 includes a row of single crystal grains covering the connection surface Sc. The gate GE may be disposed corresponding to the first single crystal region ga1, as shown in Figures 2A to 2F; and / or the gate GE may be disposed corresponding to the second single crystal region ga2, as shown in Figures 2G to 2I.

[0075] Specifically, please continue to refer to Figures 2A to 2F. The gate GE covers a row of the single grains located on the first top surface Su in a direction perpendicular to the substrate 201; wherein the first doping portion Np1 is located on the first top surface Su, and the second doping portion Np2 is located on the substrate 201 and the connecting surface Sc.

[0076] The orthographic projection of the gate GE on the substrate 201 has a first boundary, and the orthographic projection of the row of single-crystal grains located on the first top surface Su on the substrate 201 has a second boundary. It should be noted that the gate GE covers the row of single-crystal grains located on the first top surface Su in a direction perpendicular to the substrate 201, including: the first boundary being within the second boundary, and the first boundary coinciding with the second boundary.

[0077] Optionally, the gate GE is arranged corresponding to the first single crystal region ga1 so that the gate GE can be placed in parallel with the substrate 201, so that the gate GE can maintain a uniform film thickness, which is beneficial to reducing the process difficulty of preparing the semiconductor device while improving the electrical properties of the semiconductor device such as mobility and on-state current.

[0078] Optionally, please continue to refer to Figures 2G to 2I. The gate GE covers a row of the single grains located on the connecting surface Sc in a direction perpendicular to the substrate 201; wherein the first doping portion Np1 is located on the first top surface Su, and the second doping portion Np2 is located on the substrate 201.

[0079] The orthographic projection of the gate GE on the substrate 201 has the first boundary, and the orthographic projection of the row of single-crystal grains located on the connection surface Sc on the substrate 201 has a third boundary. It should be noted that the gate GE covers the row of single-crystal grains located on the connection surface Sc in a direction perpendicular to the substrate 201, including: the first boundary being within the third boundary, and the first boundary coinciding with the third boundary.

[0080] Figure 3 is a schematic diagram of the relationship between the single crystal grain size and the connection surface length provided in an embodiment of the present application. When the gate GE is set corresponding to the second single crystal region ga2, on the connection surface Sc, the grain size of the single crystal grains in a row of the single crystal grains in the second single crystal region ga2 is greater than the distance between the first edge L1 and the second edge L2 (that is, as shown by Lg in Figure 3), so that in the direction from the first edge L1 to the second edge L2, the length of the single crystal grains in a row of the second single crystal region ga2 is greater than or equal to the length of the connection surface Sc, so that the part of the gate GE corresponding to the channel portion pl is a single crystal grain, thereby improving the mobility of the semiconductor device.

[0081] Optionally, when the gate GE is set corresponding to the second single crystal region ga2, the end point of the row of single crystal grains included in the second single crystal region ga2 is located on the side of the second edge L2 away from the first edge L1, so that the size of the row of single crystal grains included in the second single crystal region ga2 is larger than the length of the connecting surface Sc, thereby ensuring that the portion of the channel portion pl corresponding to the gate GE is a single crystal grain, and then ensuring that the electrical properties of the semiconductor device such as mobility and on-state current are improved.

[0082] Optionally, in the direction from the first edge L1 to the second edge L2, the length of the connecting surface Sc may be 0.1 μm to 0.7 μm. In the direction from the first edge L1 to the second edge L2, the grain size of the single crystal grains in the row included in the second single crystal region ga2 may be greater than or equal to 0.1 μm to 0.7 μm. Optionally, in the direction from the first edge L1 to the second edge L2, the length of the connecting surface Sc may be 0.1 μm, 0.2 μm, 0.3 μm, 0.4 μm, 0.5 μm, 0.6 μm, or 0.7 μm. In the direction from the first edge L1 to the second edge L2, the grain size of the single crystal grains in the row included in the second single crystal region ga2 may be 0.1 μm, 0.2 μm, 0.3 μm, 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1 μm, 1.2 μm, 1.5 μm, etc.

[0083] Optionally, in the direction from the first edge L1 to the second edge L2, the length of the connecting surface Sc is equal to 0.4 microns. In the direction from the first edge L1 to the second edge L2, the length of the second single crystal region ga2 (i.e., the diameter of the single crystal grains in a row of the single crystal grains) is greater than or equal to 0.4 microns, to balance the performance and volume requirements of the semiconductor.

[0084] 2J is a second cross-sectional view taken along line AA' shown in FIG2G , and FIG2K is a second cross-sectional view taken along line BB' shown in FIG2G . When the gate GE is disposed corresponding to the second single crystal region ga2 , the array substrate may still include an insulating pad layer 204 .

[0085] Fig. 2L is a third cross-sectional view taken along line BB' shown in Fig. 2G. Optionally, when the gate GE is disposed corresponding to the second single crystal region ga2, the active defining portion BS may still include a corresponding groove.

[0086] Optionally, when the grains are formed by the existing excimer laser annealing process, the laser energy and scanning speed of the excimer laser annealing process may be controlled so that the row of single crystal grains included in the second single crystal region ga2 covers the connection surface Sc.

[0087] Optionally, please continue to refer to Figures 2A to 2L. Regardless of whether the gate GE is set corresponding to the first single crystal area ga1 or the gate GE is set corresponding to the second single crystal area ga2, the length of the gate GE in the direction from the first edge L1 to the second edge L2 can be less than or equal to the length of the corresponding row of single crystal grains, thereby reducing the probability of the gate GE corresponding to the grain boundary of the channel portion pl, and reducing the impact of process factors on the performance of the semiconductor device (such as displacement deviation in the process causing the gate GE preparation position to deviate from the expected position, causing the gate GE to correspond to the grain boundary; changes in material properties during the preparation process causing the gate GE to exceed the originally expected position, causing the gate GE to correspond to the grain boundary, etc.), so that the semiconductor device meets the design requirements of short channel, high mobility and small volume.

[0088] Optionally, when the gate GE is set corresponding to the second single crystal region ga2, the part of the light-shielding portion corresponding to the portion exceeding the first edge L1 is less than or equal to the part of the light-shielding portion corresponding to the portion exceeding the second edge L2, so that when the grains located on the connecting surface Sc exceed the second edge L2 far during the process, the grains included in the second single crystal region ga2 can still be effectively blocked.

[0089] Continuing with Figures 2A to 2L , the array substrate further includes a source-drain electrode layer 206. The source-drain electrode layer 206 is located on the active layer 202. The source-drain electrode layer 206 includes a first electrode E1 electrically connected to the first doped portion Np1 and a second electrode E2 electrically connected to the second doped portion Np2. The first electrode E1 is one of the source and drain electrodes, and the second electrode E2 is the other of the source and drain electrodes.

[0090] Optionally, referring to FIG. 2A to FIG. 2L , the array substrate further includes a gate insulating layer 207 . The gate insulating layer 207 is located between the active layer 202 and the gate layer 203 to separate the active layer 202 and the gate layer 203 .

[0091] Optionally, the gate insulating layer 207 may be a single-layer structure or a stacked-layer structure of multiple layers.

[0092] Optionally, the array substrate further includes an interlayer dielectric layer 208, wherein the interlayer dielectric layer 208 is located between the source and drain layer 206 and the gate layer 203, and the first electrode E1 is electrically connected to the first doped portion Np1 through a via hole penetrating the interlayer dielectric layer 208 and the gate insulating layer 207, and the second electrode E2 is electrically connected to the second doped portion Np2 through a via hole penetrating the interlayer dielectric layer 208 and the gate insulating layer 207.

[0093] Optionally, the second doped portion Np2 extends along the second direction so that when the semiconductor device is electrically connected to a corresponding trace (such as a data line, a power line, or other signal line), an overlapping area between the trace and the semiconductor device is reduced, thereby reducing parasitic capacitance.

[0094] 4A to 4F are flowcharts of the preparation of an array substrate provided in an embodiment of the present application. The present application also provides a method for preparing an array substrate, which is used to prepare any of the above-mentioned array substrates.

[0095] The method for preparing the array substrate includes:

[0096] An active definition portion BS is prepared on a substrate 201, as shown in FIG4A and FIG4B ; wherein the active definition portion BS includes a first bottom surface Sd in contact with the top surface of the substrate 201, a first top surface Su parallel to the first bottom surface Sd, and a connecting surface Sc connected between the first top surface Su and the first bottom surface Sd and arranged at an angle.

[0097] An active layer 202 is formed on the substrate 201 and the active definition portion BS. The active layer 202 includes a single crystal starting point gr. Crystal grains of the active layer 202 diffuse and grow horizontally on the substrate 201 and the active definition portion BS in a direction perpendicular to the single crystal starting point gr. The single crystal starting point gr corresponds to the junction of the first top surface Su and the connection surface Sc. The two rows of single crystal grains on either side of the single crystal starting point gr, parallel to the first edge L1, constitute a single crystal region ga. The channel portion p1 of the active layer 202 is located in the single crystal region ga, as shown in Figures 4C and 4D. The single crystal starting point gr corresponds to a grain boundary, x1 represents a single row of single crystal grains, and x2 represents a grain boundary.

[0098] A gate insulating layer 207 and a gate layer 203 are prepared on the active layer 202, as shown in FIG4D ; wherein the gate layer 203 includes a gate GE arranged corresponding to the channel portion pl of the active layer 202, and the gate GE covers only one row of the two rows of single crystal grains in a direction perpendicular to the substrate 201.

[0099] An interlayer dielectric layer 208 is prepared on the gate layer 203 and the gate insulation layer 207; wherein the interlayer dielectric layer 208 includes a first via hole H1 and a second via hole H2, the first via hole H1 exposes the first doped portion Np1 of the active layer 202, and the second via hole H2 exposes the second doped portion Np2 of the active layer 202, as shown in Figure 4E.

[0100] A source-drain layer 206 is prepared on the interlayer dielectric layer 208; wherein the source-drain layer 206 includes a first electrode E1 and a second electrode E2, the first electrode E1 is electrically connected to the first doped portion Np1 through the first via H1, and the second electrode E2 is electrically connected to the second doped portion Np2 through the second via H2, as shown in Figure 4F.

[0101] Optionally, before forming the active definition portion BS on the substrate 201, the step includes forming a buffer layer 2012 on the base 2011, as shown in Figures 4A and 4B. Optionally, the substrate 201 includes the base 2011 and the buffer layer 2012; the buffer layer 2012 is made of silicon oxide or silicon nitride.

[0102] Optionally, before the step of forming the active definition portion BS on the substrate 201, a light shielding layer 205 is formed on the base 2011, as shown in FIG4A and FIG4B , wherein the light shielding layer 205 includes a light shielding portion corresponding to the channel portion p1.

[0103] Optionally, the active defining portion BS is made of a material including silicon oxide, silicon nitride, and the like.

[0104] Optionally, the step of preparing the active definition portion BS on the substrate 201 includes: preparing the active definition portion BS and an insulating pad layer 204 on the substrate 201, as shown in Figure 4C; wherein the insulating pad layer 204 is located on the active definition portion BS and the substrate 201.

[0105] Optionally, the insulating pad layer 204 is made of silicon oxide. When depositing the active layer 202, the active layer 202 and the insulating pad layer 204 are formed continuously to reduce back channel defects in the active layer 202 and improve the electrical performance of the semiconductor device.

[0106] Optionally, the step of preparing the active layer 202 on the substrate 201 and the active definition portion BS includes: preparing a semiconductor layer 202a on the substrate 201 and the active definition portion BS, performing a doping process on the semiconductor layer 202a corresponding to the first doping portion Np1 and the second doping portion Np2, and patterning the semiconductor layer 202a to obtain the active layer 202, as shown in Figures 4C to 4D.

[0107] Optionally, the semiconductor layer 202 a includes silicon semiconductor material (such as single crystal silicon, amorphous silicon, etc.).

[0108] Optionally, the gate insulating layer 207 is made of a material including silicon nitride, silicon oxide, etc.; the gate layer 203 is made of a material including at least one of molybdenum, titanium, nickel, aluminum, copper, silver, etc.; the interlayer dielectric layer 208 is made of a material including silicon nitride, silicon oxide, etc.; the source and drain layer 206 is made of a material including at least one of molybdenum, titanium, nickel, aluminum, copper, silver, etc.

[0109] Optionally, the array substrate further includes a planar layer located on the source and drain electrode layer 206 .

[0110] Figure 5A is a top view of the active layer, measured using a scanning electron microscope, according to an embodiment of the present application. The inventors of this application have conducted practical verification of the array substrate of this application. In the array substrates actually produced, the grains in the channel portion p1 of the semiconductor device begin with the first edge L1 of the active defining portion BS, and crystallize along the connecting surface Sc of the active defining portion BS and the first top surface Su of the active defining portion BS (i.e., the first edge L1 serves to position the grains). For the grains on the connecting surface Sc of the active defining portion BS, the length of the connecting surface Sc can be controlled so that the grains cover the entire connecting surface Sc.

[0111] Figures 5B to 5C are cross-sectional views of the semiconductor device measured by a scanning electron microscope according to an embodiment of the present application; wherein, in the semiconductor device shown in Figure 5B, the gate GE is located on the first top surface Su of the active definition portion BS; and in the semiconductor device shown in Figure 5C, the gate GE is located on the connection surface Sc of the active definition portion BS. Analysis of the semiconductor device actually manufactured using a scanning electron microscope can verify that the grain boundary is located at the first edge L1 of the active definition portion BS (i.e., the starting point of the grain is located at the first edge L1; in the direction from the first edge L1 to the second edge L2, the extension distance of the grain boundary corresponding to the first edge L1 is less than the extension distance of the grain boundary corresponding to the second edge L2), and the connection surface Sc of the active definition portion BS is covered with a single grain.

[0112] FIG6 is a schematic diagram of the characteristic curve of the semiconductor device provided in an embodiment of the present application; FIG7 is a cross-sectional view of the semiconductor device including the insulating pad layer measured by a scanning electron microscope provided in an embodiment of the present application. The inventors of the present application have actually verified the design of the semiconductor device of the present application including the insulating pad layer 204 and not including the insulating pad layer 204; the semiconductor devices actually produced including the insulating pad layer 204 and the semiconductor devices not including the insulating pad layer 204 were tested. By comparing the transfer curve of the semiconductor device including the insulating pad layer 204 with the transfer curve of the semiconductor device not including the insulating pad layer 204, it was found that: due to the large number of back channel defects in the semiconductor device not including the insulating pad layer 204, the mobility of the semiconductor device not including the insulating pad layer 204 is only about half of the mobility of the semiconductor device including the insulating pad layer 204; and compared with the semiconductor device including the insulating pad layer 204, the uniformity of the semiconductor device not including the insulating pad layer 204 is poor.

[0113] The semiconductor device provided in this application can be manufactured using existing processes, which is beneficial to improving the device's integration, maximum operating frequency, and current density, thereby realizing the integrated design of the driving circuit on a glass substrate.

[0114] FIG8 is a schematic structural diagram of a display panel provided in an embodiment of the present application. An embodiment of the present application further provides a display panel, which includes any of the above-mentioned array substrates.

[0115] Optionally, the display panel includes a passive light-emitting display panel (such as a liquid crystal display panel, a reflective display panel, etc.), a self-luminous display panel (such as a display panel including light-emitting devices such as organic light-emitting diodes, sub-millimeter light-emitting diodes, and micro light-emitting diodes).

[0116] Optionally, the display panel includes a plurality of sub-pixels Pi and a plurality of pixel driving circuits. The plurality of sub-pixels Pi are electrically connected to corresponding pixel driving circuits, and the pixel driving circuits include the semiconductor device.

[0117] Optionally, the display panel includes a driving module electrically connected to the sub-pixel Pi, and the driving module includes the semiconductor device.

[0118] The present application also provides a display device comprising any of the above-mentioned array substrates.

[0119] Optionally, the display device includes a television, a computer, a mobile phone, a wristband, etc.

[0120] This document uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for technical personnel in this field, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. An array substrate, wherein: comprising a substrate and a plurality of semiconductor devices located on the substrate; The substrate has an active definition portion, the active definition portion includes a first bottom surface in contact with the top surface of the substrate, a first top surface parallel to the first bottom surface, and a connecting surface connected between the first top surface and the first bottom surface and arranged in an inclined manner, the junction of the connecting surface and the first top surface is a first edge, and the junction of the connecting surface and the first bottom surface is a second edge; The semiconductor device comprises: an active layer, disposed on the substrate and the active definition portion, comprising a first doping portion, a second doping portion, and a channel portion located between the first doping portion and the second doping portion; and A gate layer, comprising a gate arranged corresponding to the channel portion, and a gate insulating layer is arranged between the gate layer and the active layer; Among them, the active layer includes a single crystal starting point, and the grains of the active layer horizontally diffuse and grow on the substrate and the active definition part in a direction perpendicular to the single crystal starting point, and the single crystal starting point corresponds to the first edge; the area where the two rows of single crystal grains on both sides of the single crystal starting point and parallel to the first edge are located is the single crystal area, the channel part is located in the single crystal area, and the gate has and only covers one of the two rows of single crystal grains in a direction perpendicular to the substrate.

2. The array substrate according to claim 1, wherein: The first bottom surface and the connecting surface have an acute angle, and the acute angle is less than 45°.

3. The array substrate according to claim 2, wherein: The acute angle is greater than or equal to 15° and less than or equal to 30°.

4. The array substrate according to claim 1, wherein: The gate covers a row of the single crystal grains located on the first top surface in a direction perpendicular to the substrate; The first doped portion is located on the first top surface, and the second doped portion is located on the substrate and the connecting surface.

5. The array substrate according to claim 1, wherein: The gate covers a row of the single crystal grains located on the connection surface in a direction perpendicular to the substrate; The first doping portion is located on the first top surface, and the second doping portion is located on the substrate.

6. The array substrate according to claim 1, wherein: The single crystal region includes a first single crystal region and a second single crystal region, the first single crystal region includes a row of single crystal grains located on the first top surface, and the second single crystal region includes a row of single crystal grains covering the connection surface; Wherein, on the connecting surface, the grain size of the single crystal grains in a row of the single crystal grains in the second single crystal region is greater than the distance between the first edge and the second edge.

7. The array substrate according to claim 1, wherein: In a direction from the first edge to the second edge, the length of the gate is less than or equal to the length of a corresponding row of the single crystal grains.

8. The array substrate according to claim 1, wherein: An insulating pad layer is disposed on a side of the active layer close to the substrate, and the insulating pad layer is disposed on the substrate and the active definition portion; Wherein, the material of the insulating pad layer includes silicon oxide.

9. The array substrate according to claim 1, wherein: The array substrate further includes: a source-drain electrode layer, located on the active layer, comprising a first electrode electrically connected to the first doped portion and a second electrode electrically connected to the second doped portion; The light shielding layer is located in the substrate and includes a light shielding portion arranged corresponding to the channel portion.

10. A display panel, wherein: The invention comprises an array substrate; the array substrate comprises a substrate and a plurality of semiconductor devices located on the substrate; The substrate has an active definition portion, the active definition portion includes a first bottom surface in contact with the top surface of the substrate, a first top surface parallel to the first bottom surface, and a connecting surface connected between the first top surface and the first bottom surface and arranged in an inclined manner, the junction of the connecting surface and the first top surface is a first edge, and the junction of the connecting surface and the first bottom surface is a second edge; The semiconductor device comprises: an active layer, disposed on the substrate and the active definition portion, comprising a first doping portion, a second doping portion, and a channel portion located between the first doping portion and the second doping portion; and A gate layer, comprising a gate arranged corresponding to the channel portion, and a gate insulating layer is arranged between the gate layer and the active layer; Among them, the active layer includes a single crystal starting point, and the grains of the active layer horizontally diffuse and grow on the substrate and the active definition part in a direction perpendicular to the single crystal starting point, and the single crystal starting point corresponds to the first edge; the area where the two rows of single crystal grains on both sides of the single crystal starting point and parallel to the first edge are located is a single crystal area, the channel part is located in the single crystal area, and the gate has and only covers one of the two rows of single crystal grains in a direction perpendicular to the substrate; the display panel includes a plurality of pixel driving circuits, and the pixel driving circuit includes the semiconductor device.

11. The display panel according to claim 10, wherein: The first bottom surface and the connecting surface have an acute angle, and the acute angle is less than 45°.

12. The display panel according to claim 11, wherein: The acute angle is greater than or equal to 15° and less than or equal to 30°.

13. The display panel according to claim 10, wherein: The gate covers a row of the single crystal grains located on the first top surface in a direction perpendicular to the substrate; wherein the first doped portion is located on the first top surface, and the second doped portion is located on the substrate and the connecting surface.

14. The display panel according to claim 10, wherein: The gate covers a row of the single grains located on the connection surface in a direction perpendicular to the substrate; wherein the first doped portion is located on the first top surface, and the second doped portion is located on the substrate.

15. The display panel according to claim 10, wherein: An insulating pad layer is disposed on a side of the active layer close to the substrate, and the insulating pad layer is disposed on the substrate and the active definition portion; wherein the material of the insulating pad layer includes silicon oxide.

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