Array substrate, display panel, and display apparatus

Abstract

An array substrate (10), comprising a base (1), a first conductive layer (2) and a second conductive layer (5), wherein the first conductive layer (2) is located on the base (1); the first conductive layer (2) comprises a gate line (22) and a first data line (21), the gate line (22) extends in a first direction (X), the first data line (21) comprises a plurality of data sub-lines (211), wherein the data sub-lines (211) extend in a second direction (Y), and the plurality of data sub-lines (211) are arranged at intervals in the second direction (Y), the first direction (X) intersecting with the second direction (Y), and the gate line (22) passes through between two adjacent data sub-lines (211), and is spaced apart from the two adjacent data sub-lines (211); and the second conductive layer (5) is located on the side of the first conductive layer (2) that is away from the base (1), the second conductive layer (5) comprises a second data line (51), wherein the second data line (51) extends in the second direction (Y), and the second data line (51) is connected in parallel to the plurality of data sub-lines (211) comprised in the first data line (21). Further provided are a display panel (100) and a display apparatus (1000). The display panel (100) comprises an array substrate (10), and the display panel (100) is used for displaying an image.

Description

Array substrate, display panel and display device

[0001] This application claims priority to Chinese patent application No. 202311435597.8, filed on October 31, 2023, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Art

[0003] Thin Film Transistor Liquid Crystal Display (TFT-LCD) panels have the characteristics of small size, low power consumption, no radiation, and relatively low manufacturing cost, and occupy an important position in the current display panel market.

[0004] Summary of the Invention

[0005] In one aspect, an array substrate is provided, comprising a substrate, a first conductive layer, and a second conductive layer.

[0006] A first conductive layer is disposed on the substrate, the first conductive layer including a gate line and a first data line. The gate line extends along a first direction. The first data line includes a plurality of data sub-lines, the data sub-lines extending along a second direction, and the plurality of data sub-lines are spaced apart along the second direction, with the first direction and the second direction intersecting. The gate line passes between two adjacent data sub-lines and is spaced apart from the two adjacent data sub-lines.

[0007] The second conductive layer is located on a side of the first conductive layer away from the substrate. The second conductive layer includes a second data line extending along the second direction. The second data line and the plurality of data sub-lines included in the first data line are connected in parallel.

[0008] In some embodiments, the array substrate includes a plurality of thin film transistors.

[0009] The array substrate further includes a semiconductor layer located between the first conductive layer and the second conductive layer, and the semiconductor layer includes an active layer pattern of the thin film transistor.

[0010] The second conductive layer further includes a source contact portion and a drain contact portion, wherein the source contact portion and the drain contact portion are respectively connected to the active layer pattern. The thickness of the source contact portion and the drain contact portion are both smaller than the thickness of the first conductive layer.

[0011] In some embodiments, the thickness of the second data line is equal to the thickness of the source contact portion.

[0012] In some embodiments, the second data line includes a first portion, the first portion of the second data line and the data sub-line are arranged opposite to each other in a direction perpendicular to the substrate, and the first portion of the second data line is thicker than the source contact portion.

[0013] In some embodiments, the second data line further includes a second portion. In an orthographic projection onto the substrate, the second portion of the second data line intersects the gate line and does not overlap with the data sub-line. The first portion of the second data line is thicker than the second portion of the second data line.

[0014] In some embodiments, a thickness of the second portion of the second data line is equal to a thickness of the source contact portion.

[0015] In some embodiments, in an orthographic projection onto the substrate, the plurality of data sub-lines included in the first data line and the second data line at least partially overlap.

[0016] In some embodiments, the array substrate further includes a first insulating layer and a first connecting portion. The first insulating layer is located between the first conductive layer and the second conductive layer. The first connecting portion penetrates the first insulating layer, and two ends of the first connecting portion are respectively connected to the data sub-line and the second data line.

[0017] In some embodiments, in an orthographic projection onto the substrate, the first connection portion is located within a range of at least one of the data sub-line and the second data line.

[0018] In some embodiments, the array substrate further includes a first electrode layer and a second connecting portion. The first electrode layer is located on a side of the second conductive layer close to the substrate, the first electrode layer including pixel electrodes. The second connecting portion penetrates the first insulating layer.

[0019] The second conductive layer further includes a source contact portion and a drain contact portion, one end of the second connecting portion is connected to the source contact portion or the drain contact portion, and the other end of the second connecting portion is connected to the pixel electrode.

[0020] In some embodiments, the array substrate further includes a first electrode layer, a second electrode layer, and a third connection portion. The first electrode layer is located on a side of the second conductive layer closer to the substrate, the first electrode layer includes a first transfer pattern, and the first transfer pattern is connected to the data sub-line. The second electrode layer is located on a side of the second conductive layer farther from the substrate, the second electrode layer includes a second transfer pattern. The second transfer pattern, the second data line, and the first transfer pattern are all connected to the third connection portion.

[0021] In some embodiments, the first switching pattern overlaps and contacts the data sub-line.

[0022] In some embodiments, the first electrode layer further includes a pixel electrode. The second electrode layer further includes a third transfer pattern. The second conductive layer further includes a source contact portion and a drain contact portion. The source contact portion or the drain contact portion is connected to the pixel electrode via the third transfer pattern.

[0023] In some embodiments, the array substrate further comprises a second electrode layer, a fourth connecting portion, and a fifth connecting portion. The second electrode layer is located on a side of the second conductive layer away from the substrate, and the second electrode layer comprises a fourth transfer pattern. The data sub-line is connected to the fourth transfer pattern via the fourth connecting portion, and the second data line is connected to the fourth transfer pattern via the fifth connecting portion.

[0024] In some embodiments, at least one gate line is disposed between two adjacent data sub-lines in the second direction.

[0025] In some embodiments, the array substrate includes a plurality of thin film transistors, and the first conductive layer includes gate patterns of the thin film transistors.

[0026] The array substrate further includes a first electrode layer, a second electrode layer, a semiconductor layer, and a first insulating layer. The first electrode layer is located on a side of the first conductive layer close to the substrate, and the first electrode layer includes a pixel electrode. The second electrode layer is located on a side of the second conductive layer away from the substrate, and the second electrode layer includes a common electrode. The pixel electrode and the common electrode are arranged opposite each other in a direction perpendicular to the substrate. A semiconductor layer is located between the first conductive layer and the second conductive layer, and the semiconductor layer includes an active layer pattern of the thin film transistor. A first insulating layer is located between the first conductive layer and the semiconductor layer, and the first insulating layer includes a first portion and a second portion. The first portion of the first insulating layer is located between the gate pattern and the active layer pattern, and the second portion of the first insulating layer is located between the pixel electrode and the common electrode. The thickness of the first portion of the first insulating layer is less than the thickness of the second portion of the first insulating layer.

[0027] In some embodiments, the first insulating layer further includes a third portion located between the data sub-line and the second data line. A thickness of the third portion of the first insulating layer is greater than a thickness of the first portion of the first insulating layer.

[0028] In some embodiments, the first insulating layer includes a first sublayer and a second sublayer stacked together. An overlapping region between the gate pattern and the active layer pattern in a direction perpendicular to the substrate does not overlap with the first sublayer. A portion of the second sublayer is located between the gate pattern and the active layer pattern.

[0029] In some embodiments, the first sub-layer is closer to the substrate than the second sub-layer.

[0030] In some embodiments, the array substrate further includes a second insulating layer, the second insulating layer being located on a side of the second conductive layer away from the substrate, and the thickness of the second insulating layer being greater than or equal to 6000 angstroms and less than or equal to 9000 angstroms.

[0031] In another aspect, a display panel is provided. The display panel includes the array substrate described in any of the above embodiments, an opposing substrate, and a liquid crystal layer. The opposing substrate and the array substrate are disposed opposite each other and spaced apart. The liquid crystal layer is disposed between the array substrate and the opposing substrate.

[0032] In another aspect, a display device is provided. The display device includes the display panel according to any one of the above embodiments and a driver chip. The driver chip is electrically connected to the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0034] FIG1 is a structural diagram of a display device according to some embodiments;

[0035] FIG2 is a planar structural diagram of a display panel according to some embodiments;

[0036] FIG3A is a planar structural diagram of a sub-pixel according to some embodiments;

[0037] FIG3B is another planar structural diagram of a sub-pixel according to some embodiments;

[0038] FIG4A is a planar structural diagram of a local area of ​​a display panel according to some embodiments;

[0039] FIG4B is another planar structural diagram of a partial area of ​​a display panel according to some embodiments;

[0040] FIG5 is a structural diagram of a display panel according to some embodiments;

[0041] FIG6 is a cross-sectional view of a local area of ​​an array substrate according to some embodiments;

[0042] FIG7A is a planar structural diagram of a local area of ​​an array substrate according to some embodiments;

[0043] FIG7B is another planar structural diagram of a local area of ​​an array substrate according to some embodiments;

[0044] 8 is a cross-sectional view of the array substrate shown in FIG. 7A along section line BB or the array substrate shown in FIG. 7B along section line CC;

[0045] 9 is a planar structural diagram of a data sub-line in the first conductive layer, a second data line in the second conductive layer, and a fourth transfer pattern in the second electrode layer according to some embodiments;

[0046] FIG10A is another planar structural diagram of a local area of ​​an array substrate according to some embodiments;

[0047] FIG10B is another planar structural diagram of a local area of ​​an array substrate according to some embodiments;

[0048] 10C is a cross-sectional view of the array substrate shown in FIG10A along section line DD or the array substrate shown in FIG10B along section line EE;

[0049] FIG11A is another planar structural diagram of a local area of ​​an array substrate according to some embodiments;

[0050] FIG11B is another planar structural diagram of a local area of ​​an array substrate according to some embodiments;

[0051] 11C is a cross-sectional view of the array substrate shown in FIG11A along section line FF or the array substrate shown in FIG11B along section line GG;

[0052] 12 is a cross-sectional view of the array substrate shown in FIG10A along section line HH or the array substrate shown in FIG10B along section line II;

[0053] 13 is a cross-sectional view of the array substrate shown in FIG. 11A along section line JJ or the array substrate shown in FIG. 11B along section line KK;

[0054] FIG14 is another cross-sectional view of a local area of ​​an array substrate according to some embodiments;

[0055] FIG15 is another cross-sectional view of a local area of ​​an array substrate according to some embodiments;

[0056] FIG16 is another cross-sectional view of a local area of ​​an array substrate according to some embodiments;

[0057] FIG. 17 is another cross-sectional view of a local area of ​​an array substrate according to some embodiments. DETAILED DESCRIPTION

[0058] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0059] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0060] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0061] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0062] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0063] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0064] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0065] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0066] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0067] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0068] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0069] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0070] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0071] For the convenience of the following description, an XYZ coordinate system is established. The third direction Z is a direction perpendicular to the substrate, the XY plane is perpendicular to the Z direction, and the first direction X intersects the second direction Y. For example, the first direction X and the second direction Y are perpendicular to each other.

[0072] It should be noted that, for example, 211 / 21 appearing in the drawings of the present disclosure indicates that component 211 belongs to component 21, and for example, 51(5) indicates that component 51 is arranged in the film layer 5. Other similar numbers appearing in the drawings also follow the above description.

[0073] As shown in FIG. 1 , some embodiments of the present disclosure provide a display device 1000 .

[0074] Exemplarily, the display device 1000 may be any device that displays images, whether in motion (e.g., video) or stationary (e.g., still images), and whether textual or graphic. More specifically, it is contemplated that the embodiments described herein may be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, video cameras, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, automotive displays (e.g., speedometer displays), navigation systems, cockpit controls and / or displays, camera view displays (e.g., displays for rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays for images of a piece of jewelry). FIG1 illustrates the display device 1000 as a mobile phone.

[0075] Exemplarily, the display device 1000 may be a Thin Film Transistor-Liquid Crystal Display (TFT-LCD) device.

[0076] In some embodiments, referring to FIG1 , a display device 1000 includes a display panel 100 and a driver chip (not shown). The driver chip is electrically connected to the display panel 100 and is configured to drive the display panel 100 to display an image.

[0077] Exemplarily, the driver chip in the display device 1000 may be a source driver IC.

[0078] For example, the driver chip in the display device 1000 can be packaged by Chip On Film (COF), Chip On Glass (COG), Chip On Flexible (COP), etc., and bound to the display panel 100 .

[0079] For example, the driver chip in the display device 1000 can be packaged using a chip-on-film (COF). When the driver chip in the display device 1000 is packaged using a chip-on-film (COF), the display device 1000 includes a COF assembly, which can include a flexible printed circuit (FPC) and the driver chip bound to the FPC.

[0080] In some embodiments, the display device 1000 may further include an optical element (not shown).

[0081] For example, the optical element may include a camera, so that the display device 1000 can realize various functions such as taking photos, recording videos, or face recognition.

[0082] The optical element may also include a sensor, etc. For example, the optical element may include an under-screen fingerprint recognition sensor, so that the display device 1000 can implement functions such as fingerprint recognition. For another example, the optical element may include an infrared sensor.

[0083] The display panel 100 is described in detail below.

[0084] In some embodiments, as shown in FIG2 , which is a planar structural diagram of a display panel 100 according to some embodiments, the display panel 100 may be a rectangular structure.

[0085] It should be noted that the aforementioned "rectangular structure" means that the shape of the boundary of the display panel 100 is rectangular as a whole, but is not limited to a standard rectangle. That is, the "rectangle" here includes not only the shape of a standard rectangle, but also, taking into account process conditions, shapes similar to rectangles. For example, as shown in FIG2 , the long and short sides of the rectangle are curved at each intersection (i.e., corner G), i.e., the corner G is smooth, so that the shape of the boundary of the display panel 100 in a plan view is a rounded rectangle.

[0086] In other embodiments, the display panel 100 may also be a circular structure, or other shapes with corners.

[0087] In the following, some embodiments of the present disclosure are schematically described by taking the display panel 100 as a rectangular structure as an example. However, the embodiments of the present disclosure include but are not limited to this. The shape of the display panel 100 may also be any other shape.

[0088] In some embodiments, referring to FIG. 2 , the display panel 100 includes a display area AA for displaying images, and a peripheral area AN located on at least one side of the display area AA.

[0089] For example, the peripheral area AN of the display panel 100 may be located at one side of the display area AA of the display panel 100 .

[0090] Alternatively, the peripheral area AN of the display panel 100 may be located on opposite sides of the display area AA of the display panel 100 .

[0091] Alternatively, please continue to refer to FIG. 2 , the peripheral area AN of the display panel 100 may surround the display area AA of the display panel 100 .

[0092] It should be noted that the specific configuration of the peripheral area AN of the display panel 100 is related to the specific design of the display panel 100 and can be designed according to actual needs. The following uses the example of the peripheral area AN of the display panel 100 surrounding the display area AA of the display panel 100 as an example to schematically illustrate some embodiments of the present disclosure.

[0093] For example, a gate driver circuit (e.g., Gate Driver On Array, GOA) and control signal lines (e.g., clock signal lines, power supply voltage signal lines, etc.) may be disposed in the peripheral area AN of the display panel 100. However, the functions of the peripheral area AN of the display panel 100 include but are not limited to these.

[0094] In some embodiments, please continue to refer to FIG. 2 . To realize the image display function of the display panel 100 , a plurality of sub-pixels 9 are disposed in the display area AA of the display panel 100 . The sub-pixel 9 is the smallest light-emitting unit in the display area AA.

[0095] Exemplarily, the multiple sub-pixels 9 within the display area AA of the display panel 100 can emit light of the same color. When the multiple sub-pixels 9 within the display area AA of the display panel 100 emit light of the same color, the display panel 100 further includes a color filter layer disposed on the light-emitting side of the multiple sub-pixels 9. For example, the multiple sub-pixels 9 within the display area AA all emit light of a color such as white light, red light, green light, or blue light. In this case, the colored light emitted by the sub-pixels 9 within the display area AA remains the same color after passing through the color filter layer, or is converted into light of another color for emission. Thus, when the multiple sub-pixels 9 within the display area AA of the display panel 100 emit light of the same color, the display area AA of the display panel 100 can achieve multi-color light emission.

[0096] For example, please continue to refer to FIG. 2 , the plurality of sub-pixels 9 in the display area AA of the display panel 100 may be arranged in an array.

[0097] For example, referring to FIG. 2 , the plurality of sub-pixels 9 in the display area AA of the display panel 100 may be arranged in a spaced relationship along a first direction X and a second direction Y. The first direction X may be the row direction in which the plurality of sub-pixels 9 in the display area AA are arranged, and the second direction Y may be the column direction in which the plurality of sub-pixels 9 in the display area AA are arranged.

[0098] In some embodiments, as shown in Figures 3A and 3B, both Figures 3A and 3B are planar structural diagrams of sub-pixels 9 according to some embodiments. In the case where the display device 1000 is a thin film transistor liquid crystal display (TFT-LCD) device, the display panel 100 within the display device 1000 is a thin film transistor liquid crystal display (TFT-LCD) panel, and the sub-pixels 9 within the display area AA of the display panel 100 may include a pixel electrode 91 and a common electrode 92. The pixel electrode 91 and the common electrode 92 are arranged relative to each other in the third direction Z, and a pixel capacitor may be formed between the pixel electrode 91 and the common electrode 92.

[0099] Exemplarily, the material of the pixel electrode 91 may include a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0100] The material of the common electrode 92 may also include a transparent conductive material, for example, the material of the common electrode 92 may include indium tin oxide (ITO) or indium zinc oxide (IZO).

[0101] 3A and 3B , in some embodiments, the sub-pixel 9 in the display area AA of the display panel 100 may further include a thin film transistor (TFT) T1. The TFT T1 includes an active layer pattern T11 and a gate pattern T12. The active layer pattern T11 and the gate pattern T12 of the TFT T1 are arranged opposite to each other in the third direction Z.

[0102] The active layer pattern T11 of the thin film transistor T1 includes a source region, a drain region, and a channel region located between the source region and the drain region.

[0103] 3A and 3B , the active layer pattern T11 of the thin film transistor T1 may be connected to the source contact s and the drain contact d, respectively. Specifically, the source region within the active layer pattern T11 of the thin film transistor T1 may be connected to the source contact s, and the drain region within the active layer pattern T11 of the thin film transistor T1 may be connected to the drain contact d.

[0104] For example, the thin film transistor T1 in the sub-pixel 9 can be a low-temperature polysilicon thin film transistor (LTPS) or an oxide thin film transistor. The active layer of the LTPS thin film transistor uses low-temperature polysilicon (LTPS), while the active layer of the oxide thin film transistor uses an oxide semiconductor (Oxide). LTPS thin film transistors have advantages such as high mobility and fast charging, while oxide thin film transistors have advantages such as low leakage current.

[0105] Exemplarily, the thin film transistor T1 in the sub-pixel 9 may be an N-type transistor or a P-type transistor.

[0106] 3A and 3B , the display panel 100 further includes a second data line 51 and a gate line 22. The gate line 22 extends along a first direction X, and the second data line 51 extends along a second direction Y.

[0107] Since the first direction X and the second direction Y intersect, the gate line 22 extending along the first direction X intersects the second data line 51 extending along the second direction Y. The gate line 22 and the second data line 51 can jointly define a plurality of pixel regions 9 a, and the sub-pixels 9 in the display panel 100 (e.g., the thin film transistor T1, the pixel electrode 91, and the common electrode 92 in the sub-pixel 9) can be located in the pixel region 9 a.

[0108] Continuing to refer to Figures 3A and 3B, when the thin film transistor T1 in the sub-pixel 9 is an N-type transistor, the drain region in the active layer pattern T11 of the thin film transistor T1 is connected to the second data line 51, and the source region in the active layer pattern T11 of the thin film transistor T1 is connected to the pixel electrode 91. The gate pattern T12 of the thin film transistor T1 is connected to the gate line 22.

[0109] Exemplarily, when the thin film transistor T1 in the sub-pixel 9 is an N-type transistor, the drain region in the active layer pattern T11 of the thin film transistor T1 can be connected to the second data line 51 through the drain contact portion d, and the source region in the active layer pattern T11 of the thin film transistor T1 can be connected to the pixel electrode 91 through the source contact portion s.

[0110] When the thin film transistor T1 in the sub-pixel 9 is a P-type transistor, the source region in the active layer pattern T11 of the thin film transistor T1 is connected to the second data line 51, and the drain region in the active layer pattern T11 of the thin film transistor T1 is connected to the pixel electrode 91. The gate pattern T12 of the thin film transistor T1 is connected to the gate line 22.

[0111] For example, please continue to refer to Figures 3A and 3B. When the thin film transistor T1 in the sub-pixel 9 is a P-type transistor, the source region in the active layer pattern T11 of the thin film transistor T1 can be connected to the second data line 51 through the source contact portion s, and the drain region in the active layer pattern T11 of the thin film transistor T1 can be connected to the pixel electrode 91 through the drain contact portion d.

[0112] The following takes the thin film transistor T1 in the sub-pixel 9 as an N-type transistor as an example to schematically illustrate some embodiments of the present disclosure, but the implementation methods of the present disclosure include but are not limited to this. The thin film transistor T1 in the sub-pixel 9 can also be a P-type transistor.

[0113] 3A and 3B , the gate line 22 can control the thin film transistor T1 in the sub-pixel 9 to turn on or off. When the thin film transistor T1 in the sub-pixel 9 is turned on, the second data line 51 can charge the pixel electrode 91 through the thin film transistor T1.

[0114] In some embodiments, referring to FIG. 3B , the display panel 100 may employ a single gate structure. In a display panel 100 employing a single gate structure, the plurality of gate lines 22 within the display panel 100 correspond one-to-one to the plurality of rows of sub-pixels 9 (i.e., the plurality of sub-pixels 9 arranged along the first direction X), i.e., each gate line 22 within the display panel 100 corresponds to a row of sub-pixels 9 (i.e., the plurality of sub-pixels 9 arranged along the first direction X). The plurality of second data lines 51 within the display panel 100 correspond one-to-one to the plurality of columns of sub-pixels 9 (i.e., the plurality of sub-pixels 9 arranged along the second direction Y), i.e., each second data line 51 within the display panel 100 corresponds to a column of sub-pixels 9 (i.e., the plurality of sub-pixels 9 arranged along the second direction Y).

[0115] In other embodiments, please continue to refer to FIG3A , and in conjunction with FIG4A and FIG4B , FIG4A and FIG4B are both planar structural diagrams of a local area of ​​the display panel 100 according to some embodiments. The display panel 100 can adopt a dual gate structure. In the display panel 100 adopting the dual gate structure, each row of sub-pixels 9 (i.e., a plurality of sub-pixels 9 arranged along the first direction X) corresponds to two gate lines 22 in the display panel 100, and each second data line 51 in the display panel 100 corresponds to two columns of sub-pixels 9 (i.e., a plurality of sub-pixels 9 arranged along the second direction Y).

[0116] 3A and 3B , in conjunction with FIG. 4A and 4B , compared to a display panel 100 with a single gate structure, the number of gate lines 22 within the display panel 100 corresponding to each row of sub-pixels 9 (i.e., a plurality of sub-pixels 9 arranged along the first direction X) in a display panel 100 with a dual gate structure is twice the number of gate lines 22 within the display panel 100 corresponding to each row of sub-pixels 9 (i.e., a plurality of sub-pixels 9 arranged along the first direction X) in the display panel 100 with a single gate structure. The number of second data lines 51 within the display panel 100 corresponding to each column of sub-pixels 9 (i.e., a plurality of sub-pixels 9 arranged along the second direction Y) in a display panel 100 with a dual gate structure is half the number of second data lines 51 within the display panel 100 corresponding to each column of sub-pixels 9 (i.e., a plurality of sub-pixels 9 arranged along the second direction Y) in a display panel 100 with a single gate structure.

[0117] That is to say, the dual gate structure adopted by the display panel 100 can reduce the number of second data lines 51 in the display panel 100, thereby reducing the cost of the driver chip, and can also reduce the fan-out wiring space, thereby reducing the size of the peripheral area AN of the display panel 100, which is conducive to realizing a narrow frame design of the display panel 100.

[0118] For example, please continue to refer to Figure 4A and combine it with Figure 3A. When the display panel 100 adopts a dual gate structure, along the second direction Y, the two gate lines 22 corresponding to a row of sub-pixels 9 (i.e., multiple sub-pixels 9 arranged along the first direction X) in the display panel 100 are located on opposite sides of a row of sub-pixels 9 (i.e., multiple sub-pixels 9 arranged along the first direction X).

[0119] One of the two gate lines 22 corresponding to a row of sub-pixels 9 (i.e., a plurality of sub-pixels 9 arranged along the first direction X) in the display panel 100 is connected to the thin film transistors T1 in a portion of the sub-pixels 9 in the row of sub-pixels 9 (i.e., a plurality of sub-pixels 9 arranged along the first direction X), and the other gate line 22 is connected to the thin film transistors T1 in another portion of the sub-pixels 9 in the row of sub-pixels 9 (i.e., a plurality of sub-pixels 9 arranged along the first direction X).

[0120] For example, referring to FIG4A and FIG3A , each row of sub-pixels 9 (i.e., a plurality of sub-pixels 9 arranged along the first direction X) includes a plurality of pixel units 9m, each pixel unit 9m including three sub-pixels 9 (specifically, the three sub-pixels 9 included in each pixel unit 9m may be a first sub-pixel 9R, a second sub-pixel 9G, and a third sub-pixel 9B). In a row of sub-pixels 9 (i.e., a plurality of sub-pixels 9 arranged along the first direction X), two adjacent pixel units 9m may form a pixel unit group 9n. One of the two gate lines 22 of the display panel 100 corresponding to a row of sub-pixels 9 (i.e., a plurality of sub-pixels 9 arranged along the first direction X) can be respectively connected to the thin film transistor T1 in the first sub-pixel 9 (i.e., the first sub-pixel 9R) in the pixel unit group 9n, the thin film transistor T1 in the fourth sub-pixel 9 (i.e., the first sub-pixel 9R), and the thin film transistor T1 in the sixth sub-pixel 9 (i.e., the third sub-pixel 9B), and the other gate line 22 can be respectively connected to the thin film transistor T1 in the second sub-pixel 9 (i.e., the second sub-pixel 9G) in the pixel unit group 9n, the thin film transistor T1 in the third sub-pixel 9 (i.e., the third sub-pixel 9B), and the thin film transistor T1 in the fifth sub-pixel 9 (i.e., the second sub-pixel 9G).

[0121] For example, referring to FIG. 4A and in combination with FIG. 3A , when the display panel 100 adopts a dual-gate structure, a second data line 51 is provided for every two columns of sub-pixels 9 (i.e., a plurality of sub-pixels 9 arranged along the second direction Y). The j-th second data line 51 can be respectively connected to the thin-film transistors T1 in the 2j-1th and 2j-th columns of the sub-pixels 9 in odd-numbered rows (i.e., a plurality of sub-pixels 9 arranged along the first direction X), and the j-th second data line 51 can also be respectively connected to the thin-film transistors T1 in the 2j-3th and 2j-2nd columns of the sub-pixels 9 in even-numbered rows (i.e., a plurality of sub-pixels 9 arranged along the first direction X). Wherein, j ≥ 1, and j is a positive integer.

[0122] It should be noted that when j=1, there are no 2j-3 column and 2j-2 column sub-pixels 9 in the display panel 100, so the first second data line 51 and the even-numbered row sub-pixels 9 (i.e., multiple sub-pixels 9 arranged along the first direction X) are not connected.

[0123] For example, please continue to refer to Figure 4A and combine it with Figure 3A. The second second data line 51 can be connected to the thin film transistors T1 in the third and fourth columns of sub-pixels 9 in the odd rows of sub-pixels 9 (i.e., multiple sub-pixels 9 arranged along the first direction X), respectively, and the second second data line 51 can also be connected to the thin film transistors T1 in the first and second columns of sub-pixels 9 in the even rows of sub-pixels 9 (i.e., multiple sub-pixels 9 arranged along the first direction X), respectively.

[0124] Alternatively, referring to FIG. 4B , in conjunction with FIG. 3A , when the display panel 100 employs a dual-gate structure, a second data line 51 is provided for every two columns of sub-pixels 9 (i.e., a plurality of sub-pixels 9 arranged along the second direction Y). The j-th second data line 51 can be respectively connected to the thin-film transistors T1 in the 2j-3th and 2j-2nd columns of sub-pixels 9 in odd-numbered rows of sub-pixels 9 (i.e., a plurality of sub-pixels 9 arranged along the first direction X). The j-th second data line 51 can also be respectively connected to the thin-film transistors T1 in the 2j-1th and 2jth columns of sub-pixels 9 in even-numbered rows of sub-pixels 9 (i.e., a plurality of sub-pixels 9 arranged along the first direction X). Wherein, j ≥ 1, and j is a positive integer.

[0125] It should be noted that when j=1, there are no 2j-3 column and 2j-2 column sub-pixels 9 in the display panel 100, so the first second data line 51 and the odd-numbered row sub-pixels 9 (i.e., multiple sub-pixels 9 arranged along the first direction X) are not connected.

[0126] For example, please continue to refer to Figure 4B and combine it with Figure 3A. The second second data line 51 can be connected to the thin film transistors T1 in the first and second columns of sub-pixels 9 in the odd rows of sub-pixels 9 (that is, the multiple sub-pixels 9 arranged along the first direction X), and the second second data line 51 can also be connected to the thin film transistors T1 in the third and fourth columns of sub-pixels 9 in the even rows of sub-pixels 9 (that is, the multiple sub-pixels 9 arranged along the first direction X).

[0127] In some embodiments, as shown in FIG5 , FIG5 is a structural diagram of a display panel 100 according to some embodiments. In the case where the display panel 100 is a thin film transistor-liquid crystal display (TFT-LCD) panel, the display panel 100 may include an array substrate 10, an opposing substrate 20, and a liquid crystal layer 30. The opposing substrate 20 and the array substrate 10 are disposed opposite each other and spaced apart, and the liquid crystal layer 30 is disposed between the array substrate 10 and the opposing substrate 20.

[0128] An electric field is generated within the display panel 100, causing the liquid crystal molecules 301 within the liquid crystal layer 30 of the display panel 100 to deflect under the action of the electric field. By adjusting the intensity of the electric field applied to the liquid crystal layer 30 within the display panel 100, the degree of deflection of the liquid crystal molecules 301 within the liquid crystal layer 30 can be controlled, thereby controlling the amount of light transmitted through the region within the liquid crystal layer 30 where the liquid crystal molecules 301 are located, thereby enabling the display panel 100 to display images.

[0129] 5 , and in combination with FIG. 3A and FIG. 3B , the electric field driving the liquid crystal molecules 301 in the liquid crystal layer 30 in the display panel 100 to deflect may be generated when a voltage is applied to the pixel electrode 91 and the common electrode 92 in the sub-pixel 9 .

[0130] For example, please continue to refer to FIG. 5 , the counter substrate 20 in the display panel 100 may be a color filter substrate.

[0131] The thin film transistor T1, pixel electrode 91, and common electrode 92 in the sub-pixel 9 in the display panel 100, as well as the second data line 51 and gate line 22 in the display panel 100, can be disposed in the array substrate 10 in the display panel 100. The array substrate 10 in the display panel 100 is described in detail below.

[0132] In some embodiments, as shown in FIG6 , FIG6 is a cross-sectional view of a local area of ​​an array substrate 10 according to some embodiments. The array substrate 10 includes a substrate 1 .

[0133] Exemplarily, the substrate 1 may be a rigid substrate, such as a glass substrate or a polymethylmethacrylate (PMMA) substrate.

[0134] Alternatively, the substrate 1 may be a flexible substrate, for example, a polyethylene terephthalate (PET) substrate, a polyethylene naphthalate (PEN) substrate, or a polyimide (PI) substrate.

[0135] In some embodiments, please continue to refer to FIG6 and combine with FIG3A and FIG3B , the array substrate 10 further includes a first conductive layer 2 . The first conductive layer 2 is located on the substrate 1 .

[0136] 6 , and in combination with FIG3A and FIG3B , the gate pattern T12 of the thin film transistor T1 may be disposed in the first conductive layer 2. That is, the first conductive layer 2 in the array substrate 10 includes the gate pattern T12 of the thin film transistor T1.

[0137] 3A and 3B , the gate line 22 may also be disposed in the first conductive layer 2 . That is, the first conductive layer 2 in the array substrate 10 includes the gate line 22 .

[0138] For example, the first conductive layer 2 in the array substrate 10 can be formed by depositing metal materials such as MO / Ti / Al / Cu (molybdenum / titanium / aluminum / copper) using a physical vapor deposition (PVD) process. For example, the first conductive layer 2 in the array substrate 10 can be formed by depositing Cu (copper) using a physical vapor deposition process.

[0139] 6 , the array substrate 10 further includes a first insulating layer 3 and a semiconductor layer 4. The semiconductor layer 4 is located on a side of the first conductive layer 2 away from the substrate 1, and the first insulating layer 3 is located between the semiconductor layer 4 and the first conductive layer 2.

[0140] 6 , and in combination with FIG3A and FIG3B , the active layer pattern T11 of the thin film transistor T1 may be disposed in the semiconductor layer 4. That is, the semiconductor layer 4 in the array substrate 10 includes the active layer pattern T11 of the thin film transistor T1.

[0141] Exemplarily, the material of the semiconductor layer 4 may be low-temperature polysilicon.

[0142] Alternatively, the material of the semiconductor layer 4 may be any one of indium gallium zinc oxide and low-temperature polycrystalline oxide. For example, the material of the semiconductor layer 4 may be indium gallium zinc oxide (IGZO). For another example, the material of the semiconductor layer 4 may be indium gallium zinc tin oxide (IGZTO).

[0143] It can be understood that when the material of the semiconductor layer 4 is low-temperature polysilicon, the thin film transistor T1 in which the active layer pattern T11 is located in the semiconductor layer 4 is a low-temperature polysilicon thin film transistor.

[0144] When the material of the semiconductor layer 4 is any one of indium gallium zinc oxide and low temperature polycrystalline oxide, the thin film transistor T1 where the active layer pattern T11 is located in the semiconductor layer 4 is an oxide thin film transistor.

[0145] Illustratively, the semiconductor layer 4 can be obtained by using an excimer laser annealing process.

[0146] Alternatively, the semiconductor layer 4 can also be obtained by a physical vapor deposition process.

[0147] For example, the material of the first insulating layer 3 may include silicon nitride, silicon oxide, or silicon oxynitride, and may be deposited by a plasma enhanced chemical vapor deposition (PECVD) process.

[0148] In some embodiments, please continue to refer to FIG6 , the array substrate 10 further includes a second conductive layer 5 . The second conductive layer 5 is located on a side of the first conductive layer 2 away from the substrate 1 .

[0149] The semiconductor layer 4 in the array substrate 10 may be located between the first conductive layer 2 and the second conductive layer 5. Since the first insulating layer 3 in the array substrate 10 is located between the semiconductor layer 4 and the first conductive layer 2, when the semiconductor layer 4 in the array substrate 10 is located between the first conductive layer 2 and the second conductive layer 5, the first insulating layer 3 in the array substrate 10 is also located between the first conductive layer 2 and the second conductive layer 5.

[0150] 6 , and in combination with FIG3A and FIG3B , the source contact portion s and the drain contact portion d may be disposed in the second conductive layer 5. That is, the second conductive layer 5 in the array substrate 10 includes the source contact portion s and the drain contact portion d.

[0151] Continuing with FIG6 , the active layer pattern T11 of the thin film transistor T1 in the semiconductor layer 4 can contact the source contact portion s and the drain contact portion d in the second conductive layer 5. That is, no insulating film layer is disposed between the active layer pattern T11 of the thin film transistor T1 in the semiconductor layer 4 and the source contact portion s and the drain contact portion d in the second conductive layer 5.

[0152] 3A and 3B , the second data line 51 may be disposed in the second conductive layer 5 . That is, the second conductive layer 5 in the array substrate 10 includes the second data line 51 .

[0153] For example, the second conductive layer 5 in the array substrate 10 can be formed by depositing metal materials such as MO / Ti / Al / Cu (molybdenum / titanium / aluminum / copper) using a physical vapor deposition process. For example, the second conductive layer 5 in the array substrate 10 can be formed by depositing Cu (copper) using a physical vapor deposition process.

[0154] In some embodiments, please continue to refer to FIG6 , the array substrate 10 further includes a first electrode layer 6 . The first electrode layer 6 is located on a side of the second conductive layer 5 close to the substrate 1 .

[0155] For example, referring to FIG. 6 , the first electrode layer 6 may be located on a side of the first insulating layer 3 close to the substrate 1 .

[0156] 3A and 3B , the pixel electrode 91 may be disposed in the first electrode layer 6 . That is, the first electrode layer 6 in the array substrate 10 includes the pixel electrode 91 .

[0157] For example, the material of the first electrode layer 6 in the array substrate 10 may include a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0158] In some embodiments, referring to FIG6 , the array substrate 10 further includes a second electrode layer 8 and a second insulating layer 7. The second insulating layer 7 and the second electrode layer 8 are both located on the side of the second conductive layer 5 in the array substrate 10 away from the substrate 1, and the second electrode layer 8 is located on the side of the second insulating layer 7 away from the substrate 1. That is, the second insulating layer 7 is closer to the substrate 1 than the second electrode layer 8.

[0159] For example, please continue to refer to FIG. 6 and combine with FIG. 3A and FIG. 3B , the common electrode 92 may be disposed in the second electrode layer 8 . That is, the second electrode layer 8 in the array substrate 10 includes the common electrode 92 .

[0160] Exemplarily, the material of the second electrode layer 8 in the array substrate 10 may include a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0161] For example, the material of the second insulating layer 7 in the array substrate 10 may include silicon nitride, silicon oxide, or silicon oxynitride, etc., which is deposited by a plasma enhanced chemical vapor deposition process.

[0162] For example, please continue to refer to Figure 6. A first insulating layer 3 and a second insulating layer 7 can be arranged between the first electrode layer 6 and the second electrode layer 8 in the array substrate 10, and the first insulating layer 3 is closer to the first electrode layer 6 than the second insulating layer 7, and the second insulating layer 7 is closer to the second electrode 8 than the first insulating layer 3.

[0163] It should be noted that Figures 3A and 3B only illustrate the first conductive layer 2, semiconductor layer 4, second conductive layer 5, first electrode layer 6, and second electrode layer 8 of the array substrate 10, and omit other film layers of the array substrate 10. For example, Figures 3A and 3B omit the substrate 1, first insulating layer 3, second insulating layer 7, and the like of the array substrate 10.

[0164] In order to facilitate the explanation of the embodiments shown in Figures 3A and 3B, the semiconductor layer 4, the second conductive layer 5 and the second electrode layer 8 in Figures 3A and 3B are made transparent to expose other film layers in the array substrate 10 located on the side of the second electrode layer 8 close to the substrate 1 (for example, the first conductive layer 2, the semiconductor layer 4, the second conductive layer 5 and the first electrode layer 6, etc.).

[0165] In some embodiments, please continue to refer to Figures 3A and 3B. The specific process of charging the sub-pixel 9 in the display panel 100 can be: the gate line 22 controls the thin film transistor T1 in the sub-pixel 9 to turn on, and when the thin film transistor T1 in the sub-pixel 9 is turned on, the second data line 51 charges the pixel electrode 91 in the sub-pixel 9 through the thin film transistor T1 in the sub-pixel 9.

[0166] During the charging process of the sub-pixels 9 in the display panel 100 , some of the sub-pixels 9 in the display panel 100 may be undercharged, which may easily cause poor display of the display panel 100 and affect the display effect of the display panel 100 .

[0167] For example, referring to FIG3A , in a display panel 100 employing a dual-gate structure, the charging time of the sub-pixels 9 within the display panel 100 is generally half that of the sub-pixels 9 within a display panel 100 employing a single-gate structure. That is, in a display panel 100 employing a dual-gate structure, the charging time of the sub-pixels 9 within the display panel 100 is shorter, and some sub-pixels 9 within the display panel 100 may be undercharged, which may easily cause poor display of the display panel 100 and affect the display quality of the display panel 100.

[0168] Especially when the display panel 100 is a high refresh rate display panel, some sub-pixels 9 in the display panel 100 are more likely to be undercharged, which is more likely to cause poor display of the display panel 100 and affect the display effect of the display panel 100.

[0169] Since in the display panel 100 adopting a dual gate structure, the gate drive of the display panel 100 is usually a positive "Z" type scan. Therefore, when some sub-pixels 9 in the display panel 100 are insufficiently charged, it is manifested that a certain column of sub-pixels in the display panel 100 (i.e., multiple sub-pixels 9 arranged along the second direction Y) are more fully charged, while another column of sub-pixels (i.e., multiple sub-pixels 9 arranged along the second direction Y) are insufficiently charged. The display panel 100 is prone to defective stripes extending along the second direction Y, which affects the display effect of the display panel 100.

[0170] Based on this, in some embodiments, as shown in Figures 7A and 7B, both of which are planar structural diagrams of a partial area of ​​an array substrate 10 according to some embodiments, it should be noted that the array substrate 10 shown in Figure 7A is an array substrate 10 in a display panel 100 adopting a dual-gate structure, and the array substrate 10 shown in Figure 7B is an array substrate 10 in a display panel 100 adopting a single-gate structure.

[0171] Figures 7A and 7B only illustrate the first conductive layer 2, semiconductor layer 4, second conductive layer 5, first electrode layer 6, and second electrode layer 8 of the array substrate 10, omitting other film layers of the array substrate 10. For example, Figures 7A and 7B omit the substrate 1, first insulating layer 3, and second insulating layer 7 of the array substrate 10.

[0172] To facilitate the description of the embodiments shown in Figures 7A and 7B, the semiconductor layer 4, the second conductive layer 5 and the second electrode layer 8 in Figures 7A and 7B are made transparent to expose other film layers (for example, the first conductive layer 2, the semiconductor layer 4, the second conductive layer 5 and the first electrode layer 6) in the array substrate 10 that are located on the side of the second electrode layer 8 close to the substrate 1.

[0173] The first conductive layer 2 of the array substrate 10 further includes first data lines 21. The first data lines 21 include a plurality of data sub-lines 211 extending along the second direction Y and arranged at intervals along the second direction Y.

[0174] The second data line 51 in the second conductive layer 5 of the array substrate 10 and the plurality of data sub-lines 211 included in the first data line 21 are connected in parallel.

[0175] By providing a first data line 21 in the first conductive layer 2 of the array substrate 10, the first data line 21 includes a plurality of data sub-lines 211, and the second data line 51 in the second conductive layer 5 of the array substrate 10 and the plurality of data sub-lines 211 included in the first data line 21 in the first conductive layer 2 are connected in parallel, the overall line resistance of the data line formed by the first data line 21 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5 can be reduced, thereby reducing the resistance-capacitance delay (RC Delay) effect of the data line formed by the first data line 21 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5. When the data line formed by the first data line 21 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5 is used to charge the sub-pixels 9 in the display panel 10, the charging efficiency of the sub-pixels 9 in the display panel 100 is improved, the probability of insufficient charging of the sub-pixels 9 in the display panel 100 is reduced, and the display effect of the display panel 100 including the above-mentioned array substrate 10 is improved.

[0176] For example, referring to FIG. 7A and FIG. 7B , a second data line 51 may be connected in parallel to at least one data sub-line 211 in the first data line 21 .

[0177] For example, a second data line 51 can be connected in parallel with a data sub-line 211 in the first data line 21, which can reduce the overall line resistance of the data line composed of the first data line 21 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5, and thus weaken the resistance-capacitance delay (RC Delay) effect of the data line composed of the first data line 21 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5. When the data line composed of the first data line 21 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5 is used to charge the sub-pixel 9 in the display panel 10, it is beneficial to improve the charging efficiency of the sub-pixel 9 in the display panel 100, reduce the probability of insufficient charging of the sub-pixel 9 in the display panel 100, and thereby improve the display effect of the display panel 100 including the above-mentioned array substrate 10.

[0178] For another example, please continue to refer to Figures 7A and 7B. A second data line 51 can be connected in parallel with multiple data sub-lines 211 in the first data line 21, respectively. This can further reduce the overall line resistance of the data line composed of the first data line 21 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5, and thus further weaken the resistance-capacitance delay (RC Delay) effect of the data line composed of the first data line 21 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5. When the data line composed of the first data line 21 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5 is used to charge the sub-pixel 9 in the display panel 10, it is beneficial to further improve the charging efficiency of the sub-pixel 9 in the display panel 100, further reduce the probability of insufficient charging of the sub-pixel 9 in the display panel 100, and further improve the display effect of the display panel 100 including the above-mentioned array substrate 10.

[0179] For example, please continue to refer to Figures 7A and 7B. When the first conductive layer 2 of the array substrate 10 includes a first data line 21 and a gate line 22, that is, the first data line 21 and the gate line 22 are arranged in the same layer, since the first data line 21 includes multiple data sub-lines 211 extending along the second direction Y and arranged at intervals along the second direction Y, the gate line 11 extends along the first direction X, and the first direction X and the second direction Y intersect. Therefore, in order to avoid the intersection of the multiple data sub-lines 211 and the gate line 22 included in the first data line 21 in the first conductive layer 2, the gate line 22 passes between two adjacent data sub-lines 211 and is spaced apart from the two adjacent data sub-lines 211.

[0180] It should be noted that the aforementioned "same-layer arrangement" refers to a layer structure formed by using the same film-forming process to form the film layer used to form the specific pattern (i.e., the first data line 21 and the gate line 22), and then using the same mask through a single patterning process. Depending on the specific pattern (i.e., the first data line 21 and the gate line 22), the single patterning process may include multiple exposure, development, or etching processes. These specific patterns (i.e., the first data line 21 and the gate line 22) may also be at different heights or have different thicknesses.

[0181] 7A and 7B , in the first conductive layer 2 of the array substrate 10 , when the gate line 22 passes between two adjacent data sub-lines 211 and is spaced apart from the two adjacent data sub-lines 211 , at least one gate line 22 is provided between two adjacent data sub-lines 211 in the second direction Y.

[0182] For example, please continue to refer to Figure 7A. When the array substrate 10 is an array substrate 10 in a display panel 100 with a dual gate structure, two gate lines 22 can be arranged between two adjacent data sub-lines 211 in the second direction Y in the first conductive layer 2 of the array substrate 10.

[0183] For another example, please continue to refer to Figure 7B. When the array substrate 10 is an array substrate 10 in a display panel 100 with a single gate structure, a gate line 22 can be set between two adjacent data sub-lines 211 in the second direction Y in the first conductive layer 2 of the array substrate 10.

[0184] 7A and 7B , the size K1 of the data sub-line 211 included in the first data line 21 in the first conductive layer 2 along the first direction X may be larger than the size K2 of the second data line 51 in the second conductive layer 5 along the first direction X. That is, the size K1 of the data sub-line 211 included in the first data line 21 in the first conductive layer 2 along the first direction X is larger, which can reduce the resistance of the data sub-line 211 included in the first data line 21 in the first conductive layer 2, and further reduce the overall line resistance of the data line composed of the first data line 21 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5, and can further weaken the resistance-capacitance delay (RC Delay) effect of the data line composed of the first data line 21 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5. When the data line composed of the first data line 21 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5 is used to charge the sub-pixel 9 in the display panel 10, it is beneficial to further improve the charging efficiency of the sub-pixel 9 in the display panel 100, further reduce the probability of insufficient charging of the sub-pixel 9 in the display panel 100, and further improve the display effect of the display panel 100 including the above-mentioned array substrate 10.

[0185] Exemplarily, referring to FIG. 7A and FIG. 7B , in the orthographic projection onto the substrate 1 , the plurality of data sub-lines 211 included in the first data line 21 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5 at least partially overlap.

[0186] It should be noted that Figures 7A and 7B illustrate some embodiments of the present disclosure by taking as an example the partial overlap of the multiple data sub-lines 211 included in the first data line 21 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5 in an orthographic projection onto the substrate 1. However, the relative positional relationship between the multiple data sub-lines 211 included in the first data line 21 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5 in the present disclosure includes but is not limited to this. For example, in an orthographic projection onto the substrate 1, the multiple data sub-lines 211 included in the first data line 21 in the first conductive layer 2 may be located within the range of the second data line 51 in the second conductive layer 5.

[0187] The materials of the multiple data sub-lines 211 included in the first data line 21 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5 generally include opaque metal (for example, copper, etc.). In the orthographic projection onto the substrate 1, by making the multiple data sub-lines 211 included in the first data line 21 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5 at least partially overlap, the total area of ​​the multiple data sub-lines 211 included in the first data line 21 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5 in the orthographic projection onto the substrate 1 can be reduced. This is beneficial for reducing the area ratio of the multiple data sub-lines 211 included in the first data line 21 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5 in the orthographic projection onto the substrate 1, that is, it is beneficial for reducing the area ratio of the opaque metal in the orthographic projection onto the substrate 1, thereby improving the aperture ratio of the array substrate 10 and improving the display effect of the display panel 100 including the array substrate 10.

[0188] The following describes in detail the connection between the second data line 51 in the second conductive layer 5 of the array substrate 10 and the plurality of data sub-lines 211 included in the first data line 21 in the first conductive layer 2 .

[0189] In some embodiments, as shown in FIG8 , and in combination with FIG7A and FIG7B , FIG8 is a cross-sectional view of the array substrate 10 shown in FIG7A along section line BB or the array substrate 10 shown in FIG7B along section line CC. The second electrode layer 8 of the array substrate 10 further includes a fourth transfer pattern a4.

[0190] The array substrate 10 also includes a fourth connection portion L4 and a fifth connection portion L5. The data sub-lines 211 included in the first data line 21 in the first conductive layer 2 are connected to the fourth transfer pattern a4 in the second electrode layer 8 via the fourth connection portion L4. The second data line 51 in the second conductive layer 5 is connected to the fourth transfer pattern a4 in the second electrode layer 8 via the fifth connection portion L5. Specifically, by connecting the data sub-lines 211 included in the first data line 21 in the first conductive layer 2 to the second data line 51 in the second conductive layer 5, respectively, the data sub-lines 211 included in the first data line 21 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5 are connected in parallel.

[0191] For example, as shown in FIG9 , FIG9 is a planar structural diagram of a data sub-line 211 in the first conductive layer 2, a second data line 51 in the second conductive layer 5, and a fourth transfer pattern a4 in the second electrode layer 8 according to some embodiments. In the case where the data sub-line 211 included in the first data line 21 in the first conductive layer 2 is connected via the fourth connection portion L4 to the fourth transfer pattern a4 in the second electrode layer 8, and the second data line 51 in the second conductive layer 5 is connected via the fifth connection portion L5 to the fourth transfer pattern a4 in the second electrode layer 8, the data sub-line 211 in the first conductive layer 2 may include a main portion 211a extending along the second direction Y, and a protruding portion 211b connected to the main portion 211a.

[0192] In the orthographic projection onto the substrate 1, at least a partial area of ​​the protruding portion 211b of the data sub-line 211 in the first conductive layer 2 does not overlap with the second data line 51 in the second conductive layer 5. The above-mentioned "the data sub-line 211 included in the first data line 21 in the first conductive layer 2 is connected to the fourth transfer pattern a4 in the second electrode layer 8 through the fourth connection portion L4" can specifically be that the protruding portion 211b of the data sub-line 211 included in the first data line 21 in the first conductive layer 2 is connected to the fourth transfer pattern a4 in the second electrode layer 8 through the fourth connection portion L4.

[0193] In an orthographic projection onto the substrate 1 , the main portion 211 a of the data sub-line 211 in the first conductive layer 2 may at least partially overlap with the second data line 51 in the second conductive layer 5 .

[0194] In the orthographic projection onto the substrate 1, by making the main body 211a of the data sub-line 211 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5 at least partially overlap, the total area of ​​the main body 211a of the data sub-line 211 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5 in the orthographic projection onto the substrate 1 can be reduced, which is beneficial to reducing the area ratio of the main body 211a of the data sub-line 211 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5 in the orthographic projection onto the substrate 1.

[0195] When the materials of the main body 211a of the data sub-line 211 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5 include opaque metal (for example, copper, etc.), by reducing the area ratio of the main body 211a of the data sub-line 211 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5 in the orthographic projection onto the substrate 1, the area ratio of the opaque metal in the orthographic projection onto the substrate 1 can be reduced, which is beneficial to improving the aperture ratio of the array substrate 10 and improving the display effect of the display panel 100 including the array substrate 10.

[0196] In some embodiments, as shown in Figures 10A, 10B, and 10C, Figures 10A and 10B are both planar structural diagrams of a partial area of ​​an array substrate 10 according to some embodiments, and Figure 10C is a cross-sectional view of the array substrate 10 shown in Figure 10A along section line DD or the array substrate 10 shown in Figure 10B along section line EE. It should be noted that the array substrate 10 shown in Figure 10A is an array substrate 10 within a display panel 100 employing a dual-gate structure, and the array substrate 10 shown in Figure 10B is an array substrate 10 within a display panel 100 employing a single-gate structure.

[0197] Figures 10A and 10B only illustrate the first conductive layer 2, semiconductor layer 4, second conductive layer 5, first electrode layer 6, and second electrode layer 8 of the array substrate 10, omitting other film layers of the array substrate 10. For example, Figures 10A and 10B omit the substrate 1, first insulating layer 3, and second insulating layer 7 of the array substrate 10.

[0198] In order to facilitate the explanation of the embodiments shown in Figures 10A and 10B, the semiconductor layer 4, the second conductive layer 5 and the second electrode layer 8 in Figures 10A and 10B are made transparent to expose other film layers (for example, the first conductive layer 2, the semiconductor layer 4, the second conductive layer 5 and the first electrode layer 6, etc.) in the array substrate 10 that are located on the side of the second electrode layer 8 close to the substrate 1.

[0199] The array substrate 10 further includes a third connection portion L3. The first electrode layer 6 of the array substrate 10 further includes a first transfer pattern a1, and the second electrode layer 8 further includes a second transfer pattern a2.

[0200] The first transfer pattern a1 in the first electrode layer 6 is connected to the data sub-line 211 in the first conductive layer 2, and the second transfer pattern a2 in the second electrode layer 8, the second data line 51 in the second conductive layer 5 and the first transfer pattern a1 in the first electrode layer 6 are all connected to the third connection part L3, that is, the data sub-line 211 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5 are both connected to the first transfer pattern a1 in the first electrode layer 6, so that the data sub-line 211 included in the first data line 21 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5 are connected in parallel.

[0201] Since the data sub-line 211 in the first conductive layer 2 is connected to the first transfer pattern a1 in the first electrode layer 6, and the second data line 51 in the second conductive layer 5, the second transfer pattern a2 in the second electrode layer 8 and the first transfer pattern a1 in the first electrode layer 6 are connected, among the data sub-line 211 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5, only the second data line 51 in the second conductive layer 5 and the second transfer pattern a2 in the second electrode layer 8 are connected, and the data sub-line 211 in the first conductive layer 2 and the second transfer pattern a2 in the second electrode layer 8 are not connected. Since the second conductive layer 5 is located between the first conductive layer 2 and the second electrode layer 8, when the data sub-line 211 in the first conductive layer 2 and the second transfer pattern a2 in the second electrode layer 8 are not connected, in the orthographic projection to the substrate 1, the data sub-line 211 in the first conductive layer 2 does not need to be set up in a partial area without overlapping with the second data line 51 in the second conductive layer 5, so as to connect the data sub-line 211 in the first conductive layer 2 and the second transfer pattern a2 in the second electrode layer 8, which is beneficial to increase the overlapping area of ​​the data sub-line 211 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5 in the orthographic projection to the substrate 1, and further reduce the total area of ​​the data sub-line 211 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5 in the orthographic projection to the substrate 1, which is beneficial to further reduce the area ratio of the data sub-line 211 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5 in the orthographic projection to the substrate 1.

[0202] In the case where the materials of the data sub-line 211 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5 include opaque metal (for example, copper, etc.), by further reducing the area ratio of the data sub-line 211 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5 in the orthographic projection onto the substrate 1, the area ratio of the opaque metal in the orthographic projection onto the substrate 1 can be further reduced, which is beneficial to further improve the aperture ratio of the array substrate 10 and further improve the display effect of the display panel 100 including the array substrate 10.

[0203] For example, referring to FIG. 10C in conjunction with FIG. 10A and FIG. 10B , the first transfer pattern a1 in the first electrode layer 6 can overlap and contact the data sub-line 211 in the first conductive layer 2. That is, no insulating film layer is provided between the first transfer pattern a1 in the first electrode layer 6 and the data sub-line 211 in the first conductive layer 2, and in an orthographic projection onto the substrate 1, the first transfer pattern a1 in the first electrode layer 6 overlaps with the data sub-line 211 in the first conductive layer 2.

[0204] Exemplarily, referring to FIG. 10C , the third connection portion L3 in the array substrate 10 may pass through the first insulating layer 3 and the second insulating layer 7 in the array substrate 10 .

[0205] In some embodiments, as shown in Figures 11A, 11B, and 11C, Figures 11A and 11B are both planar structural diagrams of a partial area of ​​an array substrate 10 according to some embodiments, and Figure 11C is a cross-sectional view of the array substrate 10 shown in Figure 11A along section line FF or the array substrate 10 shown in Figure 11B along section line GG. It should be noted that the array substrate 10 shown in Figure 11A is an array substrate 10 within a display panel 100 employing a dual-gate structure, and the array substrate 10 shown in Figure 11B is an array substrate 10 within a display panel 100 employing a single-gate structure.

[0206] Figures 11A and 11B only illustrate the first conductive layer 2, semiconductor layer 4, second conductive layer 5, and first electrode layer 6 of the array substrate 10, omitting other film layers of the array substrate 10. For example, Figures 11A and 11B omit the substrate 1, first insulating layer 3, second insulating layer 7, and second electrode layer 8 of the array substrate 10.

[0207] To facilitate the description of the embodiment shown in Figures 11A and 11B, the semiconductor layer 4 and the second conductive layer 5 in Figures 11A and 11B are made transparent to expose other film layers (for example, the first conductive layer 2, the semiconductor layer 4 and the first electrode layer 6) in the array substrate 10 located on the side of the second conductive layer 5 close to the substrate 1.

[0208] The array substrate 10 also includes a first connection portion L1. The first connection portion L1 penetrates the first insulating layer 3 of the array substrate 10. The two ends of the first connection portion L1 are respectively connected to the data sub-line 211 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5. That is, the data sub-line 211 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5 are connected via the first connection portion L1.

[0209] By providing the first connection portion L1 in the array substrate 10, and connecting the data sub-line 211 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5 through the first connection portion L1, on the one hand, since the first connection portion L1 only passes through the first insulating layer 3 of the array substrate 10, the length C1 of the first connection portion L1 is relatively small, thereby reducing the resistance of the first connection portion L1. When the data sub-line 211 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5 are connected through the first connection portion L1, the line resistance of the first data line 21 in the first conductive layer 2, the second data line 51 in the second conductive layer 5, and the first connection portion L1 as a whole can be reduced, thereby reducing the resistance-capacitance delay (RC Delay) effect of the first data line 21 in the first conductive layer 2, the second data line 51 in the second conductive layer 5, and the first connection portion L1 as a whole. When the data sub-line 211 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5 are connected through the first connecting portion L1, when the data line composed of the first data line 21 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5 is used to charge the sub-pixel 9 in the display panel 10, it is beneficial to improve the charging efficiency of the sub-pixel 9 in the display panel 100, reduce the probability of insufficient charging of the sub-pixel 9 in the display panel 100, and thereby improve the display effect of the display panel 100 including the above-mentioned array substrate 10.

[0210] It should be noted that the above-mentioned "length of the first connection portion L1" refers to the dimension of the first connection portion L1 along the third direction Z (i.e., the direction perpendicular to the substrate 1). The following description of the "length of the first connection portion L1" also follows this description and is not repeated here.

[0211] On the other hand, since the data sub-line 211 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5 are directly connected through the first connection portion L1, that is, the data sub-line 211 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5 do not need to be connected through a switching pattern, therefore, in the orthographic projection onto the substrate 1, the data sub-line 211 in the first conductive layer 2 does not need to be set up in a partial area so that there is no overlap with the second data line 51 in the second conductive layer 5, so as to connect the data sub-line 211 in the first conductive layer 2 and the switching pattern, which is beneficial to increase the overlapping area of ​​the data sub-line 211 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5 in the orthographic projection onto the substrate 1, and further reduce the total area of ​​the data sub-line 211 in the first conductive layer 2 and the second data line 51 in the orthographic projection onto the substrate 1, which is beneficial to further reduce the area ratio of the data sub-line 211 in the first conductive layer 2 and the second data line 51 in the orthographic projection onto the substrate 1.

[0212] In the case where the materials of the data sub-line 211 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5 include opaque metal (for example, copper, etc.), by further reducing the area ratio of the data sub-line 211 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5 in the orthographic projection onto the substrate 1, the area ratio of the opaque metal in the orthographic projection onto the substrate 1 can be further reduced, which is beneficial to further improve the aperture ratio of the array substrate 10 and further improve the display effect of the display panel 100 including the array substrate 10.

[0213] For example, please continue to refer to Figures 11A and 11B. In the orthographic projection onto the substrate 1, the first connection portion L1 in the array substrate 10 is located within the range of at least one of the data sub-line 211 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5.

[0214] For example, please continue to refer to Figures 11A and 11B. In the orthographic projection onto the substrate 1, the first connection portion L1 in the array substrate 10 is located within the range of the data sub-line 211 in the first conductive layer 2 and also within the range of the second data line 51 in the second conductive layer 5.

[0215] For another example, in an orthographic projection onto the substrate 1 , the first connection portion L1 in the array substrate 10 may be located within the range of the data sub-line 211 in the first conductive layer 2 .

[0216] For another example, in an orthographic projection onto the substrate 1 , the first connection portion L1 in the array substrate 10 may be located within the range of the second data line 51 in the second conductive layer 5 .

[0217] The connection between the pixel electrode 91 in the first electrode layer 6 of the array substrate 10 and the source contact portion s or the drain contact portion d in the second conductive layer 5 is described in detail below.

[0218] In some embodiments, as shown in FIG12 , which is a cross-sectional view of the array substrate 10 shown in FIG10A along section line HH or the array substrate 10 shown in FIG10B along section line II, the second electrode layer 8 of the array substrate 10 further includes a third transfer pattern a3. The source contact portion s or the drain contact portion d in the second conductive layer 5 of the array substrate 10 can be connected to the pixel electrode 91 in the first electrode layer 6 via the third transfer pattern a3 in the second electrode layer 8.

[0219] For example, referring to FIG. 12 , the array substrate 10 further includes a sixth connection portion L6. The sixth connection portion L6 penetrates the first insulating layer 3 and the second insulating layer 7 of the array substrate 10. The sixth connection portion L6 can connect the source contact portion s or the drain contact portion d in the second conductive layer 5 of the array substrate 10, the third transfer pattern a3 in the second electrode layer 8, and the pixel electrode 91 in the first electrode layer 6.

[0220] In some embodiments, as shown in FIG13 , FIG13 is a cross-sectional view of the array substrate 10 shown in FIG11A along section line JJ or the array substrate 10 shown in FIG11B along section line KK. The array substrate 10 further includes a second connection portion L2. The second connection portion L2 extends through the first insulating layer 3 within the array substrate 10. One end of the second connection portion L2 is connected to the source contact portion s or the drain contact portion d within the second conductive layer 5, and the other end of the second connection portion L2 is connected to the pixel electrode 91 within the first electrode layer 6. In other words, the source contact portion s or the drain contact portion d within the second conductive layer 5 can be connected to the pixel electrode 91 within the first electrode layer 6 via the second connection portion L2.

[0221] By setting a second connection portion L2 in the array substrate 10, and the source contact portion s or the drain contact portion d in the second conductive layer 5 is connected to the pixel electrode 91 in the first electrode layer 6 through the second connection portion L2, since the second connection portion L2 only passes through the first insulating layer 3 of the array substrate 10, the length C2 of the second connection portion L2 is small, and thus the resistance of the second connection portion L2 is small. When the source contact portion s or the drain contact portion d in the second conductive layer 5 is connected to the pixel electrode 91 in the first electrode layer 6 through the second connection portion L2, when the thin film transistor T1 in the sub-pixel 9 is turned on and the sub-pixel 9 in the display panel 10 is charged, it is beneficial to improve the charging efficiency of the sub-pixel 9 in the display panel 100 and reduce the probability of insufficient charging of the sub-pixel 9 in the display panel 100, thereby improving the display effect of the display panel 100 including the above-mentioned array substrate 10.

[0222] It should be noted that the above-mentioned "length of the second connection portion L2" refers to the dimension of the second connection portion L2 along the third direction Z (i.e., the direction perpendicular to the substrate 1). The following description of the "length of the second connection portion L2" also follows this description and is not repeated here.

[0223] The following describes in detail the thickness hs of the source contact portion s, the thickness hd of the drain contact portion d, the thickness h51 of the second data line 51 in the second conductive layer 5 of the array substrate 10, and the thickness h2 of the first conductive layer 2 of the array substrate 10.

[0224] In some embodiments, as shown in Figures 14 and 15, which are cross-sectional views of a local area of ​​the array substrate 10 according to some embodiments, the thickness hs of the source contact portion s in the second conductive layer 5 of the array substrate 10 may be 3000 angstroms to 8000 angstroms.

[0225] It should be noted that the aforementioned "thickness of the source contact portion s" refers to the dimension of the source contact portion s along the third direction Z (i.e., the direction perpendicular to the substrate 1). The following description of the "thickness of the source contact portion s" also follows this description and is not repeated here.

[0226] Exemplarily, the thickness of the source contact portion s in the second conductive layer 5 of the array substrate 10 (i.e., the dimension of the source contact portion s along the third direction Z) hs can be 3000 angstroms, 3500 angstroms, 4000 angstroms, 4500 angstroms, 5000 angstroms, 5500 angstroms, 6000 angstroms, 6500 angstroms, 7000 angstroms, 7500 angstroms or 8000 angstroms, etc.

[0227] Continuing to refer to FIG. 14 and FIG. 15 , the thickness hd of the drain contact portion d in the second conductive layer 5 of the array substrate 10 may be 3000 angstroms to 8000 angstroms.

[0228] It should be noted that the aforementioned "thickness of the drain contact portion d" refers to the dimension of the drain contact portion d along the third direction Z (i.e., the direction perpendicular to the substrate 1). The following description of the "thickness of the drain contact portion d" also follows this description and is not repeated here.

[0229] Exemplarily, the thickness of the drain contact portion d in the second conductive layer 5 of the array substrate 10 (i.e., the dimension of the drain contact portion d along the third direction Z) hd can be 3000 angstroms, 3500 angstroms, 4000 angstroms, 4500 angstroms, 5000 angstroms, 5500 angstroms, 6000 angstroms, 6500 angstroms, 7000 angstroms, 7500 angstroms or 8000 angstroms, etc.

[0230] Continuing to refer to FIG. 14 and FIG. 15 , the thickness h2 of the first conductive layer 2 of the array substrate 10 may be 3000 angstroms to 10000 angstroms.

[0231] It should be noted that the above-mentioned "thickness of the first conductive layer 2" refers to the dimension of the first conductive layer 2 along the third direction Z (i.e., the direction perpendicular to the substrate 1). The following description of the "thickness of the first conductive layer 2" also follows this description and is not repeated here.

[0232] Exemplarily, the thickness h2 of the first conductive layer 2 of the array substrate 10 (i.e., the dimension of the first conductive layer 2 along the third direction Z) can be 3000 angstroms, 3500 angstroms, 4000 angstroms, 4500 angstroms, 5000 angstroms, 5500 angstroms, 6000 angstroms, 6500 angstroms, 7000 angstroms, 7500 angstroms, 8000 angstroms, 8500 angstroms, 9000 angstroms, 9500 angstroms or 10000 angstroms, etc.

[0233] In some embodiments, referring again to FIG. 14 and FIG. 15 , the thickness hs of the source contact portion s (i.e., the dimension of the source contact portion s along the third direction Z) and the thickness hd of the drain contact portion d (i.e., the dimension of the drain contact portion d along the third direction Z) within the second conductive layer 5 of the array substrate 10 are both smaller than the thickness h2 of the first conductive layer 2 of the array substrate 10 (i.e., the dimension of the first conductive layer 2 along the third direction Z). That is, the thickness hs of the source contact portion s and the thickness hd of the drain contact portion d within the second conductive layer 5 of the array substrate 10 are smaller, while the thickness h2 of the first conductive layer 2 of the array substrate 10 is larger.

[0234] Continuing to refer to FIG. 14 and FIG. 15 , when the active layer pattern T11 of the thin film transistor T1 in the semiconductor layer 4 of the array substrate 10 contacts the source contact portion s and the drain contact portion d in the second conductive layer 5 , the thickness of the source contact portion s (i.e., the dimension of the source contact portion s along the third direction Z) hs and the thickness of the drain contact portion d (i.e., the dimension of the drain contact portion d along the third direction Z) hd in the second conductive layer 5 of the array substrate 10 are both smaller than the thickness of the first conductive layer 2 of the array substrate 10 (i.e., the dimension of the first conductive layer 2 along the third direction Z) h2. That is, the thickness of the source contact portion s (i.e., the dimension of the source contact portion s along the third direction Z) hs and the thickness of the drain contact portion d (i.e., the dimension of the drain contact portion d along the third direction Z) hd in the second conductive layer 5 of the array substrate 10 are relatively small. When the source contact portion s and the drain contact portion d located in the second conductive layer 5 are formed by an etching process, the etching time is relatively short, which can reduce or avoid the etching of the channel region of the active layer pattern T11 of the thin film transistor T1 in the semiconductor layer 4 during the etching process, thereby reducing the channel length of the active layer pattern T11 of the thin film transistor T1.

[0235] It is understood that the channel length of the active layer pattern T11 of the thin film transistor T1 is negatively correlated with the on-state current Ion of the thin film transistor T1, that is, the on-state current Ion of the thin film transistor T1 increases as the channel length of the active layer pattern T11 of the thin film transistor T1 decreases. Therefore, reducing the channel length of the active layer pattern T11 of the thin film transistor T1 in the sub-pixel 9 can increase the on-state current Ion of the thin film transistor T1. When the thin film transistor T1 in the sub-pixel 9 is turned on and charges the sub-pixel 9 in the display panel 100, it is beneficial to improve the charging efficiency of the sub-pixel 9 in the display panel 100, reduce the probability of insufficient charging of the sub-pixel 9 in the display panel 100, and thereby improve the display effect of the display panel 100 including the above-mentioned array substrate 10.

[0236] For example, please continue to refer to Figures 14 and 15. When the thickness of the source contact portion s (i.e., the dimension of the source contact portion s along the third direction Z) hs and the thickness of the drain contact portion d (i.e., the dimension of the drain contact portion d along the third direction Z) hd in the second conductive layer 5 of the array substrate 10 are both smaller than the thickness of the first conductive layer 2 of the array substrate 10 (i.e., the dimension of the first conductive layer 2 along the third direction Z) h2, the thickness of the source contact portion s (i.e., the dimension of the source contact portion s along the third direction Z) hs in the second conductive layer 5 of the array substrate 10 can be 3000 angstroms to 6000 angstroms.

[0237] For example, the thickness of the source contact portion s in the second conductive layer 5 of the array substrate 10 (i.e., the dimension of the source contact portion s along the third direction Z) hs can be 3000 angstroms, 3500 angstroms, 4000 angstroms, 4500 angstroms, 5000 angstroms, 5500 angstroms or 6000 angstroms, etc.

[0238] For example, please continue to refer to Figures 14 and 15. When the thickness of the source contact portion s (i.e., the dimension of the source contact portion s along the third direction Z) hs and the thickness of the drain contact portion d (i.e., the dimension of the drain contact portion d along the third direction Z) hd in the second conductive layer 5 of the array substrate 10 are both smaller than the thickness of the first conductive layer 2 of the array substrate 10 (i.e., the dimension of the first conductive layer 2 along the third direction Z) h2, the thickness of the drain contact portion d (i.e., the dimension of the drain contact portion d along the third direction Z) hd in the second conductive layer 5 of the array substrate 10 can be 3000 angstroms to 6000 angstroms.

[0239] For example, the thickness of the drain contact portion d in the second conductive layer 5 of the array substrate 10 (i.e., the dimension of the drain contact portion d along the third direction Z) hd can be 3000 angstroms, 3500 angstroms, 4000 angstroms, 4500 angstroms, 5000 angstroms, 5500 angstroms or 6000 angstroms, etc.

[0240] For example, please continue to refer to Figures 14 and 15. When the thickness of the source contact portion s (i.e., the dimension of the source contact portion s along the third direction Z) hs and the thickness of the drain contact portion d (i.e., the dimension of the drain contact portion d along the third direction Z) hd in the second conductive layer 5 of the array substrate 10 are both smaller than the thickness of the first conductive layer 2 of the array substrate 10 (i.e., the dimension of the first conductive layer 2 along the third direction Z) h2, the thickness of the first conductive layer 2 of the array substrate 10 (i.e., the dimension of the first conductive layer 2 along the third direction Z) h2 can be 6000 angstroms to 10000 angstroms.

[0241] For example, the thickness h2 of the first conductive layer 2 of the array substrate 10 (i.e., the dimension of the first conductive layer 2 along the third direction Z) can be 6000 angstroms, 6500 angstroms, 7000 angstroms, 7500 angstroms, 8000 angstroms, 8500 angstroms, 9000 angstroms, 9500 angstroms or 10000 angstroms, etc.

[0242] Continuing to refer to FIG. 14 and FIG. 15 , the thickness h5 of the second conductive layer 5 of the array substrate 10 can be uniformly set, or the thickness h5 of the second conductive layer 5 of the array substrate 10 can also be differentiated.

[0243] It should be noted that the above-mentioned "thickness of the second conductive layer 5" refers to the dimension of the second conductive layer 5 along the third direction Z (i.e., the direction perpendicular to the substrate 1). The following description of the "thickness of the second conductive layer 5" also follows this description and is not repeated here.

[0244] The following describes in detail an embodiment in which the thickness h5 of the second conductive layer 5 of the array substrate 10 (ie, the dimension of the second conductive layer 5 along the third direction Z) is uniformly set.

[0245] In some embodiments, please continue to refer to Figure 14, the thickness h51 of the second data line 51 in the second conductive layer 5 of the array substrate 10 is equal to the thickness hs of the source contact portion s in the second conductive layer 5 (that is, the dimension of the source contact portion s along the third direction Z).

[0246] It should be noted that the above “thickness of the second data line 51 ” refers to the dimension of the second data line 51 along the third direction Z (i.e., the direction perpendicular to the substrate 1 ). The following description of “thickness of the second data line 51 ” also follows this description and will not be repeated.

[0247] Since the second data line 51 and the source contact portion s are both located in the second conductive layer 5 of the array substrate 10, by making the thickness of the second data line 51 (i.e., the dimension of the second data line 51 along the third direction Z) h51 and the thickness of the source contact portion s (i.e., the dimension of the source contact portion s along the third direction Z) hs equal, when forming the second conductive layer 5 of the array substrate 10, the thickness of the second conductive layer 5 in the area corresponding to the second data line 51 in the second conductive layer 5 (i.e., the dimension of the second conductive layer 5 along the third direction Z) h5 and the thickness of the second conductive layer 5 in the area corresponding to the source contact portion s in the second conductive layer 5 (i.e., the dimension of the second conductive layer 5 along the third direction Z) h5 are uniform, which is beneficial to simplifying the preparation process of the second conductive layer 5, and further beneficial to simplifying the preparation process of the array substrate 10.

[0248] For example, referring to FIG. 14 , the thickness h51 of the second data line 51 in the second conductive layer 5 of the array substrate 10 (ie, the dimension of the second data line 51 along the third direction Z) may be 3000 angstroms to 8000 angstroms.

[0249] For example, the thickness h51 of the second data line 51 in the second conductive layer 5 of the array substrate 10 (i.e., the dimension of the second data line 51 along the third direction Z) can be 3000 angstroms, 3500 angstroms, 4000 angstroms, 4500 angstroms, 5000 angstroms, 5500 angstroms, 6000 angstroms, 6500 angstroms, 7000 angstroms, 7500 angstroms or 8000 angstroms, etc.

[0250] Continuing to refer to FIG14 , since the thickness of the source contact portion s in the second conductive layer 5 of the array substrate 10 (i.e., the dimension of the source contact portion s along the third direction Z) hs is less than the thickness of the first conductive layer 2 of the array substrate 10 (i.e., the dimension of the first conductive layer 2 along the third direction Z) h2, the thickness of the source contact portion s in the second conductive layer 5 of the array substrate 10 (i.e., the dimension of the source contact portion s along the third direction Z) hs is 3000 angstroms to 6000 angstroms, and the thickness of the second data line 51 in the second conductive layer 5 of the array substrate 10 (i.e., the dimension of the second data line 51 along the third direction Z) is 1000 angstroms to 1000 angstroms. Therefore, when the thickness of the source contact portion s in the second conductive layer 5 of the array substrate 10 (that is, the dimension of the source contact portion s along the third direction Z) hs is smaller than the thickness of the first conductive layer 2 of the array substrate 10 (that is, the dimension of the first conductive layer 2 along the third direction Z) h2, the thickness of the second data line 51 in the second conductive layer 5 of the array substrate 10 (that is, the dimension of the second data line 51 along the third direction Z) h51 is also 3000 angstroms to 6000 angstroms.

[0251] For example, the thickness h51 of the second data line 51 in the second conductive layer 5 of the array substrate 10 (i.e., the dimension of the second data line 51 along the third direction Z) can be 3000 angstroms, 3500 angstroms, 4000 angstroms, 4500 angstroms, 5000 angstroms, 5500 angstroms or 6000 angstroms, etc.

[0252] In some embodiments, please continue to refer to Figure 14, the thickness of the second data line 51 in the second conductive layer 5 of the array substrate 10 (i.e., the dimension of the second data line 51 along the third direction Z) h51 and the thickness of the drain contact portion d in the second conductive layer 5 (i.e., the dimension of the drain contact portion d along the third direction Z) hd are equal.

[0253] Since the second data line 51 and the drain contact portion d are both located in the second conductive layer 5 of the array substrate 10, by making the thickness of the second data line 51 (i.e., the dimension of the second data line 51 along the third direction Z) h51 and the thickness of the drain contact portion d (i.e., the dimension of the drain contact portion d along the third direction Z) hd equal, when forming the second conductive layer 5 of the array substrate 10, the thickness of the second conductive layer 5 in the area corresponding to the second data line 51 in the second conductive layer 5 (i.e., the dimension of the second conductive layer 5 along the third direction Z) h5 and the thickness of the second conductive layer 5 in the area corresponding to the drain contact portion d in the second conductive layer 5 (i.e., the dimension of the second conductive layer 5 along the third direction Z) h5 are uniform, which is beneficial to simplifying the preparation process of the second conductive layer 5, and further beneficial to simplifying the preparation process of the array substrate 10.

[0254] An embodiment in which the thickness h5 of the second conductive layer 5 of the array substrate 10 (ie, the dimension of the second conductive layer 5 along the third direction Z) is set differently is described in detail below.

[0255] 15 , in some embodiments, the second data line 51 in the second conductive layer 5 of the array substrate 10 includes a first portion 51 a. The first portion 51 a of the second data line 51 and the data sub-line 211 in the first conductive layer 2 are arranged relative to each other in a third direction Z (i.e., a direction perpendicular to the substrate 1).

[0256] The thickness h51a of the first portion 51a of the second data line 51 in the second conductive layer 5 is greater than the thickness hs of the source contact portion s (i.e., the dimension of the source contact portion s along the third direction Z). That is, the thickness h51a of the first portion 51a of the second data line 51 in the second conductive layer 5 is greater, and the thickness hs of the source contact portion s in the second conductive layer 5 (i.e., the dimension of the source contact portion s along the third direction Z) is smaller.

[0257] It should be noted that the aforementioned "thickness of the first portion 51a of the second data line 51" refers to the dimension of the first portion 51a of the second data line 51 along the third direction Z (i.e., a direction perpendicular to the substrate 1). The following description of the "thickness of the first portion 51a of the second data line 51" also follows this description and is not further elaborated.

[0258] By making the thickness of the source contact portion s in the second conductive layer 5 (i.e., the dimension of the source contact portion s along the third direction Z) hs smaller, it is beneficial to reduce the channel length of the active layer pattern T11 of the thin film transistor T1 in the sub-pixel 9, thereby increasing the on-state current Ion of the thin film transistor T1. When the thin film transistor T1 in the sub-pixel 9 is turned on to charge the sub-pixel 9 in the display panel 100, it is beneficial to improve the charging efficiency of the sub-pixel 9 in the display panel 100, reduce the probability of insufficient charging of the sub-pixel 9 in the display panel 100, and thereby improve the display effect of the display panel 100 including the above-mentioned array substrate 10.

[0259] On this basis, by making the thickness of the first part 51a of the second data line 51 in the second conductive layer 5 (that is, the dimension of the first part 51a of the second data line 51 along the third direction Z) h51a larger, the line resistance of the second data line 51 in the second conductive layer 5 can be reduced, and thus the resistance-capacitance delay (RC Delay) effect of the second data line 51 in the second conductive layer 5 can be weakened. When the second data line 51 in the second conductive layer 5 is used to charge the sub-pixel 9 in the display panel 100, it is beneficial to further improve the charging efficiency of the sub-pixel 9 in the display panel 100, further reduce the probability of insufficient charging of the sub-pixel 9 in the display panel 100, and further improve the display effect of the display panel 100 including the above-mentioned array substrate 10.

[0260] For example, referring to FIG. 15 , the thickness h51a of the first portion 51a of the second data line 51 in the second conductive layer 5 (ie, the dimension of the first portion 51a of the second data line 51 along the third direction Z) may be 6000 angstroms to 15000 angstroms.

[0261] For example, the thickness h51a of the first portion 51a of the second data line 51 in the second conductive layer 5 (i.e., the dimension of the first portion 51a of the second data line 51 along the third direction Z) can be 6000 angstroms, 6500 angstroms, 7000 angstroms, 7500 angstroms, 8000 angstroms, 8500 angstroms, 9000 angstroms, 9500 angstroms, 10000 angstroms, 10500 angstroms, 11000 angstroms, 11500 angstroms, 12000 angstroms, 12500 angstroms, 13000 angstroms, 13500 angstroms, 14000 angstroms, 14500 angstroms or 15000 angstroms, etc.

[0262] For example, please continue to refer to Figure 15. Along the third direction Z (i.e., the direction perpendicular to the substrate 1), the first part 51a of the second data line 51 in the second conductive layer 5 may include at least two film layer structures, that is, the first part 51a of the second data line 51 can be formed by at least two deposition processes.

[0263] In some embodiments, referring to FIG. 15 , the second data line 51 within the second conductive layer 5 of the array substrate 10 includes a second portion 51b. In an orthographic projection onto the substrate 1, the second portion 51b of the second data line 51 intersects the gate line 22 within the first conductive layer 2 and does not overlap with the data sub-line 211 within the first conductive layer 2. The thickness h51a of the first portion 51a of the second data line 51 (i.e., the dimension of the first portion 51a of the second data line 51 along the third direction Z) is greater than the thickness h51b of the second portion 51b of the second data line 51. Specifically, the thickness h51a of the first portion 51a of the second data line 51 (i.e., the dimension of the first portion 51a of the second data line 51 along the third direction Z) is greater, while the thickness h51b of the second portion 51b of the second data line 51 is smaller.

[0264] It should be noted that the aforementioned "thickness of the second portion 51b of the second data line 51" refers to the dimension of the second portion 51b of the second data line 51 along the third direction Z (i.e., a direction perpendicular to the substrate 1). The following description of the "thickness of the second portion 51b of the second data line 51" also follows this description and is not further elaborated.

[0265] Because the second portion 51b of the second data line 51 intersects the gate line 22 in the first conductive layer 2 in an orthographic projection onto the substrate 1, a sloped region exists within the second portion 51b of the second data line 51. By reducing the thickness h51b of the second portion 51b of the second data line 51 (i.e., the dimension of the second portion 51b of the second data line 51 along the third direction Z), the etching time is shortened when the second data line 51 is formed through an etching process. This reduces the probability of a short circuit in the sloped region within the second portion 51b of the second data line 51, thereby improving the yield of the array substrate 10.

[0266] For example, referring to FIG. 15 , the thickness h51b of the second portion 51b of the second data line 51 in the second conductive layer 5 (ie, the dimension of the second portion 51b of the second data line 51 along the third direction Z) may be 3000 angstroms to 8000 angstroms.

[0267] For example, the thickness h51b of the second portion 51b of the second data line 51 in the second conductive layer 5 (i.e., the dimension of the second portion 51b of the second data line 51 along the third direction Z) can be 3000 angstroms, 3500 angstroms, 4000 angstroms, 4500 angstroms, 5000 angstroms, 5500 angstroms, 6000 angstroms, 6500 angstroms, 7000 angstroms, 7500 angstroms or 8000 angstroms, etc.

[0268] In some embodiments, please continue to refer to Figure 15, the thickness of the second portion 51b of the second data line 51 (i.e., the dimension of the second portion 51b of the second data line 51 along the third direction Z) h51b and the thickness of the source contact portion s (i.e., the dimension of the source contact portion s along the third direction Z) hs can be equal.

[0269] The following describes in detail how the thickness h3 of the first insulating layer 3 of the array substrate 10 is set.

[0270] In some embodiments, as shown in FIG16 , FIG16 is a cross-sectional view of a partial region of the array substrate 10 according to some embodiments. The first insulating layer 3 of the array substrate 10 includes a first portion 3a and a second portion 3b. The first portion 3a of the first insulating layer 3 is located between the gate pattern T12 of the thin-film transistor T1 in the first conductive layer 2 and the active layer pattern T11 of the thin-film transistor T1 in the semiconductor layer 4. The second portion 3b of the first insulating layer 3 is located between the pixel electrode 91 in the first electrode layer 6 and the common electrode 92 in the second electrode layer 8. The thickness h3a of the first portion 3a of the first insulating layer 3 is less than the thickness h3b of the second portion 3b of the first insulating layer 3. That is, the thickness h3a of the first portion 3a of the first insulating layer 3 is smaller, while the thickness h3b of the second portion 3b of the first insulating layer 3 is larger.

[0271] It should be noted that the aforementioned "thickness of the first portion 3a of the first insulating layer 3" refers to the dimension of the first portion 3a of the first insulating layer 3 along the third direction Z (i.e., perpendicular to the substrate 1). The aforementioned "thickness of the second portion 3b of the first insulating layer 3" refers to the dimension of the second portion 3b of the first insulating layer 3 along the third direction Z (i.e., perpendicular to the substrate 1). The following descriptions of the "thickness of the first portion 3a of the first insulating layer 3" and the "thickness of the second portion 3b of the first insulating layer 3" also follow this description and are not further elaborated.

[0272] It is understood that, when the display panel 100 is a thin film transistor-liquid crystal display (TFT-LCD) panel, the on-state current Ion of the thin film transistor T1 in the display panel 100 is positively correlated with the capacitance of the first portion 3a of the first insulating layer 3 between the active layer pattern T11 and the gate pattern T12 of the thin film transistor T1. That is, the on-state current Ion of the thin film transistor T1 in the display panel 100 increases as the capacitance of the first portion 3a of the first insulating layer 3 between the active layer pattern T11 and the gate pattern T12 of the thin film transistor T1 increases.

[0273] The capacitance of the first portion 3a of the first insulating layer 3 between the active layer pattern T11 and the gate pattern T12 of the thin film transistor T1 is negatively correlated with the thickness h3a of the first portion 3a of the first insulating layer 3 (i.e., the dimension h3a of the first portion 3a of the first insulating layer 3 along the third direction Z), that is, the capacitance of the first portion 3a of the first insulating layer 3 between the active layer pattern T11 and the gate pattern T12 of the thin film transistor T1 increases as the thickness h3a of the first portion 3a of the first insulating layer 3 (i.e., the dimension h3a of the first portion 3a of the first insulating layer 3 along the third direction Z) decreases.

[0274] By making the thickness h3a of the first part 3a of the first insulating layer 3 between the gate pattern T12 of the thin film transistor T1 in the first conductive layer 2 and the active layer pattern T11 of the thin film transistor T1 in the semiconductor layer 4 smaller (that is, the dimension of the first part 3a of the first insulating layer 3 along the third direction Z), the capacitance of the first part 3a of the first insulating layer 3 between the active layer pattern T11 and the gate pattern T12 of the thin film transistor T1 can be made larger, thereby making the on-state current Ion of the thin film transistor T1 larger. When the thin film transistor T1 in the sub-pixel 9 is turned on and charges the sub-pixel 9 in the display panel 100, it is beneficial to improve the charging efficiency of the sub-pixel 9 in the display panel 100 and reduce the probability of insufficient charging of the sub-pixel 9 in the display panel 100, thereby improving the display effect of the display panel 100 including the above-mentioned array substrate 10.

[0275] It can be understood that since the second part 3b of the first insulating layer 3 in the array substrate 10 is located between the pixel electrode 91 in the first electrode layer 6 and the common electrode 92 in the second electrode layer 8, the pixel capacitance jointly formed by the pixel electrode 91 and the common electrode 92 in the sub-pixel 9 is negatively correlated with the thickness h3b of the second part 3b of the first insulating layer 3 (that is, the size of the second part 3b of the first insulating layer 3 along the third direction Z), that is, the pixel capacitance jointly formed by the pixel electrode 91 and the common electrode 92 in the sub-pixel 9 of the display panel 100 decreases as the thickness h3b of the second part 3b of the first insulating layer 3 (that is, the size of the second part 3b of the first insulating layer 3 along the third direction Z) increases.

[0276] By making the thickness h3b of the second part 3b of the first insulating layer 3 between the pixel electrode 91 in the first electrode layer 6 and the common electrode 92 in the second electrode layer 8 larger (that is, the dimension of the second part 3b of the first insulating layer 3 along the third direction Z), the pixel capacitance formed by the pixel electrode 91 and the common electrode 92 in the sub-pixel 9 of the display panel 100 can be made smaller. When charging the sub-pixel 9 in the display panel 100, it is beneficial to shorten the charging time of the sub-pixel 9 in the display panel 100, reduce the probability of insufficient charging of the sub-pixel 9 in the display panel 100, and thereby improve the display effect of the display panel 100 including the above-mentioned array substrate 10.

[0277] For example, referring to FIG. 16 , the thickness h3a of the first portion 3a of the first insulating layer 3 (ie, the dimension of the first portion 3a of the first insulating layer 3 along the third direction Z) may be 2500 angstroms to 4000 angstroms.

[0278] For example, the thickness h3a of the first portion 3a of the first insulating layer 3 (i.e., the dimension of the first portion 3a of the first insulating layer 3 along the third direction Z) may be 2500 angstroms, 2600 angstroms, 2700 angstroms, 2800 angstroms, 2900 angstroms, 3000 angstroms, 3100 angstroms, 3200 angstroms, 3300 angstroms, 3400 angstroms, 3500 angstroms, 3600 angstroms, 3700 angstroms, 3800 angstroms, 3900 angstroms, or 4000 angstroms, etc.

[0279] For example, referring to FIG. 16 , the thickness h3b of the second portion 3b of the first insulating layer 3 (ie, the dimension of the second portion 3b of the first insulating layer 3 along the third direction Z) may be 4000 angstroms to 5500 angstroms.

[0280] For example, the thickness of the second portion 3b of the first insulating layer 3 (i.e., the dimension of the second portion 3b of the first insulating layer 3 along the third direction Z) h3b can be 4000 angstroms, 4100 angstroms, 4200 angstroms, 4300 angstroms, 4400 angstroms, 4500 angstroms, 4600 angstroms, 4700 angstroms, 4800 angstroms, 4900 angstroms, 5000 angstroms, 5100 angstroms, 5200 angstroms, 5300 angstroms, 5400 angstroms or 5500 angstroms, etc.

[0281] In some embodiments, as shown in FIG17 and in conjunction with FIG16 , FIG17 is a cross-sectional view of a partial region of an array substrate 10 according to some embodiments. The first insulating layer 3 of the array substrate 10 further includes a third portion 3c. The third portion 3c of the first insulating layer 3 is located between the data sub-line 211 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5.

[0282] The thickness h3c of the third portion 3c of the first insulating layer 3 is greater than the thickness h3a of the first portion 3a of the first insulating layer 3 (i.e., the dimension of the first portion 3a of the first insulating layer 3 along the third direction Z). That is, the thickness h3c of the third portion 3c of the first insulating layer 3 is greater, and the thickness h3a of the first portion 3a of the first insulating layer 3 (i.e., the dimension of the first portion 3a of the first insulating layer 3 along the third direction Z) is smaller.

[0283] It should be noted that the aforementioned "thickness of the third portion 3 c of the first insulating layer 3" refers to the dimension of the third portion 3 c of the first insulating layer 3 along the third direction Z (i.e., a direction perpendicular to the substrate 1). The following description of the "thickness of the third portion 3 c of the first insulating layer 3" also follows this description and is not further elaborated.

[0284] It can be understood that the parasitic capacitance between the data sub-line 211 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5 is negatively correlated with the thickness h3c of the third portion 3c of the first insulating layer 3 located between the data sub-line 211 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5 (i.e., the dimension of the third portion 3c of the first insulating layer 3 along the third direction Z). In other words, the parasitic capacitance between the data sub-line 211 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5 decreases as the thickness h3c of the third portion 3c of the first insulating layer 3 (i.e., the dimension of the third portion 3c of the first insulating layer 3 along the third direction Z) increases.

[0285] By making the thickness h3c of the third portion 3c of the first insulating layer 3 located between the data sub-line 211 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5 larger (that is, the dimension of the third portion 3c of the first insulating layer 3 along the third direction Z), on the one hand, the parasitic capacitance between the data sub-line 211 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5 can be reduced, and then the resistance-capacitance delay (RC Delay) effect of the data line formed by the first data line 21 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5 can be further weakened, which is beneficial to improving the charging efficiency of the sub-pixel 9 in the display panel 100, reducing the probability of insufficient charging of the sub-pixel 9 in the display panel 100, and thereby improving the display effect of the display panel 100 including the above-mentioned array substrate 10.

[0286] On the other hand, since the thickness h3c of the third portion 3c of the first insulating layer 3 located between the data sub-line 211 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5 is relatively large (that is, the dimension of the third portion 3c of the first insulating layer 3 along the third direction Z) is relatively large, it is beneficial to improve the insulation performance of the third portion 3c of the first insulating layer 3, and can avoid electrical breakdown of the third portion 3c of the first insulating layer 3, thereby reducing the probability of electrical breakdown of the first insulating layer 3, thereby reducing the probability of short circuit between the gate line 22 in the first conductive layer 2 and the second data line 51 in the second conductive layer 5, that is, reducing the probability of data gate short (DGS) defect in the array substrate 10, which is beneficial to improving the yield of the array substrate 10.

[0287] For example, referring to FIG. 17 , the thickness h3c of the third portion 3c of the first insulating layer 3 (ie, the dimension of the third portion 3c of the first insulating layer 3 along the third direction Z) may be 4000 angstroms to 5500 angstroms.

[0288] For example, the thickness of the third portion 3c of the first insulating layer 3 (i.e., the dimension of the third portion 3c of the first insulating layer 3 along the third direction Z) h3c can be 4000 angstroms, 4100 angstroms, 4200 angstroms, 4300 angstroms, 4400 angstroms, 4500 angstroms, 4600 angstroms, 4700 angstroms, 4800 angstroms, 4900 angstroms, 5000 angstroms, 5100 angstroms, 5200 angstroms, 5300 angstroms, 5400 angstroms or 5500 angstroms, etc.

[0289] In some embodiments, please continue to refer to FIG. 16 , the first insulating layer 3 of the array substrate 10 includes a first sub-layer 31 and a second sub-layer 32 that are stacked.

[0290] The overlapping region M between the gate pattern T12 of the thin film transistor T1 in the first conductive layer 2 and the active layer pattern T11 of the thin film transistor T1 in the semiconductor layer 4 in the third direction Z (i.e., a direction perpendicular to the substrate 1) does not overlap with the first sub-layer 31 in the first insulating layer 3. In other words, the first sub-layer 31 in the first insulating layer 3 is not located between the gate pattern T12 of the thin film transistor T1 in the first conductive layer 2 and the active layer pattern T11 of the thin film transistor T1 in the semiconductor layer 4.

[0291] A portion of the second sub-layer 32 in the first insulating layer 3 is located between the gate pattern T12 of the thin film transistor T1 in the first conductive layer 2 and the active layer pattern T11 of the thin film transistor T1 in the semiconductor layer 4. That is, a portion of the second sub-layer 32 in the first insulating layer 3 is disposed between the gate pattern T12 of the thin film transistor T1 in the first conductive layer 2 and the active layer pattern T11 of the thin film transistor T1 in the semiconductor layer 4.

[0292] For example, referring to FIG. 16 , the first sub-layer 31 in the first insulating layer 3 may be closer to the substrate 1 than the second sub-layer 32 in the first insulating layer 3 .

[0293] For example, the material of the second sub-layer 32 in the first insulating layer 3 may include amorphous silicon.

[0294] The following describes in detail how the thickness h7 of the second insulating layer 7 of the array substrate 10 is set.

[0295] In some embodiments, referring to FIG. 16 , the thickness h7 of the second insulating layer 7 of the array substrate 10 is greater than or equal to 6000 angstroms and less than or equal to 9000 angstroms.

[0296] It should be noted that the above-mentioned "thickness of the second insulating layer 7" refers to the dimension of the second insulating layer 7 along the third direction Z (i.e., the direction perpendicular to the substrate 1). The following description of the "thickness of the second insulating layer 7" also follows this description and is not repeated here.

[0297] 16 , the first portion 3a of the first insulating layer 3 is located between the gate pattern T12 of the thin film transistor T1 in the first conductive layer 2 and the active layer pattern T11 of the thin film transistor T1 in the semiconductor layer 4, the second portion 3b of the first insulating layer 3 is located between the pixel electrode 91 in the first electrode layer 6 and the common electrode 92 in the second electrode layer 8, and the thickness h3a of the first portion 3a of the first insulating layer 3 is less than the thickness h3b of the second portion 3b of the first insulating layer 3, that is, the thickness h3a of the first portion 3a of the first insulating layer 3 is small and the thickness h3b of the second portion 3b of the first insulating layer 3 is large. Since the second portion 3b of the first insulating layer 3 and the partial area of ​​the second insulating layer 7 in the array substrate 10 are both located in the first electrode layer 6 Between the pixel electrode 91 in the sub-pixel 9 and the common electrode 92 in the second electrode layer 8, therefore, the sum of the thickness of the second portion 3b of the first insulating layer 3 (i.e., the size of the second portion 3b of the first insulating layer 3 along the third direction Z) h3b and the thickness of the second insulating layer 7 (i.e., the size of the second insulating layer 7 along the third direction Z) h7 is negatively correlated with the pixel capacitance jointly formed by the pixel electrode 91 and the common electrode 92 in the sub-pixel 9, that is, the pixel capacitance jointly formed by the pixel electrode 91 and the common electrode 92 in the sub-pixel 9 of the display panel 100 decreases with the increase of the thickness of the second portion 3b of the first insulating layer 3 (i.e., the size of the second portion 3b of the first insulating layer 3 along the third direction Z) h3b and the thickness of the second insulating layer 7 (i.e., the size of the second insulating layer 7 along the third direction Z) h7.

[0298] While ensuring that the pixel capacitance formed by the pixel electrode 91 and the common electrode 92 in the sub-pixel 9 of the display panel 100 is small, when charging the sub-pixel 9 in the display panel 100, the charging time of the sub-pixel 9 in the display panel 100 is short, and the probability of insufficient charging of the sub-pixel 9 in the display panel 100 is low, when the thickness h3b of the second part 3b of the first insulating layer 3 is large, the thickness of the second insulating layer 7 (that is, the dimension of the second insulating layer 7 along the third direction Z) h7 can be appropriately reduced.

[0299] By reducing the thickness h7 of the second insulating layer 7 (ie, the dimension of the second insulating layer 7 along the third direction Z), it is beneficial to improve the yield of the second insulating layer 7 and reduce the difficulty of the process of preparing the second insulating layer 7.

[0300] On the other hand, please continue to refer to Figure 16, and in combination with Figure 12, when the source contact portion s or the drain contact portion d in the second conductive layer 5 of the array substrate 10, the third transfer pattern a3 in the second electrode layer 8 and the pixel electrode 91 in the first electrode layer 6 are connected through the sixth connection portion L6, and the sixth connection portion L6 passes through the first insulating layer 3 and the second insulating layer 7 of the array substrate 10, by reducing the thickness of the second insulating layer 7 (that is, the dimension of the second insulating layer 7 along the third direction Z) h7, when forming the sixth connection portion L6, the etching path can be shortened and the difficulty of the etching process can be reduced, which is beneficial to improving the connection reliability when the source contact portion s or the drain contact portion d in the second conductive layer 5 of the array substrate 10, the third transfer pattern a3 in the second electrode layer 8 and the pixel electrode 91 in the first electrode layer 6 are connected through the sixth connection portion L6, and the resistance of the sixth connection portion L6 can also be reduced.

[0301] 16 , the thickness h7 of the second insulating layer 7 in the array substrate 10 (ie, the dimension of the second insulating layer 7 along the third direction Z) may be 6000 angstroms, 6500 angstroms, 7000 angstroms, 7500 angstroms, 8000 angstroms, 8500 angstroms, or 9000 angstroms.

[0302] Although some embodiments of the present application are described herein with reference to Figures 7A to 17 regarding the arrangement and connection of the second data line 51 in the second conductive layer 5 and the multiple data sub-lines 211 included in the first data line 21 in the first conductive layer 2, the connection between the pixel electrode 91 in the first electrode layer 6 and the source contact s or the drain contact d in the second conductive layer 5, the thickness hs of the source contact s and the thickness hd of the drain contact d in the second conductive layer 5, the arrangement of the thickness h51 of the second data line 51 and the thickness h2 of the first conductive layer 2 of the array substrate 10, the arrangement of the thickness h3 of the first insulating layer 3, and the arrangement of the thickness h7 of the second insulating layer 7, the above description of some embodiments of the present application with reference to Figures 7A to 17 is exemplary and not exhaustive, and is therefore not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the above embodiments.

[0303] Specifically, the arrangement and connection manner of the second data line 51 in the second conductive layer 5 and the multiple data sub-lines 211 included in the first data line 21 in the first conductive layer 2 in the embodiments shown in Figures 7A to 17, the connection manner of the pixel electrode 91 in the first electrode layer 6 and the source contact portion s or the drain contact portion d in the second conductive layer 5, the thickness hs of the source contact portion s in the second conductive layer 5, the thickness hd of the drain contact portion d, the arrangement manner of the thickness h51 of the second data line 51 and the thickness h2 of the first conductive layer 2 of the array substrate 10, the arrangement manner of the thickness h3 of the first insulating layer 3, and the arrangement manner of the thickness h7 of the second insulating layer 7, etc. can all be arbitrarily combined, and any combination of the above embodiments is within the protection scope of this application.

[0304] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. An array substrate, comprising: A substrate; A first conductive layer located on the substrate; the first conductive layer includes gate lines and first data lines, the gate lines extending in a first direction; the first data lines include a plurality of data sub-lines, the data sub-lines extending in a second direction, and the plurality of data sub-lines being spaced apart from each other in the second direction, the first direction and the second direction intersecting; the gate lines pass between two adjacent ones of the data sub-lines and are spaced apart from two adjacent ones of the data sub-lines; A second conductive layer located on a side of the first conductive layer away from the substrate; the second conductive layer includes second data lines, the second data lines extending in the second direction; the second data lines and the plurality of data sub-lines included in the first data lines are connected in parallel.

2. The array substrate according to claim 1, wherein, The array substrate includes a plurality of thin film transistors; The array substrate further includes a semiconductor layer located between the first conductive layer and the second conductive layer; the semiconductor layer includes active layer patterns of the thin film transistors; The second conductive layer further includes a source contact portion and a drain contact portion, the source contact portion and the drain contact portion being respectively connected to the active layer patterns; The thickness of the source contact portion and the thickness of the drain contact portion are both smaller than the thickness of the first conductive layer.

3. The array substrate according to claim 2, wherein, The thickness of the second data line is equal to the thickness of the source contact portion.

4. The array substrate according to claim 2, wherein, The second data line includes a first portion, and the first portion of the second data line and the data sub-line are disposed opposite to each other in a direction perpendicular to the substrate; The thickness of the first portion of the second data line is greater than the thickness of the source contact portion.

5. The array substrate according to claim 4, wherein, The second data line further includes a second portion, in a positive projection onto the substrate, the second portion of the second data line intersects with the gate line and does not overlap with the data sub-line; The thickness of the first portion of the second data line is greater than the thickness of the second portion of the second data line.

6. The array substrate according to claim 5, wherein, The thickness of the second portion of the second data line is equal to the thickness of the source contact portion.

7. The array substrate according to any one of claims 1 to 6, wherein In a positive projection onto the substrate, at least a part of the plurality of data sub-lines included in the first data line and the second data line overlap.

8. The array substrate according to claim 7, the array substrate further comprising: A first insulating layer located between the first conductive layer and the second conductive layer; A first connection portion passing through the first insulating layer; Two ends of the first connection portion are respectively connected to the data sub-line and the second data line.

9. The array substrate according to claim 8, wherein, In a positive projection onto the substrate, the first connection portion is located within a range of at least one of the data sub-line and the second data line.

10. The array substrate according to claim 8 or 9, the array substrate further comprising: A first electrode layer located on a side of the second conductive layer close to the substrate; the first electrode layer includes pixel electrodes; A second connection portion, the second connection portion passing through the first insulating layer; The second conductive layer further includes a source contact portion and a drain contact portion, one end of the second connection portion is connected to the source contact portion or the drain contact portion, and the other end of the second connection portion is connected to the pixel electrode.

11. The array substrate according to claim 7, the array substrate further comprising: A first electrode layer located on a side of the second conductive layer close to the substrate; The first electrode layer includes a first transfer pattern, and the first transfer pattern is connected to the data sub-line; A second electrode layer located on a side of the second conductive layer away from the substrate; the second electrode layer includes a second transfer pattern; A third connection portion, the second transfer pattern, the second data line, and the first transfer pattern are all connected to the third connection portion.

12. The array substrate according to claim 11, wherein, The first transfer pattern and the data sub-line overlap and are in contact.

13. The array substrate according to claim 11 or 12, wherein, The first electrode layer further includes a pixel electrode; The second electrode layer further includes a third transfer pattern; The second conductive layer further includes a source contact portion and a drain contact portion, and the source contact portion or the drain contact portion is connected to the pixel electrode through the third transfer pattern.

14. The array substrate according to any one of claims 1 to 7, the array substrate further comprising: A second electrode layer located on a side of the second conductive layer away from the substrate; The second electrode layer includes a fourth transfer pattern; A fourth connection portion and a fifth connection portion; The data sub-line is connected to the fourth transfer pattern through the fourth connection portion, and the second data line is connected to the fourth transfer pattern through the fifth connection portion.

15. The array substrate according to any one of claims 1 to 14, wherein, At least one gate line is provided between two adjacent data sub-lines in the second direction.

16. The array substrate according to any one of claims 1 to 15, the array substrate includes a plurality of thin film transistors; the first conductive layer includes a gate pattern of the thin film transistor; The array substrate further comprises: A first electrode layer located on a side of the first conductive layer close to the substrate; the first electrode layer includes a pixel electrode; A second electrode layer located on a side of the second conductive layer away from the substrate; the second electrode layer includes a common electrode; the pixel electrode and the common electrode are disposed opposite to each other in a direction perpendicular to the substrate; A semiconductor layer located between the first conductive layer and the second conductive layer; the semiconductor layer includes an active layer pattern of the thin film transistor; A first insulating layer located between the first conductive layer and the semiconductor layer; the first insulating layer includes a first part and a second part, the first part of the first insulating layer is located between the gate pattern and the active layer pattern, and the second part of the first insulating layer is located between the pixel electrode and the common electrode; Wherein, the thickness of the first part of the first insulating layer is less than the thickness of the second part of the first insulating layer.

17. The array substrate according to claim 16, wherein, The first insulating layer further includes a third part located between the data sub-line and the second data line; The thickness of the third part of the first insulating layer is greater than the thickness of the first part of the first insulating layer.

18. The array substrate according to claim 16 or 17, wherein, The first insulating layer includes a first sub-layer and a second sub-layer stacked; An overlapping area of the gate pattern and the active layer pattern in a direction perpendicular to the substrate does not overlap with the first sub-layer; A part of the second sub-layer is located between the gate pattern and the active layer pattern.

19. The array substrate according to claim 18, wherein, The first sub-layer is closer to the substrate than the second sub-layer.

20. The array substrate according to any one of claims 16 to 19, further comprising a second insulating layer on a side of the second conductive layer away from the substrate; The thickness of the second insulating layer is greater than or equal to 6000 angstroms and less than or equal to 9000 angstroms.

21. A display panel, comprising: The array substrate according to any one of claims 1 to 20; A counter substrate, which is opposite to and spaced apart from the array substrate; A liquid crystal layer disposed between the array substrate and the counter substrate.

22. A display device, comprising: The display panel according to claim 21; A driving chip electrically connected to the display panel.

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