Chip preparation method and chip

Abstract

A chip preparation method, comprising the steps of: bonding a cover plate layer (100) to a device layer (200); etching the device layer (200) to form an elastic structure (211) on the device layer (200); etching the cover plate layer (100) to remove part of a first insulating layer (120), such that a cover plate wafer (110) of the cover plate layer (100) is partially exposed; and bonding the side of the device layer (200) facing away from the cover plate layer (100) to a substrate layer (300), wherein the device layer (200) can be grounded by means of the substrate layer (300), and the elastic structure (211) can abut against the exposed cover plate wafer (110) under the action of the substrate layer (300). There is no need to perform additional wire bonding on the cover plate wafer (110), thereby avoiding increase of the packaging thickness and generating no additional stress problem, ensuring the performance of the chip. Further provided is a chip.

Description

Chip preparation method and chip Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a chip preparation method and a chip. Background Art

[0002] MEMS (Micro-Electro Mechanical System) technology integrates sensor structures and corresponding electronic circuits within a small housing. Compared to sensors manufactured using traditional processing methods, MEMS sensors, fabricated using integrated circuit and micromachining techniques, offer advantages such as small size, light weight, low cost, low power consumption, high reliability, easy integration, strong overload resistance, and mass production. These advantages hold broad potential for dual-use applications in both military and civilian applications.

[0003] The cover plate in a MEMS sensor not only serves as an airtight packaging cavity but also shields against external electromagnetic interference, so it needs to be grounded. The currently common cover plate grounding method is to connect the cover plate to the ground electrode via additional top / external bonding wires after packaging. However, this method increases the package thickness due to the high pull-up arc portion of the bonding wire, and may also generate additional stress during the process, ultimately affecting the performance of the MEMS sensor.

[0004] Summary of the Invention

[0005] Based on this, it is necessary to provide a chip preparation method and chip that can achieve cover grounding without increasing the package thickness, generating additional stress, and avoiding affecting the performance of the sensor in order to address the problem that the cover in the existing MEMS sensor is grounded by wire bonding, which leads to an increase in package thickness and generates additional stress.

[0006] A chip preparation method comprises the steps of:

[0007] S110, providing a cover layer, a device layer, and a substrate layer, wherein the cover layer includes a cover wafer and a first insulating layer formed on one side of the cover wafer;

[0008] S120, bonding the cover layer to the device layer, with the first insulating layer located between the cover wafer and the device layer;

[0009] S130, etching the device layer to form an elastic structure and a functional structure on the device layer;

[0010] S140, etching the first insulating layer to remove a portion of the first insulating layer, so that a side of the cover wafer facing the device layer is partially exposed;

[0011] S150, bonding the side of the device layer facing away from the cover layer to the substrate layer, the device layer can be grounded through the substrate layer, and the elastic structure can move toward the cover layer under the action of the substrate layer until the elastic structure abuts against the exposed cover wafer.

[0012] In one embodiment, the chip preparation method further includes the steps of:

[0013] S210, etching the cover wafer to form a first cavity and a second cavity arranged at intervals on one side of the cover wafer;

[0014] S220 , coating the cover wafer to form the first insulating layer on a surface of the cover wafer on a side where the first cavity and the second cavity are formed.

[0015] In one embodiment, in step S130, the position and number of the elastic structures formed by etching the device layer correspond to the position and number of the first cavities, and the position and number of the functional structures formed by etching the device layer correspond to the position and number of the second cavities.

[0016] In one embodiment, in the step S130 , the elastic structure formed by etching the device layer has a first through-groove, the first through-groove passes through the device layer, and the first through-groove corresponds to the first cavity.

[0017] In one embodiment, in step S140 , gaseous hydrofluoric acid etches the first insulating layer through the first through groove and the first cavity.

[0018] In one embodiment, the chip preparation method further includes the steps of:

[0019] S310, etching the device wafer to form a first boss and a plurality of second bosses on one side of the device wafer;

[0020] S320, coating the device wafer to form a first metal layer on the surface of the second boss, wherein the device wafer and the first metal layer constitute the device layer;

[0021] In step S120, the first insulating layer is bonded to a side of the device wafer facing away from the first boss and the second boss;

[0022] In step S130, the device wafer is etched to form the elastic structure and the functional structure on the device wafer, wherein the first boss is located on the elastic structure, and the functional structure is located between the second bosses;

[0023] In step S150 , the first metal layer is bonded to the substrate layer, and the first boss is able to abut against the substrate layer.

[0024] In one embodiment, the chip preparation method further includes the steps of:

[0025] S410, coating one side of the substrate wafer to form a second metal layer;

[0026] S420, etching the second metal layer to divide the second metal layer into a plurality of electrodes;

[0027] S430, coating a portion of the electrodes to form a contact layer on the surface thereof, wherein the substrate wafer, the plurality of electrodes, and the contact layer constitute the substrate layer;

[0028] In step S150 , the first metal layer is bonded to the partially exposed electrode, and the elastic structure is in contact with the contact layer via the first boss, so as to move toward the cover wafer under the action of the contact layer.

[0029] In one embodiment, the plurality of electrodes include a ground electrode;

[0030] In step S430, the ground electrode corresponding to the elastic structure on the substrate wafer is plated to form the abutting layer on the surface of the ground electrode;

[0031] In step S150 , the first metal layer is bonded to the exposed ground electrode.

[0032] In one embodiment, the sum of the thicknesses of the first insulating layer and the first metal layer is less than or equal to the thickness of the contact layer.

[0033] In one embodiment,

[0034] In step S320, the device wafer is plated to form a first metal layer on the surface of the second boss and also to form a first metal layer on the surface of the first boss;

[0035] The plurality of electrodes include a ground electrode;

[0036] In step S430, the ground electrode corresponding to the elastic structure on the substrate wafer is plated to form the abutting layer on the surface of the ground electrode;

[0037] In step S150 , the first metal layer is bonded to the exposed ground electrode.

[0038] In one embodiment, the thickness of the first insulating layer is less than or equal to the thickness of the contact layer.

[0039] In one embodiment, the abutting layer includes a second insulating layer and a protective layer sequentially formed on a portion of the electrode surface, and the elastic structure abuts against the protective layer through the first boss.

[0040] A chip, comprising:

[0041] A cover layer, comprising a cover wafer and a first insulating layer, wherein a surface of the cover wafer includes a first region and a second region, and the first insulating layer covers the first region;

[0042] a device layer fixedly connected to the cover layer, wherein the first insulating layer is located between the cover wafer and the device layer, and an elastic structure and a functional structure are formed on the device layer; and

[0043] The substrate layer is fixedly connected to a side of the device layer facing away from the cover layer, so that the device layer is grounded through the substrate layer, and the elastic structure can abut against the second area under the action of the substrate layer.

[0044] In one embodiment, a first cavity is defined in the second region, the elastic structure abuts against the first cavity in the second region, and a first through-groove is defined in the elastic structure, the first through-groove corresponding to the first cavity.

[0045] In one embodiment, the device layer includes a device wafer and a first metal layer, the elastic structure and the functional structure are formed on the device wafer, a first boss and a plurality of second bosses are formed at intervals on one side of the device wafer, the first boss is located on the elastic structure, the first metal layer is formed on the surface of the second boss, and the functional structure is located between two adjacent second bosses;

[0046] The first insulating layer is fixedly connected to the side of the device wafer facing away from the first boss and the second boss, the first metal layer is fixedly connected to the substrate layer, and the first boss abuts the substrate layer so that the elastic structure abuts the second area under the action of the substrate layer.

[0047] In one embodiment, the substrate layer includes a substrate wafer, a contact layer and a plurality of electrodes, the plurality of electrodes are arranged at intervals on one side of the substrate wafer, the contact layer is arranged on the surface of part of the electrodes, the first metal layer is fixedly connected to the partially exposed electrodes, and the first boss is in contact with the contact layer.

[0048] In one embodiment, the sum of the thicknesses of the first insulating layer and the first metal layer is less than or equal to the thickness of the contact layer.

[0049] In one embodiment, the substrate layer includes a substrate wafer, a contact layer and a plurality of electrodes, the plurality of electrodes are arranged at intervals on one side of the substrate wafer, the contact layer is arranged on the surface of part of the electrodes, the first metal layer is also formed on the surface of the first boss, the first metal layer on the second boss is fixedly connected to the partially exposed electrode, and the first metal layer on the first boss is in contact with the contact layer.

[0050] In one embodiment, the thickness of the first insulating layer is less than or equal to the thickness of the contact layer.

[0051] In one embodiment, a second cavity is defined in the second region, a third cavity is formed between two adjacent second bosses and the substrate layer, and the functional structure corresponds to the second cavity and the third cavity.

[0052] Using the aforementioned chip fabrication method and chip, the device wafer is etched to form an elastic structure on the device layer. The first insulating layer is partially etched away, exposing the side of the cover wafer facing the device layer. This allows the elastic structure to abut against the exposed cover wafer under the influence of the substrate layer, achieving grounding of the cover wafer through the device and substrate layers. This eliminates the need for additional wire bonding on the cover wafer, thus avoiding increased package thickness and generating additional stress, ensuring chip performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0054] FIG1 is a schematic diagram of the overall process of a chip preparation method according to an embodiment of the present application;

[0055] FIG2 is a schematic diagram of the process for preparing a cover layer in the chip preparation method shown in FIG1 ;

[0056] FIG3 is a schematic diagram of the process for preparing a device layer in the chip preparation method shown in FIG1 ;

[0057] FIG4 is a schematic diagram of the process for preparing a substrate layer in the chip preparation method shown in FIG1 ;

[0058] FIG5 is a schematic structural diagram of the cover layer in step S110 of the chip preparation method shown in FIG1 ;

[0059] FIG6 is a schematic structural diagram of the device layer in step S110 of the chip preparation method shown in FIG1 ;

[0060] FIG7 is a schematic structural diagram of the chip manufacturing method shown in FIG1 after the cover layer and the device layer are bonded in step S120;

[0061] FIG8 is a schematic structural diagram of the chip preparation method shown in FIG1 after step S130 and step S140;

[0062] FIG9 is a schematic structural diagram of the substrate layer in step S110 of the chip preparation method shown in FIG1 ;

[0063] FIG10 is a schematic diagram of the process structure in step S150 of the chip preparation method shown in FIG1 ;

[0064] FIG. 11 is a schematic diagram of the chip structure after step S150 in the chip preparation method shown in FIG. 1 . DETAILED DESCRIPTION

[0065] To make the above-mentioned objects, features, and advantages of the present application more clearly understood, the specific embodiments of the present application are described in detail below with reference to the accompanying drawings. The following description sets forth many specific details to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways than those described herein, and those skilled in the art can make similar improvements without violating the scope of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0066] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0067] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of such features. Throughout the description of this application, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0068] In this application, unless otherwise specified or limited, the terms "installed," "connected," "connect," "fixed," etc. should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection or electrical connection; direct connection or indirect connection through an intermediate medium; internal communication between two elements or interaction between two elements, unless otherwise specified. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0069] In this application, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0070] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or there may be an intermediate element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be an intermediate element. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only implementation methods.

[0071] On the one hand, as shown in FIG1 , the present application provides a chip preparation method, comprising the steps of:

[0072] S110 , providing a cover layer 100 (see FIG5 ), a device layer 200 (see FIG6 ) and a substrate layer 300 (see FIG9 ), wherein the cover layer 100 includes a cover wafer 110 and a first insulating layer 120 formed on one side of the cover wafer 110 .

[0073] S120 , as shown in FIG. 7 , the cover layer 100 is bonded to the device layer 200 , with the first insulating layer 120 located between the cover wafer 110 and the device layer 200 .

[0074] S130 , referring to FIG. 7 and FIG. 8 , the device layer 200 is etched to form an elastic structure 211 and a functional structure 212 on the device layer 200 .

[0075] S140 , please continue to refer to FIG. 8 , the first insulating layer 120 is etched to remove a portion of the first insulating layer 120 , so that a side of the cover wafer 110 facing the device layer 200 is partially exposed.

[0076] S150, as shown in Figures 10 and 11, the side of the device layer 200 facing away from the cover layer 100 is bonded to the substrate layer 300, the device layer 200 can be grounded through the substrate layer 300, and the elastic structure 211 can move toward the cover layer 100 under the action of the substrate layer 300 until the elastic structure 211 abuts against the exposed cover wafer 110, thereby achieving grounding of the cover wafer 110 through the device layer 200 and the substrate layer 300.

[0077] It should be noted that in this embodiment, the chip is a MEMS sensor, such as a MEMS accelerometer, a MEMS gyroscope, or a MEMS inertial measurement unit (IMU). Of course, in other embodiments, the chip can also be other products, which is not limited here. Accordingly, the functional structure 212 can be used to detect acceleration and / or angular velocity.

[0078] It is understood that the order of operations from step S120 to step S140 is not specifically limited. It is sufficient to ensure that, before step S150 is performed, the cover layer 100 and the device layer 200 are bonded, the elastic structure 211 and the functional structure 212 are etched on the device layer 200, and the first insulating layer 120 is etched to partially expose the cover wafer 110. Furthermore, with respect to step S130, etching the device layer 200 to form the elastic structure 211 and the functional structure 212 can be performed simultaneously or sequentially, and this is not specifically limited here.

[0079] Using the aforementioned chip fabrication method, the device layer 200 is etched to form an elastic structure 211 thereon, and the first insulating layer 120 is partially etched away, exposing a portion of the cover wafer 110 facing the device layer 200. This allows the elastic structure 211 to abut against the exposed cover wafer 110 under the action of the substrate layer 300, achieving grounding of the cover wafer 110 through the device layer 200 and the substrate layer 300. This eliminates the need for additional wire bonding on the cover wafer 110, thereby avoiding increasing the package thickness and generating additional stress, thereby ensuring chip performance.

[0080] The steps of the chip preparation method are further described below:

[0081] Referring to FIG. 2 and FIG. 5 , in one embodiment, the chip manufacturing method further includes the steps of preparing the cover layer 100 :

[0082] S210 , etching the cover wafer 110 to form a first cavity 111 and a second cavity 112 on one side of the cover wafer 110 .

[0083] S220 , coating the cover wafer 110 to form a first insulating layer 120 on a surface of the cover wafer 110 on a side where the first cavity 111 and the second cavity 112 are formed.

[0084] In conjunction with the preparation steps of the cover layer 100, it should be noted that, as shown in Figure 8, in step S130, the device layer 200 is etched to form an elastic structure 211 and a functional structure 212 on the device layer 200. The position and number of the elastic structure 211 correspond to the position and number of the first cavity 111, and the position and number of the functional structure 212 correspond to the position and number of the second cavity 112. Specifically, a first cavity 111 is formed at both ends of the cover wafer 110, and two second cavities 112 are formed between the two first cavities 111. Correspondingly, an elastic structure 211 is formed at both ends of the device layer 200, and two functional structures 212 are formed between the two elastic structures 211. The functional structure 212 is a movable structure, and the second cavity 112 provides a space for the functional structure 212 to move upward.

[0085] In addition, as shown in FIG8 , in step S140, the first insulating layer 120 is etched, and the first insulating layer 120 between the cover wafer 110 and the elastic structure 211 can be fully removed through the first cavity 111. This not only exposes the portion of the cover wafer 110 opposite the elastic structure 211, but also releases the elastic structure 211, allowing it to move relative to the device layer 200. Thus, in step S150, the elastic structure 211 can move toward the cover layer 100 under the action of the substrate layer 300 until it abuts against the exposed cover wafer 110. Furthermore, since the cover wafer 110 is a silicon wafer, the cover wafer 110 can be grounded through the device layer 200 and the substrate layer 300.

[0086] Referring to FIG. 3 and FIG. 6 , in one embodiment, the chip manufacturing method further includes the steps of preparing the device layer 200 :

[0087] S310 , etching the device wafer 210 to form a first boss 213 and a plurality of second bosses 214 on one side of the device wafer 210 .

[0088] S320 , coating the device wafer 210 to form a first metal layer 220 on the surface of the second boss 214 .

[0089] The device wafer 210 and the first metal layer 220 constitute the device layer 200 .

[0090] In combination with the preparation steps of the device layer 200, it can be understood that:

[0091] As shown in FIG7 , in step S120 , the first insulating layer 120 is bonded to a side of the device wafer 210 facing away from the first and second bosses 213 and 214 . Specifically, the first insulating layer 120 is SiO 2 , and the device wafer 210 is a silicon wafer. In step S120 , the cover layer 100 and the device layer 200 are melt-bonded via the first insulating layer 120 and the device wafer 210 .

[0092] As shown in FIG. 8 , in step S130 , the device wafer 210 is etched to form an elastic structure 211 and a functional structure 212 on the device wafer 210 , wherein the first boss 213 is located on the elastic structure 211 and the functional structure 212 is located between two adjacent second bosses 214 .

[0093] Specifically, both ends of the device wafer 210 are etched to form first bosses 213 at both ends of the device wafer 210, and three second bosses 214 spaced apart are formed between the two first bosses 213. In step S130, the device wafer 210 is etched to form the elastic structure 211 and the functional structure 212, wherein the first bosses 213 are located on the corresponding elastic structure 211, and a functional structure 212 is provided between two adjacent second bosses 214.

[0094] It should be explained that the elastic structure 211 is a part of the device wafer 210 and is connected to other parts of the device wafer 210 .

[0095] As shown in Figures 10 and 11, in step S150, the side of the device layer 200 facing away from the cover layer 100 is bonded to the substrate layer 300, that is, the first metal layer 220 is bonded to the substrate layer 300. The first boss 213 can abut against the substrate layer 300, so that the elastic structure 211 can abut against the exposed cover wafer 110 under the action of the substrate layer 300. The cover wafer 110 is grounded in sequence through the elastic structure 211, other parts of the device wafer 210, the first metal layer 220, and the substrate layer 300. In addition, the functional structure 212 is a movable structure. A third cavity is formed between the adjacent second bosses 214 and the substrate layer 300. The functional structure 212 also corresponds to the third cavity, and the third cavity provides space for the functional structure 212 to move downward.

[0096] In other embodiments, in step S320, the first metal layer 220 can also be formed on the surface of the first boss 213 while the first metal layer 220 is formed on the surface of the second boss 214, so as to increase the height of the first boss 213 protruding from the device wafer 210, thereby ensuring that after the first metal layer 220 on the first boss 213 abuts against the substrate layer 300, the elastic structure 211 can abut against the exposed cover wafer 110 under the action of the substrate layer 300.

[0097] Referring to FIG. 4 and FIG. 9 , in one embodiment, the chip manufacturing method further includes the steps of preparing the substrate layer 300 :

[0098] S410 , coating one side of the substrate wafer 310 to form a second metal layer.

[0099] S420 , etching the second metal layer to divide the second metal layer into a plurality of electrodes.

[0100] Optionally, the plurality of electrodes include a ground electrode 321 and a sensing electrode 322 .

[0101] S430 , coating a portion of the electrodes to form an abutting layer on the surface thereof.

[0102] The substrate wafer 310 , the plurality of electrodes, and the contact layer constitute the substrate layer 300 .

[0103] In combination with the preparation steps of the substrate layer 300, it can be understood that:

[0104] In step S150, the device layer 200 is bonded to the substrate layer 300 using the first metal layer 220 and the second metal layer. Specifically, the first metal layer 220 of the device layer 200 is bonded to the partially exposed electrode. Furthermore, the elastic structure 211 abuts the contact layer. Because the contact layer increases the height of the corresponding electrode, the contact layer causes the elastic structure 211 to move toward the cover wafer 110 until it abuts the exposed cover wafer 110.

[0105] Therefore, in step S430, the electrode surface corresponding to the elastic structure 211 needs to be plated. Furthermore, the ground electrode 321 corresponding to the elastic structure 211 on the substrate wafer 310 is plated. Specifically, the ground electrodes 321 located at both ends of the substrate wafer 310 are plated.

[0106] In one embodiment, the contact layer includes a second insulating layer 330 and a protective layer 340. Specifically, the ground electrode 321 corresponding to the elastic structure 211 on the substrate wafer 310 is plated to sequentially form the second insulating layer 330 and the protective layer 340 on its surface.

[0107] Optionally, the substrate wafer 310 is a silicon wafer, the second insulating layer 330 is SiO 2 , and the protective layer 340 is Si 3 N 4 .

[0108] Specifically, in step S430, after the ground electrodes 321 at both ends of the substrate wafer 310 are plated, the ground electrodes 321 at both ends are covered by the second insulating layer 330 and the protective layer 340, while the sensing electrode 322 and the other ground electrodes 321 are exposed. In step S150, the first metal layer 220 on the second boss 214 of the device layer 200 is bonded to the corresponding ground electrode 321 among the exposed electrodes. In this way, the device layer 200 can be bonded to the substrate layer 300 while the device layer 200 is grounded through the ground electrode 321. Therefore, after the elastic structure 211 abuts the cover wafer 110, the cover wafer 110 is grounded.

[0109] In combination with the preparation steps of the device layer 200 , it can be determined that the first metal layer 220 on the second protrusion 214 in the device layer 200 is bonded to the exposed and corresponding ground electrode 321 .

[0110] It should also be noted that the first metal layer 220 is Ge, the second metal layer is Al, that is, the ground electrode 321 is Al, that is, the device layer 200 and the substrate layer 300 are bonded using Al-Ge.

[0111] To ensure stable grounding of the cover wafer 110 via the elastic structure 211, in one embodiment, the elastic structure 211 is bonded to the cover wafer 110 after being brought into contact with the cover wafer 110. Since the ambient temperature for Al-Ge bonding is approximately 430°C, and the ambient temperature for Si-Si bonding is approximately 420°C, the bonding of the first metal layer 220 to the ground electrode 321 and the bonding between the cover wafer 110 and the elastic structure 211 can be performed within the same process window.

[0112] To sum up, it can be determined without a doubt that in step S150, during the bonding process of the first metal layer 220 and the ground electrode 321, the cover wafer 110 and the elastic structure 211 are also bonded, thereby ensuring that the cover wafer 110 can be electrically connected to the ground electrode 321 through the device layer 200.

[0113] Of course, in other embodiments, the first metal layer 220 and the ground electrode 321 may also be made of other materials as long as they can achieve their respective functions. For example, after the first metal layer 220 and the ground electrode 321 are bonded, electrical connection between the device wafer 210 and the ground electrode 321 is to be achieved. No other restrictions are imposed here.

[0114] In addition, the functional structure 212 corresponds to the sensing electrode 322 in the substrate layer 300 to implement the function corresponding to the functional structure 212, such as measuring acceleration, angular velocity, etc.

[0115] In step S130 , the elastic structure 211 formed by etching the device wafer 210 has a first through-groove 215 . The first through-groove 215 penetrates the device wafer 210 and corresponds to the first cavity 111 of the cover wafer 110 .

[0116] In step S140, gaseous hydrofluoric acid (VHF) is used to etch the first insulating layer 120. The VHF can contact the first insulating layer 120 on the cover layer 100 through the first through groove 215 and the first cavity 111, and then partially remove the first insulating layer 120.

[0117] It should be noted that during the VHF etching process, guided by the first through-slots 215, the first insulating layer 120 exposed in the vertical direction through the first through-slots 215 can be completely etched. However, in the horizontal direction, without sufficient space for flow, the flow is restricted, and only a few microns of the first insulating layer 120 can be etched away horizontally. This can affect the release of the elastic structure 211, thereby affecting its mobility; it can also affect the electrical connection between the cover wafer 110 and the elastic structure 211, thereby affecting the grounding of the cover wafer 110. By providing the first cavity 111, after the VHF etches a few microns of the first insulating layer 120 near the first through groove 215 in the horizontal direction, the first cavity 111 is connected to the first through groove 215, and the VHF flows into the first cavity 111. The first cavity 111 provides a horizontal flow space for the VHF, fully etches the first insulating layer 120 between the elastic structure 211 and the cover wafer 110, so that the elastic structure 211 is released and the exposed area of ​​the cover wafer 110 meets the grounding requirements.

[0118] In one embodiment, the sum of the thicknesses of the first insulating layer 120 and the first metal layer 220 is less than or equal to the thickness of the abutting layer. Specifically, the sum of the thicknesses of the first insulating layer 120 and the first metal layer 220 is less than or equal to the sum of the thicknesses of the second insulating layer 330 and the protective layer 340, so as to ensure that in step S150, after the first boss 213 abuts against the protective layer 340, the elastic structure 211 can abut against the cover wafer 110 under the action of the protective layer 340.

[0119] It should be explained that, in this embodiment, the thickness of the first insulating layer 120 refers to its thickness after bonding to the device wafer 210 , and the thickness of the first metal layer 220 refers to its thickness before bonding to the ground electrode 321 .

[0120] In addition, in step S310, the device wafer 210 is etched to form a first boss 213 and a second boss 214. The function of the first boss 213 is to abut against the abutting layer, and the protrusion heights of the first boss 213 and the second boss 214 are the same. The setting of the abutting layer increases the height difference, thereby ensuring that the elastic structure 211 abuts against the cover wafer 110 under the action of the abutting layer.

[0121] Of course, in other embodiments, when the first metal layer 220 is also formed on the surface of the first boss 213, the first metal layer 220 on the surfaces of the first boss 213 and the second boss 214 has the same thickness. Therefore, it is only necessary that the thickness of the first insulating layer 120 is less than or equal to the thickness of the abutting layer. Specifically, the thickness of the first insulating layer 120 is less than or equal to the sum of the thicknesses of the second insulating layer 330 and the protective layer 340 to ensure that the elastic structure 211 abuts against the cover wafer 110 under the action of the protective layer 340.

[0122] Step S150 in this embodiment is described with reference to FIG10 and FIG11 :

[0123] In step S150, the device layer 200 is first brought closer to the substrate layer 300 until the first protrusion 213 abuts the protective layer 340. Pressure is then continuously applied to the device layer 200 until the first metal layer 220 on the surface of the second protrusion 214 abuts the ground electrode 321. During this process, the elastic structure 211 is resilient and can swing relative to other positions on the device wafer 210. Therefore, the elastic structure 211, pushed by the protective layer 340, can move toward the cover layer 100 until it abuts the cover wafer 110.

[0124] It should be further explained that since the second metal layer is Al, that is, the ground electrode 321 is Al, Al is a relatively soft material and can play a certain buffering role, preventing the first boss 213 from rigidly contacting the protective layer 340, thereby preventing the elastic structure 211 from being broken when pressure is applied to the device layer 200.

[0125] On the other hand, referring to FIG. 11 , based on the above chip preparation method, the present application further provides a chip 10 , including a cover layer 100 , a device layer 200 and a substrate layer 300 .

[0126] 8 , the cover layer 100 includes a cover wafer 110 and a first insulating layer 120 . One side surface of the cover wafer 110 includes a first region and a second region. The first insulating layer 120 covers the first region, leaving the second region exposed.

[0127] The cover layer 100 is fixedly connected to the device layer 200 , and the first insulating layer 120 is located between the cover wafer 110 and the device layer 200 .

[0128] An elastic structure 211 and a functional structure 212 are formed on the device layer 200 .

[0129] The substrate layer 300 is fixedly connected to the side of the device layer 200 facing away from the cover layer 100, so that the device layer 200 is grounded through the substrate layer 300. At the same time, the elastic structure 211 can abut against the second area under the action of the substrate layer 300, thereby achieving grounding of the cover wafer 110 through the device layer 200 and the substrate layer 300.

[0130] It can be understood from the above that the second region is the region where the first insulating layer 120 is removed.

[0131] With the aforementioned chip, the elastic structure 211 in the device layer 200 abuts against the cover wafer 110 under the action of the substrate layer 300. The device layer 200 is grounded via the substrate layer 300, thereby indirectly grounding the cover wafer 110 through the device layer 200 and the substrate layer 300. This eliminates the need for additional wire bonding on the cover wafer 110, thus avoiding increased package thickness and generating additional stress, ensuring chip performance.

[0132] In one embodiment, the second region is separated into a first cavity 111 and a second cavity 112 , the elastic structure 211 abuts against the first cavity 111 of the second region, and the functional structure 212 is disposed corresponding to the second cavity 112 .

[0133] It should be noted that the functions of the first cavity 111 and the second cavity 112 have been described above and will not be repeated here.

[0134] Specifically, in the embodiment shown in FIG8 , first cavities 111 are defined at both ends of the cover wafer 110, and corresponding elastic structures 211 are formed at both ends of the device layer 200 to respectively abut against the first cavities 111 at both ends of the cover wafer 110. Two second cavities 112 are formed between the two first cavities 111, and two functional structures 212 are formed between the two elastic structures 211 on the device layer 200, corresponding to the two second cavities 112.

[0135] Please refer to Figures 6 to 8. In one embodiment, the device layer 200 includes a device wafer 210 and a first metal layer 220. The elastic structure 211 and the functional structure 212 are formed on the device wafer 210. A first boss 213 and a plurality of second bosses 214 are formed at intervals on the side of the device wafer 210 facing away from the cover layer 100. The first boss 213 is located on the elastic structure 211, and the first boss 213 abuts against the substrate layer 300, so that the elastic structure 211 abuts against the second area under the action of the substrate layer 300. The first metal layer 220 is formed on the surface of the second boss 214, and the first metal layer 220 is fixedly connected to the substrate layer 300. The functional structure 212 is located between two adjacent second bosses 214. The first insulating layer 120 is fixedly connected to the side of the device wafer 210 facing away from the first boss 213 and the second boss 214.

[0136] Furthermore, first bosses 213 are formed at both ends of the device wafer 210 , and the two first bosses 213 are respectively located on the two elastic structures 211 .

[0137] Furthermore, the device wafer 210 has three second bosses 214 formed between the two first bosses 213 . A third cavity is formed between two adjacent second bosses 214 and the substrate layer 300 . The functional structure 212 corresponds to the third cavity.

[0138] In one embodiment, a first through-groove 215 is defined on the elastic structure 211 . The first through-groove 215 corresponds to the first cavity 111 in the second region of the cover wafer 110 .

[0139] Referring to Figures 9 to 11 , in one embodiment, the substrate layer 300 includes a substrate wafer 310, an abutting layer, and a plurality of electrodes. The plurality of electrodes are spaced apart and arranged on one side of the substrate wafer 310. The abutting layer is disposed on the surface of some of the electrodes and abuts against the elastic structure 211. The device layer 200 is fixedly connected to the exposed portions of the electrodes.

[0140] Furthermore, the abutting layer includes a second insulating layer 330 and a protective layer 340. The second insulating layer 330 is arranged on the surface of part of the electrode, and the protective layer 340 is arranged on the surface of the second insulating layer 330. The protective layer 340 abuts against the elastic structure 211, and the device layer 200 is fixedly connected to the partially exposed electrode.

[0141] In one embodiment, the plurality of electrodes include a ground electrode 321 and a sensing electrode 322. A contact layer is provided on the surface of the ground electrode 321 on the substrate wafer 310 corresponding to the elastic structure 211. The first boss 213 contacts the contact layer, and the first metal layer 220 is fixedly connected to the exposed ground electrode 321, thereby achieving a fixed connection between the device layer 200 and the substrate layer 300, and grounding of the device layer 200 and the cover wafer 110. The functional structure 212 corresponds to the sensing electrode 322 to implement the corresponding function of the functional structure 212, such as measuring acceleration and angular velocity.

[0142] Furthermore, the sum of the thicknesses of the first insulating layer 120 and the first metal layer 220 is less than or equal to the thickness of the contact layer. Specifically, the sum of the thicknesses of the first insulating layer 120 and the first metal layer 220 is less than or equal to the sum of the thicknesses of the second insulating layer 330 and the protective layer 340 .

[0143] In other embodiments, when a first metal layer 220 is also formed on the surface of the first boss 213, the thickness of the first insulating layer 120 is less than or equal to the thickness of the abutting layer. Specifically, the thickness of the first insulating layer 120 is less than or equal to the sum of the thicknesses of the second insulating layer 330 and the protective layer 340.

[0144] In one embodiment, the first insulating layer 120 is SiO 2 , the device wafer 210 is a silicon wafer, and the cover layer 100 and the device layer 200 are fixedly connected by melt bonding of the first insulating layer 120 and the device wafer 210 .

[0145] In one embodiment, the first metal layer 220 is Ge, the second metal layer is Al, and the device layer 200 and the substrate layer 300 are fixedly connected through Al-Ge bonding between the first metal layer 220 and the ground electrode 321 .

[0146] Furthermore, the cover wafer 110 and the device wafer 210 are both silicon wafers. While the device layer 200 and the substrate layer 300 are fixedly connected after Al-Ge bonding of the first metal layer 220 and the ground electrode 321, the cover wafer 110 and the elastic structure 211 are fixedly connected after Si-Si bonding.

[0147] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0148] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A chip preparation method, characterized in that: Includes steps: S110, providing a cover layer, a device layer and a substrate layer, wherein the cover layer includes a cover wafer and a first insulating layer formed on one side of the cover wafer; S120, bonding the cover layer to the device layer, with the first insulating layer being located between the cover wafer and the device layer; S130, etching the device layer to form an elastic structure and a functional structure on the device layer; S140, etching the first insulating layer to remove a portion of the first insulating layer, so that a side of the cover wafer facing the device layer is partially exposed; S150, bonding the side of the device layer facing away from the cover layer to the substrate layer, the device layer can be grounded through the substrate layer, and the elastic structure can move toward the cover layer under the action of the substrate layer until the elastic structure abuts against the exposed cover wafer.

2. The chip preparation method according to claim 1, characterized in that: The chip preparation method further comprises the steps of: S210, etching the cover wafer to form a first cavity and a second cavity arranged at intervals on one side of the cover wafer; S220 , coating the cover wafer to form the first insulating layer on a surface of the cover wafer on one side where the first cavity and the second cavity are opened.

3. The chip preparation method according to claim 2, characterized in that: In the step S130, the position and number of the elastic structures formed by etching the device layer correspond to the position and number of the first cavities, and the position and number of the functional structures formed by etching the device layer correspond to the position and number of the second cavities.

4. The chip preparation method according to claim 2, characterized in that: In the step S130 , the elastic structure formed by etching the device layer has a first through-groove, the first through-groove penetrates the device layer, and the first through-groove corresponds to the first cavity.

5. The chip preparation method according to claim 4, characterized in that: In step S140 , gaseous hydrofluoric acid etches the first insulating layer through the first through groove and the first cavity.

6. The chip preparation method according to claim 1, characterized in that: The chip preparation method further comprises the steps of: S310, etching the device wafer to form a first boss and a plurality of second bosses on one side of the device wafer; S320, coating the device wafer to form a first metal layer on the surface of the second boss, wherein the device wafer and the first metal layer constitute the device layer; In step S120, the first insulating layer is bonded to a side of the device wafer away from the first boss and the second boss; In step S130, the device wafer is etched to form the elastic structure and the functional structure on the device wafer, wherein the first boss is located on the elastic structure, and the functional structure is located between the second bosses; In step S150 , the first metal layer is bonded to the substrate layer, and the first boss is able to abut against the substrate layer.

7. The chip preparation method according to claim 6, characterized in that: The chip preparation method further comprises the steps of: S410, coating one side of the substrate wafer to form a second metal layer; S420, etching the second metal layer to divide the second metal layer into a plurality of electrodes; S430, coating a portion of the electrodes to form a contact layer on the surface thereof, wherein the substrate wafer, the plurality of electrodes and the contact layer constitute the substrate layer; In step S150 , the first metal layer is bonded to the partially exposed electrode, and the elastic structure is in contact with the contact layer via the first boss, so as to move toward the cover wafer under the action of the contact layer.

8. The chip preparation method according to claim 7, characterized in that: The plurality of electrodes include a ground electrode; In step S430, the ground electrode corresponding to the elastic structure on the substrate wafer is plated to form the abutment layer on the surface of the ground electrode; In step S150, the first metal layer is bonded to the exposed ground electrode.

9. The chip preparation method according to claim 8, characterized in that: The sum of the thickness of the first insulating layer and the first metal layer is less than or equal to the thickness of the contact layer.

10. The chip preparation method according to claim 7, characterized in that: In step S320, the device wafer is plated to form a first metal layer on the surface of the second boss and a first metal layer on the surface of the first boss; The plurality of electrodes include a ground electrode; In step S430, the ground electrode corresponding to the elastic structure on the substrate wafer is plated to form the abutment layer on the surface of the ground electrode; In step S150, the first metal layer is bonded to the exposed ground electrode.

11. The chip preparation method according to claim 10, characterized in that: The thickness of the first insulating layer is less than or equal to the thickness of the abutting layer.

12. The chip preparation method according to claim 7, characterized in that: The abutting layer includes a second insulating layer and a protective layer which are sequentially formed on a portion of the electrode surface, and the elastic structure abuts against the protective layer through the first boss.

13. A chip, characterized in that: include: A cover layer, comprising a cover wafer and a first insulating layer, wherein a surface of one side of the cover wafer comprises a first region and a second region, and the first insulating layer covers the first region; A device layer is fixedly connected to the cover layer, and the first insulating layer is located between the cover wafer and the device layer, and an elastic structure and a functional structure are formed on the device layer; and The substrate layer is fixedly connected to a side of the device layer facing away from the cover layer, so that the device layer is grounded through the substrate layer, and the elastic structure can abut against the second region under the action of the substrate layer.

14. The chip according to claim 13, characterized in that: The second area is provided with a first cavity, the elastic structure abuts against the first cavity of the second area, and the elastic structure is provided with a first through groove, and the first through groove corresponds to the first cavity.

15. The chip according to claim 13, characterized in that: The device layer includes a device wafer and a first metal layer, the elastic structure and the functional structure are formed on the device wafer, a first boss and a plurality of second bosses are formed at intervals on one side of the device wafer, the first boss is located on the elastic structure, the first metal layer is formed on the surface of the second boss, and the functional structure is located between two adjacent second bosses; The first insulating layer is fixedly connected to the side of the device wafer away from the first boss and the second boss, the first metal layer is fixedly connected to the substrate layer, and the first boss abuts against the substrate layer so that the elastic structure abuts against the second area under the action of the substrate layer.

16. The chip according to claim 15, characterized in that: The substrate layer includes a substrate wafer, a contact layer and a plurality of electrodes. The plurality of electrodes are arranged at intervals on one side of the substrate wafer. The contact layer is arranged on the surface of a portion of the electrodes. The first metal layer is fixedly connected to the partially exposed electrodes, and the first boss is in contact with the contact layer.

17. The chip according to claim 16, characterized in that: The sum of the thickness of the first insulating layer and the first metal layer is less than or equal to the thickness of the contact layer.

18. The chip according to claim 15, characterized in that: The substrate layer includes a substrate wafer, a contact layer and a plurality of electrodes, wherein the plurality of electrodes are arranged at intervals on one side of the substrate wafer, the contact layer is arranged on the surface of part of the electrodes, the first metal layer is also formed on the surface of the first boss, the first metal layer on the second boss is fixedly connected to the partially exposed electrode, and the first metal layer on the first boss is in contact with the contact layer.

19. The chip according to claim 18, characterized in that: The thickness of the first insulating layer is less than or equal to the thickness of the abutting layer.

20. The chip according to claim 15, characterized in that The second region is provided with a second cavity, and a third cavity is formed between two adjacent second bosses and the substrate layer. The functional structure corresponds to the second cavity and the third cavity.

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