Method for manufacturing thin film transistor, and thin film transistor

Abstract

Disclosed is a method for manufacturing a thin film transistor, the method including: a semiconductor layer formation step for forming an oxide semiconductor layer on a substrate; a gate insulating layer formation step for forming a gate insulating layer, which is composed of a silicon nitride film (SiN:F) containing fluorine, on the oxide semiconductor layer; and a gate electrode formation step for forming a gate electrode on the gate insulating layer by a patterning method that uses a resist. The gate electrode formation step includes: a surface treatment step for forming a surface treatment layer, which improves the adhesion of a resist, on the gate insulating layer; and a resist coating step for applying a resist on the surface treatment layer.

Description

Thin film transistor manufacturing method, thin film transistor

[0001] The present invention relates to a method for manufacturing a thin film transistor and a thin film transistor.

[0002] In recent years, active development has been made on thin film transistors using an In-Ga-Zn-O (IGZO) oxide semiconductor as the semiconductor layer (channel layer). In these thin film transistors, various insulating layers such as a protective layer and a gate insulating layer made of a silicon nitride film (SiN) or a silicon oxide film (SiO) are formed around the semiconductor layer. For example, Patent Document 1 discloses a thin film transistor using SiCl ４ Gas and SiF ４ The present invention describes a method for manufacturing a thin film transistor, in which an insulating layer made of a fluorine-containing silicon oxide film is formed on an oxide semiconductor layer by a plasma CVD method using a mixed gas containing a fluorine gas and an oxygen gas as a process gas. In this manufacturing method, by forming a fluorine-containing silicon oxide film on a semiconductor layer that is an oxide semiconductor, the fluorine terminates defects in the oxide semiconductor, thereby improving electrical characteristics.

[0003] Japanese Patent Application Publication No. 2018-195610

[0004] However, the manufacturing method described in Patent Document 1 requires relatively expensive SiCl ４ However, there is a problem in that the cost is high because gas is used. ４ Without using gas, SiF ４ When a fluorine-containing silicon oxide film is formed using a mixed gas of fluorine gas and oxygen gas, the film formation becomes unstable on a semiconductor layer that is an oxide semiconductor.

[0005] On the other hand, SiF ４In the case of depositing a fluorine-containing silicon nitride film using a mixed gas consisting of fluorine gas, nitrogen gas, and hydrogen gas, the film can be stably deposited even on a semiconductor layer that is an oxide semiconductor, and can exhibit high insulating properties. However, in this case, when a gate electrode or the like is formed on the fluorine-containing silicon nitride film by a patterning method using a resist, the adhesion between the fluorine-containing silicon nitride film and the resist is not high, and the developer penetrates between the fluorine-containing silicon nitride film and the resist during patterning of the resist, making the patterning process unstable.

[0006] The present invention has been made in view of the above problems, and has as its main object to enable stable patterning of a resist on a gate insulating film in a method for manufacturing a thin film transistor using a fluorine-containing silicon nitride film as a gate insulating film.

[0007] That is, the method for manufacturing a thin film transistor of the present invention is a method for manufacturing a top-gate thin film transistor, and includes a gate insulating layer forming step of forming a gate insulating layer made of a fluorine-containing silicon nitride film (SiN:F) on a semiconductor layer formed on a substrate, and a gate electrode forming step of forming a gate electrode on the gate insulating layer, wherein the gate electrode forming step includes a surface treatment step of forming a surface treatment layer on the gate insulating layer to improve adhesion of a resist, a resist patterning step of applying a resist to the surface of the surface treatment layer and then patterning the resist, and a gate electrode forming step of forming a gate electrode on the gate insulating layer from which the resist has been removed in the resist patterning step.

[0008] In this manufacturing method, the surface treatment layer improves the adhesion between the fluorine-containing silicon nitride film that constitutes the gate insulating layer and the resist, thereby preventing the developer from penetrating between the fluorine-containing silicon nitride film and the resist during resist patterning, enabling stable patterning, which improves the manufacturing yield of top-gate thin-film transistors and reduces manufacturing costs.

[0009] A specific embodiment of the surface treatment step includes a hydrophobization step of applying a primer to the gate insulating layer to hydrophobize it, and an annealing step of removing the solvent contained in the primer by heat treatment. By using this method, the surface of the gate insulating layer is hydrophobized, thereby more reliably preventing the intrusion of an aqueous developer during resist patterning. Furthermore, by performing heat treatment after applying the primer to remove the solvent, chemical bonding between the primer and the fluorine-containing silicon nitride film can be promoted, further improving adhesion between the resist layer and the fluorine-containing silicon nitride film.

[0010] The primer applied to the gate insulating layer is likely to remain even after the resist is removed, which may cause unexpected fixed charges or deteriorate the fluorine-containing silicon nitride film. Therefore, it is preferable that the gate electrode formation process includes a surface treatment layer removal process of removing the surface treatment layer remaining on the gate insulating layer after removing the applied resist. In this way, the amount of primer layer remaining after resist removal can be reduced, resulting in good thin film transistor characteristics.

[0011] A specific example of the gate insulating layer forming step is to form the gate insulating layer by a plasma CVD method.

[0012] Furthermore, a method for manufacturing a thin film transistor of the present invention is a method for manufacturing a bottom-gate thin film transistor, comprising: a gate insulating layer forming step of forming a gate insulating layer made of a fluorine-containing silicon nitride film (SiN:F) on a gate electrode formed on a substrate; and a semiconductor layer forming step of forming a semiconductor layer on the gate insulating layer, wherein the semiconductor layer forming step comprises: a surface treatment step of forming a surface treatment layer on the gate insulating layer to improve adhesion of a resist, a resist patterning step of applying a resist to the surface of the surface treatment layer and then patterning the resist, and a semiconductor film forming step of forming a semiconductor film on the gate insulating layer from which the resist has been removed in the resist patterning step. This manufacturing method can achieve the same effects in manufacturing bottom-gate thin film transistors as the method for manufacturing top-gate thin film transistors described above.

[0013] The thin-film transistor of the present invention is a top-gate thin-film transistor in which a semiconductor layer, a gate insulating layer made of a fluorine-containing silicon nitride film (SiN:F), and a gate electrode are sequentially stacked on a substrate, and is characterized in that a surface treatment layer for improving adhesion of a resist is present at the interface between the gate insulating layer and the gate electrode.

[0014] Furthermore, the thin-film transistor of the present invention is a bottom-gate thin-film transistor in which a gate electrode, a gate insulating layer made of a fluorine-containing silicon nitride film (SiN:F), and a semiconductor layer are sequentially stacked on a substrate, and is characterized in that a surface treatment layer for improving adhesion of a resist is present at the interface between the gate insulating layer and the semiconductor layer.

[0015] Such a thin film transistor can achieve the same effects as those of the above-described method for manufacturing a thin film transistor of the present invention.

[0016] According to the present invention thus configured, in a method for manufacturing a thin film transistor using a fluorine-containing silicon nitride film as a gate insulating film, resist patterning on the gate insulating film can be stably carried out.

[0017] 1 is a longitudinal sectional view schematically showing the configuration of a thin film transistor according to an embodiment of the present invention; 2 is a diagram schematically showing the configuration of a plasma processing apparatus used in the manufacturing method of the embodiment; 3 is a schematic diagram illustrating a gate electrode forming step in the manufacturing method of the embodiment; 4 is a photograph showing an evaluation sample obtained in an experimental example; 5 is a schematic diagram illustrating a gate electrode forming step in a manufacturing method of another embodiment;

[0018] A thin film transistor 1 according to one embodiment of the present invention and a method for manufacturing the same will be described below.

[0019] 1. Thin-Film Transistor The thin-film transistor 1 of this embodiment is a so-called top-gate TFT, which uses an oxide semiconductor for the channel. As shown in FIG. 1 , the thin-film transistor 1 includes a semiconductor layer 3 serving as a channel layer, a gate insulating layer 4, and a gate electrode 5, which are stacked in this order from the substrate 2 side, and a source electrode 6 and a drain electrode 7 provided on either side of the semiconductor layer 3.

[0020] The substrate 2 is made of any material that can transmit light, and may be made of, for example, a resin material such as plastic (synthetic resin) such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), acrylic, polyimide, etc., or a glass material.

[0021] The semiconductor layer 3 (channel layer) allows current to pass between the source electrode 6 and the drain electrode 7. The semiconductor layer 3 of this embodiment is made of an oxide semiconductor and contains, as a main component, an oxide of at least one element selected from, for example, In, Ga, Zn, Sn, Al, Ti, etc. Specific examples of materials that may constitute the semiconductor layer 3 include In—Ga—Zn—O (IGZO), In—Al—Mg—O, In—Al—Zn—O, and In—Hf—Zn—O. The semiconductor layer 3 is made of an amorphous oxide semiconductor film. While the semiconductor layer 3 of this embodiment has a single-layer structure, it is not limited thereto and may have a stacked structure formed by stacking multiple layers having different compositions and crystallinity.

[0022] The gate insulating layer 4 is made of any insulating material having high insulating properties, and in this example, it is made of an insulating film (gate insulating film) whose main component is a silicon nitride film containing fluorine (SiN:F). The gate insulating layer 4 may have a single layer structure or a laminated structure of two or more layers. For example, a SiN ｘ , SiON, Al ２ O ３ , Y ２ O ３ , Ta ２ O ５ , Hf ２ Alternatively, an insulating film containing one or more oxides selected from the above may be laminated.

[0023] The gate electrode 5 controls the carrier density in the semiconductor layer 3 by the gate voltage applied to the thin film transistor 1. The gate electrode 5 is made of any material having high conductivity, and may be made of one or more metals selected from the group consisting of Si, Al, Mo, Cr, Ta, Ti, Pt, Au, and Ag. The gate electrode 5 may also be made of a conductive film of a metal oxide such as Al—Nd, Ag alloy, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), indium zinc oxide (IZO), or In—Ga—Zn—O (IGZO). The gate electrode 5 may have a single-layer structure or a stacked structure of two or more layers of these conductive films. In the thin film transistor 1 of this embodiment, a surface treatment layer used for surface treatment, such as a primer containing hexamethyldisilazane or the like, is present (residual) at the interface between the gate electrode 5 and the gate insulating layer 4.

[0024] The source electrode 6 and the drain electrode 7 are formed apart from each other so as to partially cover the surface of the semiconductor layer 3. Like the gate electrode 5, the source electrode 6 and the drain electrode 7 are made of a highly conductive material so as to function as electrodes. The source electrode 6 and the drain electrode 7 may have a single-layer structure made of a single material, or may have a laminated structure in which multiple layers made of different materials are stacked.

[0025] 2. Method for Manufacturing Thin Film Transistor Next, a method for manufacturing the thin film transistor 1 having the above-described structure will be described. The method for manufacturing the thin film transistor 1 of this embodiment includes (1) a semiconductor layer forming step, (2) a gate insulating layer forming step, (3) a gate electrode forming step, and (4) a source / drain electrode forming step. Each step will be described below.

[0026] (1) Semiconductor Layer Formation Step First, an oxide semiconductor film is formed on the substrate 2. The oxide semiconductor film may be formed by a known method, for example, by sputtering a conductive oxide sintered body such as InGaZnO as a target using inductively coupled plasma. However, the method is not limited to this, and the oxide semiconductor film may be formed by other methods. Then, the oxide semiconductor film formed on the substrate 2 may be patterned by, for example, a photolithography process.

[0027] (2) Gate Insulation Layer Formation Step Next, a gate insulation film (gate insulation layer 4) is formed on the oxide semiconductor film that constitutes the semiconductor layer 3. In this embodiment, a gate insulation film containing a fluorine-containing silicon nitride film as a main component is formed by a plasma CVD method using an inductively coupled plasma processing apparatus 100.

[0028] 2, the plasma processing apparatus 100 includes a vacuum vessel 20 having a processing chamber 10 formed therein that is evacuated and into which a process gas G is introduced, an antenna 30 provided inside the processing chamber 10, and a high frequency power supply 40 that applies a high frequency (13.56 MHz) to the antenna 30. When a high frequency is applied from the high frequency power supply 40 to the antenna 30, a high frequency magnetic field generated from the antenna 30 is formed inside the processing chamber 10, thereby generating an inductive electric field, and thereby an inductively coupled plasma P is generated.

[0029] Specifically, in this process, SiF ４A mixed gas consisting of nitrogen gas and hydrogen gas is supplied as a process gas into the processing chamber 10, and in this state, high frequency power is applied to the antenna 30 to generate an inductively coupled plasma. In this embodiment, the supply flow rate of the process gas, the high frequency power (RF power) applied to the antenna 30, the pressure inside the processing chamber, the processing time, the substrate temperature, and the like may be known conditions.

[0030] (3) Gate Electrode Forming Step Next, a gate electrode 5 is formed on the gate insulating layer 4. This gate electrode forming step includes (3-1) a surface treatment step, (3-2) a resist patterning step, (3-3) a surface treatment layer removing step, and (3-4) a film forming step.

[0031] (3-1) Surface Treatment Step The surface treatment step is a step of forming a surface treatment layer on the surface of the gate insulating layer 4 to improve adhesion of the resist to the gate insulating layer 4. The surface treatment step of this embodiment includes (3-1-1) a hydrophobizing step of hydrophobizing the surface of the gate insulating layer, and (3-1-2) an annealing step of removing the solvent contained in the applied primer by heat treatment.

[0032] (3-1-1) Hydrophobizing Step In this step, a primer is applied to the surface of the gate insulating layer (FIGS. 3(a) and 3(b)). The paint constituting the primer has the property of making the surface of the fluorine-containing silicon nitride film constituting the gate insulating layer 4 hydrophobic, and for example, hexamethyldisilazane (HMDS) is preferable. However, the paint constituting the primer is not limited to this, and any paint having similar properties can be used. The primer may be applied using, for example, a spin coater or the like, but is not limited to this.

[0033] (3-1-2) Annealing Step After applying a primer to the gate insulating layer 4, an annealing step is performed. This annealing step removes the solvent contained in the applied primer and promotes chemical bonding between the primer and the surface of the fluorine-containing silicon nitride film. The annealing step is preferably performed in air or an inert gas atmosphere such as nitrogen at a temperature of 100° C. or higher and 130° C. or lower for 1 minute or longer and 10 minutes or shorter, but is not limited thereto.

[0034] (3-2) Resist Patterning Step After forming a surface treatment layer on the surface of the gate insulating layer 4, a resist pattern is formed on the surface treatment layer by a photolithography process. Specifically, after applying a photoresist (photosensitive material) to the entire surface of the surface treatment layer (FIG. 3(c)), exposure and development are performed to remove the photoresist from the surface region of the gate insulating layer 4 where the gate electrode is to be formed (FIG. 3(d)).

[0035] (3-3) Surface Treatment Layer Removal Step Next, a process is performed to remove the surface treatment layer (primer) remaining on the surface region of the gate insulating layer 4 on which the gate electrode will be formed. Specifically, the surface treatment layer is removed by, for example, ashing, UV cleaning, dry etching, or the like (FIG. 3(e)).

[0036] (3-4) Film Formation Step Then, a gate electrode is formed on the surface of the gate insulating layer 4 exposed by removing the surface treatment layer. The method for forming the gate electrode is not particularly limited, and may be performed by a known method such as vacuum deposition. After the gate electrode is formed, the patterned photoresist is peeled off from the gate insulating layer 4 by a lift-off method or the like (FIG. 3(f)).

[0037] (4) Source / Drain Electrode Formation Step Then, the source electrode 6 and the drain electrode 7 are formed on the semiconductor layer 3. The formation of the source electrode 6 and the drain electrode 7 is not particularly limited, and may be performed by any known method.

[0038] (5) Post-annealing Step After all components have been formed, post-annealing (heat treatment) may be performed as needed. This post-annealing may be performed, for example, in a nitrogen atmosphere at atmospheric pressure. The furnace temperature during post-annealing is not particularly limited, and is, for example, 150°C or higher and 350°C or lower. The heat treatment time is also not particularly limited, and is, for example, 1 hour or higher and 3 hours or lower.

[0039] In this manner, the thin film transistor 1 of this embodiment can be obtained.

[0040] 3. Effects of the Present Embodiment According to the manufacturing method of the present embodiment configured as described above, in the gate electrode formation step, a surface treatment layer is formed on the surface of the gate insulating layer 4 before applying the resist, which can improve adhesion between the fluorine-containing silicon nitride film that constitutes the gate insulating layer 4 and the resist. This can prevent the developer from penetrating between the fluorine-containing silicon nitride film and the resist during resist patterning, making it possible to stably pattern the resist. This can improve the manufacturing yield of the top-gate thin film transistor 1 and reduce manufacturing costs.

[0041] The effects of the manufacturing method of the thin film transistor 1 of this embodiment were confirmed by an experimental example. In the experimental example, (A) a sample in which a resist was formed on the surface of a fluorine-containing silicon nitride film without an intervening surface treatment layer, and (B) a sample in which a resist was formed on the surface of a fluorine-containing silicon nitride film via a surface treatment layer were prepared. The surface treatment layer was formed by applying a primer, hexamethyldisilazane, to the surface of the fluorine-containing silicon nitride film and then heat-treating it at 110°C for 1 minute. These samples were then exposed and developed to pattern the resist. The results are shown in FIG. 4.

[0042] As shown in Figure 4, in the sample in which the resist was formed without a surface treatment layer (primer), the resist peeled off during patterning, whereas in the sample in which the resist was formed via a surface treatment layer (primer), the resist remained even after patterning without peeling off.

[0043] 4. Other Modified Embodiments The present invention is not limited to the above-described embodiment. For example, in the surface treatment step of the above-described embodiment, a primer is applied as the surface treatment layer, but this is not limiting. In other embodiments, in the (3-1) hydrophobizing step, a fluorine-free silicon nitride film or silicon oxide film may be formed as the surface treatment layer on the surface of the gate insulating layer 4, which is a fluorine-containing silicon nitride film (see FIGS. 5(a) and 5(b)). This also improves the adhesion of the resist and prevents the intrusion of a developer during resist patterning. In this case, in the (3) gate electrode formation step, after the (3-2) resist patterning step (see FIGS. 5(c) and 5(d)), the (3-4) film formation step (see FIG. 5(e)) may be performed without performing the (3-3) surface treatment layer removal step.

[0044] In another embodiment, in the gate electrode forming step, the surface treatment layer does not need to be removed after the gate electrode 5 is formed.

[0045] Although the thin-film transistor 1 and its manufacturing method of the above embodiment are directed to a top-gate thin-film transistor, this is not limiting. The thin-film transistor 1 of other embodiments may be a so-called bottom-gate thin-film transistor in which the gate electrode 5, the gate insulating layer 4, and the semiconductor layer 3 are arranged in this order from the substrate 2 side. In this case, the semiconductor layer formation step of forming the semiconductor layer 3 on the gate insulating layer 4, which is a fluorine-containing silicon nitride film, may include a surface treatment step of forming a surface treatment layer on the gate insulating layer 4 to improve the adhesion of the resist, a resist patterning step of applying a resist to the surface of the surface treatment layer and then patterning the resist, and a semiconductor film formation step of forming the semiconductor layer 3 on the gate insulating layer 4 exposed in the resist patterning step. This prevents a developer from penetrating between the fluorine-containing silicon nitride film and the resist during the resist patterning step when forming the semiconductor layer 3, ensuring stable patterning. In the bottom-gate thin-film transistor 1 manufactured in this manner, a surface treatment layer used for surface treatment, such as a fluorine-free silicon nitride film or silicon oxide film, exists (remains) at the interface between the gate insulating layer 4 and the semiconductor layer 3. A primer containing hexamethyldisilazane or the like may remain as a surface treatment layer at the interface between the gate insulating layer 4 and the semiconductor layer 3.

[0046] Furthermore, the present invention is not limited to the above-described embodiment, and it goes without saying that various modifications are possible without departing from the spirit of the present invention.

[0047] According to the above-described method for manufacturing a thin film transistor of the present invention, in a method for manufacturing a thin film transistor using a fluorine-containing silicon nitride film as a gate insulating film, it becomes possible to stably pattern a resist on the gate insulating film.

[0048] REFERENCE SIGNS LIST 1 thin film transistor 2 substrate 3 semiconductor layer 4 gate insulating layer 5 gate electrode 6 source electrode 7 drain electrode

Claims

1. A method for manufacturing a top-gate type thin film transistor, comprising: a gate insulating layer forming step of forming a gate insulating layer made of a fluorine-containing silicon nitride film (SiN:F) on a semiconductor layer formed on a substrate; and a gate electrode forming step of forming a gate electrode on the gate insulating layer, the gate electrode forming step comprising: a surface treatment step of forming a surface treatment layer on the gate insulating layer to improve adhesion of a resist; a resist patterning step of applying a resist to a surface of the surface treatment layer and then patterning the resist; and a gate electrode forming step of forming a gate electrode on the gate insulating layer from which the resist has been removed in the resist patterning step.

2. The method for manufacturing a thin film transistor according to claim 1, wherein the surface treatment process includes a hydrophobization process for applying a primer onto the gate insulating layer to make it hydrophobic, and an annealing process for removing a solvent contained in the primer by heat treatment.

3. The method for manufacturing a thin film transistor according to claim 2, wherein the gate electrode formation step further comprises a surface treatment layer removal step of removing the surface treatment layer remaining on the gate insulating layer after removing the applied resist.

4. The method for manufacturing a thin film transistor according to claim 1, wherein in the gate insulating layer forming step, the gate insulating layer is formed by a plasma CVD method.

5. A method for manufacturing a bottom-gate type thin film transistor, comprising: a gate insulating layer forming step of forming a gate insulating layer made of a fluorine-containing silicon nitride film (SiN:F) on a gate electrode formed on a substrate; and a semiconductor layer forming step of forming a semiconductor layer on the gate insulating layer, the semiconductor layer forming step comprising: a surface treatment step of forming a surface treatment layer on the gate insulating layer to improve adhesion of a resist; a resist patterning step of applying a resist to a surface of the surface treatment layer and then patterning the resist; and a semiconductor film forming step of forming a semiconductor film on the gate insulating layer from which the resist has been removed in the resist patterning step.

6. A top-gate type thin film transistor in which a semiconductor layer, a gate insulating layer made of a fluorine-containing silicon nitride film (SiN:F), and a gate electrode are laminated in this order on a substrate, and a surface treatment layer that improves the adhesion of a resist is present at the interface between the gate insulating layer and the gate electrode.

7. A bottom-gate type thin-film transistor in which a gate electrode, a gate insulating layer made of a fluorine-containing silicon nitride film (SiN:F), and a semiconductor layer are laminated in this order on a substrate, and a surface treatment layer that improves the adhesion of a resist is present at the interface between the gate insulating layer and the semiconductor layer.

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