Method and apparatus for accelerating physical verification of large-scale integrated circuit and storage medium

Abstract

Disclosed are a method and apparatus for accelerating physical verification of a large-scale integrated circuit, and a storage medium. The method comprises: establishing a corresponding physical verification task for each round of design at every development stage of an integrated circuit design; and for any round of design at any development stage of the integrated circuit design, classifying and grouping checking rules in a physical verification checking rule base on the basis of technological process characteristics and / or physical verification requirements of the round of design, each classification comprising at least one attention group, splitting the physical verification task of the round of design into at least one sub-task, each sub-task corresponding to one attention group, and executing sub-tasks of all classifications in parallel, each sub-task using a checking rule comprised in a corresponding attention group to perform physical verification on the round of design of the integrated circuit.

Description

Method, device and storage medium for accelerating physical verification of large-scale integrated circuits Technical Field

[0001] The embodiments of the present disclosure relate to, but are not limited to, the field of integrated circuit technology, and in particular to a method, device, and storage medium for accelerating physical verification of large-scale integrated circuits. Background Art

[0002] Physical verification of a chip is a step in the chip design process. Its primary purpose is to ensure that the chip's physical characteristics meet the design specifications. Verification tools and processes check physical rules such as minimum line width, minimum spacing, and maximum via size. These checks are based on design rule checking (DRC) and layout verification of schematics (LVS).

[0003] For large-scale chips, conventional physical verification often takes a long time, and the entire chip development and design process inevitably requires multiple rounds of repeated checking of verification results, which is quite time-consuming.

[0004] Summary of the Invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] The present disclosure provides a method for accelerating physical verification of large-scale integrated circuits, including:

[0007] Establish corresponding physical verification tasks for each design round at each development stage of integrated circuit design;

[0008] For any round of design in any development stage of the integrated circuit design, the inspection rules in the physical verification inspection rule library are classified and grouped according to the process characteristics and / or physical verification requirements of the design round, each classification includes at least one focus group, and the physical verification task of the design round is split into at least one subtask, each subtask corresponds to a focus group, and all classified subtasks are executed in parallel, and each subtask uses the inspection rules contained in the corresponding focus group to physically verify the design round of the integrated circuit.

[0009] An embodiment of the present disclosure provides an apparatus for accelerating physical verification of large-scale integrated circuits, comprising: a memory and a processor, wherein the memory stores a computer program, and when the computer program is executed by the processor, the steps of the method for accelerating physical verification of large-scale integrated circuits are implemented.

[0010] An embodiment of the present disclosure provides a non-transitory computer-readable storage medium storing a computer program. When the computer program is executed by a processor, the steps of the method for accelerating physical verification of large-scale integrated circuits are implemented.

[0011] Other features and advantages of the present disclosure will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present disclosure. Other advantages of the present disclosure can be realized and obtained through the solutions described in the description and the drawings.

[0012] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0013] Summary of the Figures

[0014] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0015] FIG1 is a flow chart of a method for accelerating physical verification of large-scale integrated circuits according to an embodiment of the present disclosure;

[0016] FIG2 is a schematic diagram of classification and grouping of a physical verification check rule base according to an embodiment of the present disclosure;

[0017] FIG3 is a schematic diagram showing the relationship between a physical verification check rule base and groups according to an embodiment of the present disclosure;

[0018] FIG4 is a schematic structural diagram of an apparatus for accelerating physical verification of large-scale integrated circuits according to an embodiment of the present disclosure.

[0019] Details

[0020] The present disclosure describes a plurality of embodiments, but this description is exemplary rather than restrictive, and it will be apparent to those skilled in the art that there may be more embodiments and implementations within the scope of the embodiments described in the present disclosure. Although many possible feature combinations are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0021] The present disclosure includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The disclosed embodiments, features, and elements of the present disclosure may also be combined with any conventional features or elements to form a unique inventive solution defined by the claims. Any features or elements of any embodiment may also be combined with features or elements from other inventive solutions to form another unique inventive solution defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in this disclosure may be implemented individually or in any appropriate combination. Therefore, the embodiments are not subject to other limitations except for the limitations set forth in the appended claims and their equivalents. In addition, various modifications and changes may be made within the scope of protection of the appended claims.

[0022] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps described herein, the method or process should not be limited to the steps in the specific order described. As will be understood by those skilled in the art, other orders of steps are also possible. Therefore, the specific order of the steps set forth in the specification should not be interpreted as limiting the claims. In addition, the claims to the method and / or process should not be limited to performing their steps in the order written, and those skilled in the art can readily understand that these orders can be changed without departing from the scope of this disclosure.

[0023] As shown in FIG1 , an embodiment of the present disclosure provides a method for accelerating physical verification of large-scale integrated circuits, including:

[0024] Step S10, establishing corresponding physical verification tasks for each design round in each development stage of the integrated circuit design;

[0025] Step S20, for any round of design in any development stage of the integrated circuit design, classify and group the inspection rules in the physical verification inspection rule library according to the process characteristics and / or physical verification requirements of the design round, each classification includes at least one focus group, and the physical verification task of the design round is split into at least one subtask, each subtask corresponds to a focus group, and all classified subtasks are executed in parallel, and each subtask uses the inspection rules contained in the corresponding focus group to physically verify the design round of the integrated circuit.

[0026] The method for accelerating the physical verification of large-scale integrated circuits provided by the embodiments of the present disclosure establishes corresponding physical verification tasks for each round of design in each development stage of the integrated circuit design; for any round of design in any development stage of the integrated circuit design, the inspection rules in the physical verification inspection rule library are classified and grouped according to the process characteristics and / or physical verification requirements of the design round, each classification includes at least one focus group, and the physical verification task of the design round is split into at least one subtask, each subtask corresponds to a focus group, and all classified subtasks are executed in parallel, and each subtask uses the inspection rules contained in the corresponding focus group to physically verify the design round of the integrated circuit. By performing physical verification on the designs of the integrated circuits in different development stages in a targeted, batched, and multi-task parallel manner, the time consumption of physical verification can be greatly shortened, and the development and design progress of the integrated circuit can be accelerated.

[0027] In an exemplary embodiment, the classification of the inspection rules includes: front-end process FE inspection rules and back-end process BE inspection rules.

[0028] Semiconductor manufacturing is divided into front-end (FE) and back-end (BE). The front-end, also known as the wafer manufacturing process, refers to the process of forming devices on the wafer through a series of complex process steps. The purpose of the front-end process is to form devices with specific functions and characteristics, such as diodes, transistors, and integrated circuits. The back-end process, also known as the packaging process, refers to the process of separating and packaging devices on the wafer. The purpose of the back-end process is to ensure the electrical performance and reliability of each device to meet application requirements. The front-end and back-end processes realize the manufacturing process from silicon wafers to semiconductor devices with specific functions and characteristics.

[0029] FE (front-end process) type inspection rules are mainly aimed at checking the basic layers of device construction, such as "POLY (Polysilicon, polysilicon layer)", "OD (Gate Oxide and Diffusion, active area)", and "NWELL (N well layer)". These inspection rules are intended to ensure that the geometry, size and position of these basic layers comply with the design rules. For example, the "POLY" layer is an important layer used to form the gate of the transistor, and its geometry and size directly affect the performance of the transistor. Therefore, the FE type inspection rules will check the geometry, size and position of the layer to ensure that it complies with the design rules.

[0030] Back-end (BE) inspection rules primarily target the metal layers and via layers that interconnect user signals. These inspection rules ensure that the geometry, size, and position of these layers conform to design rules to ensure circuit performance and reliability. For example, for metal layers, BE inspection rules check parameters such as metal line width, spacing, and length to ensure they conform to design rules. Furthermore, the connection relationships between metal lines are checked to ensure that electrical connections between circuit components are correctly implemented.

[0031] In an exemplary embodiment, the inspection rules in the physical verification inspection rule library are classified and grouped according to the process characteristics and / or physical verification requirements of the design round, including:

[0032] The inspection rules in the physical verification inspection rule library are divided into two categories: front-end process inspection rules and back-end process inspection rules; a front-end process inspection rule set is generated from all front-end process inspection rules, and a back-end process inspection rule set is generated from all back-end process inspection rules;

[0033] Eliminate inspection rules that are not needed and / or not of concern in the current design round from the front-end process inspection rule set and the back-end process inspection rule set based on the process characteristics and physical verification requirements of the current design round, and use the eliminated front-end process inspection rule set and the back-end process inspection rule set as two inspection rule sets to be grouped;

[0034] The inspection rules in each inspection rule set to be grouped are grouped, and each group serves as a focus group for this round of design.

[0035] In an exemplary embodiment, based on the process characteristics and / or physical verification requirements of the current design round, the following check rules that are not needed and / or not of concern in the current design round are eliminated from the front-end process check rule set and the back-end process check rule set:

[0036] Searching the front-end process inspection rule set for inspection rules that are not needed and / or not of concern for the current design round based on the process characteristics and physical verification requirements of the current design round, and classifying the found inspection rules into a first non-concern group; and removing all inspection rules in the first non-concern group from the front-end process inspection rule set;

[0037] According to the process characteristics and physical verification requirements of this round of design, the inspection rules that are not needed and / or not of concern in this round of design are searched from the back-end process inspection rule set, and the found inspection rules are classified into a second non-concern group; all inspection rules in the second non-concern group are removed from the back-end process inspection rule set.

[0038] In an exemplary embodiment, the classifying and grouping of the inspection rules in the physical verification inspection rule library according to the process characteristics and / or physical verification requirements of the round design includes:

[0039] Apply the instructions provided by the physical verification tool to determine the group of interest for this round of design.

[0040] The instruction “DRC SELECT CHECK” provided by the physical verification tool can be used to determine the focus group.

[0041] In an exemplary embodiment, the inspection rules in the physical verification inspection rule library are classified and grouped according to the process characteristics and / or physical verification requirements of the design round, further comprising:

[0042] Apply the instructions provided by the physical verification tool to determine the non-interest groups for this round of design.

[0043] The instruction “DRC UNSELECT CHECK” provided by the physical verification tool can be used to determine the non-focus group.

[0044] Figure 2 shows a schematic diagram of the classification and grouping of a physical verification check rule base. As shown in Figure 2, the physical verification check rule base T is divided into two sets: a front-end process check rule set T_FE and a back-end process check rule set T_BE. According to the process characteristics and / or physical verification requirements of a certain round of design, the check rules that are not needed and / or not of concern in this round of design are eliminated from the front-end process check rule set, and the remaining check rules in the front-end process check rule set are grouped into G1_FE, G2_FE...Gm_FE, and each group is used as a focus group for this round of design. According to the process characteristics and / or physical verification requirements of this round of design, the check rules that are not needed and / or not of concern in this round of design are eliminated from the back-end process check rule set, and the remaining check rules in the back-end process check rule set are grouped into G1_BE, G2_BE...Gn_BE, and each group is used as a focus group for this round of design.

[0045] Use the "DRC SELECT CHECK" and "DRC UNSELECT CHECK" commands provided by the physical verification tool Calibre to group. The following is a reference example: GROUP GROUP_BE_G1"?M1?""?VIA1?" GROUP GROUP_BE_G2"?M2?""?VIA2?""?M3?""?VIA3?""?M4?""?VIA4?" GROUP GROUP_BE_G3"?M1?""?VIA1?""?M2?""?VIA2?""?M3?""?VIA3?""?M4?" "?VIA4?" GROUP GROUP_UnCheck"VIA0.S.7?""VIA0.S.8?""DM?""?DN?""M?.S.13?""M?.S.18?" DRC SELECT CHECK GROUP_BE_G1 DRC SELECT CHECK GROUP_BE_G2 DRC SELECT CHECK GROUP_BE_G3 DRC UNSELECT CHECK GROUP_UnCheck

[0046] In the above example, BE type check rules are grouped to create three focus groups ("GROUP_BE_G1", "GROUP_BE_G2", and "GROUP_BE_G3") and one unfocused group (GROUP_UnCheck). Each group contains certain check rule content.

[0047] The physical verification task of a certain round of design is divided into three subtasks. The first subtask corresponds to the focus group "GROUP_BE_G1", the second subtask corresponds to the focus group "GROUP_BE_G2", and the third subtask corresponds to the focus group "GROUP_BE_G3". For the first subtask, the "DRC SELECT CHECK" instruction is used to tell the verification tool that this verification will only check the check rules contained in the selected group "GROUP_BE_G1". For the second subtask, the "DRC SELECT CHECK" instruction is used to tell the verification tool that this verification will only check the check rules contained in the selected group "GROUP_BE_G2". For the third subtask, the "DRC SELECT CHECK" instruction is used to tell the verification tool that this verification will only check the check rules contained in the selected group "GROUP_BE_G3".

[0048] Sometimes the check rules captured by wildcard matching will include some rules that are not of concern to the current design and that you do not want the verification tool to check. In this case, you can write these rules into the "GROUP_UnCheck" group and then use the "DRC UNSELECT CHECK" command to tell the verification tool that these check rules do not need to be checked.

[0049] In other implementations, you can also directly enter the rules that need to be checked or not checked after the "DRC SELECT CHECK" and "DRC UNSELECT CHECK" commands to achieve the same effect. For example: DRC SELECT CHECK "?M1?" "?VIA1?" DRC UNSELECT CHECK "VIA0.S.7?" "VIA0.S.8?" "DM?" "?DN?" "M?.S.13?" "M?.S.18?"

[0050] The physical verification rule file is written in the SVRF (Standard Verification Rule Format) language. The symbol "?" in the above text is a wildcard. For example, "?M1?" is used to match all check rules with the word "M1" in the name, such as "M1.S.1", "M1.W.1", "DM1.W.1", "M10.S.1", and "M11.W.1", where M1 is the first metal layer.

[0051] The following uses the concept of mathematical sets to illustrate the relationship between the physical verification check rule base and grouping. Let the set of all check rules that need to be checked be A_Total (physical verification check rule base). By checking the control options of the rule file, we can obtain two subsets A_FE and A_BE: #DEFINE FRONT_END / / Turn on to check Front-End rules #DEFINE BACK_END / / Turn on to check Back-End rules

[0052] These two parameters control whether the verification tool should perform FE or BE verification, which can easily split a complete physical verification task into two independent tasks, greatly shortening the required verification time.

[0053] However, for large-scale integrated circuit (chip) design projects, not only is the amount of data required for physical verification large, but the number of check rule entries that need to be checked is also very large. If physical verification is only divided into two major categories, FE and BE, the verification time is still relatively long. In this case, the "DRC SELECT CHECK" and "DRC UNSELECT CHECK" commands provided by the verification tool Calibre can be used to group them.

[0054] The total set A_Total is the union of the two subsets A_FE and A_BE, that is:

[0055] A_Total=A_FE∪A_BE

[0056] And the intersection of subsets A_FE and A_BE is an empty set, that is:

[0057]

[0058] Based on the total set A_Total, or the subsets A_FE and A_BE, it can be divided into multiple groups, namely:

[0059] A_Total=A_G1∪A_G2∪……∪A_Gn (n is a positive integer)

[0060] A_FE=A_G1∪A_G2∪……∪A_Gm (m is a positive integer)

[0061] A_BE=A_G1∪A_G2∪……∪A_Gk (k is a positive integer)

[0062] Intersections between these groups are allowed, which means that the inspection rules of each group are allowed to be repeated, namely:

[0063] or (i≠j, i and j are any integers between 1 and n)

[0064] Physical verification inspection rules have many types of entries, often tens of thousands. If wildcard characters "?" are used to match and group them, the inspection rules of each group may overlap, or some inspection rules may not fall within the matching range, resulting in omissions.

[0065] The following is an example to introduce a more rigorous grouping method. Figure 3 shows a schematic diagram of a complete grouping of a set. As shown in Figure 3,

[0066] Assume that the current total set is A Total, through the "DRC SELECT CHECK" command, three subsets were specifically summarized and divided: A G1 、A G2 、A G3 , these three subsets may overlap with each other or be independent of each other, but the union of these three subsets A G123 is not equal to the total set A Total , that is: A G123 =A G1 ∪A G2 ∪A G3 ; A Total ≠A G123

[0067] At this time, you can use the "complement set" method to complete the missing set content. Use the "DRC UNSELECT CHECK" command to let the tool remove A G1 、A G2 、A G3 The inspection rules of the three subsets, and the remaining inspection rules are grouped into one subset A G4 , it is A G123 The complement of , that is: A Total =A G123 ∪A G4

[0068] In an exemplary embodiment, grouping the inspection rules in each set of inspection rules to be grouped includes:

[0069] The inspection rules in each inspection rule set to be grouped are grouped according to a preset grouping rule, so that the amount of physical verification tasks among different groups is balanced.

[0070] In an exemplary embodiment, the preset grouping rule includes any one or more combinations of the following:

[0071] The number of inspection rule entries in different groups is similar or equal;

[0072] The variance of the verification running time of different groups is smaller than the preset value.

[0073] The purpose of grouping check rules is to shorten verification time and quickly obtain complete verification result reports. Generally speaking, when initially grouping, all verification rules can be assigned as evenly as possible to each group. In other words, try to ensure that the number of rules to be checked in each group is equal or similar. As long as the tool verifies that the calculation time for each check rule is roughly the same, the total verification calculation time for each group will be relatively close.

[0074] Sometimes, the verification operation time of certain check rules will be much longer than that of other check rules. This is because different check rules correspond to different verification algorithms. Some check rules can be implemented with just a few lines of code, while others require complex and lengthy operations. Therefore, based on the results of the initial grouping, you can perform one or two rounds of iterative optimization of the grouping, and reallocate some specific check rules from the time-consuming group to the time-saving group to balance the verification operation time of each group. The specific operation is to view the operation log files of each group's verification job, analyze and organize the operation time data of all the check rules of the group, and then select some check rules whose total time just makes up for the gap between the several groups and reallocate them.

[0075] In an exemplary embodiment, the types and number of checking rules that are not required and / or not of concern in the current design round are determined by the development stage of the integrated circuit design and the round in the development stage;

[0076] If the current design is in the integrated circuit design development stage that requires complete physical verification, the number of check rules that are not required and / or not of concern in the current design is 0;

[0077] If the current round of design is in an integrated circuit design development stage where complete physical verification is not required, the number of check rules that are not required and / or not concerned about in the current round of design is greater than zero.

[0078] In an exemplary embodiment, the development stages of the integrated circuit design include: an early development stage of the integrated circuit design, a mid-development stage of the integrated circuit design, and a late development stage of the integrated circuit design;

[0079] The early development stage of integrated circuit design includes floorplan and may also include wiring of some circuits (power and ground);

[0080] The mid-stage development of integrated circuit design includes wiring;

[0081] The post-development stage of integrated circuit design includes testing and adjusting the integrated circuit after layout and routing before manufacturing.

[0082] In an exemplary embodiment, the early development stage and the mid-development stage of integrated circuit design are integrated circuit development stages that do not require complete physical verification; the late development stage of integrated circuit design is an integrated circuit development stage that requires complete physical verification.

[0083] In other implementations, the integrated circuit design and development stages can also be arbitrarily divided according to actual conditions. This document does not limit the division method of the development stages.

[0084] The early development stage of integrated circuit design mainly includes the layout and wiring of some circuits.

[0085] Various types of components need to be placed during layout. Component types vary, and may include the following categories: processors, memories, analog circuits, digital circuits, clock circuits, power supply circuits, communication interfaces, etc.

[0086] During the early stages of integrated circuit (chip) design, physical verification primarily involves evaluating the rationality of the current layout (floorplan) by checking for violations of specific physical check rules. These specific physical check rules are generally related to the fundamental level of FE (Feature-Enhanced Elementary Interface) (FE) checks. During this early stage, wiring work often hasn't yet begun. Beyond the power / ground metal lines prioritized during layout, the design data contains no other metal lines. Therefore, checking BE (Benchmark-Enhanced Elementary Interface) rules is less necessary at this stage. Therefore, during this early stage, FE (Feature-Enhanced Elementary Interface) check rules are of greater concern, while BE (Benchmark-Enhanced Elementary Interface) check rules can be less frequently checked or even eliminated.

[0087] During the early stages of integrated circuit (chip) design development, if the layout is confirmed to be free of FE-type issues, a check can be performed on the data after the power and ground routing has been completed. However, many issues may still exist at this stage, especially power network short circuits. Power network short circuits can lead to a large number of physical verification violations. The causes of these violations are known and easy to resolve, but these numerous physical violations caused by power network short circuits not only affect the physical verification analysis report but also significantly increase the verification operation time of the physical verification tool. Therefore, at this stage, these power network short-circuit related check rules can be removed through the "DRC UNSELECT CHECK" command of the physical verification tool and not checked.

[0088] The mid-stage development phase of integrated circuit design primarily involves routing. The primary purpose of routing is to connect the various components within the circuit, enabling signal transmission and power supply. During the routing process, certain design rules must be followed to ensure circuit stability, reliability, and performance. Factors typically considered during routing include line width and spacing, signal integrity, power integrity, heat dissipation, and modularity.

[0089] During the mid-stage development of integrated circuit (chip) design, certain rule violations may require special attention, requiring rapid resolution and verification of expected results. Therefore, in some rounds of physical verification, only these rules can be selected for physical verification. This allows for targeted, batch-by-batch physical verification to address design issues one by one.

[0090] In the later development stages of integrated circuit (chip) design, complete physical verification of the design data is required. Only after passing all rule checks can it be sent to the foundry for manufacturing. However, the design data may not pass all the check rules in one verification. It needs to be modified and verified repeatedly for gradual convergence. At this time, you can consider splitting the physical verification task containing complete check rules into multiple subtasks. Each subtask is checked and verified independently, thereby shortening the iteration cycle and accelerating the convergence speed. As long as the sum of the check rules of all subtasks can cover all the rule contents that need to be checked and verified, and there are no omissions in the check rules, then such a split combination is reasonable and the physical verification results obtained are credible. After the results of the split verification meet the expectations, you can return to the conventional verification method to verify the final version of the design data. The verification results this time will be predictable and guaranteed, thereby accelerating the progress of the chip design project.

[0091] As shown in FIG4 , an embodiment of the present disclosure provides a device for accelerating physical verification of large-scale integrated circuits, comprising: a memory and a processor, wherein the memory stores a computer program, and when the computer program is executed by the processor, the steps of the method for accelerating physical verification of large-scale integrated circuits are implemented.

[0092] An embodiment of the present disclosure provides a non-transitory computer-readable storage medium storing a computer program. When the computer program is executed by a processor, the steps of the method for accelerating physical verification of large-scale integrated circuits are implemented.

[0093] It will be appreciated by those skilled in the art that the functional modules / units in the apparatus disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In a hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As is well known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those skilled in the art that communication media generally embodies computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0094] It should be noted that the above-described embodiments or implementations are merely illustrative and not restrictive. Therefore, the present disclosure is not limited to what is specifically shown and described herein. Various modifications, substitutions, or omissions may be made to the forms and details of the implementations without departing from the scope of the present disclosure.

Claims

1. A method for accelerating the physical verification of large-scale integrated circuits, including: establishing corresponding physical verification tasks for each round of design in each development stage of the integrated circuit design; for any round of design in any development stage of the integrated circuit design, classifying and grouping the inspection rules in the physical verification inspection rule library according to the process characteristics and / or physical verification requirements of this round of design. Each classification includes at least one focus group. Split the physical verification task of this round of design into at least one subtask, each subtask corresponding to a focus group, and execute all subtasks of each classification in parallel. Each subtask uses the inspection rules included in the corresponding focus group to perform physical verification on this round of design of the integrated circuit.

2. The method according to claim 1, wherein: classifying and grouping the inspection rules in the physical verification inspection rule library according to the process characteristics and / or physical verification requirements of this round of design includes: dividing the inspection rules in the physical verification inspection rule library into two categories: front-end process inspection rules and back-end process inspection rules; generating a front-end process inspection rule set from all front-end process inspection rules, and generating a back-end process inspection rule set from all back-end process inspection rules; eliminating the inspection rules that this round of design does not need and / or does not pay attention to from the front-end process inspection rule set and the back-end process inspection rule set according to the process characteristics and / or physical verification requirements of this round of design, and using the remaining front-end process inspection rule set and back-end process inspection rule set as two inspection rule sets to be grouped; grouping the inspection rules in each inspection rule set to be grouped, and each group is used as a focus group for this round of design.

3. The method according to claim 1, wherein: classifying and grouping the inspection rules in the physical verification inspection rule library according to the process characteristics and / or physical verification requirements of this round of design includes: using the instructions provided by the physical verification tool to determine the focus group of this round of design.

4. The method according to claim 2, wherein: classifying and grouping the inspection rules in the physical verification inspection rule library according to the process characteristics and / or physical verification requirements of this round of design includes: using the instructions provided by the physical verification tool to determine the non-focus group of this round of design.

5. The method according to claim 2, wherein: eliminating the inspection rules that this round of design does not need and / or does not pay attention to from the front-end process inspection rule set and the back-end process inspection rule set according to the process characteristics and / or physical verification requirements of this round of design includes: searching for the inspection rules that this round of design does not need and / or does not pay attention to from the front-end process inspection rule set according to the process characteristics and / or physical verification requirements of this round of design, classifying the found inspection rules into the first non-focus group; eliminating all inspection rules in the first non-focus group from the front-end process inspection rule set; Find the inspection rules that are not required and not concerned in this round of design from the set of post-process inspection rules according to the characteristics of the process flow of this round of design and / or the physical verification requirements, and classify the found inspection rules into the second non-concerned group; remove all the inspection rules in the second non-concerned group from the set of post-process inspection rules.

6. The method according to claim 1, wherein: Group the inspection rules in each inspection rule set to be grouped, including: Group the inspection rules in each inspection rule set to be grouped according to a preset grouping rule, so that the physical verification task amounts between different groups are balanced.

7. The method according to claim 6, wherein: The preset grouping rule includes any one or more combinations of the following: The number of inspection rule entries in different groups is similar or equal; The variance of the verification running time in different groups is less than a preset value.

8. The method according to claim 1, wherein: The types and quantities of inspection rules that are not required and / or not concerned in this round of design are determined by the development stage and the round number in the development stage of the integrated circuit design; If this round of design is in the integrated circuit design development stage that requires complete physical verification, the number of inspection rules that are not required and / or not concerned in this round of design is 0; If this round of design is in the integrated circuit design development stage that does not require complete physical verification, the number of inspection rules that are not required and / or not concerned in this round of design is greater than 0.

9. An apparatus for accelerating the physical verification of large-scale integrated circuits, comprising: A memory and a processor, the memory stores a computer program, and when the computer program is executed by the processor, it implements the steps of the method for accelerating the physical verification of large-scale integrated circuits according to any one of claims 1-8 above.

10. A non-transitory computer-readable storage medium, storing a computer program, and when the computer program is executed by a processor, it implements the steps of the method for accelerating the physical verification of large-scale integrated circuits according to any one of claims 1-8 above.

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