Display substrate and display panel

Abstract

A display substrate, comprising a drive substrate, a planarization layer, an insulating layer and a pixel definition layer, wherein the planarization layer, the insulating layer and the pixel definition layer are sequentially stacked on one side of the drive substrate, and the planarization layer is provided with a plurality of first inclined areas. In the first inclined area, the size of the planarization layer in a first direction is gradually increased from 0 to a maximum value, the first direction being a direction of the planarization layer away from the drive substrate. Orthographic projections of the plurality of first inclined areas and the pixel definition layer on the drive substrate at least partially do not overlap. The insulating layer has at least one boundary. An orthographic projection of at least part of the boundary of the insulating layer on the drive substrate is located outside an orthographic projection area of the first inclined area on the drive substrate.

Description

Display substrate and display panel Technical Field

[0001] The embodiments of the present disclosure belong to the field of display technology, and particularly relate to a display substrate and a display panel. Background Art

[0002] OLED (Organic Light-Emitting Diode) displays have attracted widespread attention due to their advantages such as self-luminescence, low power consumption, lightness, flexibility, brilliant colors, high contrast, and fast response rate.

[0003] Summary of the Invention

[0004] In a first aspect, an embodiment of the present disclosure provides a display substrate, comprising a driving substrate, a planar layer, an insulating layer, and a pixel definition layer, wherein the planar layer, the insulating layer, and the pixel definition layer are sequentially stacked on one side of the driving substrate.

[0005] The flat layer has a plurality of first climbing areas, in which the size of the flat layer along a first direction gradually increases from 0 to a maximum value, and the first direction is a direction of the flat layer away from the driving substrate;

[0006] The plurality of first climbing areas and the orthographic projection of the pixel definition layer on the driving substrate at least partially do not overlap;

[0007] The insulating layer has at least one boundary, and an orthographic projection of at least part of the boundary of the insulating layer on the driving substrate is located outside an orthographic projection area of ​​the first climbing region on the driving substrate.

[0008] In a second aspect, an embodiment of the present disclosure further provides a display substrate, comprising a driving substrate, a planar layer, an insulating layer, and a pixel definition layer, wherein the planar layer, the insulating layer, and the pixel definition layer are sequentially stacked on one side of the driving substrate.

[0009] The flat layer has a flat area and a plurality of first climbing areas, and the flat area and the plurality of first climbing areas are respectively connected.

[0010] The plurality of first climbing areas and the orthographic projection of the pixel definition layer on the driving substrate at least partially do not overlap;

[0011] In the first climbing area, the size of the flat layer along the first direction gradually increases from 0 to a maximum value; in the flat area, the size of any position of the flat layer along the first direction is approximately the maximum value; the first direction is the direction in which the flat layer moves away from the drive substrate;

[0012] The insulating layer has at least one boundary, and the orthographic projection of at least part of the boundary of the insulating layer on the driving substrate is located within the orthographic projection area of ​​the flat area on the driving substrate, or at least part of the boundary of the insulating layer does not overlap with the orthographic projection of the flat layer on the driving substrate.

[0013] In some embodiments, the display substrate has a display area, a hole area, and a hole peripheral area, wherein the hole peripheral area is at least partially disposed around the hole area; and the display area is at least partially disposed around the hole peripheral area.

[0014] The planar layer and the pixel definition layer extend from the display area to the hole peripheral area respectively, and the insulating layer is located in the display area and the hole peripheral area;

[0015] In the hole peripheral area, the cutoff boundaries of the pixel definition layer, the planar layer, and the insulating layer are arranged in sequence along the second direction; in the hole peripheral area, the cutoff boundaries of the pixel definition layer, the planar layer, and the insulating layer are boundaries on one side of the pixel definition layer, the planar layer, and the insulating layer close to the hole area;

[0016] The second direction is a direction in which the hole peripheral area is away from the display area and close to the hole area.

[0017] In some embodiments, a plurality of partition grooves are formed in the insulating layer in the area surrounding the hole, and the plurality of partition grooves are sequentially spaced apart along the second direction to separate the insulating layer into a plurality of partition portions.

[0018] In some embodiments, the orthographic projections of the plurality of partition grooves on the driving substrate are closed around the periphery of the hole area;

[0019] The plurality of partition grooves at least partially overlap with an orthographic projection of the flat area on the driving substrate.

[0020] In some embodiments, the flat layer in the hole peripheral area has the first climbing area and the flat area, and the flat area and the first climbing area are arranged sequentially along the second direction;

[0021] The orthographic projections of the plurality of partition grooves on the driving substrate are located within the orthographic projection region of the flat area on the driving substrate.

[0022] In some embodiments, the number of the partition grooves is 2 to 5.

[0023] In some embodiments, the widths of the plurality of partition portions along the second direction are equal.

[0024] In some embodiments, the widths of the plurality of partition portions along the second direction are different.

[0025] In some embodiments, the partition portion closest to the hole area is a first partition portion, the partition portion closest to the display area is a second partition portion, and the partition portion located between the first partition portion and the second partition portion is a middle partition portion; there is at least one middle partition portion;

[0026] The widths of the first partition portion and the second partition portion along the second direction are respectively greater than the width of the middle partition portion along the second direction;

[0027] A width of the second partition portion along the second direction is greater than a width of the first partition portion along the second direction.

[0028] In some embodiments, the width of the first partition portion along the second direction ranges from 81 to 83 μm;

[0029] The width of the second partition portion along the second direction ranges from 85 to 89 μm;

[0030] The width of the middle partition along the second direction ranges from 75 to 80 μm.

[0031] In some embodiments, the width of the first partition portion along the second direction is 81 μm;

[0032] The width of the second partition portion along the second direction is 88 μm;

[0033] A width of the middle partition along the second direction is 80 μm.

[0034] In some embodiments, a width of any partition portion along the second direction is not less than 10 μm.

[0035] In some embodiments, a width of the partition groove along the second direction is smaller than a width of the partition portion along the second direction.

[0036] In some embodiments, the width of the partition groove along the second direction ranges from 3 μm to 10 μm.

[0037] In some embodiments, a side boundary of the first partition portion close to the hole region is a cutoff boundary of the insulating layer.

[0038] A distance between orthographic projections of a cutoff boundary of the insulating layer and a cutoff boundary of the planar layer on the drive substrate is greater than or equal to 3.5 μm and smaller than a width of the first partition portion along the second direction.

[0039] In some embodiments, a portion of the insulating layer located in the display area and a portion of the insulating layer located in the hole peripheral area are separated from each other in the hole peripheral area.

[0040] The orthographic projection of the pixel definition layer on the driving substrate covers at least a portion of a separation boundary of the insulating layer.

[0041] In some embodiments, a side boundary of the second partition portion close to the hole area is located on a side of a cutoff boundary of the pixel definition layer close to the hole area.

[0042] A distance between a side boundary of the second partition portion close to the hole area and an orthographic projection of a cutoff boundary of the pixel definition layer on the drive substrate is greater than or equal to 3 μm and smaller than a width of the second partition portion along the second direction.

[0043] In some embodiments, a distance between a side boundary of the second partition portion close to the hole area and an orthographic projection of a cutoff boundary of the pixel definition layer on the driving substrate is greater than 5 μm.

[0044] In some embodiments, the driving substrate includes a base, a plurality of conductive layers, and a plurality of inorganic insulating layers.

[0045] The plurality of conductive layers and the plurality of inorganic insulating layers are alternately stacked in sequence on a side of the substrate close to the flat layer;

[0046] The substrate extends from the display area to the hole peripheral area,

[0047] The plurality of conductive layers are located in the display area, and at least part of the conductive layers are also located in the hole peripheral area.

[0048] The plurality of inorganic insulating layers extend from the display area to the hole peripheral area,

[0049] The display substrate further includes a plurality of first spacer columns, a first dam, and a plurality of second spacer columns, wherein the plurality of first spacer columns, the first dam, and the plurality of second spacer columns are located in the hole peripheral area, and the plurality of first spacer columns, the first dam, and the plurality of second spacer columns are sequentially spaced apart along the second direction;

[0050] The plurality of first isolation pillars and the plurality of second isolation pillars are respectively formed by at least one of the conductive layers;

[0051] The first dam includes a first sub-film layer that is the same layer and material as the planar layer and a second sub-film layer that is the same layer and material as the pixel definition layer, and the first sub-film layer and the second sub-film layer are stacked in sequence;

[0052] The multiple first isolation columns, the first dam and the multiple second isolation columns are located on a side of the cut-off boundary of the insulating layer close to the hole area, and the multiple first isolation columns, the first dam and the multiple second isolation columns do not overlap with the orthographic projection of the insulating layer on the substrate.

[0053] In some embodiments, a distance between a cutoff boundary of the insulating layer and a boundary of the first isolation pillar closest to the cutoff boundary of the insulating layer is greater than or equal to 4 μm.

[0054] In some embodiments, the planar layer includes a plurality of sub-layers, and the plurality of sub-layers are stacked in sequence.

[0055] The display substrate further includes a plurality of first traces located in the area surrounding the hole and between two adjacent sub-layers, and at least part of the orthographic projections of the first traces on the driving substrate are located in the flat area.

[0056] The orthographic projections of the first wiring and the partition groove on the driving substrate do not overlap.

[0057] In some embodiments, a distance between adjacent boundaries of the orthographic projection of the first trace and the partition groove on the driving substrate is greater than 1 μm.

[0058] In some embodiments, the partition portion at least partially overlaps with the orthographic projection of the planar layer on the driving substrate.

[0059] The partition portion is provided with a plurality of first vents, the orthographic projections of the plurality of first vents on the drive substrate being located in an overlapping region of the orthographic projections of the partition portion and the flat layer, and the plurality of first vents are evenly distributed;

[0060] The display substrate further includes a plurality of first filling structures, which are arranged in the same layer as the pixel definition layer and made of the same material.

[0061] The plurality of first filling structures correspond to the plurality of first vents one by one, and the orthographic projection of each first filling structure on the driving substrate covers the corresponding first vent.

[0062] In some embodiments, a distance between respective side boundaries of an orthographic projection of the first filling structure and its corresponding first venting port on the driving substrate is greater than or equal to 5 μm.

[0063] In some embodiments, the orthographic projection shape of the first vent on the driving substrate includes a triangle, a rectangle, a circle, an ellipse or a polygon.

[0064] The orthographic projection shape of the first filling structure on the driving substrate includes a triangle, a rectangle, a circle, an ellipse or a polygon.

[0065] In some embodiments, the orthographic projection area of ​​the first vent on the driving substrate is 3×3 μm. 2 ~10×10μm 2 .

[0066] In some embodiments, the well area is at least one,

[0067] The shape of the hole area includes circle, ellipse, capsule or inverted trapezoid.

[0068] In some embodiments, the display substrate further comprises a binding area located on one side of the display area; the binding area comprises a first area,

[0069] At least part of the conductive layer is also located in the first region, and the insulating layer is also located in the first region.

[0070] The display substrate further includes a power supply electrode located in the first area.

[0071] The power electrode includes a first conductive pattern and at least one conductive layer, wherein the at least one conductive layer and the first conductive pattern are sequentially stacked in a direction away from the drive substrate.

[0072] The first conductive pattern is located on a side of the insulating layer away from the drive substrate, and the first conductive pattern partially overlaps with the insulating layer.

[0073] The orthographic projection of the first conductive pattern on the driving substrate covers at least a portion of the overlapping boundary of the insulating layer with the first conductive pattern, and the orthographic projection of the overlapping boundary of the first conductive pattern with the insulating layer on the driving substrate is at least partially located within the orthographic projection area of ​​the insulating layer on the driving substrate.

[0074] In some embodiments, a width of an orthographically overlapping region of the first conductive pattern and the insulating layer on the driving substrate is greater than or equal to 3 μm.

[0075] In some embodiments, a second filling structure is further included, located in the first area, and the second filling structure is disposed in the same layer as the pixel definition layer and is made of the same material.

[0076] The orthographic projection of the second filling structure on the drive substrate covers a first boundary of the insulating layer overlapping with the first conductive pattern and a second boundary of the first conductive pattern overlapping with the insulating layer.

[0077] A distance between an orthographic projection of the first boundary and a boundary of the second filling structure located on a side thereof away from the insulating layer on the drive substrate is greater than or equal to 5 μm;

[0078] A distance between the second boundary and an orthographic projection of a boundary of the second filling structure located on a side of the second filling structure away from the first conductive pattern on the driving substrate is greater than or equal to 10 μm.

[0079] In some embodiments, the binding region further comprises a second region,

[0080] At least part of the conductive layer is located in the second area, and the insulating layer further includes a plurality of partition strips located in the second area.

[0081] The display substrate further includes a power line and a plurality of second dams, at least partially located in the second area;

[0082] In the second area, the plurality of partition bars and the plurality of second dams extend along the third direction respectively, and the plurality of partition bars and the plurality of second dams are alternately arranged in sequence along the fourth direction.

[0083] The planar layer and the pixel definition layer also extend to the second region,

[0084] The second dam includes a third sub-film layer that is the same layer and material as the planar layer and a fourth sub-film layer that is the same layer and material as the pixel definition layer, and the third sub-film layer and the fourth sub-film layer are stacked in sequence;

[0085] The power line includes at least one conductive layer, and the power line extends along the fourth direction;

[0086] The third direction and the fourth direction intersect;

[0087] The power line intersects with the plurality of partition bars and the orthographic projections of the plurality of second dams on the driving substrate;

[0088] A passivation layer is further provided between the power line and the partition bar, and the passivation layer covers the second area;

[0089] The edge region of the partition bar overlaps with the second dam, the planarization layer, and the pixel definition layer, and a portion of the partition bar other than the edge region contacts the passivation layer.

[0090] In some embodiments, a width of an edge region of the partition bar overlapping the pixel definition layer along the fourth direction is greater than or equal to 5 μm.

[0091] In some embodiments, an orthographic projection of a boundary of the partition strip on the flat layer is located in the flat area.

[0092] In some embodiments, in the overlapping area between the partition bar and the power line boundary, a partial boundary of the partition bar extends outward along the extension direction of the power line boundary to form a protrusion, and the protrusion covers a portion of the power line boundary.

[0093] In some embodiments, a dimension of the protrusion along an extension direction of the power line boundary is greater than or equal to 5 μm.

[0094] In some embodiments, the binding area further includes a third area, and the third area is located between the display area and the second dam closest to the display area.

[0095] The planar layer and the pixel definition layer extend from the display area to the third area respectively, and the insulating layer is also located in the third area;

[0096] In the third region, the cutoff boundaries of the pixel definition layer, the planarization layer, and the insulating layer are arranged in sequence along the fifth direction; in the third region, the cutoff boundaries of the pixel definition layer, the planarization layer, and the insulating layer are boundaries on one side of the pixel definition layer, the planarization layer, and the insulating layer close to the second dam;

[0097] The fifth direction is a direction in which the third area is away from the display area and close to the second dam.

[0098] In some embodiments, in the third region, the orthographic projections of the insulating layer and the planar layer on the driving substrate at least partially overlap.

[0099] A plurality of second vents are formed in the insulating layer, the orthographic projections of the plurality of second vents on the driving substrate are located in an overlapping area of ​​the orthographic projections of the insulating layer and the flat layer, and the plurality of second vents are evenly distributed;

[0100] The display substrate further includes a plurality of third filling structures, which are arranged in the same layer as the pixel definition layer and made of the same material.

[0101] The plurality of third filling structures correspond to the plurality of second air release ports one by one, and the orthographic projection of each third filling structure on the driving substrate covers the corresponding second air release port.

[0102] In some embodiments, the flat layer in the third area has the first climbing area and the flat area, and the flat area and the first climbing area are arranged sequentially along the fifth direction;

[0103] The orthographic projections of the plurality of second air discharge ports on the driving substrate are located within the orthographic projection area of ​​the flat area on the driving substrate.

[0104] In some embodiments, in the third region, the planar layer includes a first sublayer, a second sublayer, and a third sublayer, wherein the first sublayer, the second sublayer, and the third sublayer are stacked sequentially away from the driving substrate.

[0105] The first sublayer, the second sublayer, and the third sublayer respectively have the first climbing area and the flat area, and the flat areas and the first climbing areas of the first sublayer, the second sublayer, and the third sublayer are respectively arranged in sequence along the fifth direction;

[0106] The orthographic projections of the plurality of second vents on the driving substrate are located within an overlapping region of the orthographic projections of at least two of the flat areas of the first sub-layer, the second sub-layer, and the third sub-layer on the driving substrate.

[0107] In some embodiments, a second conductive pattern is further included, which is provided in the same layer as the first conductive pattern, and the second conductive pattern is located between the insulating layer and the third filling structure.

[0108] The orthographic projection of the second conductive pattern on the driving substrate at least covers a partial boundary of the second vent.

[0109] The orthographic projection of the boundary of the second conductive pattern on the driving substrate is located within the orthographic projection area of ​​the insulating layer on the driving substrate;

[0110] An orthographic projection of the third filling structure on the driving substrate covers a boundary of the second vent and a boundary of the second conductive pattern.

[0111] In some embodiments, a portion of the insulating layer located in the display area and a portion of the insulating layer located in the third area are separated from each other in the third area.

[0112] The orthographic projection of the pixel definition layer on the driving substrate covers at least a portion of a separation boundary of the insulating layer.

[0113] In some embodiments, the slope angle of the first climbing area ranges from 15° to 80°.

[0114] In some embodiments, a width of an orthographic projection of the first climbing region on the driving substrate along the second direction ranges from 1 to 30 μm.

[0115] In a third aspect, an embodiment of the present disclosure further provides a display panel, which includes the above-mentioned display substrate.

[0116] The display substrate provided by the embodiment of the present disclosure makes the orthographic projection of the boundary of the insulating layer on the driving substrate located within the orthographic projection area of ​​the flat area on the driving substrate, or the orthographic projection of the boundary of the insulating layer on the driving substrate does not overlap with the position or area where any first climbing area in the display substrate does not overlap with the orthographic projection of the pixel definition layer on the driving substrate. In addition, the preparation process of the insulating layer can avoid the formation of a large film layer difference in the flat layer located therebelow, thereby avoiding the inorganic packaging layer for packaging the light-emitting device formed above the display substrate from breaking at the large film layer difference, thereby preventing water vapor from invading from the broken part, and further avoiding the problems of poor reliability GDSH and poor GDSX in the display panel using the display substrate.

[0117] The display panel provided by the embodiment of the present disclosure, by adopting the display substrate of the above embodiment, can improve or avoid reliability GDSH failure and GDSX failure, thereby improving the quality of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0118] The accompanying drawings are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing the detailed exemplary embodiments with reference to the accompanying drawings, in which:

[0119] FIG. 1 a is a schematic structural diagram of a light-emitting unit in an OLED display panel according to a related art.

[0120] FIG. 1 b is a partial cross-sectional view of an embodiment of a display area of ​​an OLED display panel in the related art.

[0121] FIG. 1c is a schematic top view of the structure of an OLED display panel in the related art.

[0122] FIG. 1 d is a schematic top view of a hole peripheral area of ​​an OLED display panel in the related art.

[0123] FIG. 1e is a schematic top view of the cutoff position of the insulating layer in the peripheral area of ​​the hole of the OLED display panel in the related art.

[0124] FIG. 1f is a focused ion beam image taken along the AA′ section line in FIG. 1e .

[0125] FIG. 2 a is a schematic top view of the structure of a display substrate in an embodiment of the present disclosure.

[0126] FIG. 2 b is a schematic top view of a local structure of a peripheral area of ​​a hole in a substrate according to an embodiment of the present disclosure.

[0127] FIG2c is a schematic cross-sectional view of the structure along the BB′ section line in FIG2b.

[0128] FIG. 2 d is a schematic top view showing the arrangement of the partition grooves in the insulating layer in the peripheral area of ​​the substrate hole according to an embodiment of the present disclosure.

[0129] FIG2e is an enlarged top view of the partition groove and the partition portion surrounding the periphery of the hole area in the embodiment of the present disclosure.

[0130] FIG2f is a schematic diagram showing the number and shape of the hole areas in an embodiment of the present disclosure.

[0131] FIG. 2g is a schematic top view showing the distribution of first isolation columns, first dams, and second isolation columns in a substrate according to an embodiment of the present disclosure.

[0132] FIG. 2 h is a partial cross-sectional view of an embodiment of a display area of ​​a display panel using the display substrate in the embodiment of the present disclosure.

[0133] FIG. 2i is a top view showing the local structure of the flat area of ​​the flat layer in the periphery of the hole in the substrate according to an embodiment of the present disclosure.

[0134] FIG. 3 a is a top view showing the local structure of the overlapping area between the insulating layer and the planar layer in the peripheral area of ​​the hole in the substrate according to an embodiment of the present disclosure.

[0135] FIG3 b is a schematic cross-sectional view of the structure along the CC′ section line in FIG3 a .

[0136] FIG. 4 a is a schematic top view showing the structure of the first region in the substrate according to an embodiment of the present disclosure.

[0137] FIG4 b is a cross-sectional view of the structure along the DD′ section line in FIG4 a .

[0138] FIG. 5 a is a schematic top view showing the structure of the second region in the substrate according to an embodiment of the present disclosure.

[0139] FIG5b is an enlarged top view of portion E in FIG5a.

[0140] FIG5c is a cross-sectional view of the structure along the FF′ section line in FIG5b.

[0141] FIG. 6 a is a schematic top view showing the structure of the third region in the substrate according to an embodiment of the present disclosure.

[0142] FIG6 b is a cross-sectional view of the structure along the GG′ section line in FIG6 a .

[0143] FIG. 6 c is a schematic top view showing a second conductive pattern and a second vent in a substrate according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0144] In order to enable those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, a display substrate and a display panel provided by the embodiments of the present disclosure are further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0145] The embodiments of the present disclosure will be described more fully below with reference to the accompanying drawings, but the illustrated embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully enable those skilled in the art to understand the scope of this disclosure.

[0146] The embodiments of the present disclosure are not limited to the embodiments shown in the drawings, but include modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the drawings are schematic in nature, and the shapes of the regions shown in the drawings illustrate specific shapes of the regions, but are not intended to be limiting.

[0147] In the related art, the OLED display panel includes a driving substrate and an organic material layer, wherein: the organic material layer is arranged on one side of the driving substrate and includes a plurality of light-emitting units, the light-emitting unit may include one or more light-emitting devices connected in series, the light-emitting device may adopt an organic light-emitting diode, which may include an anode, an organic material layer and a cathode stacked in sequence in a direction away from the driving substrate. By applying an electrical signal to the anode and the cathode, the organic material layer can be driven to emit light. The specific light-emitting principle of the light-emitting device will not be described in detail here.

[0148] Among them, the organic material layer of each light-emitting device can achieve color display by emitting monochromatic light or white light in conjunction with a color filter. That is, each light-emitting device shares the same continuous organic material layer, and the organic material layer can emit white light or other monochromatic light. The color filter layer has multiple filter parts that correspond one-to-one with the light-emitting units. A filter part and the corresponding light-emitting unit can constitute a sub-pixel, and multiple sub-pixels constitute a pixel. Different filter parts can transmit different colors of light, so that different sub-pixels can emit different colors. The same pixel can include multiple sub-pixels of different colors. For example, a pixel can include three sub-pixels that emit red, green, and blue colors respectively. In this way, color display can be achieved through multiple pixels.

[0149] In the related art, the organic material layer is a continuous whole-layer structure, which makes it easy for leakage to occur between a light-emitting unit and the surrounding light-emitting units, resulting in cross-color. Each light-emitting unit may include multiple light-emitting devices connected in series. The light-emitting devices of the same light-emitting unit share an anode and a cathode. There are multiple light-emitting sublayers between the anode and the cathode, and at least two adjacent light-emitting sublayers can be connected in series through a charge generation layer. Positive charges (holes) can be transferred between two adjacent light-emitting units through the charge generation layer. For example, when the light-emitting unit of the red filter part in the corresponding color filter layer emits light, due to the influence of leakage, the light-emitting unit of the green filter part in the corresponding color filter layer will also emit light, resulting in a decrease in the purity of the light emission of a single pixel and a decrease in the color gamut of the entire display panel.

[0150] In some embodiments, referring to FIG. 1a , a schematic diagram of the structure of a light-emitting unit in a related art OLED display panel is shown. The light-emitting unit may include multiple light-emitting devices LD connected in series. Each light-emitting unit includes an anode ANO, a cathode CAT, and multiple light-emitting sublayers OLP between the anode ANO and the cathode CAT. The light-emitting devices LD in the same light-emitting unit may share the same anode ANO and the same cathode CAT. In other words, the same light-emitting unit may have only one anode ANO and one cathode CAT.

[0151] For example, referring to Figure 1a , the organic material layer may include multiple sub-layers (OLP) connected in series, facing away from the drive substrate. At least one sub-layer (OLP) is connected in series to an adjacent sub-layer (OLP) via a charge generation layer (CGL). When an electrical signal is applied to the anode (ANO) and cathode (CAT), each sub-layer (OLP) emits light, and different sub-layers (OLP) can be used to emit light of different colors.

[0152] In some embodiments, referring to FIG. 1 a , any light-emitting sublayer OLP may include a hole injection layer HIL, a hole transport layer HTL, a light-emitting material layer EML, an electron transport layer ETL, and an electron injection layer EIL, arranged in a direction away from the drive substrate. The specific light-emitting principle is not further described herein. The number of hole injection layers HIL, hole transport layers HTL, electron transport layers ETL, and electron injection layers EIL is not specifically limited, and adjacent light-emitting sublayers OLP may share one or more of the hole injection layer HIL, hole transport layer HTL, electron transport layer ETL, and electron injection layer EIL. Furthermore, a charge generation layer CGL may be provided between at least two adjacent light-emitting sublayers OLP, thereby connecting the two sublayers OLP in series.

[0153] In some embodiments, referring to FIG. 1a , the organic material layer may include three sublayers (OLP) of different colors: a first sublayer (OLPr) emitting red light, a second sublayer (OLPg) emitting green light, and a third sublayer (OLPb) emitting blue light. When the first, second, and third sublayers (OLPr, OLPg, and OLPb) emit light simultaneously, the organic material layer (OL) emits white light. The first and second sublayers (OLPr, OLPg) share a hole injection layer (HIL), a hole transport layer (HTL1), an electron transport layer (ETL2), and an electron injection layer (EIL). The light-emitting material layer (G-EML) of the second sublayer (OLPg) is located on the surface of the light-emitting material layer (R-EML) of the first sublayer (OLPr) facing away from the drive substrate, thereby directly connecting the first and second sublayers (OLPr, OLPg) in series without requiring a dedicated charge generation layer. A charge generation layer (CGL) may be provided on the surface of the second sublayer (OLPg) facing away from the drive substrate. The third sublayer OLPb shares a common electron injection layer (EIL) with the first and second sublayers OLPr and OLPg. Its hole injection layer (HIL2) is located on the surface of the charge generation layer (CGL) facing away from the drive substrate. Its hole transport layers (HTL2 and HTL3) are stacked on the side of the charge generation layer (CGL) facing away from the drive substrate. The charge generation layer (CGL) connects the third sublayer OLPb in series with the second and first sublayers OLPg and OLPr. Furthermore, a hole-first insulating layer (HBL) can be provided between the electron transport layer (HYL) and the light-emitting material layer (BEML) of the third sublayer OLPb.

[0154] The organic material layer OL structure in FIG1a is for illustrative purposes only and does not constitute a limitation on its film layer. It may include only two sub-layers OLP, or more, or only one sub-layer OLP, as long as it can cooperate with the color filter layer to achieve color display.

[0155] In some embodiments, since the light-emitting units share an organic material layer, the carriers (e.g., holes) of one light-emitting unit may move through film layers such as the charge generation layer CGL to other light-emitting units, especially to adjacent light-emitting units, causing leakage, affecting the purity of the light emission, and causing cross-color.

[0156] In the related art, as shown in FIG1b, it is a partial cross-sectional view of an embodiment of the display area of ​​the OLED display panel in the related art, wherein the OLED display panel may include a driving substrate, a plurality of anodes 12, a pixel definition layer 4, an organic material layer 8, a cathode 9, an encapsulation layer 13 and a polarizer 14, wherein the pixel definition layer 4 and the anode 12 are arranged on the same side of the driving substrate, a plurality of first openings are opened in the pixel definition layer 4, and the anode 12 is exposed at the first opening; the driving substrate includes a base 10, a pixel circuit 11, a flat layer 2 and an insulating layer 3 arranged on one side of the base 10 in sequence, and the anode 12 is located on the side of the insulating layer 3 away from the base 10; the pixel definition layer 4 is located on the anode 1 2 is located on the side of the pixel definition layer 4 away from the substrate 10; the organic material layer 8 is located on the side of the pixel definition layer 4 away from the substrate 10, and the organic material layer 8 covers the entire display area; the cathode 9 is located on the side of the organic material layer 8 away from the substrate 10, and the cathode 9 covers the organic material layer 8; any anode 12 in the OLED display panel and its corresponding organic material layer 8 and cathode 9 can constitute a light-emitting unit, and the pixel definition layer 4 can separate each light-emitting unit and define the range of each light-emitting unit; the encapsulation layer 13 is located on the side of the cathode 9 away from the substrate 10, and is used to encapsulate the light-emitting unit; the polarizer 14 is located on the side of the encapsulation layer 13 away from the substrate 10, and is used to reduce the reflection of ambient light by the OLED display panel.

[0157] As shown in Figure 1b, a second opening is also defined in pixel definition layer 4. This second opening is located outside the region corresponding to anode 12. A recess 300 is defined in the region corresponding to insulating layer 3 and planar layer 2. The cross-section of recess 300, perpendicular to the substrate, is trapezoidal. This second opening and the narrower-at-top, wider-at-bottom trapezoidal recess 300 disconnect at least a portion of the organic material layer 8 recessed therein, thereby preventing carrier migration between light-emitting units and, consequently, avoiding color crosstalk caused by leakage.

[0158] In some embodiments, as shown in Figures 1c and 1d, Figure 1c is a schematic top view of the structure of the OLED display panel in the related art; Figure 1d is a schematic top view of the hole peripheral area of ​​the OLED display panel in the related art; a through hole 200 is provided in the display area 100 of the OLED display panel, which penetrates its thickness, and the through hole 200 is used to install a camera. Part of the insulating layer 3 is also located in the hole peripheral area 102 of the through hole 200, and a partition groove 30 is provided in the insulating layer 3 in the hole peripheral area 102. The partition groove 30 is used to further isolate the organic material layer and the cathode layer extending from the display area 100 to the hole peripheral area 102. Under reliability test conditions, the OLED display panel with a partition groove 30 opened in the insulating layer 3 of the hole peripheral area 102 has an incidence rate of display black spot phenomenon (GDSH) at the boundary between the display area 100 and the hole peripheral area 102 of 10%. In order to further reduce the incidence rate of GDSH, it is necessary to further improve the power-off effect of the organic material layer and the cathode in the hole peripheral area 102, and at the same time, it is necessary to further optimize the cut-off position of the insulating layer 3 in the hole peripheral area 102.

[0159] In some embodiments, as shown in Figures 1e and 1f, Figure 1e is a top view schematic diagram of the cut-off position of the insulating layer in the hole peripheral area of ​​the OLED display panel in the related art; Figure 1f is a focused ion beam image along the AA' section line in Figure 1e; wherein, the flat layer 2 extends from the display area 100 to the hole peripheral area 102, and the flat layer 2 forms a climbing area 203 at the cut-off position in the hole peripheral area 102; the cut-off position s1 of the insulating layer 3 in the hole peripheral area 102, which is close to the hole area 101, is located in the climbing area 203 of the flat layer 2. For example, the cut-off position s1 of the insulating layer 3 close to the hole area 101 is 2.55 μm away from the cut-off position s2 of the flat layer 2 close to the hole area 101. In addition, due to the influence of fluctuations in the actual film layer stacking process, the cut-off position s1 of the insulating layer 3 close to the hole area 101 may be located on the upper part of the climbing area 203 of the flat layer 2, which is close to its flat area 201. During the process of preparing the insulating layer 3, a depression of approximately 2000 angstroms is dry-etched into the planar layer 2 beneath the insulating layer 3 at the cutoff position s1. Furthermore, to prevent moisture intrusion along the organic layer and resulting in GDSH defects, the pixel definition layer is removed at this location. Therefore, the pixel definition layer cannot fill the cutoff position s1 in the planar layer 2 and the discontinuity of the insulating layer 3 at the cutoff position s1. This causes a significant crack in the inorganic encapsulation layer 131 on the side of the insulating layer 3 facing away from the planar layer 2, allowing moisture to intrude through the cracked inorganic encapsulation layer 131, resulting in even more severe GDSH defects. Furthermore, significant anomalies in the insulating layer 3 are observed in the overall climbing region 203 of the planar layer 2. This is suspected to be due to the stress difference in the film layer at this location caused by the cracked inorganic encapsulation layer 131. Therefore, the cutoff position design of the insulating layer in the hole periphery area needs to be improved.

[0160] In some embodiments, the insulating layer is also applied to the border area (such as the binding side border area) to protect the exposed metal conductive structure, but the cutoff position of the insulating layer in the border area is located in the climbing area of ​​the flat layer or the cutoff position of the metal conductive structure (such as the conductive structure in the border area and the anode in the display area, which is in direct contact with the insulating layer or other inorganic insulating layers can be sandwiched between the two). A large film layer discontinuity will be formed, thereby causing the inorganic packaging layer above the film layer discontinuity to break (CVD Crack). In particular, when the cutoff position of the insulating layer is located in the climbing area of ​​three stacked flat layers, the risk of the inorganic packaging layer breaking is even more uncontrollable, and water vapor invades from the broken position of the inorganic packaging layer, eventually leading to poor reliability GDSH and GDSX of the OLED display panel (that is, poor packaging of the border area allows water vapor to enter, resulting in poor display in the display area).

[0161] In order to solve the problem of poor GDSH and GDSX reliability of OLED display panels caused by the cut-off position design of the insulating layer in the related art, on the first aspect, the present embodiment provides a display substrate, which includes a driving substrate, a flat layer, an insulating layer and a pixel definition layer, and the flat layer, the insulating layer and the pixel definition layer are stacked in sequence on one side of the driving substrate, and the flat layer has a plurality of first climbing areas. In the first climbing area, the size of the flat layer along the first direction gradually increases from 0 to a maximum value, and the first direction is the direction of the flat layer away from the driving substrate; the plurality of first climbing areas and the positive projection of the pixel definition layer on the driving substrate do not overlap at least partially; the insulating layer has at least one boundary, and the positive projection of at least part of the boundary of the insulating layer on the driving substrate is located outside the positive projection area of ​​the first climbing area on the driving substrate.

[0162] In some embodiments, the display substrate has a display area, in which a plurality of anodes are arranged between the insulating layer and the pixel definition layer. A plurality of openings are provided in the pixel definition layer, and the plurality of anodes correspond to the plurality of openings, respectively. The anodes are at least partially exposed at the corresponding openings. Subsequently, an organic material layer and a cathode are sequentially formed on the side of the pixel definition layer away from the driving substrate. The organic material layer covers the entire display area, and the cathode covers the organic material layer. Any anode in the display substrate and its corresponding organic material layer and cathode can constitute a light-emitting device. The pixel definition layer can separate the light-emitting devices and define the range of each light-emitting device. The encapsulation layer is located on the side of the cathode away from the driving substrate and is used to encapsulate the light-emitting device. The encapsulation layer is an inorganic encapsulation layer, an organic encapsulation layer, and an inorganic encapsulation layer stacked in sequence. The organic material layer can be made of organic electroluminescent material.

[0163] Among them, since the multiple first climbing areas do not overlap with the orthographic projection of the pixel definition layer on the driving substrate, when the boundary of the insulating layer is located on the first climbing area, a larger film layer step will be formed in the first climbing area. In addition, the boundary step of the insulating layer at this position, if the pixel definition layer is not set above the position of the larger step, the larger step cannot be reduced or filled by the pixel definition layer, which makes it easier for the inorganic packaging layer that encapsulates the light-emitting device formed above the display substrate to break.

[0164] In this embodiment, by making the orthographic projection of the boundary of the insulating layer on the driving substrate outside the orthographic projection area of ​​the first climbing area on the driving substrate at a position or area where any first climbing area in the display substrate does not overlap with the orthographic projection of the pixel definition layer on the driving substrate, the preparation process of the insulating layer can be prevented from forming a large film layer step in the flat layer located thereunder, thereby preventing the inorganic packaging layer for packaging the light-emitting device formed above the display substrate from breaking at the large film layer step, thereby preventing water vapor from invading from the fracture, and further avoiding the problems of poor reliability GDSH and poor GDSX in the display panel using the display substrate.

[0165] The present disclosure also provides a display substrate, referring to Figures 2a, 2b, and 2c. Figure 2a is a schematic top view of the structure of the display substrate in the present disclosure; Figure 2b is a schematic top view of the local structure of the peripheral area of ​​the hole in the display substrate in the present disclosure; and Figure 2c is a schematic cross-sectional view of the structure along the BB' section line in Figure 2b. The display substrate includes a driving substrate 1, a flat layer 2, an insulating layer 3, and a pixel definition layer 4. The flat layer 2, the insulating layer 3, and the pixel definition layer 4 are sequentially stacked on one side of the driving substrate 1. The flat layer 2 has a flat area 201 and a plurality of first climbing areas 202. The flat area 201 and the plurality of first climbing areas 202 are respectively connected. The multiple first climbing areas 201 do not overlap with the orthographic projections of the pixel definition layer 4 on the driving substrate 1 at least partially; in the first climbing area 202, the size of the flat layer 2 along the first direction Z gradually increases from 0 to a maximum value; in the flat area 201, the size of any position of the flat layer 2 along the first direction Z is approximately the maximum value; the first direction Z is the direction of the flat layer 2 away from the driving substrate 1; the insulating layer 3 has at least one boundary, and the orthographic projection of at least part of the boundary of the insulating layer 3 on the driving substrate 1 is located within the orthographic projection area of ​​the flat area 201 on the driving substrate 1, or, at least part of the boundary of the insulating layer 3 does not overlap with the orthographic projection of the flat layer 2 on the driving substrate 1.

[0166] The first climbing region 202 refers only to the region formed at the boundary of the planar layer 2, where the size along the first direction Z gradually increases from 0 to a maximum value. The climbing regions formed by partially raising the planar layer 2 by some film layers in the drive substrate 1 and partially not raising the planar layer 2 by some film layers in the drive substrate 1 do not constitute the first climbing region as claimed in this application.

[0167] In some embodiments, the slope angle α of the first climbing region 202 ranges from 15° to 80°. In some embodiments, when the boundary of the planar layer 2 has a structural feature in which the dimension along the first direction Z gradually increases from 0 to a maximum value, if the slope angle formed at the boundary of the planar layer 2 is less than 15°, the climbing region formed at the boundary of the planar layer 2 is not the first climbing region claimed in this application, and at least a portion of the boundary of the insulating layer 2 may overlap with the orthographic projection of the climbing region at the boundary of the planar layer 2 on the drive substrate 1.

[0168] In this embodiment, by making any first climbing area 202 in the display substrate not overlap with the orthographic projection of the pixel definition layer 4 on the driving substrate 1 at a position or area where the orthographic projection of the boundary of the insulating layer 3 on the driving substrate 1 is located within the orthographic projection area of ​​the flat area 201 on the driving substrate 1, or, the boundary of the insulating layer 3 does not overlap with the orthographic projection of the flat layer 2 on the driving substrate 1, it can avoid the preparation process of the insulating layer 3 from forming a large film layer discontinuity in the flat layer located thereunder, thereby avoiding the inorganic packaging layer for packaging the light-emitting device formed above the display substrate from breaking at the large film layer discontinuity, thereby preventing water vapor from invading from the broken part, and then avoiding the problems of poor reliability GDSH and poor GDSX in the display panel using the display substrate.

[0169] In some embodiments, referring to Figures 2a, 2b and 2c, the display substrate has a display area 100, a hole area 101 and a hole peripheral area 102, and the hole peripheral area 102 is at least partially surrounded by the hole area 101; the display area 100 is at least partially surrounded by the hole peripheral area 102; the planar layer 2 and the pixel definition layer 4 extend from the display area 100 to the hole peripheral area 102, respectively, and the insulating layer 3 is located in the display area 100 and the hole peripheral area 102; in the hole peripheral area 102, the cutoff boundaries a, b, c of the pixel definition layer 4, the planar layer 2 and the insulating layer 3 are arranged in sequence along the second direction X; in the hole peripheral area 102, the cutoff boundaries a, b, c of the pixel definition layer 4, the planar layer 2 and the insulating layer 3 are the side boundaries of the pixel definition layer 4, the planar layer 2 and the insulating layer 3 close to the hole area 101; the second direction X is the direction of the hole peripheral area 102 away from the display area 100 and close to the hole area 101.

[0170] The pixel definition layer 4, planar layer 2, and insulating layer 3 are extensively laid out in the display area 100 and the aperture perimeter area 102. Within the aperture perimeter area 102, the cutoff boundary a of the pixel definition layer 4, the cutoff boundary b of the planar layer 2, and the cutoff boundary c of the insulating layer 3 refer to the boundaries of the pixel definition layer 4, planar layer 2, and insulating layer 3 extensively laid out in the aperture perimeter area 102, extending to the side close to the aperture area 101. In some embodiments, the cutoff boundary a of the pixel definition layer 4 and the cutoff boundary b of the planar layer 2 refer to the boundaries of the portion extending from the display area 100 to the aperture perimeter area 102, and the cutoff boundary c of the insulating layer 3 refers to the boundary of the insulating layer 3 pattern located in the aperture perimeter area 102, close to the aperture area 01. The cutoff boundaries a, b, and c of the pixel definition layer 4, planar layer 2, and insulating layer 3 do not mean that these layers cease at this point; rather, the patterns are disconnected at the cutoff boundaries.

[0171] In this embodiment, referring to Figures 2b and 2c, the orthographic projection of the insulating layer 3 on the driving substrate 1 covers the cutoff boundary b of the flat layer 2, that is, the cutoff boundary c of the insulating layer 3 does not overlap with the orthographic projection of the flat layer 2 on the driving substrate 1, thereby avoiding the formation of a large film layer discontinuity in the flat layer 2 located thereunder during the preparation process of the insulating layer 3, thereby avoiding the inorganic packaging layer for encapsulating the light-emitting device formed above the display substrate from breaking at the large film layer discontinuity, and then preventing water vapor from invading from the broken part, thereby avoiding the problems of poor reliability GDSH and poor GDSX in the display panel using the display substrate.

[0172] In some embodiments, referring to Figures 2b, 2c, and 2d, Figure 2d is a top view schematically illustrating the arrangement of partition grooves in the insulating layer within the hole periphery region of the substrate according to an embodiment of the present disclosure; a plurality of partition grooves 30 are provided in the insulating layer 3 within the hole periphery region 102. The plurality of partition grooves 30 are sequentially spaced apart along the second direction X to separate the insulating layer 3 into a plurality of partition portions 31. The provision of the plurality of partition grooves 30 can further isolate the organic material layer and cathode layer extending from the display area 100 to the hole periphery region 102, thereby further improving the power-off effect of the hole periphery region 102 and further reducing the incidence of GDSH.

[0173] In some embodiments, referring to Figures 2d and 2e, Figure 2e is an enlarged top view of the partition grooves and partition portions surrounding the periphery of the hole area in an embodiment of the present disclosure; wherein, the orthographic projections of the plurality of partition grooves 30 on the driving substrate 1 are closed around the periphery of the hole area 101; and the orthographic projections of the plurality of partition portions 31 on the driving substrate 1 are closed around the periphery of the hole area 101. That is, the plurality of partition grooves 30 are all annular, and the plurality of partition portions 31 are also all annular, which further improves the power-off effect of the hole periphery area 102, thereby further reducing the incidence of GDSH.

[0174] In some embodiments, referring to FIG. 2f , a schematic diagram illustrating the number and shape of aperture regions in an embodiment of the present disclosure is provided. There is at least one aperture region 101, and the shapes of aperture region 101 include circular, elliptical, capsule-shaped, or inverted trapezoidal. For example, aperture region 101 may be a single aperture region, a double aperture region, or a triple aperture region. For another example, the aperture region 101 may be shaped like a circular hole, a racetrack-shaped hole, or a pill-shaped hole.

[0175] In some embodiments, referring to Figure 2f, the hole area 101 can be a closed hole or a non-closed hole. For example, an inverted trapezoidal or bangs-shaped hole are both non-closed holes. A non-closed hole refers to a hole area 101 in the display area 100 where the display area 100 is not set on at least one side of the hole area 101. Accordingly, for the non-closed hole area 101, the partition groove 30 and the partition portion 31 surrounding the periphery of the hole area 101 are also not closed, that is, the partition groove 30 and the partition portion 31 are only located in the hole peripheral area 102 at the junction of the hole area 101 and the display area 100.

[0176] In some embodiments, referring to Figure 2c, the flat layer 2 within the hole peripheral area 102 has a first climbing area 202 and a flat area 201, and the flat area 201 and the first climbing area 202 are arranged in sequence along the second direction X; the plurality of partition grooves 30 at least partially overlap with the orthographic projection of the flat area 201 on the driving substrate 1.

[0177] In some embodiments, a width s of an orthographic projection of the first climbing region 202 on the driving substrate 1 along the second direction X ranges from 1 μm to 30 μm.

[0178] In some embodiments, the orthographic projections of the plurality of partition grooves 30 on the driving substrate 1 are located within the orthographic projection area of ​​the flat area 201 on the driving substrate 1 . With such a configuration, a depression 20 with a depth of about 2000 angstroms will be dry-etched in the flat area 201 of the flat layer 2 below the insulating layer 3 corresponding to the position of the partition groove 30. On the one hand, the partition groove 30 and the depression 20 can further isolate the organic material layer and the cathode layer extending from the display area 100 to the hole peripheral area 102, thereby further improving the power-off effect of the hole peripheral area 102, and further reducing the incidence of GDSH; on the other hand, the partition groove 30 is located in the flat area 201 of the flat layer 2, which can prevent the preparation process of the insulating layer 3 from forming a large and irregular film layer difference in the flat area 201 of the flat layer 2 located below it, thereby preventing the inorganic packaging layer for packaging the light-emitting device formed above the display substrate from breaking at the large and irregular film layer difference, thereby preventing water vapor from invading from the broken part, and then avoiding the display panel using the display substrate from having poor reliability GDSH and poor GDSX.

[0179] In some embodiments, the number of partition grooves 30 is 2 to 5. Compared to the solution of the related art in which only one partition groove is provided in the insulating layer in the hole peripheral area, the number of partition grooves 30 in this embodiment is increased, which can further isolate the organic material layer and cathode layer extending from the display area 100 to the hole peripheral area 102, thereby further improving the power-off effect of the hole peripheral area 102 and further reducing the incidence of GDSH.

[0180] In some embodiments, the widths of the plurality of partition portions 31 along the second direction X are equal.

[0181] In some embodiments, referring to FIG. 2 b , the widths of the plurality of partition portions 31 along the second direction X are different.

[0182] In some embodiments, referring to Figure 2b, the partition portion 31 closest to the hole area 101 is the first partition portion 310, the partition portion 31 closest to the display area 100 is the second partition portion 311, and the partition portion 31 located between the first partition portion 310 and the second partition portion 311 is the middle partition portion 312; there is at least one middle partition portion 312; the widths d1 and d2 of the first partition portion 310 and the second partition portion 311 along the second direction X are respectively greater than the width d3 of the middle partition portion 312 along the second direction X; the width d2 of the second partition portion 311 along the second direction X is greater than the width d1 of the first partition portion 310 along the second direction X.

[0183] 2 b , a width d1 of the first partition portion 310 along the second direction X ranges from 81 to 83 μm; a width d2 of the second partition portion 311 along the second direction X ranges from 85 to 89 μm; and a width d3 of the middle partition portion 312 along the second direction X ranges from 75 to 80 μm.

[0184] In some embodiments, the width d1 of the first partition portion 310 along the second direction X is 81 μm; the width d2 of the second partition portion 311 along the second direction X is 88 μm; and the width d3 of the middle partition portion 312 along the second direction X is 80 μm.

[0185] In some embodiments, the width of any partition portion 3 along the second direction X is not less than 10 μm.

[0186] In some embodiments, the minimum and maximum widths of the partition portion 3 along the second direction X are mainly based on the limitations of the cutoff boundary a of the pixel definition layer 4, the cutoff boundary b of the flat layer 2, and the cutoff boundary c of the insulating layer 3, as well as the limitations of the width of the hole peripheral area 102, while taking into account the risk of peeling off on the contact surface between the insulating layer 3 and the flat layer 2, and are determined based on actual process capabilities and actual product design.

[0187] In some embodiments, referring to FIG. 2 b , the width of the partition groove 30 along the second direction X is smaller than the width of the partition portion 31 along the second direction X. This is more conducive to further isolating the organic material layer and cathode layer extending from the display area 100 to the hole peripheral area 102 , thereby further improving the power-off effect of the hole peripheral area 102 .

[0188] 2b , the width e of the partitioning groove 30 along the second direction X ranges from 3 to 10 μm. For example, the width e of the partitioning groove 30 along the second direction X can be any value such as 10 μm, 9 μm, 8 μm, 7 μm, 6 μm, 5 μm, 4 μm, or 3 μm.

[0189] In some embodiments, referring to Figures 2b and 2c, a boundary of the first partition portion 310 adjacent to the hole region 101 is a cutoff boundary c of the insulating layer 3, and a distance f between the orthographic projections of the cutoff boundary c of the insulating layer 3 and the cutoff boundary b of the planar layer 2 on the driver substrate 1 is greater than or equal to 3.5 μm and less than a width d1 of the first partition portion 310 along the second direction X. This ensures that the cutoff boundary c of the insulating layer 3 and the orthographic projection of the planar layer 2 on the driver substrate 1 do not overlap, i.e., the insulating layer 3 covers the starting position of the first climbing region 202 of the planar layer 2, thereby preventing a large film step in the first climbing region 202 of the planar layer 2 located therebelow during the preparation process of the insulating layer 3. This further prevents the inorganic encapsulation layer encapsulating the light-emitting device formed above the display substrate from breaking at the large film step, thereby preventing moisture intrusion through the break, and avoiding reliability issues such as poor GDSH and GDSX in a display panel using the display substrate.

[0190] In some embodiments, referring to Figures 2b and 2c, the portion of the insulating layer 3 located in the display area 100 and the portion located in the aperture perimeter area 102 are separated from each other in the aperture perimeter area 102, and the orthographic projection of the pixel definition layer 4 on the drive substrate 1 covers at least a portion of the separation boundary of the insulating layer 3. The separation boundary of the insulating layer 3 is formed by the pattern of the portion located in the display area 100 and the pattern of the portion located in the aperture perimeter area 102, which are separated from each other in the aperture perimeter area 102. The pixel definition layer 4 extends from the display area 100 to the aperture perimeter area 102, and a flat layer 2 is provided below the disconnected portion of the insulating layer 3. With this configuration, the pixel definition layer 4 can fill the large film discontinuity formed at the disconnected portion of the insulating layer 3 (including the thickness discontinuity of the insulating layer 3 and the concave discontinuity formed in the underlying flat layer 2), thereby preventing the large film discontinuity at the disconnected portion of the insulating layer 3 from causing the inorganic encapsulation layer to break. This prevents moisture from invading through the discontinuity, thus avoiding reliability issues such as poor GDSH and GDSX in display panels using this display substrate.

[0191] In some embodiments, referring to Figures 2b and 2c, a side boundary g of the second partition portion 311 near the hole region 101 is located on a side of the cutoff boundary a of the pixel definition layer 4 near the hole region 101, and a distance h between the side boundary g of the second partition portion 311 near the hole region 101 and the orthographic projection of the cutoff boundary a of the pixel definition layer 4 on the drive substrate 1 is greater than or equal to 3 μm and less than a width d2 of the second partition portion 311 along the second direction X. This configuration ensures that the pixel definition layer 4 completely covers the disconnection boundary of the insulating layer 3 at the disconnection location of the hole peripheral region 102, thereby fully filling the large film discontinuity formed in the insulating layer 3 at the disconnection location, thereby preventing the large film discontinuity at the disconnection location of the insulating layer 3 from causing the inorganic encapsulation layer to break.

[0192] 2 b and 2 c , a distance h between a side boundary g of the second partition portion 311 close to the hole area 101 and an orthographic projection of a cutoff boundary a of the pixel definition layer 4 on the driving substrate 1 is greater than 5 μm.

[0193] In some embodiments, referring to Figures 2b and 2c, the driving substrate 1 includes a base, multiple conductive layers, and multiple inorganic insulating layers, which are alternately stacked on one side of the base close to the flat layer 2; the base extends from the display area 100 to the hole peripheral area 102, the multiple conductive layers are located in the display area 100, at least part of the conductive layers are located in the hole peripheral area 102, the multiple inorganic insulating layers extend from the display area 100 to the hole peripheral area 102, the display substrate further includes multiple first isolation columns 5, a first dam 6, and multiple second isolation columns 7, the multiple first isolation columns 5, the first dam 6, and the multiple second isolation columns 7 are located in the hole peripheral area 102, And multiple first isolation columns 5, first dams 6 and multiple second isolation columns 7 are arranged in sequence along the second direction X; the multiple first isolation columns 5 and the multiple second isolation columns 7 are respectively formed by at least one conductive layer; the first dam 6 includes a first sub-membrane layer of the same layer and material as the flat layer 2 and a second sub-membrane layer of the same layer and material as the pixel definition layer 4, and the first sub-membrane layer and the second sub-membrane layer are stacked in sequence; the multiple first isolation columns 5, the first dam 6 and the multiple second isolation columns 7 are located on the side of the cut-off boundary c of the insulating layer 3 close to the hole area 101, and the multiple first isolation columns 5, the first dam 6 and the multiple second isolation columns 7 do not overlap with the positive projection of the insulating layer 3 on the substrate.

[0194] The first spacer 5 and the second spacer 7 are used to isolate the organic material layer and the cathode layer extending from the display area 100 to the hole peripheral area 102. The first spacer 5 and the second spacer 7 are conductive structures formed by a single patterning process with at least one conductive layer in the drive substrate 1. For example, the first spacer 5 and the second spacer 7 are conductive structures formed by a single patterning process with the anode layer in the drive substrate 1. That is, the first spacer 5 and the second spacer 7 are sandwich isolation structures formed by sequentially stacking titanium / aluminum / titanium film layers. In some embodiments, the first spacer 5 and the second spacer 7 can also be conductive structures formed by a single patterning process with multiple conductive layers in the drive substrate 1. For example, the first spacer 5 and the second spacer 7 are respectively formed by sequentially stacking a conductive layer on the same layer as the anode in the drive substrate 1, a conductive layer on the same layer as the first gate in the drive substrate 1, and a conductive layer on the same layer as the second gate in the drive substrate 1. The inorganic insulating layer used for isolation and insulation between any two adjacent conductive layers of the first gate, the second gate, and the anode can be retained.

[0195] In some embodiments, referring to Figure 2g, a top-view schematic diagram of the distribution of the first isolation column, the first dam, and the second isolation column in the substrate is shown in an embodiment of the present disclosure, wherein, for example: the hole area 101 is circular, the orthographic projections of the plurality of first isolation columns 5 on the substrate are all circular, the orthographic projections of the plurality of second isolation columns 7 on the substrate are all circular, the orthographic projections of the plurality of second isolation columns 7 on the substrate are sequentially surrounding the periphery of the hole area 101, the orthographic projections of the plurality of first isolation columns 5 on the substrate are sequentially surrounding the periphery of the second isolation columns 7, and the plurality of second isolation columns 7 and the plurality of first isolation columns 5 form a group of concentric rings with the hole area 101 as the center.

[0196] In some embodiments, referring to FIG. 2g , the orthographic projection of the first dam 6 on the substrate is circular, and the orthographic projection of the first dam 6 on the substrate surrounds the periphery of the second spacer 7. Referring to FIG. 2c , the film layer forming the first dam 6, which is made of the same material and layer as the pixel definition layer 4, covers the organic film layer made of the same material and layer as the planarization layer 2. Both the pixel definition layer 4 and the planarization layer 2 are made of an organic insulating material, such as an organic resin. The first dam 6 is formed by stacking layers of organic insulating materials, allowing the first dam 6 to be made taller or thicker, thereby blocking the organic encapsulation material in the encapsulation layer and preventing it from overflowing onto the side of the first dam 6 away from the display area 100 during encapsulation. Specifically, the organic encapsulation layer in the encapsulation layer extends from the display area 100 to cover the area on the side of the first dam 6 near the display area 100, and does not extend beyond the first dam 6. The inorganic encapsulation layer in the encapsulation layer extends from the display area 100 to cover the entire aperture perimeter area 102.

[0197] In some embodiments, refer to FIG2h, which is a partial cross-sectional view of an embodiment of the display area of ​​a display panel using a display substrate in an embodiment of the present disclosure. In this embodiment, the drive substrate 1 in the display substrate further includes a pixel circuit 11 and multiple anodes 12 disposed on one side of a substrate 10. The pixel circuit 11 is located in the display area 100, and the multiple anodes 12 are disposed on the same layer. The planar layer 2, insulating layer 3, anodes 12, and pixel definition layer 4 are sequentially stacked on the side of the pixel circuit 11 facing away from the substrate 10. The display panel using this display substrate further includes an organic material layer 8, a cathode 9, an encapsulation layer 13, and a polarizer 14. The organic material layer 8, cathode 9, encapsulation layer 13, and polarizer 14 are sequentially stacked on the side of the pixel definition layer 4 facing away from the drive substrate 1. The pixel circuit 11 includes a transistor and a capacitor. The transistor includes an active layer 110, a gate 111, a source 112 and a drain 113 arranged in the same layer; the capacitor includes a first plate 114 and a second plate 115; the pixel circuit 11 also includes a conductive connection structure 116; the active layer 110, the gate 111, the source 112 and the drain 113 arranged in the same layer, and the conductive connection structure 116 are sequentially arranged away from the substrate 10; the gate 111 and the first plate 114 are arranged in the same layer; the conductive connection structure 116 connects the anode 12 and the drain 113; the pixel circuit 11 also includes a buffer layer 117, a first gate insulating layer 118, a second gate insulating layer 119 and the intermediate dielectric layer 121, the buffer layer 117 is located between the active layer 110 and the substrate 10; the first gate insulating layer 118 is located between the active layer 110 and the gate 111; the second gate insulating layer 119 is located between the first electrode 114 and the second electrode 115; the intermediate dielectric layer 121 is located between the second electrode 115 and the source 112 drain 113 of the same layer; the flat layer 2 includes a first flat layer 21 and a second flat layer 22, the first flat layer 21 is located between the source 112 drain 113 of the same layer and the conductive connection structure 116; the second flat layer 22 and the insulating layer 3 are located between the anode 12 and the conductive connection structure 116. The inorganic insulating layer includes a buffer layer 117, a first gate insulating layer 118, a second gate insulating layer 119, and an intermediate dielectric layer 121. The insulating layer 3 is located on the side of the planar layer 2 facing away from the substrate 10, and the anode 12 is located on the side of the insulating layer 3 facing away from the substrate 10. The pixel definition layer 4 is located on the side of the anode 12 facing away from the substrate 10. The organic material layer 8 is located on the side of the pixel definition layer 4 facing away from the substrate 10. A first opening is defined in the pixel definition layer 4, exposing the anode 12 at the first opening. The portion of the organic material layer 8 located in the first opening of the pixel definition layer 4 emits light under the action of the electric field formed between the anode 12 and the cathode 9. The encapsulation layer 13 is located on the side of the cathode 9 facing away from the substrate 10. The polarizer 14 is located on the side of the encapsulation layer 13 facing away from the substrate 10. The anode 12 is located in the display area 100. The encapsulation layer 13 and the polarizer 14 extend from the display area 100 to the cover hole peripheral area 102. The first and second spacer columns 5 and 7, along with at least one conductive layer in the pixel circuit 11, are formed through a single patterning process.

[0198] In some embodiments, a second opening is further defined in the pixel definition layer 4. The second opening is located in an area outside the area corresponding to the anode 12. A groove 300 is defined in the area of ​​the insulating layer 3 and the planar layer 2 corresponding to the second opening. The groove 300 is narrow at the top and wide at the bottom. The second opening and the groove 300, which is narrow at the top and wide at the bottom, disconnect at least a portion of the organic material layer 8 recessed therein, thereby preventing carriers from migrating between light-emitting units and thereby avoiding cross-coloring caused by leakage.

[0199] In some embodiments, referring to Figures 2b and 2c, a distance i between the cutoff boundary c of the insulating layer 3 and the boundary of the first spacer 5 closest to the cutoff boundary c of the insulating layer 3 is greater than or equal to 4 μm. This configuration ensures that the residual insulating layer 3 on the edge side surfaces of the first spacer 5 and the second spacer 7 is completely etched away, thereby enabling the first spacer 5 and the second spacer 7 to further isolate the organic material layer 8 and the cathode 9 extending into the hole peripheral region 102, thereby further improving the power-off effect in the hole peripheral region 102 and further reducing the incidence of GDSH. Furthermore, it ensures that the insulating layer 3 covers the first climbing region 202 of the planar layer 2 with a sufficient margin.

[0200] In some embodiments, referring to Figures 2c and 2i, Figure 2i is a top view of the partial structure of the flat area of ​​the flat layer in the hole peripheral area of ​​the display substrate in the embodiment of the present disclosure; the flat layer 2 includes multiple sub-layers 23, which are stacked in sequence. The display substrate also includes multiple first traces 15, which are located in the hole peripheral area 102 and between two adjacent sub-layers 23. The orthographic projections of at least some of the first traces 15 on the driver substrate 1 are located in the flat area 201, and the orthographic projections of the first traces 15 and the partition groove 30 on the driver substrate 1 do not overlap. This arrangement can prevent the first traces 15 from being exposed due to over-engraving of the corresponding sub-layer 23 when the partition groove 30 is formed, thereby preventing the exposed first traces 15 from being corroded by intruding water vapor, thereby reducing the incidence of GDSH.

[0201] In some embodiments, referring to Figures 2c and 2i , the distance j between adjacent boundaries of the orthographic projections of the first trace 15 and the partitioning groove 30 on the driver substrate 1 is greater than 1 μm. This configuration prevents process errors in forming the partitioning groove 30 from exposing the first trace 15, thereby protecting the exposed first trace 15 from corrosion by intruding water vapor and reducing the incidence of GDSH.

[0202] In some embodiments, the first trace 15 may be any signal trace, such as a data trace.

[0203] In some embodiments, referring to Figures 3a and 3b, Figure 3a is a top view of the local structure of the overlapping area of ​​the insulating layer and the flat layer in the peripheral area of ​​the hole in the display substrate of the embodiment of the present disclosure; Figure 3b is a schematic cross-sectional view of the structure along the CC' section line in Figure 3a; wherein, the partition portion 31 and the orthographic projection of the flat layer 2 on the driving substrate 1 at least partially overlap, and a plurality of first vents 301 are formed in the partition portion 31. The orthographic projections of the plurality of first vents 301 on the driving substrate 1 are located in the overlapping area of ​​the orthographic projections of the partition portion 31 and the flat layer 2, and the plurality of first vents 301 are evenly distributed; the display substrate further includes a plurality of first filling structures 16, the plurality of first filling structures 16 are arranged in the same layer as the pixel definition layer 4 and are made of the same material, the plurality of first filling structures 16 correspond one-to-one to the plurality of first vents 301, and the orthographic projection of each first filling structure 16 on the driving substrate 1 covers its corresponding first vent 301.

[0204] Among them, the flat layer 2 is formed of an organic insulating material. The organic material of the flat layer 2 needs to be degassed during the preparation process. The insulating layer 3 is made of an inorganic insulating material, such as silicon nitride, silicon oxide, or silicon oxynitride. If the insulating layer 3 completely covers the flat layer 2, the degassing of the organic material during the preparation process will cause the insulating layer 3 to peel off, resulting in subsequent peeling particles contaminating the display area 100 and causing defects. By opening a first vent 301 in the area where the insulating layer 3 overlaps with the flat layer 2, it is possible to prevent the insulating layer 3 from blocking the degassing of the organic material, thereby preventing defects in the display substrate. In addition, the first filling structure 16 can fill the film layer discontinuity between the insulating layer 3 and the flat layer 2 at the location where the first vent 301 is opened, thereby preventing the inorganic encapsulation layer from breaking at a larger film layer discontinuity, thereby preventing water vapor from invading from the fracture, and avoiding reliability GDSH defects in the display panel using this display substrate.

[0205] In some embodiments, referring to Figures 3a and 3b , the spacing k between the corresponding side boundaries of the orthographic projection of the first filling structure 16 and its corresponding first vent 301 on the drive substrate 1 is greater than or equal to 5 μm. This allows the first filling structure 16 to fully cover the first vent 301, further ensuring that the first filling structure 16 can fully fill the film discontinuity between the insulating layer 3 and the planar layer 2 at the location where the first vent 301 is opened. This prevents the inorganic encapsulation layer from breaking at the location of the large film discontinuity, prevents moisture from invading through the broken portion, and avoids poor reliability GDSH performance in display panels using this display substrate.

[0206] In some embodiments, the orthographic projection shape of the first vent 301 on the driving substrate 1 includes a triangle, rectangle, circle, ellipse or polygon. The orthographic projection shape of the first filling structure 16 on the driving substrate 1 includes a triangle, rectangle, circle, ellipse or polygon.

[0207] In some embodiments, the orthographic projection shapes of the first vent 301 and the first filling structure 16 on the driving substrate 1 may be the same or different, as long as the first filling structure 16 completely covers the first vent 301 .

[0208] In some embodiments, the orthographic projection area of ​​the first vent 301 on the driving substrate 1 is 3×3 μm. 2 ~10×10μm 2 .

[0209] In some embodiments, referring to Figures 2a, 4a, and 4b, Figure 4a is a schematic top view of the structure of the first area in the display substrate of the embodiment of the present disclosure; Figure 4b is a cross-sectional view of the structure along the DD' section line in Figure 4a; wherein the display substrate further has a binding area 103, which is located on one side of the display area 100; the binding area 103 includes a first area 104, at least part of the conductive layer is also located in the first area 104, the insulating layer 3 is also located in the first area 104, the display substrate further includes a power electrode 17, which is located in the first area 104, and the power electrode 17 includes a first conductive pattern 171 and at least one conductive pattern The conductive layer 172, at least one conductive layer 172 and the first conductive pattern 171 are stacked in sequence along the direction away from the driving substrate 1, the first conductive pattern 171 is located on the side of the insulating layer 3 away from the driving substrate 1, the first conductive pattern 171 partially overlaps with the insulating layer 3, and the orthographic projection of the first conductive pattern 171 on the driving substrate 1 covers at least a partial overlapping boundary m of the insulating layer 3 with the first conductive pattern 171, and the orthographic projection of the overlapping boundary n of the first conductive pattern 171 with the insulating layer 3 on the driving substrate 1 is at least partially located within the orthographic projection area of ​​the insulating layer 3 on the driving substrate 1.

[0210] The first conductive pattern 171 is provided in the same layer and made of the same material as the anode in the display area 100. By ensuring that the orthographic projection of the first conductive pattern 171 on the drive substrate 1 covers the overlapping boundary m between the insulating layer 3 and the first conductive pattern 171, and that the orthographic projection of the overlapping boundary n between the first conductive pattern 171 and the insulating layer 3 on the drive substrate 1 is located within the orthographic projection area of ​​the insulating layer 3 on the drive substrate 1, the overlapping boundaries between the first conductive pattern 171 and the insulating layer 3 are staggered. In other words, the orthographic projections of the overlapping boundaries between the first conductive pattern 171 and the insulating layer 3 on the drive substrate 1 do not overlap. This prevents the coating of the first conductive pattern 171 on the boundary of the insulating layer 3 from being broken (undercut) due to the boundary discontinuity of the insulating layer 3, which could increase the resistance of the power electrode 17 or cause unstable conductivity.

[0211] In some embodiments, referring to FIG. 4 a and FIG. 4 b , a width p1 of an orthographically projected overlapping region of the first conductive pattern 171 and the insulating layer 3 on the driving substrate is greater than or equal to 3 μm.

[0212] In some embodiments, referring to Figures 4a and 4b, the display substrate also includes a second filling structure 18, which is located in the first area 104. The second filling structure 18 is arranged in the same layer as the pixel definition layer 4 and uses the same material. The orthographic projection of the second filling structure 18 on the driving substrate 1 covers the first boundary m of the insulating layer 3 overlapping with the first conductive pattern 171 and the second boundary n of the first conductive pattern 171 overlapping with the insulating layer 3. The distance p2 between the first boundary m and the orthographic projection of the boundary of the second filling structure 18 located on the side away from the insulating layer 3 on the driving substrate 1 is greater than or equal to 5μm; the distance p3 between the second boundary n and the orthographic projection of the boundary of the second filling structure 18 located on the side away from the first conductive pattern 171 on the driving substrate 1 is greater than or equal to 10μm.

[0213] Among them, because the first conductive pattern 171 is easily broken (undercut) at the first boundary m of the insulating layer 3 due to the discontinuity of the insulating layer 3, the depression caused by the break can easily cause the inorganic encapsulation layer to break at this location, resulting in a reliability GDSX risk for the display substrate. In this embodiment, by providing a second filling structure 18, the first boundary m of the insulating layer 3 and the second boundary n of the first conductive pattern 171 are covered, and the film layer discontinuity formed at the first boundary m and the second boundary n can be filled, thereby improving or completely eliminating the film layer discontinuity at the first boundary m and the second boundary n. As a result, the inorganic encapsulation layer breaks at the film layer discontinuity, ultimately avoiding the risk of reliability GDSX for the display substrate.

[0214] In some embodiments, the power electrode 17 is a VSS electrode.

[0215] In some embodiments, referring to Figures 2a, 5a, 5b and 5c, Figure 5a is a schematic top view of the structure of the second area in the display substrate of the embodiment of the present disclosure; Figure 5b is an enlarged top view of part E in Figure 5a; Figure 5c is a cross-sectional view of the structure along the FF' section line in Figure 5b; the binding area 103 also includes a second area 105, at least part of the conductive layer is located in the second area 105, the insulating layer 3 also includes a plurality of partition bars 32 located in the second area 105, the display substrate also includes a power line 19 and a plurality of second dams 24, at least partially located in the second area 105; in the second area 105, the plurality of partition bars 32 and the plurality of second dams 24 extend respectively along the third direction Y, and the plurality of partition bars 32 and the plurality of second dams 24 are alternately arranged in sequence along the fourth direction L, and the flat layer 2 and the pixel definition layer 4 also extends to the second area 105, the second dam 24 includes a third sub-film layer of the same layer and material as the planar layer 2 and a fourth sub-film layer of the same layer and material as the pixel definition layer 4, and the third sub-film layer and the fourth sub-film layer are stacked in sequence; the power line 19 includes at least one conductive layer, and the power line 19 extends along the fourth direction L; the third direction Y and the fourth direction L intersect; the power line 19 and the positive projections of multiple partition bars 32 and multiple second dams 24 on the driving substrate 1 intersect with each other; a passivation layer 25 is also provided between the power line 19 and the partition bar 32, and the passivation layer 25 covers the second area 105; the edge area of ​​the partition bar 32 overlaps with the second dam 24, the planar layer 2 and the pixel definition layer 4, and the part other than the edge area of ​​the partition bar 32 contacts the passivation layer 25.

[0216] Among them, the passivation layer 25 around the second dam 24 in the second area 105 is exposed. Since the etching of the insulating layer 3 during the preparation process of the insulating layer 3 will cause over-etching of the passivation layer 25 located thereunder, the insulating layer 3 above the passivation layer 25 around the second dam 24 in the second area 105 is retained, thereby avoiding over-etching of the passivation layer 25 caused by the etching of the insulating layer 3 in the second area 105, and further avoiding exposure of the conductive structure located below the passivation layer 25. The edge area of ​​the partition bar 32 overlaps with the flat layer 2, and the edge area of ​​the partition bar 32 can cover the boundary of the flat layer 2. At this time, the boundary of the partition bar 32 may be located on the first climbing area 202 or the flat area 201 of the flat layer 2. If the pixel definition layer 4 is not covered above the edge area of ​​the partition bar 32, then when the partition bar 32 is prepared, its boundary is likely to be over-engraved in the first climbing area 202 or the flat area 201 of the flat layer 2 to form a depression, causing the inorganic packaging layer to break, and then causing GDSX defects in the display substrate. Therefore, by making the edge area of ​​the partition bar 32 overlap with the second dam 24, the flat layer 2 and the pixel definition layer 4, the pixel definition layer 4 can cover the boundary of the partition bar 32, thereby filling the film layer discontinuity formed by the boundary of the partition bar 32 and the depression in the flat layer 2, thereby avoiding the breakage of the inorganic packaging layer and avoiding GDSX defects in the display substrate.

[0217] In some embodiments, referring to Figures 5b and 5c, within the second region 105, the width r1 of the overlapping region between the partitioning strips 32 and the planar layer 2 along the fourth direction L is less than the width r2 of the overlapping region between the partitioning strips 32 and the pixel definition layer 4 along the fourth direction L. This configuration allows, on the one hand, the partitioning strips 32 to cover the boundaries of the planar layer 2, preventing the overlap between the boundaries of the partitioning strips 32 and the planar layer 2, which would cause a larger film discontinuity. On the other hand, the pixel definition layer 4 can fully cover and fill the larger film discontinuity formed by the boundaries of the partitioning strips 32 and the recesses formed by these boundaries in the planar layer 2, thereby preventing the inorganic encapsulation layer from breaking at the larger film discontinuity and, in turn, preventing GDSX defects in the display substrate.

[0218] In some embodiments, referring to Figures 5b and 5c, the width r2 of the edge region of the partitioning strip 32 overlapping the pixel definition layer 4 along the fourth direction L is greater than or equal to 5 μm. With this configuration, the pixel definition layer 4 can fully cover the large film discontinuity formed by the boundary of the partitioning strip 32 and the depression formed by the boundary in the planar layer 2, and fully fill the large film discontinuity, thereby preventing the inorganic encapsulation layer from breaking at the large film discontinuity and thus preventing GDSX defects in the display substrate.

[0219] In some embodiments, referring to FIG. 5c , the orthographic projection of the boundary of the partition strip 32 on the flat layer 2 is located in the flat region 201. This configuration can prevent the formation of uncontrollable large film discontinuities in the flat layer 2 below the boundary of the partition strip 32 during the preparation process, thereby preventing the inorganic encapsulation layer from breaking at the uncontrollable large film discontinuities and further preventing GDSX defects in the display substrate.

[0220] In some embodiments, referring to Figures 5a and 5b, in the overlapping area between the partition bar 32 and the boundary of the power cord 19, the local boundary of the partition bar 32 extends outward along the extension direction of the boundary of the power cord 19 to form a protrusion 320, which covers part of the boundary of the power cord 19.

[0221] Such a setting can prevent the boundary of the power line 19 located at the boundary of the partition bar 32 from being exposed when the preparation process of the partition bar 32 has large deviations; because although the boundary of the power line 19 is covered by the passivation layer 25, the passivation layer 25 may be over-etched in the preparation process of the partition bar 32, so that the power line 19 is exposed, and due to the influence of the fluctuation of the preparation process of the partition bar 32, the partition bar 32 may not be able to effectively cover the power line 19 at its boundary position, thereby causing the boundary of the power line 19 located at the boundary of the partition bar 32 to be exposed, and finally in the reliability process, water vapor invades and causes GDSX defects in the display substrate.

[0222] In some embodiments, referring to Figures 5a and 5b , the dimension of protrusion 320 along the edge of power line 19 is greater than or equal to 5 μm. This dimension of protrusion 320 can completely prevent the edge of power line 19 from being exposed at the edge of partition strip 32 when the manufacturing process of partition strip 32 has large deviations.

[0223] In some embodiments, the power line 19 may be a VDD power line or a VSS power line.

[0224] In some embodiments, referring to FIG. 2a, FIG. 6a and FIG. 6b, FIG. 6a is a schematic top view of the structure of the third region in the display substrate of the embodiment of the present disclosure; FIG. 6b is a cross-sectional view of the structure along the GG' section line in FIG. 6a; wherein the binding area 103 further includes a third region 106, the third region 106 being located between the display area 100 and the second dam 24 closest to the display area 100, the flat layer 2 and the pixel definition layer 4 respectively extending from the display area 100 to the third region 106, and the insulating layer 3 also Located in the third area 106; in the third area 106, the cutoff boundaries a', b', c' of the pixel definition layer 4, the planar layer 2 and the insulating layer 3 are arranged in sequence along the fifth direction T; in the third area 106, the cutoff boundaries a', b', c' of the pixel definition layer 4, the planar layer 2 and the insulating layer 3 are the side boundaries of the pixel definition layer 4, the planar layer 2 and the insulating layer 3 close to the second dam 24; the fifth direction T is the direction of the third area 106 away from the display area 100 and close to the second dam 24.

[0225] In this embodiment, referring to Figures 6a and 6b, in the third area 106, the orthographic projection of the insulating layer 3 on the driving substrate 1 covers the cutoff boundary b' of the flat layer 2, that is, the cutoff boundary c' of the insulating layer 3 does not overlap with the orthographic projection of the flat layer 2 on the driving substrate 1, thereby avoiding the formation of a large film layer discontinuity in the flat layer 2 located thereunder during the preparation process of the insulating layer 3, thereby avoiding the inorganic packaging layer for encapsulating the light-emitting device formed above the display substrate from breaking at the large film layer discontinuity, and then preventing water vapor from invading from the broken part, thereby avoiding the problems of poor reliability GDSH and poor GDSX in the display panel using the display substrate.

[0226] In some embodiments, referring to Figures 6a and 6b, within the third area 106, the orthographic projections of the insulating layer 3 and the flat layer 2 on the driving substrate 1 at least partially overlap, and a plurality of second vents 302 are provided in the insulating layer 3. The orthographic projections of the plurality of second vents 302 on the driving substrate 1 are located in the overlapping area of ​​the orthographic projections of the insulating layer 3 and the flat layer 2, and the plurality of second vents 302 are evenly distributed; the display substrate further includes a plurality of third filling structures 26, which are arranged in the same layer as the pixel definition layer 4 and are made of the same material. The plurality of third filling structures 26 correspond one-to-one to the plurality of second vents 302, and the orthographic projection of each third filling structure 26 on the driving substrate 1 covers its corresponding second vent 302.

[0227] Among them, the flattening layer 2 is formed of an organic insulating material. The organic material of the flattening layer 2 needs to be degassed during the preparation process. The insulating layer 3 is formed of an inorganic insulating material, such as silicon nitride, silicon oxide, or silicon oxynitride. If the insulating layer 3 completely covers the flattening layer 2, the degassing of the organic material during the preparation process will cause the insulating layer 3 to peel off, resulting in subsequent peeling particles contaminating the display area 100 and causing defects. By providing a second degassing port 302 in the area where the insulating layer 3 overlaps with the flattening layer 2 in the third area 106, it is possible to prevent the insulating layer 3 from blocking the degassing of the organic material, thereby preventing defects in the display substrate. In addition, the third filling structure 26 can fill the film discontinuity between the insulating layer 3 and the flattening layer 2 at the location where the second degassing port 302 is provided, thereby preventing the inorganic encapsulation layer from breaking at the larger film discontinuity, thereby preventing water vapor from invading through the break and avoiding reliability GDSX defects in the display panel using this display substrate.

[0228] In some embodiments, referring to FIG. 6b , the planar layer 2 within the third region 106 includes a first climbing region 202 and a flat region 201, with the flat region 201 and the first climbing region 202 arranged sequentially along the fifth direction T. The orthographic projections of the plurality of second vents 302 on the driver substrate 1 are located within the orthographic projections of the flat region 201 on the driver substrate 1. This arrangement prevents the formation of uncontrolled large film discontinuities in the planar layer 2 below the boundaries of the second vents 302 during the fabrication process. This prevents the inorganic encapsulation layer from breaking at the uncontrolled large film discontinuities, further preventing GDSX defects in the display substrate.

[0229] In some embodiments, referring to Figure 6b, within the third area 106, the flat layer 2 includes a first sublayer 231, a second sublayer 232, and a third sublayer 233. The first sublayer 231, the second sublayer 232, and the third sublayer 233 are stacked in sequence away from the driving substrate 1. The first sublayer 231, the second sublayer 232, and the third sublayer 233 respectively have a first climbing area 202 and a flat area 201, and the flat areas 201 and the first climbing areas 202 of the first sublayer 231, the second sublayer 232, and the third sublayer 233 are respectively arranged in sequence along the fifth direction T; the orthographic projections of the multiple second vents 302 on the driving substrate 1 are located in the overlapping area of ​​the orthographic projections of the flat areas 201 of at least two of the first sublayer 231, the second sublayer 232, and the third sublayer 233 on the driving substrate 1.

[0230] Among them, by making the orthographic projections of the multiple second vents 302 on the driving substrate 1 located in the overlapping area of ​​the orthographic projections of at least two flat areas 201 of the first sub-layer 231, the second sub-layer 232 and the third sub-layer 233 on the driving substrate 1, it is ensured that the setting position of the second vents 302 can avoid the first climbing area 202 of the third sub-layer 233 located on the top layer, so as to avoid the formation of an uncontrollable large film layer step difference between the boundary of the second vents 302 and the first climbing area 202 of the third sub-layer 233, thereby avoiding the inorganic encapsulation layer from breaking at the uncontrollable large film layer step difference, and further avoiding GDSX defects in the display substrate.

[0231] 6 b , the first climbing region 202 of the second sublayer 232 is filled by the first climbing region 202 of the third sublayer 233 , and the first climbing region 202 of the first sublayer 231 is filled by the first climbing region 202 of the second sublayer 232 .

[0232] In some embodiments, referring to Figures 6a, 6b and 6c, Figure 6c is a top view schematic diagram of the second conductive pattern and the second vent in the display substrate of an embodiment of the present disclosure, wherein the display substrate further includes a second conductive pattern 27, which is arranged in the same layer as the first conductive pattern 171, and the second conductive pattern 27 is located between the insulating layer 3 and the third filling structure 26, the orthographic projection of the second conductive pattern 27 on the driving substrate 1 at least covers a local boundary m1 of the second vent 302, and the orthographic projection of the boundary n1 of the second conductive pattern 27 on the driving substrate 1 is located in the orthographic projection area of ​​the insulating layer 3 on the driving substrate 1; the orthographic projection of the third filling structure 26 on the driving substrate 1 covers the boundary m1 of the second vent 302 and the boundary n1 of the second conductive pattern 27.

[0233] Among them, because the second conductive pattern 27 is easily broken (undercut) at the boundary of the second vent 302 due to the discontinuity of the insulating layer 3, the depression caused by the break can easily cause the inorganic encapsulation layer to break at this location, resulting in a reliability GDSX risk on the display substrate. In this embodiment, by providing a third filling structure 26, the boundary m1 of the second vent 302 and the boundary n1 of the second conductive pattern 27 are covered, and the film layer discontinuity formed at the boundary m1 of the second vent 302 and the boundary n1 of the second conductive pattern 27 can be filled, thereby improving or completely eliminating the film layer discontinuity at the boundary m1 of the second vent 302 and the boundary n1 of the second conductive pattern 27. As a result, the inorganic encapsulation layer breaks at the film layer discontinuity, ultimately avoiding the risk of reliability GDSX on the display substrate.

[0234] 6 a and 6 b , a portion of the insulating layer 3 located in the display area 100 and a portion located in the third area 106 are separated from each other in the third area 106 , and an orthographic projection of the pixel definition layer 4 on the driving substrate 1 covers at least a portion of the separation boundary of the insulating layer 3 .

[0235] The boundary of the insulating layer 3 is formed by the pattern of the portion located in the display area 100 and the pattern of the portion located in the third area 106 of the aperture, which are separated from each other in the third area 106. The pixel definition layer 4 extends from the display area 100 to the third area 106, with a flat layer 2 provided below the disconnected portion of the insulating layer 3. With this arrangement, the pixel definition layer 4 can fill the large film discontinuity formed at the disconnected portion of the insulating layer 3 (including the thickness discontinuity of the insulating layer 3 and the concave discontinuity formed in the underlying flat layer 2), thereby preventing the large film discontinuity at the disconnected portion of the insulating layer 3 from causing a break in the inorganic encapsulation layer. This in turn prevents moisture from invading through the break, thus avoiding reliability issues with GDSX in display panels using this display substrate.

[0236] In this embodiment, by making any first climbing area in the display substrate not overlap with the orthographic projection of the pixel definition layer on the driving substrate, the orthographic projection of the boundary of the insulating layer on the driving substrate is located within the orthographic projection area of ​​the flat area on the driving substrate, or the boundary of the insulating layer and the orthographic projection of the flat layer on the driving substrate do not overlap, the preparation process of the insulating layer can be prevented from forming a large film layer step in the flat layer located therebelow, thereby preventing the inorganic packaging layer for packaging the light-emitting device formed above the display substrate from breaking at the large film layer step, thereby preventing water vapor from invading from the fracture, and then avoiding the problems of poor reliability GDSH and poor GDSX in the display panel using the display substrate.

[0237] In a second aspect, an embodiment of the present disclosure provides a display panel, comprising the display substrate in the above embodiment.

[0238] The display panel also includes an organic material layer, a cathode, an encapsulation layer, and a polarizer. The organic material layer, cathode, encapsulation layer, and polarizer are stacked in sequence on the side of the pixel definition layer in the display substrate that is away from the drive substrate. The organic material layer and cathode cover the entire display area. The organic material layer is located on the side of the pixel definition layer in the display substrate that is away from the drive substrate; an opening is provided in the pixel definition layer, and the anode is exposed at the opening. The portion of the organic material layer located in the opening of the pixel definition layer emits light under the action of the electric field formed between the anode and the cathode. The encapsulation layer is located on the side of the cathode that is away from the display substrate; the polarizer is located on the side of the encapsulation layer that is away from the display substrate. The anode is located in the display area; the pixel definition layer and the planarization layer extend from the display area to the area surrounding the hole; the encapsulation layer and the polarizer extend from the display area to the area surrounding the covered hole.

[0239] The display panel provided in this embodiment, by adopting the display substrate in the above embodiments, can improve or avoid reliability GDSH failure and GDSX failure, thereby improving the quality of the display panel.

[0240] The display panel provided in the embodiments of the present disclosure may be any product or component with a display function, such as an OLED panel, an OLED TV, an OLED billboard, a display, a mobile phone, or a navigation device.

[0241] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A display substrate, wherein, It includes a driving substrate, a planarization layer, an insulating layer, and a pixel definition layer. The planarization layer, the insulating layer, and the pixel definition layer are sequentially stacked on one side of the driving substrate. The planarization layer has a plurality of first ramp regions. In the first ramp regions, the dimension of the planarization layer in a first direction gradually increases from 0 to a maximum value. The first direction is the direction away from the driving substrate of the planarization layer. The plurality of first ramp regions and the positive projection of the pixel definition layer on the driving substrate are at least partially non-overlapping. The insulating layer has at least one boundary, and at least a part of the boundary of the insulating layer is located outside the positive projection region of the first ramp region on the driving substrate in the positive projection on the driving substrate.

2. A display substrate, wherein, It includes a driving substrate, a planarization layer, an insulating layer, and a pixel definition layer. The planarization layer, the insulating layer, and the pixel definition layer are sequentially stacked on one side of the driving substrate. The planarization layer has a planar region and a plurality of first ramp regions, and the planar region and the plurality of first ramp regions are respectively docked. The plurality of first ramp regions and the positive projection of the pixel definition layer on the driving substrate are at least partially non-overlapping. In the first ramp regions, the dimension of the planarization layer in the first direction gradually increases from 0 to a maximum value; in the planar region, the dimension of any position of the planarization layer in the first direction is approximately the maximum value; the first direction is the direction away from the driving substrate of the planarization layer. The insulating layer has at least one boundary, and at least a part of the boundary of the insulating layer is located in the positive projection region of the planar region on the driving substrate in the positive projection on the driving substrate, or at least a part of the boundary of the insulating layer does not overlap with the positive projection of the planarization layer on the driving substrate.

3. The display substrate according to claim 2, wherein, The display substrate has a display region, a hole region, and a hole peripheral region. The hole peripheral region at least partially surrounds the hole region; the display region at least partially surrounds the hole peripheral region. The planarization layer and the pixel definition layer respectively extend from the display region to the hole peripheral region, and the insulating layer is located in the display region and the hole peripheral region. In the hole peripheral region, the cut-off boundaries of the pixel definition layer, the planarization layer, and the insulating layer are sequentially arranged in a second direction; in the hole peripheral region, the cut-off boundaries of the pixel definition layer, the planarization layer, and the insulating layer are the boundaries on the side of the pixel definition layer, the planarization layer, and the insulating layer close to the hole region. The second direction is the direction in which the hole peripheral region is away from the display region and close to the hole region.

4. The display substrate according to claim 3, wherein, A plurality of partition grooves are formed in the insulating layer in the hole peripheral region, and the plurality of partition grooves are sequentially and spaced apart in the second direction to divide the insulating layer into a plurality of partition parts.

5. The display substrate according to claim 4, wherein, The positive projection of the plurality of partition grooves on the driving substrate closes and surrounds the periphery of the hole region. The positive projection of the plurality of partition parts on the driving substrate closes and surrounds the periphery of the hole region.

6. The display substrate according to claim 5, wherein, The planarization layer in the hole peripheral region has the first ramp regions and the planar region, and the planar region and the first ramp regions are sequentially arranged in the second direction. The positive projection of the multiple partition grooves on the driving substrate overlaps at least partially with the flat area.

7. The display substrate according to claim 5, wherein, The number of the partition grooves is 2 to 5.

8. The display substrate according to claim 5, wherein, The widths of the multiple partition parts along the second direction are equal.

9. The display substrate according to claim 5, wherein, The widths of the multiple partition parts along the second direction are unequal.

10. The display substrate according to claim 9, wherein, The partition part closest to the hole area is the first partition part, the partition part closest to the display area is the second partition part, and the partition parts located between the first partition part and the second partition part are intermediate partition parts; there is at least one intermediate partition part; The widths of the first partition part and the second partition part along the second direction are respectively greater than the width of the intermediate partition part along the second direction; The width of the second partition part along the second direction is greater than the width of the first partition part along the second direction.

11. The display substrate according to claim 10, wherein, The width range of the first partition part along the second direction is 81 to 83 μm; The width range of the second partition part along the second direction is 85 to 89 μm; The width range of the intermediate partition part along the second direction is 75 to 80 μm.

12. The display substrate according to claim 11, wherein, The width of the first partition part along the second direction is 81 μm; The width of the second partition part along the second direction is 88 μm; The width of the intermediate partition part along the second direction is 80 μm.

13. The display substrate according to claim 8 or 9, wherein The width of any of the partition parts along the second direction is not less than 10 μm.

14. The display substrate according to any one of claims 4-12, wherein, The width of the partition groove along the second direction is less than the width of the partition part along the second direction.

15. The display substrate according to claim 14, wherein, The width range of the partition groove along the second direction is 3 to 10 μm.

16. The display substrate according to claim 10, wherein, One side boundary of the first partition part close to the hole area is the cut-off boundary of the insulating layer, The distance between the positive projection of the cut-off boundary of the insulating layer and the cut-off boundary of the flat layer on the driving substrate is greater than or equal to 3.5 μm and less than the width of the first partition part along the second direction.

17. The display substrate according to claim 10, wherein, The part of the insulating layer located in the display area and the part located in the hole peripheral area are separated from each other in the hole peripheral area, The positive projection of the pixel definition layer on the driving substrate covers at least part of the separation boundary of the insulating layer.

18. The display substrate according to claim 17, wherein, One side boundary of the second partition part close to the hole area is located on the side close to the hole area of the cut-off boundary of the pixel definition layer, The distance between the positive projection of one side boundary of the second partition part close to the hole area and the cut-off boundary of the pixel definition layer on the driving substrate is greater than or equal to 3 μm and less than the width of the second partition part along the second direction.

19. The display substrate according to claim 18, wherein, The distance between the positive projection of one side boundary of the second partition part close to the hole area and the cut-off boundary of the pixel definition layer on the driving substrate is 5 μm or more.

20. The display substrate according to claim 3, wherein The driving substrate includes a substrate, multiple conductive layers and multiple inorganic insulating layers, The multiple conductive layers and the multiple inorganic insulating layers are alternately stacked in sequence on the side of the substrate close to the flat layer; The substrate extends from the display area to the hole peripheral area, The multiple conductive layers are located in the display area, and at least part of the conductive layers are also located in the hole peripheral area, The multiple inorganic insulating layers extend from the display area to the periphery area of the hole. The display substrate further includes a plurality of first isolation pillars, a first dam, and a plurality of second isolation pillars. The plurality of first isolation pillars, the first dam, and the plurality of second isolation pillars are located in the periphery area of the hole, and the plurality of first isolation pillars, the first dam, and the plurality of second isolation pillars are arranged at intervals in sequence along the second direction. The plurality of first isolation pillars and the plurality of second isolation pillars are respectively formed by at least one of the conductive layers. The first dam includes a first sub-film layer of the same layer and the same material as the planarization layer and a second sub-film layer of the same layer and the same material as the pixel definition layer. The first sub-film layer and the second sub-film layer are stacked in sequence. The plurality of first isolation pillars, the first dam, and the plurality of second isolation pillars are located on one side of the cut-off boundary of the insulating layer close to the hole area, and the plurality of first isolation pillars, the first dam, and the plurality of second isolation pillars do not overlap with the orthographic projection of the insulating layer on the substrate.

21. The display substrate according to claim 20, wherein, The distance between the cut-off boundary of the insulating layer and the boundary of the first isolation pillar closest to the cut-off boundary of the insulating layer is greater than or equal to 4 μm.

22. The display substrate according to claim 6, wherein, The planarization layer includes a plurality of sub-layers, and the plurality of sub-layers are stacked in sequence. The display substrate further includes a plurality of first traces, which are located in the periphery area of the hole and between two adjacent sub-layers. At least part of the orthographic projection of the first traces on the driving substrate is located in the planar area. The orthographic projection of the first traces and the partition grooves on the driving substrate do not overlap.

23. The display substrate according to claim 22, wherein The distance between the adjacent boundaries of the orthographic projection of the first traces and the partition grooves on the driving substrate is greater than 1 μm.

24. The display substrate according to claim 4, wherein, The partition part at least partially overlaps with the orthographic projection of the planarization layer on the driving substrate. A plurality of first air vent openings are formed in the partition part. The orthographic projection of the plurality of first air vent openings on the driving substrate is located in the overlapping area of the orthographic projection of the partition part and the planarization layer, and the plurality of first air vent openings are evenly distributed. The display substrate further includes a plurality of first filling structures, which are arranged on the same layer as the pixel definition layer and made of the same material. The plurality of first filling structures correspond to the plurality of first air vent openings one by one, and the orthographic projection of each first filling structure on the driving substrate covers its corresponding first air vent opening.

25. The display substrate according to claim 24, wherein, The distance between the corresponding side boundaries of the orthographic projection of the first filling structure and its corresponding first air vent opening on the driving substrate is greater than or equal to 5 μm.

26. The display substrate according to claim 25, wherein, The shape of the orthographic projection of the first air vent opening on the driving substrate includes a triangle, a rectangle, a circle, an ellipse or a polygon. The shape of the orthographic projection of the first filling structure on the driving substrate includes a triangle, a rectangle, a circle, an ellipse or a polygon.

27. The display substrate according to claim 26, wherein The size of the orthographic projection area of the first air vent on the driving substrate is 3×3 μm 2 ~10×10 μm 2 .

28. The display substrate according to claim 3, wherein, There is at least one hole area. The shape of the hole area includes a circle, an ellipse, a capsule shape or an inverted trapezoid.

29. The display substrate according to claim 20, wherein, The display substrate further has a bonding area, which is located on one side of the display area. The bonding area includes a first area. At least part of the conductive layer is also located in the first area, and the insulating layer is also located in the first area. The display substrate further includes a power electrode located in the first region. The power electrode includes a first conductive pattern and at least one of the conductive layers, and the at least one conductive layer and the first conductive pattern are sequentially stacked in a direction away from the driving substrate. The first conductive pattern is located on a side of the insulating layer facing away from the driving substrate, and the first conductive pattern partially overlaps with the insulating layer. A positive projection of the first conductive pattern on the driving substrate covers an overlapping boundary of the insulating layer with at least a part of the first conductive pattern, and a positive projection on the driving substrate of an overlapping boundary of the first conductive pattern with the insulating layer is at least partially located within a positive projection area of the insulating layer on the driving substrate.

30. The display substrate according to claim 29, wherein, A width of an overlapping area of the first conductive pattern and the insulating layer in a positive projection on the driving substrate is greater than or equal to 3 μm.

31. The display substrate according to claim 30, wherein, It further includes a second filling structure located in the first region. The second filling structure is provided on the same layer as the pixel defining layer and uses the same material. A positive projection of the second filling structure on the driving substrate covers a first boundary of the insulating layer overlapping with the first conductive pattern and a second boundary of the first conductive pattern overlapping with the insulating layer. A distance between the first boundary and a boundary of the second filling structure on a side away from the insulating layer in a positive projection on the driving substrate is greater than or equal to 5 μm. A distance between the second boundary and a boundary of the second filling structure on a side away from the first conductive pattern in a positive projection on the driving substrate is greater than or equal to 10 μm.

32. The display substrate according to claim 29, wherein, The bonding region further includes a second region. At least a part of the conductive layer is located in the second region. The insulating layer further includes a plurality of partition strips located in the second region. The display substrate further includes a power line and a plurality of second dams, at least partially located in the second region. Within the second region, the plurality of partition strips and the plurality of second dams extend along a third direction respectively, and the plurality of partition strips and the plurality of second dams are alternately arranged in sequence along a fourth direction. The planarization layer and the pixel defining layer also extend to the second region. The second dam includes a third sub-layer made of the same material and on the same layer as the planarization layer and a fourth sub-layer made of the same material and on the same layer as the pixel defining layer, and the third sub-layer and the fourth sub-layer are sequentially stacked. The power line includes at least one of the conductive layers, and the power line extends along the fourth direction. The third direction and the fourth direction intersect. A positive projection of the power line on the driving substrate intersects with the plurality of partition strips and the plurality of second dams. A passivation layer is further provided between the power line and the plurality of partition strips, and the passivation layer covers the second region. An edge region of the partition strip overlaps with the second dam, the planarization layer, and the pixel defining layer, and a part other than the edge region of the partition strip contacts the passivation layer.

33. The display substrate according to claim 32, wherein, A width along the fourth direction of an edge region of the partition strip overlapping with the pixel defining layer is greater than or equal to 5 μm.

34. The display substrate according to claim 32, wherein, A positive projection of a boundary of the partition strip on the planarization layer is located in the flat region.

35. The display substrate according to any one of claims 32-34, wherein, In the overlapping region of the partition strip and the boundary of the power line, a partial boundary of the partition strip extends outward along the extension direction of the boundary of the power line to form a protrusion, and the protrusion covers a partial boundary of the power line.

36. The display substrate according to claim 35, wherein, The size of the protrusion along the extension direction of the boundary of the power line is greater than or equal to 5 μm.

37. The display substrate according to claim 32, wherein, The bonding area further includes a third area, and the third area is located between the display area and the second dam closest to the display area. The planarization layer and the pixel definition layer extend from the display area to the third area respectively, and the insulating layer is also located in the third area. In the third area, the cut-off boundaries of the pixel definition layer, the planarization layer, and the insulating layer are arranged in sequence along a fifth direction; in the third area, the cut-off boundaries of the pixel definition layer, the planarization layer, and the insulating layer are the side boundaries of the pixel definition layer, the planarization layer, and the insulating layer close to the second dam. The fifth direction is the direction in which the third area is far from the display area and close to the second dam.

38. The display substrate according to claim 37, wherein, In the third area, the positive projection of the insulating layer and the planarization layer on the driving substrate at least partially overlap. A plurality of second outgassing ports are formed in the insulating layer, and the positive projection of the plurality of second outgassing ports on the driving substrate is located in the overlapping region of the positive projections of the insulating layer and the planarization layer, and the plurality of second outgassing ports are evenly distributed. The display substrate further includes a plurality of third filling structures, and the plurality of third filling structures are provided on the same layer as the pixel definition layer and made of the same material. The plurality of third filling structures correspond to the plurality of second outgassing ports one by one, and the positive projection of each third filling structure on the driving substrate covers its corresponding second outgassing port.

39. The display substrate according to claim 38, wherein, The planarization layer in the third area has the first ramp area and the flat area, and the flat area and the first ramp area are arranged in sequence along the fifth direction. The positive projection of the plurality of second outgassing ports on the driving substrate is located in the positive projection area of the flat area on the driving substrate.

40. The display substrate according to claim 38, wherein, In the third area, the planarization layer includes a first sub-layer, a second sub-layer, and a third sub-layer, and the first sub-layer, the second sub-layer, and the third sub-layer are stacked in sequence away from the driving substrate. The first sub-layer, the second sub-layer, and the third sub-layer respectively have the first ramp area and the flat area, and the flat areas and the first ramp areas of the first sub-layer, the second sub-layer, and the third sub-layer are respectively arranged in sequence along the fifth direction. The positive projection of the plurality of second outgassing ports on the driving substrate is located in the overlapping region of the positive projections of the flat areas of at least two of the first sub-layer, the second sub-layer, and the third sub-layer on the driving substrate.

41. The display substrate according to claim 38, wherein, It further includes a second conductive pattern, which is provided on the same layer as the first conductive pattern, and the second conductive pattern is located between the insulating layer and the third filling structure. The positive projection of the second conductive pattern on the driving substrate at least covers a partial boundary of the second outgassing port. The orthographic projection of the boundary of the second conductive pattern on the driving substrate is located within the orthographic projection area of the insulating layer on the driving substrate; The orthographic projection of the third filling structure on the driving substrate covers the boundary of the second outgassing port and the boundary of the second conductive pattern.

42. The display substrate according to claim 37, wherein The portion of the insulating layer located in the display area and the portion located in the third area are separated from each other in the third area, The orthographic projection of the pixel defining layer on the driving substrate covers at least a part of the separation boundary of the insulating layer.

43. The display substrate according to claim 2, wherein, The slope angle range of the first ramp area is 15° to 80°.

44. The display substrate according to claim 6, wherein, The width range of the orthographic projection of the first ramp area on the driving substrate along the second direction is 1 to 30 μm.

45. A display panel, wherein, A display substrate according to any one of claims 1-44.

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