Method for fabricating double superlattices obtained by layer transfer

Abstract

The invention relates to a method (500) for fabricating a structure comprising a stack of superlattices, comprising the steps of: forming (510Car) a first superlattice (Stck1) on a first substrate by stacking a plurality of first channel layers alternating with a plurality of first sacrificial layers; forming (520Don) a second superlattice (Stck2) on a second substrate by stacking a plurality of second channel layers alternating with a plurality of second sacrificial layers; and assembling (560) the second superlattice (Stck2) on the first superlattice (Stck1) at a dielectric separation layer which separates the first superlattice (Stck1) and the second superlattice (Stck2) and keeps them attached to one another, the first superlattice (Stck1), the separation layer and the second superlattice (Stck2) being stacked in this order.

Description

METHOD FOR PRODUCING DOUBLE SUPERNETWORKS OBTAINED BY LAYER TRANSFER TECHNICAL FIELD OF THE INVENTION

[0001] The invention relates generally to superlattices, consisting of at least one periodic stack of thin layers, and particularly to superlattices including layers of semiconductor materials. More particularly, the invention relates to double superlattices. TECHNOLOGICAL BACKGROUND

[0002] Superlattices have attracted attention for their mechanical and semiconducting properties, and for the possibility they offer of forming quantum dots.

[0003] They are also used for the development of so-called nanosheet transistors, also known as Nanosheet transistors, or GAAFET for Gate-all-around Field-Effect Transistors in English terminology, whose conduction channels are formed by a stack of layers of nanometric thickness each surrounded by a gate metal, as described in US patents 10,249,739 B2 and US 11,018,222 B1. These are semiconductor structures with an enveloping gate, or GAA for Gate-All-Around in English terminology.

[0004] This principle has been adopted to form so-called CFET transistors, for Complementary Field Effect Transistor in English terminology, presenting a three-dimensional structure formed using a pair of stacked superlattices: a first superlattice formed on a substrate is used to form an n-type transistor while a second superlattice formed on the first superlattice is used to form a p-type transistor, or vice versa. This three-dimensional structure is advantageous in terms of integration compared to conventional approaches used to implement CMOS technology, which usually employs p-type transistors and n-type transistors fabricated side-by-side in the same plane.In particular, the CFET approach makes it possible in principle to halve the size of a pair of p- and n-type transistors, or to shorten the connections between the two transistors and therefore to reduce the electrical resistance of the corresponding connections. This approach is described for example in documents US 2019 / 0319095 A1, US 2021 / 0104523 A1, and US 2023 / 0326925 A1.

[0005] Whether it is Nanosheet transistors or CFET transistors, the manufacturing processes considered involve the fabrication of superlattices comprising stacks of two alternating types of materials: one is intended to form the channel regions of the transistors, the other to form sacrificial layers intended to be removed to be replaced by a gate dielectric and gate metal structure during the fabrication of the transistors.

[0006] Manufacturing CFET transistors requires stacking two types of transistors, n-type and p-type, on top of each other. Two approaches are possible.

[0007] The first approach is called "sequential", in the sense that the transistors of the two types are formed sequentially, during separate steps. In this approach, a semiconductor structure made of silicon or other semiconductor material, or a superlattice intended to form second Nanosheet transistors, is transferred onto a semiconductor substrate already carrying, for example, first Nanosheet transistors. First, the first transistors are formed on the substrate, then the semiconductor structure is transferred onto it, in which the second transistors are then formed. The thermal budget for the process of transferring the semiconductor structure and for forming the second transistors is limited by the need to avoid degrading the first transistors.Furthermore, the alignment control of the second transistors with the first transistors must be extremely strict and specific electrical contact structures between the two stages must be provided.

[0008] The second approach is called "monolithic", in the sense that the first and second transistors are formed on the same substrate, at least part of the manufacturing steps being applied simultaneously to all of the layers in which the first and second transistors are formed. Reference may be made to document US 2019 / 0319095 A1. One of the main advantages of this approach is the self-alignment of the second transistors on the first transistors, which allows a higher density of transistors on the substrate, and reduces parasitic capacitances and resistances between the first and second transistors.

[0009] The monolithic approach requires thicker superlattices as the starting structure than the sequential approach, since these superlattices form the basic structure of two stacked transistors fabricated simultaneously. Superlattices are generally fabricated epitaxially. However, the number of stackable layers for the formation of these superlattices is limited by the critical epitaxy thickness, a thickness beyond which the quality of the deposited layers degrades due to elastic relaxation and / or plastic relaxation phenomena. The monolithic approach is close to and could require exceeding the critical epitaxy thickness.

[0010] Furthermore, the monolithic approach is technologically more complex to implement than the sequential approach, in particular for the formation of a dielectric separation layer between the first transistors and the second transistors. This favors the integration of the internal spaces of the structure and the formation of the metal layers for the sources and drains of the transistors. The vertical distance between the first transistors and the second transistors can be reduced to the thickness of the dielectric layer, with positive effects on the reduction of parasitic capacitances and resistances between the first and second transistors. However, obtaining such a dielectric layer requires a complex procedure and the use of a sacrificial layer removed to leave space for the dielectric layer.This sacrificial layer associated with the dielectric separation layer must be compatible with a sacrificial layer intended to form a space for receiving the dielectric and gate metal layers. Thus, the two sacrificial layers used must be able to be selectively attacked with respect to each other and with respect to the semiconductor material forming the conduction channel of the transistors. For example, silicon is used for the channel, and silicon alloyed with different percentages of germanium for the sacrificial layers. From a technical point of view, although such structures can be used, obtaining them remains complex and delicate.

[0011] Document US 2021 / 082901 A1 discusses the assembly of multilayer stacks formed on separate or non-separate substrates.

[0012] US 2023 / 197721 A1 discusses bonding substrates to form stacked transistors.

[0013] Document US 2023 / 197721 A1 discusses the formation of structures comprising a stress-relaxed layer.

[0014] Thus, there is a need for superlattice structures comprising layers in sufficient number and quality to guarantee the homogeneity and performance of transistors formed from these layers. In addition, the manufacturing processes of CFET transistors require basic structures facilitating and making their manufacturing more reliable, and, if possible, improving the characteristics of the devices obtained, in particular miniaturization, parasitic capacitances, or even the electrical resistances of the connections.

[0015] The applicant's objective is to provide a method for manufacturing a structure capable of facilitating the integration and production of Nanosheet transistors, and more specifically CFET transistors, i.e. p-type transistors and stacked n-type transistors. This manufacturing method must preferably be particularly suited to the monolithic approach to the manufacture of CFET transistors.

[0016] To achieve this aim, one aspect of the invention is a method of manufacturing a structure comprising a stack of superlattices, the method comprising the steps of: forming a first superlattice on a first substrate by stacking a plurality of first channel layers alternating with a plurality of first sacrificial layers; forming a second superlattice on a second substrate by stacking a plurality of second channel layers alternating with a plurality of second sacrificial layers; forming an embrittlement plane of the second substrate by implanting ions of a light species into the second substrate through the second superlattice;and assembling the second superlattice to the first superlattice at a dielectric separation layer that separates and holds the first superlattice and the second superlattice attached to each other, the first superlattice, the separation layer and the second superlattice being stacked in that order; and removing at least a portion of the second substrate by fracturing the second substrate, and removing that at least a portion of the second substrate, after the assembling step.;

[0017] A first advantage of the process is to provide a stack of superlattices which can be either identical or distinct in composition and / or orientation.

[0018] A second advantage of the process is the possibility of exceeding the critical epitaxy thickness for the structures obtained, which limits the number and thickness of layers that can be epitaxied on top of each other without losing quality in the crystalline structures of these layers.

[0019] A third advantage of the method lies in the provision within the stack of a separation layer between two superlattices, this layer being able to have structural characteristics incompatible with conventional methods of forming superlattices. Indeed, superlattices are conventionally formed by successive depositions of layers by epitaxy. However, with the present method, the separation layer can be made of a dielectric such as a nitride or an oxide which can be amorphous, incompatible with the formation by epitaxy of semiconductor layers of good crystalline quality on the surface of this amorphous layer: deposition by epitaxy requires on the contrary a crystalline base layer.The present invention thus makes it possible to use any type of dielectric, for example SiN, SiCN, or even SiO2, which can be chosen according to its own dielectric characteristics and its compatibility with the steps planned for the manufacture of transistors based on the stacking of super networks.

[0020] A fourth advantage arises from the intended applications for this superlattice stack, which is the formation of CFET transistors. The dielectric separation layer can be configured to perform an electrical isolation function between the stacked transistors, but also serve as etch stop layers for differentiated treatments between the transistors or the integration of such structures on the back side of the carrier substrate.

[0021] Thus, the manufacturing method according to the invention is suitable for the production of structures which can serve as the basis for a monolithic method for producing an electronic circuit integrating CFET transistors.

[0022] According to additional non-limiting characteristics of the method according to the invention, considered individually or according to any technically feasible combination:

[0023] - the separation layer can be continuously formed in a plane parallel to a surface of the first substrate on which the first superlattice is formed;

[0024] - the first channel layers and the second channel layers may each be formed of a semiconductor material, and the first sacrificial layers and the second sacrificial layers may each be formed of a material capable of exhibiting a faster etch rate than the first channel layers and the second channel layers, respectively;

[0025] - the method may further comprise a step of removing at least a portion of the second substrate after the assembly step;

[0026] - the method may further comprise a step of releasing a channel layer from the second superlattice after the step of removing the at least part of the second substrate;

[0027] - the method may further comprise the steps of (i) forming a first covering layer of the first superlattice before the assembling step, and (ii) forming a second covering layer of the second superlattice before the assembling step, wherein the assembling step may comprise contacting the first covering layer with the second covering layer, the first covering layer and the second covering layer together forming the separation layer;

[0028] - the first capping layer and the second capping layer may each comprise silicon, and at least one of the first capping layer and the second capping layer may be formed of an oxide;

[0029] - at least one of the first covering layer and the second covering layer formed of an oxide can be formed by a step of forming a silicon layer followed by a step of oxidizing this silicon layer;

[0030] - the method may further comprise a step of forming an etch stop layer on the second substrate before forming the second superlattice;

[0031] - the attack stop layer may be formed from a layer of the same material as the second sacrificial layers;

[0032] - the first channel layers and the second channel layers may be formed of silicon; the first sacrificial layers may be formed of a first alloy of silicon and germanium; and the second sacrificial layers may be formed of a second alloy of silicon and germanium; and

[0033] - the method may comprise the steps of forming a second capping layer of the second superlattice before the assembly step, the second capping layer comprising silicon and being formed on and in direct contact with one of the second sacrificial layers; and oxidizing the second capping layer.

[0034] The invention extends to a structure of a superlattice stack, comprising: a carrier substrate; a first superlattice on the carrier substrate; a dielectric separation layer on the first superlattice; and a second superlattice on the separation layer.

[0035] According to additional non-limiting characteristics of the structure according to the invention, considered individually or according to any technically feasible combination:

[0036] - the separation layer can be continuously formed in a plane parallel to a surface of the carrier substrate supporting the first superlattice;

[0037] - the first superlattice may be formed from a stack of a plurality of first channel layers alternating with a plurality of first sacrificial layers; the second superlattice may be formed from a stack of a plurality of second channel layers alternating with a plurality of second sacrificial layers; the first channel layers and the second channel layers may each be formed from a semiconductor material, and the first sacrificial layers and the second sacrificial layers may each be formed from a material capable of exhibiting a faster etch rate than the first channel layers and the second channel layers, respectively;

[0038] - the separation layer may comprise a layer formed from silicon nitride, silicon carbide nitride, or silicon oxide; and

[0039] - the separation layer may comprise a layer formed from silicon oxide. BRIEF DESCRIPTION OF THE FIGURES

[0040] Other characteristics and advantages of the invention will emerge from the detailed description of the invention which follows with reference to the appended figures in which:

[0041] Illustrates a manufacturing method according to the invention;

[0042] Illustrates a continuation of the process of the;

[0043] Illustrates variants of structures that can be obtained by the process of figures 1 and 2;

[0044] Illustrates variations of the separation layers of the ; and

[0045] This is a diagram summarizing the manufacturing process of Figures 1 and 2. DETAILED DESCRIPTION OF THE INVENTION

[0046] Method of implementation

[0047] An embodiment of the present invention is described by means of Figures 1 to 5 and the associated description below.

[0048] Illustrates in (C) a Strc structure formed from a carrier substrate Car, a first superlattice Stck1, a separation layer Sep, and a second superlattice Stck2, stacked in this order. The first superlattice Stck1 comprises a plurality of first layers Ch1 stacked alternately with a plurality of first layers Sac1, preferably such that each first layer Ch1 is interposed between and in direct contact with two of the first layers Sac1. The second superlattice Stck2 comprises a plurality of second layers Ch2 stacked alternately with a plurality of second layers Sac2, preferably such that each second layer Ch2 is interposed between and in direct contact with two of the second layers Sac2.

[0049] The first Ch1 layers and the second Ch2 layers are layers formed of at least one semiconductor material for forming channel regions of transistors and may be referred to as the first channel Ch1 layers and the second channel Ch2 layers, respectively. These channel layers may be formed of the same material, or of different materials.

[0050] The first Sac1 layers and the second Sac2 layers are layers formed from at least one material capable of exhibiting faster etching rates than the first Ch1 layers and the second Ch2 layers, and may be referred to as the first sacrificial Sac1 layers and the second sacrificial Sac2 layers, respectively. These sacrificial layers may be formed from the same material, or from different materials. In particular, the Sac1 layers may have a Si composition 1-X Ge xand Sac2 layers can have a Si composition 1-y Ge y where x and y represent the proportions of germanium in the Sac1 and Sac2 layers, respectively, with x being different from or equal to y. These Sac1 and Sac2 layers of SiGe alloy can be associated with Ch1 and Ch2 layers of silicon, thanks to the compatibility of epitaxial growth of these two materials which have a fairly close lattice parameter. The proportions x and y are preferably less than 40%, for example between 15% and 35%.

[0051] The second layers Sac1 and Sac2 are intended to serve as sacrificial layers in a Nanosheet transistor formation procedure, during which the layers Sac1 and Sac2 are removed by etching, which may be chemical, so as to obtain a structure of floating ribbons formed of the layers Ch1 and Ch2. These floating ribbons will subsequently be surrounded by a gate dielectric layer and a gate metal so as to form Nanosheet transistors.

[0052] Figures 1, 2 and 5 illustrate a method for manufacturing the Strc structure, which is advantageously based on the separate manufacturing of the two superlattices Stck1 and Stck2 on two respective substrates, then the transfer of the second superlattice Stck2 onto the first superlattice Stck1. The first and second superlattices each comprise at least two channel layers Ch1 and Ch2 respectively. The diagram represents a diagram showing the steps of the manufacturing method 500.

[0053] Illustrates in (A) the formation of the first Stck1 supernetwork on a Car carrier substrate, during a step 510 Car . In this example, the carrier substrate Car consists of a monocrystalline silicon wafer.

[0054] On a surface S Car of the Car substrate, Ch1 layers of silicon Si 5 to 15 nm thick, preferably 7 to 10 nm thick, are grown by epitaxy, alternating with Sac1 layers of a first alloy of silicon and germanium of formula Si 1-x Ge x 5 to 10 nm thick, preferably 6 to 9 nm thick, and where x represents the percentage of germanium in the alloy, preferably starting and ending with a Sac1 layer. On the last Sac1 layer, 520 are formed during a step Cara covering layer Cap1, here formed of silicon Si and having the function of preventing the oxidation of the last layer Sac1. The layer Cap1 can have a thickness of between 1 and 2 nm.

[0055] Illustrates in (B) the formation of the second Stck2 supernetwork on a donor substrate Don, during a step 520 Don . In this example, the donor substrate Don consists of a monocrystalline silicon wafer.

[0056] On a surface S Don of the Don substrate, Ch2 layers of silicon Si 5 to 15 nm thick, preferably 7 to 10 nm thick, are grown by epitaxy, alternating with Sac2 layers of the first alloy of silicon and germanium of formula Si 1-x Ge x5 to 10 nm thick, preferably 6 to 9 nm thick. Preferably, the growth is carried out so that one begins and ends with a Sac2 layer. On the last Sac2 layer, a covering Cap2 layer, made of silicon, is formed during a step 530 Don. The Cap2 layer has the function of preventing the oxidation of the last Sac2 layer, and it is preferentially configured to be oxidized subsequently to form a bonding interface with the Cap1 layer. The thickness of the Cap2 layer depends on the thickness targeted for the future oxidized layer. By aiming for an oxide layer with a thickness between 10 and 35 nm, the Cap2 layer in this case must have a thickness between approximately 4 and 16 nm. This Cap2 layer is however optional, its interest depending on the ease of oxidizing the material constituting the last layer of the second Stck2 superlattice and the interest in integrating it into a dielectric separation layer between the two superlattices.

[0057] Optionally, before the formation of the second superlattice Stck2, a layer Stp formed for example from the first alloy of silicon and germanium of formula Si can be formed on the donor substrate Don 1-x Ge xwith a thickness between 5 and 10 nm, during a step 510 Don . This layer is an etch stop layer and is intended to protect the integrity of the layers of the second Stck2 superlattice during the fabrication steps following the fracture of the donor substrate described later and illustrated in (B) and (C) of the.

[0058] Illustrates in (C) an oxidation of the Cap2 layer of silicon Si to form a covering layer Ox2 of silicon oxide SiO2 of 10 to 35 nm thickness, during a step 540 Don oxidation.

[0059] Preferably, the carrier substrates Car and donor Don respectively comprising the first and second superlattices are substantially identical. This advantageously makes it easy to produce them on a large scale, thus facilitating their industrialization. Furthermore, the use of substantially identical support and donor substrates advantageously makes it possible to have a symmetrical assembled structure having similar thermal expansion coefficients for the two carrier and donor substrates, which advantageously avoids problems of mechanical deformation following the bonding steps and future heat treatments.

[0060] The oxidation temperature and duration used are limited to avoid exceeding the authorized thermal budget to avoid or at least limit the diffusion of germanium from one layer to another of the superlattices, and in particular the contamination of the channel layers by germanium over their entire thicknesses.

[0061] Also illustrated in (C) is an implantation of light species such as hydrogen, helium, or a combination of such species into the donor substrate Don through the surface S Don , the second supernetwork Stck2 and the covering layer Ox2, so as to form a weakening plane Imp in the donor substrate Don, during a step 550 Don .

[0062] Following the formation of the embrittlement plane Imp, the donor substrate Don is turned over and the oxide layer Ox2 is brought into intimate contact with the silicon layer Cap1 and is assembled there, for example by molecular bonding or any other assembly technique by bringing into direct contact surfaces of elements to be assembled, so as to obtain the structure illustrated in (A) of the, during an assembly step 560. The separation layer Sep is formed at this step by bonding the last layers formed respectively on the carrier substrate Car and on the donor substrate Don, and corresponds to the assembly formed by the layers separating the first superlattice Stck1 and the second superlattice Stck2, the layers Cap1 and Ox2 in the present embodiment, as illustrated by the. This separation layer Sep preferably completely overlaps the donor substrate Don. In addition, the separation layer Sep is continuously formed in a plane parallel to the surface SCar of the carrier substrate Car supporting the first superlattice Stck1. Even if the separation layer does not strictly overlap the entire carrier substrate Car, it is at least formed continuously over an area intended to form an assembly of semiconductor components such as transistors, possibly an assembly of CFET transistors.

[0063] Illustrates in (B) the fracture of the donor substrate Don at the level of the embrittlement plane Imp obtained by ion implantation, so that a part Don b is removed from the structure shown in (A) while a part Don a remains fixed there, during a step 570 of fracture and removal. This fracture can be obtained by heat treatment, possibly assisted by mechanical stress to initiate the fracture, according to conventional layer transfer techniques well known in the field of microelectronics.

[0064] Following assembly and fracture of the donor substrate, a heat treatment can be applied to consolidate the assembly and repair the assembled layers. The temperature and duration of the heat treatment are limited to avoid exceeding the authorized thermal budget to avoid or at least limit the diffusion of germanium from one layer to another of the superlattices, and in particular the contamination of the channel layers by germanium over their entire thickness. The heat treatment can typically consist of an annealing of 2 hours or less at a maximum temperature of 750°C and preferably below 700°C.

[0065] An alternative to the formation of an embrittlement plane and the fracture of the Don donor substrate at this plane may be to thin the Don donor substrate after its assembly, for example by etching, grinding and / or chemical mechanical polishing (CMP). This thinning may be used to completely remove the second Don substrate if it is pushed, for example, up to the barrier layer Stp.

[0066] Illustrates in (C) the structure illustrated in (B) after it has been subjected to mechanical and / or chemical attacks to eliminate the Don part a of the donor substrate Don, and of the etch stop layer Stp, during a disengagement step 580. Thus, the layer Ch2 of the second superlattice furthest from the carrier substrate Car is disengaged during this step.

[0067] The structure at (C) of the presents the structure Strc formed of the carrier substrate Car, the first superlattice Stck1, the capping layer Cap1 formed of silicon, the layer Ox2 of silicon oxide, and the second superlattice Stck2, stacked in this order. The capping layer Cap1 and the layer Ox2 of silicon oxide form a dielectric separation layer Sep between the first superlattice Stck1 and the second superlattice Stck2, as indicated by the at (C). The separation layer is considered a dielectric layer in that it is formed at least in part of a material considered to be dielectric, such as silicon nitride, silicon carbide nitride, or silicon oxide. This structure is ready to be subjected to a monolithic process for forming CFET transistors.

[0068] The figures are labeled "Si" or "SiGe" at the locations of certain layers, and in particular those forming the Stck1 and Stck2 superlattices, in order to increase their readability by indicating their compositions for a given example. These indications are not, however, to be interpreted as limiting the nature of the layers thus annotated. Other materials, and in particular those cited in this description, may be used to form these layers.

[0069] Illustrated in (C') and (C'') are the structures Strc' and Strc'', respectively, with possible variations Sep' and Sep'' of the separation layer Sep of the structure Strc. In (C), the separation layer Sep is formed by bonding the covering layer Ox2, formed of oxide, to the covering layer Cap1, constituting the last layers formed on the donor substrate Don and on the carrier substrate Car, respectively.

[0070] A first variation illustrated in (C') consists of forming a silicon oxide layer Ox1 as the last layer formed on the carrier substrate Car and forming a silicon cover layer Cap2 as the last layer formed on the donor substrate Don. Thus, the separation layer Sep' is formed by the assembly by molecular bonding of the Ox1 layer with the Cap2 layer.

[0071] A second variation illustrated in (C'') consists of forming two layers of silicon oxide as the last respective layers formed on the substrates Car and Don. Thus, the separation layer Sep'' is formed by the assembly by molecular bonding of these two layers of silicon oxide, finally forming only one layer Ox of silicon oxide.

[0072] The separating layer Sep, which is also the layer linking the two superlattices to each other, is not limited to being formed from crystalline silicon and / or amorphous silicon oxide obtained by oxidation of silicon. Thus, although illustrates in (A) and (B) a process in which the oxide layer Ox2 is formed by the oxidation of a silicon layer, the Ox2 layer could be formed by direct deposition of a silicon oxide layer. This remark applies to the variations illustrated in (C') and (C'') of the for the Ox1 layer of (C') and to the oxide layers forming the Ox layer of (C'').

[0073] The separation layer may also be composed of layers formed from amorphous silicon or other materials as long as these are compatible with the superlattice processing method envisaged subsequently. Thus, in general, dielectric, semiconductor or metallic materials may be used to form the layers composing the separation layer, the main constraint being that these materials must be in the form of layers of sufficiently high flatness and sufficiently low roughness to be assembled by a direct bonding method such as molecular bonding. In the case where the superlattices are intended to form CFET transistors, dielectric materials and / or semiconductor materials will preferably be used. For example, one or a combination of materials chosen from silicon nitride (SiN), silicon carbide nitride (SiCN), an oxide thereof (SiON, SiCNO x), or silicon oxide (SiO2) deposited or formed by an oxidation method. Dielectric materials known as "high k" materials in English terminology, such as HfO2, ZrO2, La2O3, Al2O3, TiO2, SrTiO3, their alloys or their alloys with silicon can also be used. More generally, any type of dielectric material used in the semiconductor industry can be used as a dielectric layer, protective layer, hard mask (hard mask in English terminology), via coating (liners for TSVs or through-silicon vias in English terminology).

[0074] Illustrates such alternatives with, in (A), a Sep separation layer formed, in this order, of Sep separation layers a , Sep b and Sep c Molecular bonding is performed at an interface plane Int located between the Sep layers c and Sep b, one of which is formed of silicon, amorphous silicon, or silicon oxide, the other being formed of amorphous silicon or silicon oxide. The Sep layer a can be formed from silicon nitride, silicon carbide nitride, silicon oxide, or other dielectric materials. Sep layers a and Sep b can be formed on the donor substrate Don instead of the Ox2 layer and the Sep layer c can be formed on the carrier substrate Car instead of the Cap1 layer. Alternatively, the Sep layers a and Sep b can be formed on the donor substrate Car instead of the Cap1 layer and the Sep layer c can be formed on the donor substrate Don instead of the Ox2 layer.

[0075] The configuration illustrated in (B) is different from the configuration illustrated in (A) in that it further comprises a separation layer Sep dformed on the same side of the interface plane Int as the Sep layer c , and may be formed from silicon nitride, silicon carbide nitride, silicon oxide, or other dielectric materials.

[0076] The separation layers of the variants illustrated by constitute MDLs, or Multiple Dielectric Layers in English terminology, and can be used to improve molecular bonding and adhesion strength for later manufacturing steps.

[0077] The manufacturing process illustrated in Figures 1 and 2 allows for a superposition of two superlattices. In addition, the process can be repeated to stack an arbitrary number of superlattices. Thus, the critical epitaxy thickness can be exceeded: each of the superlattices taken individually can respect this thickness so as to be formed of high-quality layers, and their stacking allows an assembly of superlattices exceeding the critical thickness while maintaining the quality of the layers composing them.

[0078] The epitaxial formation of the layers constituting the superlattices involves the reproduction of the crystalline structure from one layer to another, so that the Ch1 (or Ch2) and Sac1 (or Sac2) layers, for example in Si and SiGe respectively, have the same crystalline structure. Usually, it is not possible to epitaxially grow a semiconductor layer with acceptable characteristics for the purpose of forming transistors on an amorphous layer such as a dielectric layer, and more particularly an oxide layer. Indeed, this does not constitute a suitable basis for the epitaxial growth of a high-quality crystalline semiconductor layer. The separation layer obtained by the method according to the invention makes it possible to position a dielectric layer between two superlattices formed from semiconductor layers of sufficient quality to produce transistors for commercial applications.

[0079] Furthermore, the separation layer can be adapted (composition, thickness of the layer(s) forming it) to the intended use of the stacked superlattices. It is thus possible to ensure a desired electrical insulation between the two superlattices Stck1 and Stck2 by modulating, for example, the thickness of the Cap2 layer which, once oxidized into an Ox2 layer, forms a high-quality dielectric layer of chosen thickness covering the entire structure, an entire wafer when the substrates are wafers.

[0080] The separation layer is formed continuously in a plane parallel to the upper surface of the substrate supporting it, covering substantially the entire surface of the substrate. Such a geometry contrasts with the situation found in CFET-type structures, in which a dielectric layer separating the n-type transistors and the p-type transistors follows the reliefs formed by the structures resulting from the formation of the transistors located between the substrate and this dielectric layer, and may be discontinuous.

[0081] Thus, the separation layer according to the invention may be of high quality, of chosen thickness, with in addition good thickness uniformity, and continuous over a portion of interest or over substantially the entire surface of a substrate, which makes it suitable for use as an etch stop layer, during the manufacturing process of the different transistors, or for differentiated treatment between the transistors formed in the first supernetwork and the transistors formed in the second supernetwork. Furthermore, by using a Car substrate of SOI type, it is also possible to produce a power supply network on the back side of the device (called BSPDN for BackSide Power Delivery Network in English terminology), using the BOX as an etch stop layer. A portion of interest may consist of a surface of a substrate intended to require the presence of the separation layer.

[0082] The carrier substrate Car and the donor substrate Don may comprise any semiconductor material. In addition to silicon, the semiconductor material may be germanium (Ge), a silicon-germanium alloy (SiGe), silicon carbide (SiC), silicon-germanium carbide (SiGeC), III-V compound semiconductors or II-VI compound semiconductors, or SOI type substrates (Silicon-On-Insulator in English terminology), and more generally any type of semiconductor substrate comprising a buried or surface layer of dielectric material. Such a dielectric layer may serve as an etch stop layer for the formation of structures on the rear face (on the side of the carrier substrate Car) of the structure obtained by the method described in Figures 1 and 2, or, in the case where it is located on the surface, as insulation in order to prevent the so-called "latch-up" phenomenon of an integrated circuit manufactured on the basis of this structure.

[0083] The Ch1 and Ch2 layers may be formed, for example, from silicon or a III-V type semiconductor compound. The Sac1 and Sac2 layers may be formed, for example, from silicon and germanium alloys generically referred to as SiGe. The Ch1 and Ch2 layers may be of the same composition in both Stck1 and Stck2 superlattices, and similarly, the Sac1 and Sac2 layers may be of the same composition Si 1-x Ge x in the two superlattices Stck1 and Stck2. This last point makes it possible to eliminate the sacrificial layers Sac1 and Sac2 during the same step.

[0084] Alternatively, the superlattices Stck1 and Stck2 can be of different natures and / or orientations. The orientation of the second superlattice with respect to the first superlattice is defined during the assembly step. The layers Sac1 (and Ch1) on the one hand and the layers Sac2 (and Ch2) on the other hand, can have different orientations, for example with crystallographic axes offset by 45°. One can also consider the use of strained silicon, silicon and germanium alloys SiGe or germanium for the channel layers of one or the other of the two superlattices or for both. When the two superlattices comprise alloys of silicon and germanium, the proportions of germanium in the alloy can be the same or different for the two superlattices. It is of course necessary to adapt the nature and characteristics of the sacrificial layers Sac1 and Sac2 to those of the layers Ch1 and Ch2.

[0085] Similarly, the numbers of channel layers and sacrificial layers in the two superlattices may be the same, respectively, or may be different.

[0086] The above embodiment has taken as an example associations between layers of silicon alternating with layers of silicon and germanium alloys to form the first superlattice and the second superlattice. However, the invention is not limited to this particular case, and could be applied for example (i) to superlattices consisting of layers of germanium alternating with layers of a silicon and germanium alloy, (ii) to superlattices consisting of layers formed from a first silicon and germanium alloy with a germanium content for example less than 20% alternating with layers formed from a second silicon and germanium alloy with a high germanium content, for example greater than 75%, (iii) to superlattices having layers of different crystallographic orientations, or (iv) to superlattices comprising layers of III-V semiconductor materials.

[0087] The embodiment described above relates to an association of superlattices intended to form transistors, and more specifically Nanosheet transistors or CFETs. The scope of the invention extends, however, beyond this field, and includes the combination of superlattices in general, not only in the field of semiconductors.

[0088] The invention is not limited to the embodiment described above and variations may be made thereto without departing from the scope of the invention as defined by the claims.

Claims

Method (500) for manufacturing a structure (Strc, Strc', Strc'') comprising a stack of superlattices, comprising the steps of:- forming (510 Car ) a first super network (Stck1) on a first substrate (Car), by stacking a plurality of first channel layers (Ch1) alternating with a plurality of first sacrificial layers (Sac1);- forming (520 Don ) a second superlattice (Stck2) on a second substrate (Don), by stacking a plurality of second channel layers (Ch2) alternating with a plurality of second sacrificial layers (Sac2);- forming (550 Don) a weakening plane (Imp) of the second substrate (Don) by implantation of ions of a light species in the second substrate (Don) through the second superlattice (Stck2);- assembling (560) the second superlattice (Stck2) to the first superlattice (Stck1) at a dielectric separation layer (Sep, Sep', Sep'') which separates and keeps fixed to each other the first superlattice (Stck1) and the second superlattice (Stck2), the first superlattice (Stck1), the separation layer (Sep) and the second superlattice (Stck2) being stacked in this order; and- eliminating (570) at least a part (Don b ) of the second substrate (Don) by fracturing the second substrate (Don), and removing this at least one part (Don b ) of the second substrate (Don), after the assembly step (560). The method of claim 1, wherein the separation layer (Sep, Sep', Sep'') is continuously formed in a plane parallel to a surface (S Car) of the first substrate (Car) on which the first super network (Stck1) is formed. The method of claim 1 or 2, wherein:- the first channel layers (Ch1) and the second channel layers (Ch2) are each formed of a semiconductor material, and- the first sacrificial layers (Sac1) and the second sacrificial layers (Sac2) are each formed of a material capable of exhibiting a faster etching rate than the first channel layers (Ch1) and the second channel layers (Ch2), respectively. The method of any one of claims 1 to 3, further comprising a step of removing (570) at least a portion (Don b ) of the second substrate (Don) after the assembly step (560). The method of claim 4, further comprising a step of releasing (580) a channel layer (Ch2) from the second superlattice (Stck2) after the step of removing (570) the at least one portion (Don b ) of the second substrate (Don). The method according to any one of claims 1 to 5, comprising the steps of:- forming (520 Car ) a first covering layer (Cap1, Ox1) of the first super network (Stck1) before the assembly step (560); and- forming (530 Don ) a second covering layer (Cap2, Ox2) of the second superlattice (Stck2) before the assembly step (560); wherein the assembly step (560) comprises bringing the first covering layer (Cap1, Ox1) into contact with the second covering layer (Cap2, Ox2), the first covering layer (Cap1, Ox1) and the second covering layer (Cap2, Ox2) together forming the separation layer (Sep, Sep', Sep''). The method of claim 6, wherein the first capping layer (Cap1) and the second capping layer (Cap2) each comprise silicon, and at least one of the first capping layer (Ox1) and the second capping layer (Ox2) is formed of an oxide. The method of claim 7, wherein at least one of the first covering layer and the second covering layer formed of an oxide is formed by a forming step (530 Don ) of a silicon layer (Cap2) followed by an oxidation step (540 Don ) of this layer of silicon. The method of any one of claims 1 to 8, further comprising a step of forming (510 Don ) of an etch stop layer (Stp) on the second substrate (Don) before the formation of the second superlattice (stck2). The method according to claim 9, wherein the etch stop layer is formed from a layer (Stp) of the same material as the second sacrificial layers (Sac2). The method according to any one of claims 1, 4, 5 to 10, wherein:- the first channel layers and the second channel layers are formed of silicon;- the first sacrificial layers are formed of a first alloy of silicon and germanium; and- the second sacrificial layers are formed of a second alloy of silicon and germanium. The method of claim 11, comprising the steps of:- forming (530 Don ) a second covering layer (Cap2) of the second superlattice (Stck2) before the assembly step (560), the second covering layer (Cap2) comprising silicon and being formed on and in direct contact with one of the second sacrificial layers (Sac2); and- oxidizing (540 Don ) the second covering layer.

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