Semiconductor element

Abstract

A semiconductor element according to an embodiment of the present disclosure comprises: a first semiconductor layer; and a first layer positioned on the first semiconductor layer, the first layer being provided with a first pad. The first layer includes a first insulating film positioned on the first pad, and a first electrode that contains a metal material and is provided to the first insulating film. The first electrode is electrically connected to the first pad and is provided up to the surface of the first insulating film. The first pad has a first portion and a second portion that is provided below the upper end of the first portion.

Description

semiconductor elements

[0001] The present disclosure relates to semiconductor devices.

[0002] An element has been proposed that has a structure in which a plurality of semiconductor substrates are stacked and is provided with aluminum pads that are used as electrodes for measurement terminals.

[0003] International Publication No. 2015 / 159766

[0004] In semiconductor devices, it is desirable to be able to accommodate junctions between metal electrodes.

[0005] It would be desirable to provide a semiconductor device suitable for bonding between metal electrodes.

[0006] A semiconductor device according to an embodiment of the present disclosure includes a first semiconductor layer and a first layer located on the first semiconductor layer and having a first pad provided thereon. The first layer includes a first insulating film located on the first pad and a first electrode including a metal material and provided on the first insulating film. The first electrode is electrically connected to the first pad and extends to the surface of the first insulating film. The first pad has a first portion and a second portion located below an upper end of the first portion. A semiconductor device according to an embodiment of the present disclosure includes a first semiconductor layer and a first layer located on the first semiconductor layer and having a first pad provided thereon. The first layer includes a wiring provided above the first pad, a first insulating film provided to cover the first pad and the wiring, and a first electrode including a metal material and provided on the first insulating film above the wiring. The first electrode is electrically connected to the first pad via the wiring and extends to the surface of the first insulating film.

[0007] FIG. 1 is a diagram illustrating a schematic configuration example of a semiconductor element according to a first embodiment of the present disclosure. FIG. 2 is a diagram illustrating a configuration example of a semiconductor element according to the first embodiment of the present disclosure. FIG. 3 is a diagram illustrating a configuration example of a semiconductor element according to a comparative example. FIG. 4 is a diagram illustrating a configuration example of a semiconductor element according to the first embodiment of the present disclosure. FIG. 5 is a diagram illustrating an example of a planar configuration of a semiconductor element according to the first embodiment of the present disclosure. FIG. 6 is a diagram illustrating an example of a cross-sectional configuration of a semiconductor element according to the first embodiment of the present disclosure. FIG. 7 is a diagram illustrating an example of a configuration example of a semiconductor element according to the first embodiment of the present disclosure. FIG. 8 is a diagram illustrating another configuration example of a semiconductor element according to the first embodiment of the present disclosure. FIG. 9A is a diagram illustrating an example of a method for manufacturing a semiconductor element according to the first embodiment of the present disclosure. FIG. 9B is a diagram illustrating an example of a method for manufacturing a semiconductor element according to the first embodiment of the present disclosure. FIG. 9C is a diagram illustrating an example of a method for manufacturing a semiconductor element according to the first embodiment of the present disclosure. FIG. 9D is a diagram illustrating an example of a method for manufacturing a semiconductor element according to the first embodiment of the present disclosure. FIG. 9E is a diagram for explaining an example of a manufacturing method of a semiconductor element according to the first embodiment of the present disclosure. FIG. 9F is a diagram for explaining an example of a manufacturing method of a semiconductor element according to the first embodiment of the present disclosure. FIG. 10 is a diagram for explaining an example of a cross-sectional configuration of a semiconductor element according to a second embodiment of the present disclosure. FIG. 11 is a diagram for explaining an example of a planar configuration of a semiconductor element according to the second embodiment of the present disclosure. FIG. 12 is a diagram for explaining an example of a configuration of a semiconductor element according to the second embodiment of the present disclosure. FIG. 13 is a diagram for explaining an example of a configuration of a semiconductor element according to the second embodiment of the present disclosure. FIG. 14A is a diagram for explaining another example of a planar configuration of a semiconductor element according to the second embodiment of the present disclosure. FIG. 14B is a diagram for explaining another example of a planar configuration of a semiconductor element according to the second embodiment of the present disclosure. FIG. 15A is a diagram for explaining an example of a manufacturing method of a semiconductor element according to the second embodiment of the present disclosure. FIG. 15B is a diagram for explaining an example of a manufacturing method of a semiconductor element according to the second embodiment of the present disclosure. FIG. 15C is a diagram for explaining an example of a manufacturing method of a semiconductor element according to the second embodiment of the present disclosure.FIG. 15D is a diagram for explaining an example of a manufacturing method for a semiconductor element according to the second embodiment of the present disclosure. FIG. 15E is a diagram for explaining an example of a manufacturing method for a semiconductor element according to the second embodiment of the present disclosure. FIG. 15F is a diagram for explaining an example of a manufacturing method for a semiconductor element according to the second embodiment of the present disclosure. FIG. 15G is a diagram for explaining an example of a manufacturing method for a semiconductor element according to the second embodiment of the present disclosure. FIG. 16 is a diagram for explaining another configuration example of a semiconductor element according to the second embodiment of the present disclosure. FIG. 17 is a diagram for explaining an example of a configuration of a semiconductor element according to Modification 1 of the present disclosure. FIG. 18 is a diagram for explaining an example of a configuration of a semiconductor element according to Modification 1 of the present disclosure. FIG. 19 is a diagram for explaining an example of a configuration of a semiconductor element according to the third embodiment of the present disclosure. FIG. 20 is a diagram for explaining an example of a configuration of a semiconductor element according to the third embodiment of the present disclosure. FIG. 21 is a diagram for explaining an example of a configuration of a semiconductor element according to Modification 2 of the present disclosure.

[0008] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be made in the following order: 1. First embodiment 2. Second embodiment 3. Third embodiment

[0009] 1. First Embodiment Fig. 1 is a diagram illustrating a schematic configuration example of a semiconductor device according to a first embodiment of the present disclosure. Fig. 1 illustrates an example of a cross-sectional configuration of a semiconductor device 1. As shown in Fig. 1, the semiconductor device 1 includes a semiconductor chip 10 and a bonding layer 112. Examples of the semiconductor chip 10 include a processor, a memory, a sensor, and other integrated circuits. The semiconductor chip 10 is, for example, a general-purpose memory, a general-purpose logic, or a custom-designed chip.

[0010] The semiconductor chip 10 may be, for example, a general-purpose logic such as a digital signal processor (DSP) or a field programmable gate array (FPGA), or may be a general-purpose memory such as a dynamic random access memory (DRAM), a static random access memory (SRAM), or a magnetic random access memory (MRAM).

[0011] The bonding layer 112 is a layer on which electrodes used for bonding between metal electrodes are provided. As will be described later, for example, metal electrodes made of copper (Cu) are formed on the bonding layer 112 as terminals (electrodes) for Cu-Cu connection. The bonding layer 112 can be provided so as to be stacked on the semiconductor chip 10 of a general-purpose memory, general-purpose logic, or the like.

[0012] The semiconductor element 1 has a configuration in which a semiconductor chip 10 and a bonding layer 112 are stacked in the Z-axis direction. As shown in Fig. 1, the left-right direction on the paper, which is perpendicular to the Z-axis direction, is the X-axis direction, and the direction perpendicular to the Z-axis and X-axis directions is the Y-axis direction. In the following figures, directions may be indicated based on the direction of the arrow in Fig. 1.

[0013] The semiconductor chip 10 has a semiconductor layer 101 and a wiring layer 111. The semiconductor element 1 has a structure in which the semiconductor layer 101, the wiring layer 111, and the bonding layer 112 are stacked. In the example shown in FIG. 1 , the semiconductor layer 101 is provided in a layer 201 of the stacked layers. The wiring layer 111 and the bonding layer 112 are provided in a layer 202. The layer 202, which has the wiring layer 111 and the bonding layer 112, is located above the layer 201, which has the semiconductor layer 101.

[0014] The semiconductor layer 101 is configured by a semiconductor substrate, for example, a Si (silicon) substrate. Various circuit elements, for example, transistors, diodes, resistors, capacitors, etc., can be formed in the semiconductor layer 101. In the example shown in FIG. 1 , a wiring layer 111 is provided on the upper surface of the semiconductor layer 101.

[0015] The semiconductor layer 101 may be an SOI (Silicon On Insulator) substrate, a SiGe (Silicon Germanium) substrate, a SiC (Silicon Carbide) substrate, etc. The semiconductor layer 101 may be made of a III-V group compound semiconductor material, or may be formed using other semiconductor materials.

[0016] The wiring layer 111 is provided by being stacked on the semiconductor layer 101. The wiring layer 111 includes, for example, a conductor film and an insulating film, and has a plurality of wirings and vias (VIAs). The wiring layer 111 has, for example, a configuration in which a plurality of wirings are stacked via an insulating film serving as an interlayer insulating film (interlayer insulating layer). The wiring layer 111 includes, for example, two or more layers of wirings, or three or more layers of wirings.

[0017] The wiring of the wiring layer 111 is formed using a metal material such as aluminum (Al), tungsten (W), copper (Cu), etc. The wiring of the wiring layer 111 may be configured using polysilicon (Poly-Si) or other conductive materials. The interlayer insulating film is formed using, for example, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), etc. The semiconductor layer 101 and the wiring layer 111 can be collectively referred to as a substrate (or a circuit layer).

[0018] 1 , the wiring layer 111 has an insulating film 81 and is located between the semiconductor layer 101 and the bonding layer 112. For example, the insulating film 81 is configured as a single layer film made of one of an oxide film (e.g., a silicon oxide film), a nitride film (e.g., a silicon nitride film), an oxynitride film, or the like, or a stacked film made of two or more of these films.

[0019] The bonding layer 112 is provided so as to be stacked with the semiconductor layer 101 and the wiring layer 111. As in the example shown in Fig. 1 , the bonding layer 112 is provided so as to be stacked with the wiring layer 111 and is located on the wiring layer 111. The bonding layer 112 may include, for example, a conductor film and an insulating film, and may have wiring, vias, etc.

[0020] The bonding layer 112 has an insulating film 82 and an insulating film 83. The insulating film 82 and the insulating film 83 are formed on the insulating film 81. The insulating film 82 and the insulating film 83 are each configured, for example, by a single layer film made of one of an oxide film (e.g., a silicon oxide film), a nitride film (e.g., a silicon nitride film), an oxynitride film, or the like, or a stacked film made of two or more of these films.

[0021] The semiconductor element 1 is also provided with pads 15 (PADs), vias 20, and electrodes 30. The pads 15 are electrodes formed using, for example, aluminum (Al). The semiconductor element 1 is provided with a plurality of pads 15 electrically connected to circuit elements inside the semiconductor element 1. The pads 15 are formed on an insulating film 81, for example, as shown in FIG. 1 . Note that a barrier metal may be provided between the pads 15 and the insulating film 81.

[0022] In the example shown in FIG. 1, the pad 15 is formed by the wiring in the uppermost layer of the wiring layer 111. The pad 15 may be formed using a metal material other than aluminum. For example, as in the example shown in FIG. 1, the insulating film 82 is provided so as to cover the end of the pad 15. Furthermore, the insulating film 83 can be formed so as to cover the insulating film 82 and the entire pad 15. The insulating film 83 has a flat surface S1 as shown in FIG.

[0023] In the semiconductor element 1, an opening 40 is formed above the pad 15. The opening 40 is defined, for example, by an end face (side face) of the insulating film 82. The pad 15 is partially exposed from the insulating film 82 through the opening 40. The pad 15 is a pad electrode, and the opening 40 can also be called a pad opening. The pad 15 can also be called a terminal (connection terminal) of the semiconductor element 1 (or semiconductor chip 10).

[0024] A plurality of pads 15 may be arranged on the semiconductor element 1. For example, although only one pad 15 is illustrated in FIG. 1 , a plurality of pads 15 may be arranged on the semiconductor element 1. As an example, the plurality of pads 15 may include a power supply pad and a GND pad, and may supply a power supply voltage and a GND voltage (ground voltage) input from the outside to each circuit of the semiconductor element 1.

[0025] Furthermore, for example, the pads 15 may include pads used for transmitting signals to and from the outside, such as input / output pads for inputting and outputting signals, input pads for inputting signals from outside the semiconductor chip 10, and output pads for outputting signals to the outside of the semiconductor chip 10.

[0026] The pads 15 of the semiconductor element 1 can be used as measurement pads (electrodes). For example, before the insulating film 83 is formed in the opening 40, the pads 15 are exposed to the outside. In the inspection process of the semiconductor element 1, a probe (needle) can be applied to the area of ​​the pads 15 in the opening 40 to determine whether the semiconductor element 1 is a non-defective product.

[0027] After inspection (testing) of the electrical characteristics of the semiconductor element 1, the insulating film 83 may be formed in the opening 40, and the vias 20 and electrodes 30 may be formed. When a measurement probe is brought into contact with the pad 15, undulations tend to occur in the pad 15, leaving a needle mark. The needle mark left on the pad 15 has a shape that includes, for example, projections and depressions.

[0028] The via 20 electrically connects the pad 15 and the electrode 30. The pad 15 is connected to the via 20, and is electrically connected to the electrode 30 through the via 20. The via 20 (also referred to as a contact) is made of a metal material such as tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), or cobalt (Co). The via 20 may also be made of other conductive materials.

[0029] 1 , the via 20 is formed in the bonding layer 112 between the pad 15 of the semiconductor chip 10 and the electrode 30. The via 20 is provided, for example, around the opening 40. The via 20 extends in the Z-axis direction around the opening 40 and is disposed so as to penetrate a portion of the insulating film 82 and the insulating film 83. The via 20 is provided so as to penetrate a portion of the insulating film 82 and the insulating film 83, and connects the pad 15 and the electrode 30. Note that a barrier metal may be provided between the via 20 and the pad 15.

[0030] The electrode 30 is an electrode formed using, for example, copper (Cu) and is provided on the insulating film 83. The electrode 30 is an electrode used to bond metal electrodes and can also be called a bonding electrode. Note that the electrode 30 may be made of a metal material other than copper, such as nickel (Ni), cobalt (Co), tin (Sn), gold (Au), or the like, or may be made of other materials.

[0031] 1, the electrode 30 is electrically connected to the pad 15 of the semiconductor chip 10, and is provided up to the surface S1 (end surface) of the insulating film 83. The electrode 30 is formed on the insulating film 83 and reaches the surface S1 of the insulating film 83. In other words, the electrode 30 is located up to the surface S1 of the insulating film 83. The electrode 30 is also electrically connected to the pad 15 through the via 20.

[0032] The electrode 30 is provided so that the surface (end face) of the electrode 30 is exposed from the insulating film 83. The electrode 30 is provided up to the surface S1 of the insulating film 83, and becomes an electrode exposed to the outside from the insulating film 83. The surface S1 of the insulating film 83 has a flat shape. The electrode 30, which is a metal electrode, can be used to bond metal electrodes together. The surface S1 of the insulating film 83 (or the bonding layer 112) becomes the bonding surface in the case of bonding between electrodes.

[0033] As an example, the semiconductor chip 10 is bonded to another semiconductor chip by bonding between metal electrodes made of Cu, i.e., Cu-Cu bonding. Examples of this other semiconductor chip include a processor, memory, sensor, other integrated circuit, etc. The other semiconductor chip may be a semiconductor chip provided with a photoelectric conversion element (e.g., a photodiode), or may be a general-purpose memory or general-purpose logic.

[0034] The pad 15 has a portion 16a and a portion 16b. As shown in the example of FIG. 1, the portion 16b of the pad 15 is provided below the upper end (tip) of the portion 16a. The portions 16a and 16b are located at different distances (intervals) from the surface of the insulating film 83 (or the bonding layer 112). The portion 16b is provided, for example, contiguous with the portion 16a in the X-axis direction (or the Y-axis direction) and is located below the portion 16a.

[0035] 1, the pad 15 has a region 45 where the portion 16b is provided. The portion 16a of the pad 15 is provided, for example, around the region 45. In the bonding layer 112, an opening 40 is provided in the region 45 where the portion 16b of the pad 15 is to be formed. In the example shown in FIG. 1, a part of the portion 16a and the portion 16b are exposed from the insulating film 82 in the opening 40.

[0036] The electrode 30 is provided, for example, above the portion 16a of the pad 15. In the example shown in Fig. 1, the electrode 30 is located above the portion 16a around the opening 40 and is electrically connected to the portion 16a through the via 20. The electrode 30 is also electrically connected to the portion 16b through the portion 16a.

[0037] 2 is a diagram illustrating an example of the configuration of the semiconductor device according to the first embodiment. The pad 15 is provided such that, for example, a distance D1b from the surface S1 of the insulating film 83 to the upper end (tip) of the portion 16b is longer than a distance D1a from the surface S1 of the insulating film 83 to the upper end of the portion 16a. The upper end of the portion 16b is formed in a region that is deeper from the surface S1 of the insulating film 83 than the upper end of the portion 16a.

[0038] Furthermore, the pad 15 may be provided such that, for example, a distance D2b from the surface S1 of the insulating film 83 to the lower end (bottom) of the portion 16b is longer than a distance D2a from the surface S1 of the insulating film 83 to the lower end of the portion 16a. The lower end of the portion 16b may be formed in a region that is deeper from the surface S1 of the insulating film 83 than the lower end of the portion 16a.

[0039] In the semiconductor device 1 according to this embodiment, the pad 15 is configured to have a portion 16a and a portion 16b. The portion 16b of the pad 15 is provided below the upper end of the portion 16a. This makes it possible to prevent a deterioration in the quality of the semiconductor device 1 due to needle marks caused by contact of a measurement probe with the pad 15.

[0040] If the pad 15 did not have the portion 16b, the needle mark formed by the contact of the measurement probe with the pad 15 would protrude to a high position. When a planarization process is performed in a later process, the protruding portion of the pad 15, which is the needle mark 18, would be exposed, as shown in Figure 3, and the metal material constituting the pad 15 would be scattered around. This could result in contamination of the semiconductor element 1 (e.g., a short circuit) or poor bonding between metal electrodes.

[0041] In the semiconductor element 1 according to this embodiment, the pad 15 has the portion 16b located at a relatively low position, as described above. Therefore, as shown in the example schematically illustrated in Fig. 4, the needle mark 18 is formed on the portion 16b within the opening 40, and the position of the needle mark 18 can be lowered. This makes it possible to prevent contamination of the semiconductor element 1 and poor bonding during bonding.

[0042] Furthermore, in the semiconductor element 1 according to this embodiment, the position of the needle mark 18 can be lowered, which allows the placement positions and heights (lengths) of the bonding electrodes 30 and vias 20 to be relatively low, thereby effectively preventing poor filling of the electrode material and poor bonding during bonding.

[0043] Fig. 5 is a diagram showing an example of a planar configuration of a semiconductor element according to the first embodiment. Fig. 6 is a diagram showing an example of a cross-sectional configuration of the semiconductor element according to the first embodiment. For example, as shown in Fig. 5, the semiconductor element 1 may have a region where a plurality of circuit elements are provided (referred to as a circuit region 300) and a region where the above-mentioned pads 15 are provided (referred to as a pad region 310).

[0044] The pad region 310 includes, for example, a plurality of pads 15 and is provided in a peripheral region of the circuit region 300. For example, as shown in the example of FIG. 5 , the semiconductor element 1 may have a plurality of pad regions 310. Note that the arrangement of the circuit region 300 and the pad region 310 is not limited to the example shown in the figure and can be set arbitrarily. For example, the pad region 310 may be provided by replacing a portion of the circuit region 300.

[0045] In the circuit region 300, for example, a plurality of circuit elements including transistors, resistors, capacitors, etc. are provided in the semiconductor layer 101. Also, as shown in the example of Fig. 6, in the circuit region 300, a plurality of wirings 19 are provided in the wiring layer 111. The wirings 19 are electrically connected to the circuit elements, such as transistors, arranged in the semiconductor layer 101.

[0046] 6 , the wiring 19 is configured as the uppermost wiring in the wiring layer 111. The insulating film 82 is provided in the circuit region 300 so as to cover the wiring 19. The insulating film 83 can be provided in the circuit region 300 and the pad region 310 so as to cover the pad 15 and the wiring 19.

[0047] In the semiconductor element 1, the pad 15 is provided such that, for example, a distance D1b from the surface S1 of the insulating film 83 to the upper end of the portion 16b is longer than a distance D1c from the surface S1 of the insulating film 83 to the upper end of the wiring 19. The upper end of the portion 16b of the pad 15 can be formed in a region that is deeper from the surface S1 of the insulating film 83 than the upper end of the wiring 19.

[0048] Furthermore, the pad 15 may be provided such that, for example, a distance D2b from the surface S1 of the insulating film 83 to the lower end of the portion 16b is longer than a distance D2c from the surface S1 of the insulating film 83 to the lower end of the wiring 19. The lower end of the portion 16b may be formed in a region that is deeper from the surface S1 of the insulating film 83 than the lower end of the wiring 19.

[0049] 7 is a diagram illustrating an example of the configuration of a semiconductor element according to the first embodiment. Fig. 7 schematically illustrates an example in which the above-described semiconductor chip 10 and semiconductor chip 12 are bonded together by bonding between metal electrodes. For example, as shown in Fig. 7, the semiconductor element 1 includes the semiconductor chip 10, a bonding layer 112, a bonding layer 122, and the semiconductor chip 12.

[0050] The semiconductor element 1 has a configuration in which a semiconductor chip 10 including a semiconductor layer 101 and a semiconductor chip 12 including a semiconductor layer 102 are stacked in the Z-axis direction. The semiconductor chip 10 and the bonding layer 112 can be collectively referred to as the semiconductor chip 10. The semiconductor chip 12 and the bonding layer 122 can be collectively referred to as the semiconductor chip 12. The semiconductor layer 101 and the semiconductor layer 102 are each formed of a semiconductor substrate (e.g., a silicon substrate, an SOI substrate, etc.).

[0051] The semiconductor layer 101 has opposing surfaces 11S1 and 11S2. The surface 11S2 of the semiconductor layer 101 is the surface opposite to the surface 11S1. The semiconductor layer 102 has opposing surfaces 12S1 and 12S2. The surface 12S2 of the semiconductor layer 102 is the surface opposite to the surface 12S1.

[0052] The surfaces 11S1 and 12S1 are, for example, element formation surfaces on which elements such as transistors are formed. Gate electrodes, gate insulating films (e.g., gate oxide films), etc. may be provided on each of the surfaces 11S1 and 12S1. As described above, the wiring layer 111 is provided on the surface 11S1 side of the semiconductor layer 101.

[0053] As an example, a photoelectric conversion element is provided for each pixel in the semiconductor layer 102. The photoelectric conversion element (photoelectric conversion unit) of each pixel is, for example, a photodiode, and is configured to be able to photoelectrically convert light. The photoelectric conversion element is a light receiving element that can receive light and generate electric charges through photoelectric conversion.

[0054] A wiring layer 121 is provided on the surface 12S1 side of the semiconductor layer 102, and a bonding layer 122 is provided on the surface 12S2 side of the semiconductor layer 102. The wiring layer 121 includes, for example, a conductor film and an insulating film, and has a plurality of wirings and vias, etc. The wiring layer 121 includes, for example, two or more layers of wiring. The wiring layer 121 has, for example, a configuration in which a plurality of wirings are stacked with an insulating film between them.

[0055] The wiring of the wiring layer 121 is formed using, for example, aluminum, tungsten, copper, polysilicon, etc. The insulating film (interlayer insulating film) is formed using, for example, silicon oxide, silicon nitride, silicon oxynitride, etc. The semiconductor layer 102 and the wiring layer 121 can be collectively referred to as a substrate (or a circuit layer).

[0056] 7, the bonding layer 122 has an insulating film 85 and an electrode 60. The insulating film 85 is configured, for example, by a single layer film made of one of an oxide film (e.g., a silicon oxide film), a nitride film (e.g., a silicon nitride film), an oxynitride film, or the like, or a stacked film made of two or more of these films.

[0057] The electrode 60 is an electrode formed using, for example, copper (Cu) and is provided on the insulating film 85. The electrode 60 is an electrode used to bond metal electrodes and can also be called a bonding electrode. Note that the electrode 60 may be made of a metal material other than copper, such as nickel, cobalt, tin, or gold, or may be made of other materials.

[0058] The semiconductor layer 102 is provided with, for example, a plurality of through electrodes 65. The through electrodes 65 are connection electrodes (connection portions) that connect circuits provided in different layers. The through electrodes 65 are formed using a metal material such as tungsten, aluminum, or copper, and are provided so as to penetrate the semiconductor layer 102. In the semiconductor element 1, the electrodes 60 are electrically connected to the circuits provided in the semiconductor layer 102 by, for example, the through electrodes 65 and wiring or the like.

[0059] 7 , the electrode 60 is provided up to the surface S2 (end face) of the insulating film 85. The electrode 60 is formed on the insulating film 85 and reaches the surface S2 of the insulating film 85. That is, the electrode 60 is located up to the surface S2 of the insulating film 85. The electrode 60 is provided so that the surface (end face) of the electrode 60 is exposed from the insulating film 85.

[0060] The electrode 60 is provided up to the surface S2 of the insulating film 85, and serves as an electrode exposed to the outside from the insulating film 85. The surface S2 of the insulating film 85 has a flat shape. The electrode 60 is electrically connected to a pad 70 shown in FIG. 7 via, for example, a through electrode 65. The pad 70 is used, for example, as a bonding pad.

[0061] The semiconductor chip 10 and the semiconductor chip 12 are stacked by bonding between the metal electrodes so that, for example, the surface 11S1 of the semiconductor layer 101 and the surface 12S2 of the semiconductor layer 102 face each other. The semiconductor chip 10 and the semiconductor chip 12 are connected by bonding the plurality of electrodes 30 on the insulating film 83 and the plurality of electrodes 60 on the insulating film 85.

[0062] 8 is a diagram illustrating another example of the configuration of the semiconductor element according to the first embodiment. The semiconductor element 1 may have a structure in which three or more semiconductor chips are stacked. For example, as shown in the example of FIG. 8, the semiconductor element 1 may have a semiconductor chip 10a, a semiconductor chip 10b, and a semiconductor chip 12. The semiconductor element 1 may also have a support substrate.

[0063] 8, the semiconductor chip 10a and the semiconductor chip 10b are stacked on the semiconductor chip 12. The semiconductor chips 10a and 10b are stacked on the semiconductor chip 12, for example, by bonding between metal electrodes. Note that, as in the example shown in FIG. 8, the semiconductor chip 12 may have a structure in which a plurality of semiconductor layers (semiconductor layer 102a and semiconductor layer 102b in FIG. 8) are stacked.

[0064] As an example, the semiconductor chip 12 is provided with a plurality of pixels P each having a photoelectric conversion element 71, and a logic circuit that processes signals output from each pixel P. For example, the photoelectric conversion element 71 and a readout circuit of each pixel P are provided on the semiconductor layer 102a and the wiring layer 121a.

[0065] The readout circuit is configured to be able to output a signal based on the charge photoelectrically converted by the photoelectric conversion element 71. Furthermore, in the semiconductor element 1, for example, a logic circuit is provided in the semiconductor layer 102b and the wiring layer 121b. For example, an AD (Analog-Digital) conversion circuit can be provided in the semiconductor layer 102b and the wiring layer 121b.

[0066] The photoelectric conversion element 71 of the pixel P is, for example, a photodiode. In addition, in the semiconductor element 1, for example, a lens 76 and a filter 75 are provided on the side where light from the subject to be measured is incident. The lens 76 (lens portion) is a lens that collects light, and is an optical member also called an on-chip lens.

[0067] The lens 76 is provided above the photoelectric conversion element 71, for example, for each pixel P or for each set of multiple pixels P. Light from a subject to be measured is incident on the lens 76 via an optical system such as an imaging lens. The lens 76 guides the incident light to the photoelectric conversion element 71 side of the pixel P. The filter 75 is configured to selectively transmit light in a specific wavelength range from the incident light.

[0068] The filter 75 is an RGB color filter, a filter that transmits infrared light, etc. The filter 75 is provided above the photoelectric conversion element 71, for example, for each pixel P or for each set of multiple pixels P. The photoelectric conversion element 71 of each pixel P photoelectrically converts light incident thereon via the lens 76 and the filter 75.

[0069] The semiconductor chip 10a may be a semiconductor chip having a signal processing circuit, such as an AI (Artificial Intelligence) circuit. The semiconductor chip 10b may be a memory, such as a DRAM. The semiconductor device 1 may also include other general-purpose logic, general-purpose memory, etc. as the semiconductor chips 10a and 10b.

[0070] In this embodiment, as described above, the pad 15 having the portion 16a and the portion 16b is provided. This allows a plurality of semiconductor chips to be appropriately stacked by bonding between the metal electrodes. Furthermore, the semiconductor element 1 can realize a structure that is advantageous for miniaturization compared to when semiconductor chips are stacked using bumps.

[0071] In addition, in this embodiment, various semiconductor chips including general-purpose products can be bonded. In the example shown in Fig. 7, for example, a semiconductor chip 12 having a photoelectric conversion element and a semiconductor chip 10 such as a general-purpose memory or general-purpose logic are stacked to realize a high-performance semiconductor element 1.

[0072] 9A to 9F are diagrams illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment. First, as shown in Fig. 9A, insulating film 81 is partially removed by dry etching to form region 46 for pad 15 on insulating film 81. Then, an aluminum film is formed as the material for pad 15, and patterning (etching, lithography, etc.) is performed to form pad 15 having portion 16a and portion 16b, as shown in Fig. 9B.

[0073] Next, insulating films 82 and 83 are formed on pads 15, and then insulating films 82 and 83 are partially removed by etching to form openings 40, as shown in Fig. 9C. Then, as shown schematically in Fig. 9D, a measurement probe P1 is brought into contact with pads 15 in openings 40 to measure the electrical characteristics and the like of semiconductor element 1. A needle mark 18 is formed in the portion of pad 15 in openings 40.

[0074] Next, as shown in Fig. 9E, an insulating film 83 is formed on the pad 15, followed by CMP (Chemical Mechanical Polishing). Then, as shown in Fig. 9F, vias 20, electrodes 30, etc. are formed. By the manufacturing method described above, the semiconductor element 1 shown in Fig. 4 and the like can be manufactured. Note that the manufacturing method described above is merely one example, and other manufacturing methods may also be adopted.

[0075] [Operations and Effects] The semiconductor element (semiconductor element 1) according to this embodiment includes a first semiconductor layer (semiconductor layer 101) and a first layer (e.g., layer 202) located on the first semiconductor layer and on which a first pad (pad 15) is provided. The first layer includes a first insulating film (insulating film 83) located on the first pad and a first electrode (electrode 30) containing a metal material and provided on the first insulating film. The first electrode is electrically connected to the first pad and extends to the surface of the first insulating film. The first pad includes a first portion (portion 16a) and a second portion (portion 16b) located below the upper end of the first portion.

[0076] In the semiconductor element 1 according to this embodiment, the pad 15 has a portion 16a and a portion 16b. The portion 16b of the pad 15 is provided below the upper end of the portion 16a. This allows the position of the needle mark 18 formed in the pad 15 to be lowered, making it possible to prevent adverse effects on the bonding between metal electrodes. This makes it possible to provide a semiconductor element that is suitable for bonding between metal electrodes.

[0077] 2. Second Embodiment Next, a second embodiment of the present disclosure will be described. In the following, components similar to those in the above-described embodiment will be denoted by the same reference numerals, and descriptions thereof will be omitted as appropriate.

[0078] Fig. 10 is a diagram showing an example of a cross-sectional configuration of a semiconductor element according to a second embodiment of the present disclosure. Fig. 11 is a diagram showing an example of a planar configuration of the semiconductor element according to the second embodiment. Pad 15 of semiconductor element 1 may be configured to have multiple portions 16b, as in the examples shown in Figs. 10 and 11 .

[0079] Each of the plurality of portions 16b of the pad 15 may be provided below the upper end of the portion 16a. The plurality of portions 16b may be provided so as to be aligned in the X-axis direction and the Y-axis direction, as in the example shown in Fig. 11. The plurality of portions 16b of the pad 15 may be formed in a dot pattern in the opening 40, for example. The pad 15 may have a dot-like shape.

[0080] In the semiconductor device 1 according to this embodiment, the pad 15 is configured to have a plurality of portions 16b. The portions 16b of the pad 15 are provided below the upper ends of the portions 16a. This makes it possible to reduce the area (or volume) of the pad 15 that comes into contact with the measurement probe. This makes it possible to lower the height (position) of the needle mark formed when the probe comes into contact with the pad 15 and slides.

[0081] 12 or 13, the semiconductor element 1 according to this embodiment can reduce the protrusion (protrusion amount) of the needle mark 18 formed on the pad 15 within the opening 40. This makes it possible to prevent contamination of the semiconductor element 1 and poor bonding during bonding.

[0082] Furthermore, in this embodiment, the height (length) of the needle mark 18 can be reduced, so that the position and height of the bonding electrodes 30 and vias 20 can be made relatively low, which effectively prevents poor filling of the electrode material and poor bonding during bonding.

[0083] 14A and 14B are diagrams showing another example of the planar configuration of the semiconductor element according to the second embodiment. The portions 16b of the pad 15 may be provided to extend in the X-axis direction (or the Y-axis direction), as in the example shown in FIG. 14A or 14B. The pad 15 may be configured to have a line-and-space pattern.

[0084] 14A or 14B, the area (and volume) of the pad 15 that the measurement probe comes into contact with can be reduced, and the protrusion (protrusion amount) of the needle mark 18 can be reduced. This makes it possible to prevent contamination of the semiconductor element 1 and poor bonding during bonding. Note that the number and arrangement of the portions 16b of the pad 15 are not limited to the examples shown in the drawings and can be changed as appropriate.

[0085] 15A to 15G are diagrams illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment. First, as shown in FIG. 15A, an aluminum film 95 is formed on an insulating film 81 as the material for the pad 15. Then, by performing patterning (etching, lithography, etc.), the pad 15 having a plurality of portions 16a and 16b is formed as shown in FIG. 15B. The pad 15 has, for example, a dot shape or a line-and-space shape.

[0086] Next, as shown in Fig. 15C, an insulating film 82 is formed on the pad 15. Then, as shown in Fig. 15D, the insulating film 82 is partially removed by etching to form an opening 40. Furthermore, as shown schematically in Fig. 15E, a measurement probe P1 is brought into contact with the pad 15 in the opening 40 to measure the electrical characteristics, etc., of the semiconductor element 1. In this case, for example, needle marks 18 are formed in a plurality of portions 16b of the pad 15.

[0087] Next, as shown in Fig. 15F, an insulating film 83 is formed on the pad 15, followed by CMP (Chemical Mechanical Polishing). Then, as shown in Fig. 15G, vias 20 and electrodes 30 are formed. By the manufacturing method described above, the semiconductor element 1 shown in Fig. 12 etc. can be manufactured. Note that the manufacturing method described above is merely one example, and other manufacturing methods may also be adopted.

[0088] 16 is a diagram illustrating another example of the configuration of the semiconductor device according to the second embodiment. The pad 15 may be made of copper (Cu). The pad 15 may be formed of Cu to have a plurality of portions 16b. By making the pad 15 of Cu, it is possible to suppress the height (length) of the needle mark 18, as in the example schematically shown in FIG. 16 .

[0089] The pads 15 may be formed by a damascene method using copper, for example. The pads 15 may have a dot shape, as in the example shown in Figure 14A or 14B above, or a line-and-space shape. The shape of the pads 15 is not limited to the examples shown in the figures and can be changed as appropriate.

[0090] [Operations and Effects] The semiconductor element (semiconductor element 1) according to this embodiment includes a first semiconductor layer (semiconductor layer 101) and a first layer (e.g., layer 202) located on the first semiconductor layer and on which a first pad (pad 15) is provided. The first layer includes a first insulating film (insulating film 83) located on the first pad and a first electrode (electrode 30) containing a metal material and provided on the first insulating film. The first electrode is electrically connected to the first pad and extends to the surface of the first insulating film. The first pad includes a first portion (portion 16a) and a second portion (portion 16b) located below the upper end of the first portion. The first pad is provided to have a plurality of second portions.

[0091] In the semiconductor element 1 according to this embodiment, the pad 15 is provided to have a plurality of portions 16b. The portions 16b of the pad 15 are provided below the upper ends of the portions 16a. This allows the position (height) of the needle marks 18 formed on the pad 15 to be lowered, making it possible to prevent adverse effects on the bonding between metal electrodes. This makes it possible to provide a semiconductor element that is suitable for bonding between metal electrodes.

[0092] 17 is a diagram for explaining a configuration example of a semiconductor element according to a first modification of the present disclosure. In the semiconductor element 1, the portion 16b of the pad 15 may not be provided, as in the example shown in Fig. 17. The pad 15 may be configured, for example, by including a plurality of portions 16a and without the portion 16b.

[0093] The multiple portions 16a of the pad 15 may be made of copper (Cu), for example, and provided on the insulating film 82. The pad 15 may be formed of copper by a damascene method, for example. The multiple portions 16a of the pad 15 may be provided so as to be aligned in the X-axis direction (or the Y-axis direction), for example.

[0094] 18, in the semiconductor element 1, a barrier metal 50 may be provided around the portion 16a of the pad 15. In addition, in the semiconductor element 1, a barrier metal may be provided around each of the pad 70, the wiring 19, etc.

[0095] In the case of the semiconductor element 1 according to this modification, it is also possible to reduce the area (and volume) of the pad 15 that the measurement probe comes into contact with, and to reduce the protrusion amount of the needle mark 18. This makes it possible to prevent contamination of the semiconductor element 1 and poor bonding during bonding.

[0096] The semiconductor device according to this modification includes a first semiconductor layer (semiconductor layer 101) and a first layer (e.g., layer 202) located on the first semiconductor layer and on which a first pad (pad 15) is provided. The first layer includes a first insulating film (insulating film 83) located on the first pad and a first electrode (electrode 30) including a metal material and provided on the first insulating film. The first electrode is electrically connected to the first pad and extends to the surface of the first insulating film. The first pad is provided to have a plurality of first portions (portions 16a).

[0097] In the semiconductor element 1 according to this embodiment, the pad 15 is provided to have a plurality of portions 16a. This allows the position (height) of the needle mark 18 formed on the pad 15 to be lowered, making it possible to prevent adverse effects on the bonding between metal electrodes. This makes it possible to provide a semiconductor element that is suitable for bonding between metal electrodes.

[0098] 3. Third Embodiment Next, a third embodiment of the present disclosure will be described. In the following, components similar to those in the above-described embodiment will be denoted by the same reference numerals, and descriptions thereof will be omitted as appropriate.

[0099] 19 is a diagram illustrating a configuration example of a semiconductor device according to the third embodiment of the present disclosure. As shown in FIG. 19 , the semiconductor device 1 may have vias 25 and wiring 35. The vias 25 and wiring 35 are each made of a metal material such as tungsten, aluminum, or copper. Note that the vias 25 and wiring 35 may each be made of another conductive material.

[0100] The via 25 is provided between the pad 15 and the wiring 35, and electrically connects the pad 15 and the wiring 35. The wiring 35 is, for example, configured by the wiring in the uppermost layer of the wiring layer 111, and is provided above the via 25. In the example shown in FIG. 19 , the via 20 and the electrode 30 are arranged above the via 25 and the wiring 35.

[0101] The pad 15 is connected to the via 25 and electrically connected to the electrode 30 through the via 25, the wiring 35, and the via 20. The via 25 and the wiring 35 are provided, for example, around the opening 40. Note that a barrier metal may be provided between the via 25 and the pad 15.

[0102] The semiconductor element 1 according to this embodiment has wiring 35 between the pad 15 and the electrode 30, and the pad 15 and the electrode 30 are electrically connected via the wiring 35. In the semiconductor element 1, the pad 15 can be configured using wiring in a layer lower than the wiring 35. This allows the pad 15 to be separated from the surface S1 of the insulating film 83. It is possible to prevent a deterioration in the quality of the semiconductor element 1 due to needle marks formed on the pad 15.

[0103] 20, the distance between the pad 15 and the surface S1 of the insulating film 83 can be ensured. This prevents the needle mark 18 (i.e., the protruding portion) of the pad 15 from being exposed to the outside and the metal material constituting the pad 15 from scattering around. This makes it possible to prevent contamination of the semiconductor element 1 and poor bonding during bonding due to the needle mark formed on the pad 15.

[0104] [Actions and Effects] The semiconductor element (semiconductor element 1) according to this embodiment includes a first semiconductor layer (semiconductor layer 101) and a first layer (e.g., layer 202) located on the first semiconductor layer and having a first pad (pad 15) provided thereon. The first layer includes a wiring (wiring 35) provided above the first pad, a first insulating film (insulating film 83) provided so as to cover the first pad and the wiring, and a first electrode (electrode 30) containing a metal material and provided on the first insulating film above the wiring. The first electrode is electrically connected to the first pad via the wiring and is provided up to the surface of the first insulating film.

[0105] In the semiconductor element 1 according to this embodiment, the pad 15 is electrically connected to the electrode 30 via the wiring 35 provided above the pad 15. This makes it possible to prevent the needle mark 18 formed on the pad 15 from adversely affecting the bonding between the metal electrodes. This makes it possible to provide a semiconductor element that is suitable for bonding between the metal electrodes.

[0106] (Modification 2) In the above-described embodiment, a configuration example of the semiconductor element 1 has been described, but this is merely an example, and the configuration of the semiconductor element 1 is not limited to the above-described example. Fig. 21 is a diagram for explaining a configuration example of a semiconductor element according to Modification 2 of the present disclosure. As in the example shown in Fig. 21 , the pad 15 may be configured to have multiple portions 16b in a layer below the wiring 35.

[0107] The pad 15 may be configured to have, for example, a dot shape. The pad 15 may also be configured to have a line-and-space shape. The pad 15 may be configured using aluminum (AL) or copper (Cu). In addition, the semiconductor element 1 may not have the portion 16b of the pad 15. The pad 15 may be configured, for example, with a plurality of portions 16a and no portion 16b.

[0108] Although the present disclosure has been described above by way of embodiments and modifications, the present technology is not limited to the above embodiments, etc., and various modifications are possible. For example, although the modifications described above have been described as modifications of the above embodiments, the configurations of the modifications can be combined as appropriate.

[0109] A semiconductor device according to one embodiment of the present disclosure includes a first semiconductor layer and a first layer located on the first semiconductor layer and having a first pad provided thereon. The first layer includes a first insulating film located on the first pad and a first electrode provided on the first insulating film. The first electrode is electrically connected to the first pad and extends to the surface of the first insulating film. The first pad has a first portion and a second portion located below the upper end of the first portion. This makes it possible to provide a semiconductor device suitable for bonding between metal electrodes.

[0110] A semiconductor device according to an embodiment of the present disclosure includes a first semiconductor layer and a first layer located above the first semiconductor layer and having a first pad. The first layer includes a wiring provided above the first pad, a first insulating film provided to cover the first pad and the wiring, and a first electrode provided on the first insulating film above the wiring. The first electrode is electrically connected to the first pad via the wiring and extends to the surface of the first insulating film. This makes it possible to provide a semiconductor device suitable for bonding between metal electrodes.

[0111] A semiconductor device according to one embodiment of the present disclosure includes a first semiconductor layer and a first layer located on the first semiconductor layer and having a first pad provided thereon. The first layer includes a first insulating film located on the first pad and a first electrode provided on the first insulating film. The first electrode is electrically connected to the first pad and extends to the surface of the first insulating film. The first pad is provided to have a plurality of first portions. This makes it possible to provide a semiconductor device suitable for bonding between metal electrodes.

[0112] Note that the effects described in this specification are merely examples and are not limited to those described above, and other effects may be present. The present disclosure may also have the following configurations. (1) A semiconductor element comprising: a first semiconductor layer; and a first layer located on the first semiconductor layer and on which a first pad is provided; the first layer having: a first insulating film located on the first pad; and a first electrode including a metal material and provided on the first insulating film; the first electrode being electrically connected to the first pad and extending to a surface of the first insulating film; and the first pad having a first portion and a second portion provided below an upper end of the first portion. (2) The semiconductor element described in (1), in which the first pad has a region where the second portion is provided, and the first portion is provided around the region. (3) The semiconductor element described in (1) or (2), in which the first pad has a region where the second portion is provided, and the first pad has a needle mark in the region. (4) The semiconductor element according to any one of (1) to (3), wherein the first electrode is provided above the first portion. (5) The semiconductor element according to any one of (1) to (4), wherein the first electrode is electrically connected to the second portion via the first portion. (6) The semiconductor element according to any one of (1) to (5), wherein the distance from the surface of the first insulating film to the upper end of the second portion is longer than the distance from the surface of the first insulating film to the upper end of the first portion. (7) The semiconductor element according to any one of (1) to (6), wherein the distance from the surface of the first insulating film to the lower end of the second portion is longer than the distance from the surface of the first insulating film to the lower end of the first portion. (8) The semiconductor element according to any one of (1) to (7), further comprising: a first region having a circuit element provided in the first semiconductor layer, and in which first wiring electrically connected to the circuit element in the first layer is provided; and a second region located around the first region and having the first pad provided in the first layer.(9) The semiconductor element according to (8), wherein the first insulating film is provided to cover the first pad and the first wiring in the first region and the second region, and the second portion of the first pad is located lower than an upper end of the first wiring in a stacking direction of the first semiconductor layer and the first layer. (10) The semiconductor element according to (8) or (9), wherein the first insulating film is provided to cover the first pad and the first wiring in the first region and the second region, and the distance from the surface of the first insulating film to the upper end of the second portion is longer than the distance from the surface of the first insulating film to the upper end of the first wiring. (11) The semiconductor element according to any one of (8) to (10), wherein the first insulating film is provided to cover the first pad and the first wiring in the first region and the second region, and the distance from the surface of the first insulating film to the lower end of the second portion is longer than the distance from the surface of the first insulating film to the lower end of the first wiring. (12) The semiconductor element according to any one of (1) to (11), wherein the first pad is provided to have a plurality of the second portions. (13) The semiconductor element according to any one of (1) to (12), wherein the first pad is configured to contain aluminum. (14) The semiconductor element according to any one of (1) to (13), wherein the first pad is configured to contain copper. (15) The semiconductor element according to any one of (1) to (14), further including: a second layer having a second electrode joined to the first electrode; and a second semiconductor layer located on the second layer. (16) The semiconductor element according to (15), wherein the second semiconductor layer has a photoelectric conversion element. (17) A semiconductor element comprising: a first semiconductor layer; and a first layer located on the first semiconductor layer and having a first pad provided thereon; wherein the first layer has: a wiring provided above the first pad; a first insulating film provided so as to cover the first pad and the wiring; and a first electrode including a metal material and provided on the first insulating film above the wiring; wherein the first electrode is electrically connected to the first pad via the wiring and is provided up to a surface of the first insulating film.(18) The semiconductor element according to (17), wherein the first pad has a needle mark. (19) The semiconductor element according to (17) or (18), wherein the first pad has a first portion and a second portion provided below an upper end of the first portion. (20) The semiconductor element according to (19), wherein the first pad is provided to have a plurality of the second portions. (21) A semiconductor element comprising: a first semiconductor layer; and a first layer located on the first semiconductor layer and on which a first pad is provided, wherein the first layer has: a first insulating film located on the first pad; and a first electrode including a metal material and provided on the first insulating film, wherein the first electrode is electrically connected to the first pad and is provided up to a surface of the first insulating film, and the first pad is provided to have a plurality of first portions.

[0113] This application claims priority based on Japanese Patent Application No. 2023-198458, filed on November 22, 2023, in the Japan Patent Office, the entire contents of which are incorporated herein by reference.

[0114] Those skilled in the art will recognize that various modifications, combinations, subcombinations, and variations may occur depending on design requirements and other factors, and are intended to be within the scope of the appended claims and their equivalents.

Claims

1. A semiconductor element comprising: a first semiconductor layer; and a first layer located on the first semiconductor layer and having a first pad provided thereon, wherein the first layer has: a first insulating film located on the first pad; and a first electrode including a metal material and provided on the first insulating film, wherein the first electrode is electrically connected to the first pad and extends to a surface of the first insulating film, and the first pad has a first portion and a second portion provided below an upper end of the first portion.

2. The semiconductor element according to claim 1, wherein the first pad has a region in which the second portion is provided, and the first portion is provided around the periphery of the region.

3. The semiconductor element according to claim 1, wherein the first pad has a region in which the second portion is provided, and the first pad has a needle mark in the region.

4. The semiconductor element according to claim 1, wherein the first electrode is provided above the first portion.

5. The semiconductor element according to claim 1, wherein the first electrode is electrically connected to the second portion via the first portion.

6. The semiconductor element according to claim 1, wherein the distance from the surface of the first insulating film to the upper end of the second portion is longer than the distance from the surface of the first insulating film to the upper end of the first portion.

7. The semiconductor element according to claim 1, wherein the distance from the surface of the first insulating film to the lower end of the second portion is longer than the distance from the surface of the first insulating film to the lower end of the first portion.

8. The semiconductor device according to claim 1, further comprising: a first region having a circuit element provided in the first semiconductor layer, in which a first wiring is provided in the first layer and electrically connected to the circuit element; and a second region located around the first region, having the first pad provided in the first layer.

9. The semiconductor element described in claim 8, wherein the first insulating film is provided so as to cover the first pad and the first wiring in the first region and the second region, and the second portion of the first pad is located lower than an upper end of the first wiring in the stacking direction of the first semiconductor layer and the first layer.

10. The semiconductor element described in claim 8, wherein the first insulating film is provided so as to cover the first pad and the first wiring in the first region and the second region, and the distance from the surface of the first insulating film to the upper end of the second portion is longer than the distance from the surface of the first insulating film to the upper end of the first wiring.

11. The semiconductor element described in claim 8, wherein the first insulating film is provided so as to cover the first pad and the first wiring in the first region and the second region, and the distance from the surface of the first insulating film to the lower end of the second portion is longer than the distance from the surface of the first insulating film to the lower end of the first wiring.

12. The semiconductor element according to claim 1, wherein the first pad is provided to have a plurality of the second portions.

13. The semiconductor element according to claim 1, wherein the first pad is comprised of aluminum.

14. The semiconductor element according to claim 1, wherein the first pad is comprised of copper.

15. The semiconductor device according to claim 1, further comprising: a second layer having a second electrode joined to the first electrode; and a second semiconductor layer located on the second layer.

16. The semiconductor element according to claim 15, wherein the second semiconductor layer includes a photoelectric conversion element.

17. A semiconductor element comprising: a first semiconductor layer; and a first layer located on the first semiconductor layer and having a first pad provided thereon, the first layer having: a wiring provided above the first pad; a first insulating film provided so as to cover the first pad and the wiring; and a first electrode including a metallic material and provided on the first insulating film above the wiring, the first electrode being electrically connected to the first pad via the wiring and provided up to a surface of the first insulating film.

18. The semiconductor element according to claim 17, wherein the first pad has a needle mark.

19. The semiconductor element according to claim 17, wherein the first pad has a first portion and a second portion provided below an upper end of the first portion.

20. A semiconductor element comprising: a first semiconductor layer; and a first layer located on the first semiconductor layer and having a first pad provided thereon, the first layer having: a first insulating film located on the first pad; and a first electrode including a metal material and provided on the first insulating film, the first electrode being electrically connected to the first pad and extending to a surface of the first insulating film, and the first pad being provided so as to have a plurality of first portions.

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