Power amplification circuit

Abstract

The present invention maintains the characteristics of a power amplification circuit without affecting the cost. This power amplification circuit has a plurality of stages of amplification units. The power amplification circuit includes a first amplification unit that amplifies an input high-frequency signal, a second amplification unit that amplifies the output of the first amplification unit, and a switch unit provided in the power supply path to the first amplification unit. Through the switch unit, power is supplied to the first amplification unit. The switch unit sets the power supply to the first amplification unit to on or off. The power is directly supplied to the second amplification unit without passing through the switch unit.

Description

Power Amplifier Circuit

[0001] The present invention relates to a power amplifier circuit.

[0002] Conventionally, there has been known a power amplifier circuit that amplifies a high-frequency signal using multiple amplifier stages connected in cascade (see, for example, Patent Document 1). In Patent Document 1, a power supply voltage is supplied to each of the multiple amplifier stages via a switch.

[0003] Japanese Patent Application Publication No. 9-8675

[0004] As in Patent Document 1, by turning a switch on or off, the power supply to each stage of amplifier can be set to on or off, preventing device damage due to excessive power supply voltage. However, with the configuration of Patent Document 1, the on-resistance of the switch may degrade the characteristics of the power amplifier circuit. Furthermore, with the configuration of Patent Document 1, the size of the switch may increase, which may result in an increase in the size of the power amplifier circuit.

[0005] The present disclosure has been made in view of the above, and its object is to maintain the characteristics of a power amplifier circuit without affecting the cost in a power amplifier circuit.

[0006] In order to solve the above-mentioned problems and achieve the object, a power amplifier circuit according to one aspect of the present disclosure is a power amplifier circuit having multiple stages of amplifier units, and includes a first amplifier unit that amplifies an input high-frequency signal, a second amplifier unit that amplifies the output of the first amplifier unit, and a switch unit provided in a power supply path to the first amplifier unit, wherein power is supplied to the first amplifier unit via the switch unit, and the switch unit sets the power supply to the first amplifier unit to on or off, and the power is supplied directly to the second amplifier unit without going through the switch unit.

[0007] A power amplifier circuit according to another aspect of the present disclosure is a power amplifier circuit having only a single stage of amplifier section, including: a first amplifier section that amplifies an input high-frequency signal; and a switch section provided in a power supply path to the first amplifier section, wherein power is supplied to the first amplifier section via the switch section, and the switch section sets the power supply to the first amplifier section to on or off. The first amplifier section includes an input terminal to which a signal to be amplified is input, a first FET having a gate to which the signal input to the input terminal is applied, a second FET connected together with the first FET between a power supply and a reference potential, an output terminal provided between the second FET and a load and which outputs an amplified signal, and a voltage divider resistor circuit for generating a bias to be applied to the gate of the second FET, wherein the first FET and the second FET are connected in tandem.

[0008] According to the present disclosure, the characteristics of the power amplifier circuit can be maintained without affecting the cost.

[0009] FIG. 1 is a diagram illustrating the configuration of a power amplifier circuit of a first comparative example. FIG. 2 is a diagram illustrating the configuration of a power amplifier circuit of a second comparative example. FIG. 3 is a diagram illustrating a power amplifier circuit according to the first embodiment. FIG. 4 is a diagram illustrating an example configuration of a communication device including a power amplifier circuit. FIG. 5 is a diagram illustrating the configuration of an amplifier unit used in a power amplifier circuit of a third comparative example. FIG. 6 is a diagram illustrating an example configuration in which a switch is connected to an amplifier unit. FIG. 7 is a diagram illustrating an amplifier unit used in a power amplifier circuit of a fourth comparative example. FIG. 8 is a diagram illustrating an amplifier unit used in a power amplifier circuit according to the second embodiment. FIG. 9 is a diagram illustrating the relationship between voltage values. FIG. 10 is a diagram illustrating an amplifier unit used in a power amplifier circuit according to the third embodiment. FIG. 11 is a waveform diagram illustrating an example signal obtained by inverting the output signal of the comparator in FIG. 10. FIG. 12 is a diagram illustrating the input voltage and output voltage of a switch provided between a power supply and the amplifier unit. FIG. 13 is a diagram illustrating the input voltage and gate bias of the switch. FIG. 14 is a diagram illustrating an example change in on-resistance. FIG. 15 is a diagram illustrating an example of a switch using only PMOS. FIG. 16 is a diagram illustrating an example of a switch using only NMOS. Fig. 17 is a diagram showing an example of a switch using PMOS and NMOS. Fig. 18 is a diagram showing an amplifier unit used in a power amplifier circuit according to a fourth embodiment. Fig. 19 is a diagram explaining the hysteresis characteristics of an output signal of a comparator. Fig. 20 is a diagram showing an example configuration of a variable resistor in Fig. 18. Fig. 21 is a diagram showing the configuration of a power amplifier circuit according to a fifth embodiment. Fig. 22 is a diagram showing an example configuration of a communication device including a power amplifier circuit.

[0010] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following description of each embodiment, components that are the same as or equivalent to those in other embodiments will be given the same reference numerals, and their description will be simplified or omitted. The present invention is not limited to each embodiment. Furthermore, the components of each embodiment include those that are easily replaceable by those skilled in the art, or those that are substantially the same. Note that the configurations described below can be combined as appropriate. Furthermore, the configurations can be omitted, replaced, or modified within the scope of the gist of the invention.

[0011] First Embodiment To facilitate understanding of the first embodiment, first and second comparative examples will be described first. FIG. 1 is a diagram showing the configuration of a power amplifier circuit 100a of the first comparative example. In FIG. 1, the power amplifier circuit 100a is a two-stage amplifier circuit and includes amplifier units 101 and 201. The first-stage (previous stage) amplifier unit 101 is a driver-stage amplifier unit. The amplifier unit 101 amplifies a signal input to an input terminal Tin and outputs the signal to the amplifier unit 201. The second-stage (next stage) amplifier unit 201 is a power-stage amplifier unit. The amplifier unit 201 amplifies a signal output from the amplifier unit 101 and outputs the signal from an output terminal Tout.

[0012] The power amplifier circuit 100a also has a switch SWa that is provided in common to the amplifier units 101 and 201. That is, a switch SWa is provided for both the amplifier units 101 and 201. A voltage from a power supply Vcc is supplied to the amplifier units 101 and 201 via the switch SWa. In this example, the output units of the amplifier units 101 and 201 are both provided with emitter-grounded transistors. Therefore, a voltage from the power supply Vcc is applied to the output sides of the amplifier units 101 and 201.

[0013] The operation of the first comparative example shown in FIG. 1 is as follows. That is, in the power amplifier circuit 100a, when the switch SWa is turned on, the voltage from the power supply Vcc is supplied to the amplifier units 101 and 201. This causes the amplifier units 101 and 201 to perform an amplification operation. When the switch SWa is turned off, the voltage from the power supply Vcc is not supplied to the amplifier units 101 and 201. At this time, the amplifier units 101 and 201 do not perform an amplification operation.

[0014] 2 is a diagram showing the configuration of a power amplifier circuit 100b of a second comparative example. In FIG. 2, the power amplifier circuit 100b differs from the power amplifier circuit 100a in that it has a switch SWb provided corresponding to the amplifier unit 101 and a switch SWc provided corresponding to the amplifier unit 201. The amplifier unit 101 is supplied with a voltage from the power supply Vcc via the switch SWb. The amplifier unit 201 is supplied with a voltage from the power supply Vcc via the switch SWc.

[0015] The operation of the second comparative example shown in FIG. 2 is as follows. That is, in the power amplifier circuit 100b, when the switch SWb is turned on, the voltage from the power supply Vcc is supplied to the amplifier unit 101. This causes the amplifier unit 101 to perform an amplification operation. When the switch SWb is turned off, the voltage from the power supply Vcc is not supplied to the amplifier unit 101. At this time, the amplifier unit 101 does not perform an amplification operation. When the switch SWc is turned on, the voltage from the power supply Vcc is supplied to the amplifier unit 201. This causes the amplifier unit 201 to perform an amplification operation. When the switch SWc is turned off, the voltage from the power supply Vcc is not supplied to the amplifier unit 201. At this time, the amplifier unit 201 does not perform an amplification operation.

[0016] Incidentally, when turning on or off the power supply to each amplifier stage, the on-resistance of the switch can affect the characteristics of the power amplifier circuit. In particular, a larger current flows through the amplifier in the power stage (second stage, or rear stage) than through the driver stage (first stage, or front stage). Therefore, providing a switch in the power stage amplifier can significantly degrade the amplification characteristics of the power stage amplifier. To reduce the on-resistance of the switch, the size of the transistor constituting the switch must be increased. Increasing the size of the transistor constituting the switch undesirably increases the overall device size. For example, with regard to the switch SWa (see FIG. 1) and the switch SWc (see FIG. 2), a problem arises in that the size of the transistor must be increased to reduce the on-resistance of the transistor that implements these switches. Increasing the size of the transistor undesirably increases the device size, significantly affecting costs.

[0017] FIG. 3 is a diagram showing a power amplifier circuit 100 according to the first embodiment. Similar to the first and second comparative examples described with reference to FIGS. 1 and 2 , the power amplifier circuit 100 includes multiple amplifier stages 101 and 201. The power amplifier circuit 100 includes a switch VccSW. The switch VccSW is provided in a power supply path from the power supply Vcc to the amplifier unit 101. Power is supplied from the power supply Vcc to the amplifier unit 101 via the switch VccSW. The switch VccSW turns on or off the power supply from the power supply Vcc to the amplifier unit 101. The switch VccSW corresponds to the switch unit in the present disclosure. The amplifier unit 101 corresponds to the first amplifier unit in the present disclosure. Note that, although a power amplifier circuit having two amplifier stages will be described here, there is no limit to the number of stages as long as it is two or more, and the power amplifier circuit may include three or more amplifier stages.

[0018] The switch VccSW is controlled to be turned on when the voltage from the power supply Vcc is equal to or lower than a predetermined threshold. The switch VccSW is controlled to be turned off when the voltage from the power supply Vcc exceeds a predetermined threshold. The predetermined threshold is, for example, the maximum drive voltage of the amplifier unit 101.

[0019] Power is supplied to the amplifier unit 201 directly from the power supply Vcc without going through the switch VccSW. Therefore, a switch corresponding to the amplifier unit 201 is not required. The size of the transistors is reduced compared to the first and second comparative examples. The amplifier unit 201 corresponds to the second amplifier unit of the present disclosure.

[0020] In the power amplifier circuit 100, when the switch VccSW is in the on state, similarly to the first and second comparative examples, the amplifier unit 101 amplifies the signal input to the input terminal Tin and outputs the amplified signal to the amplifier unit 201. The amplifier unit 201 amplifies the output signal of the amplifier unit 101 and outputs it from the output terminal Tout.

[0021] A switch VccSW is provided corresponding to the amplifier unit 101, and no switch is provided corresponding to the amplifier unit 201. The switch VccSW is turned off when the voltage from the power supply Vcc is equal to or higher than a predetermined threshold. By controlling the switch VccSW in this way, the characteristics of the power amplifier circuit can be maintained without affecting costs.

[0022] In the power amplifier circuit 100, the amplifier unit 101 may be formed on a silicon die, and the amplifier unit 201 may be formed on a die other than the silicon die. The silicon die refers to a die made of Si, such as a die made of an SOI (Silicon-on-Insulator) substrate. The die other than the silicon die may be, for example, a die made of GaAs. With this configuration, as described below, even when the amplifier unit 101 is made of multiple transistors stacked on a silicon die, it is possible to suppress the maximum voltage applied to the power amplifier circuit, ensure voltage resistance, and prevent deterioration of the characteristics of the power amplifier circuit.

[0023] (Communication Device) Here, a communication device including a power amplifier circuit will be described. Fig. 4 is a diagram showing an example configuration of a communication device including a power amplifier circuit. In Fig. 4, the communication device 1000 includes a power amplifier circuit M1, band select switches BS1 and BS2, filters SF1 to SF5, antenna switches AS1 and AS2, antennas ANT1 and ANT2, a power control unit 400, a baseband integrated circuit (IC) 500, and a switch VddSW. The switch VddSW corresponds to the switch unit of the present disclosure.

[0024] The power amplifier circuit M1 is a PA (Power Amplifier) ​​module and has a function as a power amplifier circuit. The power amplifier circuit M1 includes a driver stage amplifier unit 101, power stage amplifier units 201 and 202, switches SW1 and SW2, and a control circuit 301.

[0025] The output terminal of the driver stage amplifier 101 is output to the input terminal of the power stage amplifier 201 via a switch SW1. The output terminal of the driver stage amplifier 101 is output to the input terminal of the power stage amplifier 202 via a switch SW2. The amplifier 101 is the amplifier in the front stage, i.e., the driver stage. The amplifiers 201 and 202 are amplifiers in the rear stage, i.e., the power stages.

[0026] The power stage amplifier units 201 and 202 are configured, for example, by bipolar transistors. The control circuit 301 is a circuit that outputs control signals that control the amplifier units 101 and 201. For example, the control circuit 301 inputs a gate bias control signal SSW to the amplifier unit 101. The control circuit 301 inputs a bias current to the amplifier units 201 and 202. The amplifier unit 101 and the control circuit 301 are realized, for example, by an SOI (Silicon on Insulator) substrate 801. The amplifier units 201 and 202 are realized, for example, by GaAs substrates 901 and 902.

[0027] Here, the switches SW1 and SW2 are controlled so that when one is on, the other is off. Therefore, when one of the power stage amplifier units 201 and 202 is performing an amplification operation, the other is in a standby state where it is not performing an amplification operation. In other words, the amplifier units 201 and 202 are alternatively in an operating state, and when not in an operating state, they are in a standby state. The amplifier unit 201 or 202 in the amplification operation state operates in, for example, a high power mode (HPM), a medium power mode (MPM), or a low power mode (LPM).

[0028] The band select switch BS1 is a switch that selects a frequency band in accordance with a band select control signal SS. The band select switch BS2 is a switch that selects a frequency band in accordance with a band select control signal SS.

[0029] The filters SF1 to SF5 are, for example, SAW (Surface Acoustic Wave) filters. The filters SF1 and SF2 extract signals of the required frequency band from the output of the band select switch BS1. The filters SF3 to SF5 extract signals of the required frequency band from the output of the band select switch BS2.

[0030] Antenna switch AS1 selects the output of filter SF1 or the output of SF2 according to the band select control signal SS. Antenna switch AS2 selects the output of filter SF3, the output of filter SF4, or the output of filter SF5 according to the band select control signal SS. Antenna ANT1 emits the signal selected by antenna switch AS1 as an electromagnetic wave. Antenna ANT2 emits the signal selected by antenna switch AS2 as an electromagnetic wave.

[0031] The power supply control unit 400 is a power supply control module that outputs a power supply Vdd. The power supply Vdd is input to the power amplifier circuit M1. The power supply control unit 400 includes, for example, a DC-DC (Direct Current-Direct Current) converter that converts a DC voltage level. Note that the first embodiment described above is based on bipolar transistors, and therefore the symbol "Vcc" is used for the power supply. However, the following description is based on FETs (Field Effect Transistors, hereinafter referred to as FETs), and therefore the symbol "Vdd" is used for the power supply.

[0032] The baseband IC 500 transmits an RF signal to the power amplifier circuit M1. The baseband IC 500 also transmits a control signal CS and a band select control signal SS to each unit within the communication device 1000 according to the frequency band to be output. The baseband IC 500 transmits the band select control signal SS to band select switches BS1 and BS2 and antenna switches AS1 and AS2. The baseband IC 500 outputs a signal that controls the power supply Vdd output by the power supply control unit 400.

[0033] The switch VddSW is provided on a power supply path from the power supply Vdd to the amplifier unit 101. Power is supplied from the power supply Vdd to the amplifier unit 101 via the switch VddSW. The switch VddSW sets the power supply to the amplifier unit 101 to on or off. The switch VddSW corresponds to the switch unit of the present disclosure.

[0034] (Operation) The baseband IC 500 controls each unit of the communication device 1000 so that the signal passes through the desired path, and transmits an RF signal. The RF signal is input to the power amplifier circuit M1 and amplified by the amplifier unit 101 in the driver stage. The RF signal amplified by the amplifier unit 101 is input to the amplifier unit 201 or 202 in the power stage, depending on the states of the switches SW1 and SW2. The signal input to and amplified by the amplifier unit 201 is output from the antenna ANT1 via the band select switch BS1, the filter SF1 or SF2, and the antenna switch AS1. The signal input to and amplified by the amplifier unit 202 is output from the antenna ANT2 via the band select switch BS2, the filters SF3 to SF5, and the antenna switch AS2.

[0035] The power supply control unit 400 is controlled by the baseband IC 500. The voltage value of the power supply Vdd output by the power supply control unit 400 is controlled according to the output power of the amplifier unit 201 or 202 that is in an operating state. For this reason, the voltage value of the power supply Vdd fluctuates. For example, the voltage value of the power supply Vdd fluctuates when average power tracking (APT) or envelope tracking (ET) is performed.

[0036] Second Embodiment To facilitate understanding of the second embodiment, a third comparative example and a fourth comparative example will be described first. FIG. 5 is a diagram showing the configuration of an amplifier unit used in a power amplifier circuit of the third comparative example. FIG. 5 shows the configuration of an amplifier unit that does not include a switch VddSW, which will be described later. In FIG. 5, the amplifier unit includes a plurality of field-effect transistors, namely, FETs 11, 12, 13, 14, 15, and 16; resistors 21, 22, 23, 24, 25, and 26; resistors 31, 32, 33, 34, 35, and 36; capacitors 41, 42, 43, 44, 45, and 46; an FET 17; a choke coil L11; a bypass capacitor C11; and a bias circuit B1.

[0037] FETs 11, 12, 13, 14, 15, and 16 are provided between a reference potential and a power supply Vdd. FETs 11, 12, 13, 14, 15, and 16 are connected in a vertical stack configuration by connecting adjacent drains and sources. That is, the source of FET 11 is connected to the reference potential, and the drain of FET 11 is connected to the source of FET 12. The drain of FET 12 is connected to the source of FET 13. The drain of FET 13 is connected to the source of FET 14. The drain of FET 14 is connected to the source of FET 15. The drain of FET 15 is connected to the source of FET 16. The drain of FET 16 is connected to the power supply Vdd via a choke coil L11. In this document, FET 11 may be referred to as the first FET, and FET 12 may be referred to as the second FET. The reference potential is, for example, ground potential. This also applies to the following description.

[0038] The voltage value of the power supply Vdd is a fixed value, but may vary as described below. An output terminal RFout is connected between the choke coil L11 and the FET 16. The output terminal RFout is connected to a subsequent amplifier section. The output terminal RFout is connected to the power supply Vdd via the choke coil L11.

[0039] The resistor 31 and the capacitor 41 are provided corresponding to the FET 11. One end of the resistor 31 and one end of the capacitor 41 are connected to the gate of the FET 11. The other end of the capacitor 41 is connected to an input terminal RFin. A signal to be amplified is input to the input terminal RFin.

[0040] The resistor 32 and the capacitor 42 are provided corresponding to the FET 12. One end of the resistor 32 and one end of the capacitor 42 are connected to the gate of the FET 12. The other end of the capacitor 42 is connected to the reference potential.

[0041] The resistor 33 and the capacitor 43 are provided corresponding to the FET 13. One end of the resistor 33 and one end of the capacitor 43 are connected to the gate of the FET 13. The other end of the capacitor 43 is connected to the reference potential.

[0042] The resistor 34 and the capacitor 44 are provided corresponding to the FET 14. One end of the resistor 34 and one end of the capacitor 44 are connected to the gate of the FET 14. The other end of the capacitor 44 is connected to the reference potential.

[0043] The resistor 35 and the capacitor 45 are provided corresponding to the FET 15. One end of the resistor 35 and one end of the capacitor 45 are connected to the gate of the FET 15. The other end of the capacitor 45 is connected to the reference potential.

[0044] The resistor 36 and the capacitor 46 are provided corresponding to the FET 16. One end of the resistor 36 and one end of the capacitor 46 are connected to the gate of the FET 16. The other end of the capacitor 46 is connected to the reference potential.

[0045] The drain and gate of the FET 17 are connected together to form a so-called diode connection, and the FET 17 is provided between the resistor 21 and the reference potential.

[0046] Resistors 21, 22, 23, 24, 25, and 26 are ladder resistors connected in series between a power supply Vdd and a reference potential. Resistors 21, 22, 23, 24, 25, and 26 form a voltage-dividing resistor circuit 20. The voltage-dividing resistor circuit 20 divides the potential difference between the power supply Vdd and the reference potential and generates a bias to be applied to each gate of FET 12 to FET 16. By realizing each of resistors 21, 22, 23, 24, 25, and 26 as the same ladder resistor, it is possible to prevent reversal of the gate bias of each stage due to mismatches between resistors. Here, "the same ladder resistor" refers to ladder resistors manufactured using the same manufacturing process and materials.

[0047] One end of the resistor 21 is connected to the drain and gate of the FET 17. One end of the resistor 21 is connected to a reference potential via a diode formed by the FET 17. The FET 17 is connected to the reference potential side of the voltage-dividing resistor circuit 20. Therefore, the FET 17 is provided between the voltage-dividing resistor circuit 20 and the reference potential.

[0048] In the voltage-dividing resistor circuit 20, resistors 21 and 22 are connected in series. The junction of resistors 21 and 22 is connected to the other end of resistor 32. The voltage at the junction of resistors 21 and 22 is applied to the gate of FET 12 as bias vg2. Resistors 22 and 23 are connected in series. The junction of resistors 22 and 23 is connected to the other end of resistor 33. The voltage at the junction of resistors 22 and 23 is applied to the gate of FET 13 as bias vg3. Resistors 23 and 24 are connected in series. The junction of resistors 23 and 24 is connected to the other end of resistor 34. The voltage at the junction of resistors 23 and 24 is applied to the gate of FET 14 as bias vg4. Resistors 24 and 25 are connected in series. The junction of resistors 24 and 25 is connected to the other end of resistor 35. The voltage at the connection point between resistors 24 and 25 is applied to the gate of FET 15 as bias vg5. Resistors 25 and 26 are connected in series. The connection point between resistors 25 and 26 is connected to the other end of resistor 36. The voltage at the connection point between resistors 25 and 26 is applied to the gate of FET 16 as bias vg6. The other end of resistor 31 is connected to bias circuit B1. A bias vg1 output by bias circuit B1 is applied to the gate of FET 11 via resistor 31.

[0049] The choke coil L11 is connected in series between the power supply voltage Vdd and the amplifier unit 101. One end of the bypass capacitor C11 is connected to the connection point between one end of the choke coil L11 and the power supply voltage Vdd. The other end of the bypass capacitor C11 is connected to the reference potential.

[0050] The amplifier 101 shown in Fig. 5 operates as follows. That is, a bias (i.e., gate bias) generated by resistive voltage division of the voltage-dividing resistor circuit 20 is applied to each gate of FETs 12 to 16. The amplifier 101 amplifies a radio frequency signal input to the input terminal RFin. The amplifier 101 outputs the amplified signal from the output terminal RFout.

[0051] In this example, FETs 11 to 16 are provided, with six FETs connected in a vertical stack. The number of FETs connected in a vertical stack (hereinafter referred to as the stack number) is determined so as to ensure a withstand voltage at the maximum voltage applied by the power supply Vdd. In other words, the stack number is determined so as not to cause breakdown even when the maximum voltage is applied. Hereinafter, the maximum voltage may be referred to as the AMR voltage (Absolute Maximum Ratings).

[0052] However, if there is a discrepancy between the operating range of the power supply Vdd, which is required to guarantee the characteristics of the power amplifier circuit, and the AMR voltage, a larger number of stacks than the number required for the power supply Vdd within the operating range is required to ensure the withstand voltage for the AMR voltage. Increasing the number of stacks increases the on-resistance of FETs close to the power supply Vdd, resulting in degradation of the characteristics of the power amplifier circuit. For example, while a stack count of "4" would be sufficient to ensure the withstand voltage within the operating range of the power supply Vdd, it is necessary to increase the stack count to "6" to ensure the withstand voltage for the AMR voltage. In this case, the two FETs 15 and 16 close to the power supply Vdd appear as on-resistance within the operating range, which causes degradation of the characteristics of the power amplifier circuit.

[0053] 6 is a diagram showing an example of a configuration in which a switch VddSW is connected to an amplifier unit. In FIG. 6, the switch VddSW is inserted between the wiring of the power supply Vdd and the choke coil L11. The number of stacks in the amplifier unit 101 is "4."

[0054] When the voltage value of the power supply Vdd exceeds the operating range, the switch VddSW is turned off. This allows the maximum voltage of the power supply Vdd applied to the power amplifier circuit to be within the operating range or to be slightly above that range. This configuration reduces the maximum voltage applied to the power amplifier circuit, ensuring a sufficient withstand voltage while reducing the number of stacks in the power amplifier circuit. Reducing the number of stacks prevents deterioration of the characteristics of the power amplifier circuit. The operating range is the voltage range used to drive the amplifier unit 101, and refers to a voltage range below the maximum drive voltage of the amplifier unit 101. In other words, when the voltage exceeds the operating range, it is synonymous with when the voltage exceeds the maximum drive voltage of the amplifier unit 101.

[0055] Here, since the switch VddSW is inserted between the power supply Vdd and the choke coil L11, the on-resistance of the switch VddSW is visible in terms of DC, but since it is grounded by the bypass capacitor C11 in terms of high frequency, the on-resistance of the switch VddSW can be made invisible.

[0056] Incidentally, when the voltage value of the power supply Vdd exceeds the operating range, if the switch VddSW is turned completely off, the voltage of the power supply Vdd is applied only to the switch VddSW. If there are no FETs capable of handling the AMR voltage of the power supply Vdd in the semiconductor process for creating the power amplifier circuit, it is necessary to increase the number of FETs connected in series in the switch VddSW to provide a withstand voltage measure.

[0057] Fig. 7 is a diagram showing an amplifier unit used in a power amplifier circuit of a fourth comparative example. Fig. 7 shows a configuration in which a switch VddSWa for voltage resistance measures is connected to an amplifier unit 101. In Fig. 7, the switch VddSWa includes switches SSW1 and SSW2 and resistors Rsw1 and Rsw2.

[0058] The switches SSW1 and SSW2 are both realized by, for example, FETs. One end of the switch SSW1 is connected to the wiring of the power supply Vdd. The other end of the switch SSW1 is connected to one end of the switch SSW2. The other end of the switch SSW2 is connected to the drain of the FET 14 via a choke coil L11. The choke coil L11 is connected in series between the switch VddSWa and the amplifier unit 101.

[0059] One end of resistor Rsw1 is connected to the wiring of power supply Vdd. The other end of resistor Rsw1 is connected to one end of resistor Rsw2. The other end of resistor Rsw2 is connected to the reference potential. The voltage divided by resistors Rsw1 and Rsw2 is applied to the connection point between switch SSW1 and switch SSW2.

[0060] As shown in Figure 7, when FET switches SSW1 and SSW2 are connected in a vertical stack, the applied voltage can be distributed to each FET, but the on-resistance of the FET becomes a value multiplied by the number of stacks. Furthermore, the area of ​​the FET also becomes multiplied by the number of stacks. If the on-resistance is to be made equal to that of one FET, the area of ​​the FET becomes the square of the number of stacks. Regarding the on-resistance of switch VddSWa, the effect can be reduced at high frequencies, but since a voltage drop occurs in the direct current of amplifier unit 101, there is a disadvantage that if the on-resistance of switch VddSWa is high, the voltage applied to amplifier unit 101 during operation will decrease.

[0061] Furthermore, if the switch VddSWa is completely turned off when the voltage value of the power supply Vdd exceeds the operating range, the voltage of the power supply Vdd will be applied only to the switch VddSWa. For this reason, the FET switches SSW1 and SSW2 used in the switch VddSWa must have a withstand voltage equal to or greater than the AMR voltage.

[0062] 8 is a diagram showing an amplifier unit used in a power amplifier circuit according to the second embodiment. To solve the problems encountered in the fourth comparative example, the second embodiment combines a switch TrP (hereinafter referred to as a PMOS switch) based on a P-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with a switch TrN (hereinafter referred to as an NMOS switch) based on an N-type MOSFET, and uses them like a transfer gate. The source of the PMOS switch TrP is connected to a power supply Vdd. The drain of the NMOS switch TrN is connected to a power supply Vdd. The drain of the PMOS switch TrP and the source of the NMOS switch TrN are connected, and power is supplied to the amplifier unit 101 from this connection point. The PMOS switch TrP corresponds to the PMOS transistor in this disclosure. The NMOS switch TrN corresponds to the NMOS transistor in this disclosure.

[0063] The switch VddSW has a PMOS gate bias circuit PB. The PMOS gate bias circuit PB provides a bias to the gate of the PMOS switch TrP. The PMOS gate bias circuit PB provides a bias to the gate of the PMOS switch TrP that turns the PMOS switch TrP off when the voltage of the power supply Vdd is equal to or higher than a predetermined threshold, and turns the PMOS switch TrP on when the voltage of the power supply Vdd is less than the predetermined threshold.

[0064] The PMOS switch TrP is turned off when the voltage of the power supply Vdd is equal to or higher than a predetermined threshold, and is turned on when the voltage of the power supply Vdd is lower than the predetermined threshold. If the switch VddSW were turned completely off, the switch VddSW alone would be required to ensure a withstand voltage against the AMR voltage. In contrast, even when the voltage of the power supply Vdd becomes high and the switch VddSW is turned off, a voltage equal to or lower than the voltage value of the power supply Vdd within the operating range is applied to the amplifier unit 101. In this way, the voltage of the power supply Vdd is divided by both the switch VddSW and the amplifier unit 101, ensuring the withstand voltages of each.

[0065] Specifically, a voltage (hereinafter referred to as voltage VREG) that is approximately half the AMR voltage is continuously applied to the gate of the NMOS switch TrN even when the PMOS switch TrP is in the off state, thereby causing the NMOS switch TrN to operate as a source follower. As a result, a voltage approximately equal to the voltage VREG minus the threshold voltage of the NMOS switch TrN is applied to the amplifier unit 101, thereby dividing the voltage of the power supply Vdd. Note that voltage VREG can be generated within the power amplifier circuit.

[0066] Furthermore, voltage continues to be applied to the upper end of the amplifier unit 101, i.e., the drain of FET 14, but when switch VddSW is turned off, the amplifier unit 101 is simultaneously turned off. Specifically, the bias vg1 from bias circuit B1 is set to 0 V, and FET 11 is turned off. As a result, the amplifier unit 101 does not amplify the RF signal, and the RF signal is no longer output from the output terminal RFout. This makes it possible to implement measures to prevent destruction of amplifier unit 201 or 202 (see FIG. 4) downstream of amplifier unit 101.

[0067] 9 is a diagram illustrating the relationship between the voltage values, showing the voltage VPA at the upper end of the amplifier unit 101 after the switch VddSW is turned off (the output voltage of the switch VddSW), the voltage Voff that turns the switch VddSW off, and the AMR voltage Vamr.

[0068] 9, arrow Y1 indicates the withstand voltage required for switch VddSW, arrow Y2 indicates the withstand voltage required for amplifier unit 101, and reciprocating arrow Y3 indicates the voltage within the operating range.

[0069] 9, the voltage Voff that turns the switch VddSW off is set between the AMR voltage Vamr and the maximum voltage of the operating range. The withstand voltage of the amplifier 101 needs to be designed to be higher than the voltage Voff that turns the switch VddSW off. In other words, the maximum voltage value of the operating range<the voltage Voff that turns the switch VddSW off<the withstand voltage of the amplifier 101<the AMR voltage.

[0070] Furthermore, the voltage VPA at the upper end of the amplifier unit 101 after the switch VddSW is turned off must be equal to or lower than the voltage Voff that turns the switch VddSW off. In other words, the voltage value at the upper end of the amplifier unit 101 when the switch VddSW is off is equal to or lower than the voltage Voff that turns the switch VddSW off.

[0071] Furthermore, the withstand voltage of the switch VddSW needs to be greater than the difference between the AMR voltage Vamr and the voltage VPA at the upper end of the amplifier unit 101 after the switch VddSW is turned off. In other words, (AMR voltage Vamr - voltage VPA at the upper end of the amplifier unit 101 when the switch VddSW is turned off) < withstand voltage of the amplifier unit 101.

[0072] 10 is a diagram showing an amplifier unit used in a power amplifier circuit according to a third embodiment. The third embodiment has a configuration in which a comparator CMP, resistors R0 and R1, an inverter INV, and a reference voltage source Vref are added to the configuration of the second embodiment.

[0073] The voltage between the power supply Vdd and the reference potential is divided by resistors R0 and R1 and input to the non-inverting input terminal (+ side) of the comparator CMP. The reference voltage of the reference voltage source Vref is input to the inverting input terminal (- side) of the comparator CMP. The comparator CMP compares the voltage of the power supply Vdd with the reference voltage of the reference voltage source Vref. The reference voltage of the reference voltage source Vref can be generated within the power amplifier circuit.

[0074] When the divided voltage of the power supply Vdd by resistors R0 and R1 exceeds the reference voltage of the reference voltage source Vref, the output signal of the comparator CMP switches from low to high. The output signal of the comparator CMP switches from low to high, thereby controlling the PMOS switch TrP to be turned off. The threshold value of the reference voltage source Vref of this comparator CMP must be set higher than the operating range of the power supply Vdd and lower than the withstand voltage of the amplifier unit 101.

[0075] Furthermore, the output signal of the comparator CMP is inverted by the inverter INV and then input to the bias circuit B1. This switches the bias vg1 from the bias circuit B1 to the amplifier unit 101 from high level to low level. This prevents the amplifier unit 101 from outputting an RF signal, thereby preventing the amplifier unit 201 or 202 in the subsequent stage from being destroyed.

[0076] 11 is a waveform diagram showing an example of a signal obtained by inverting the output signal of the comparator CMP in FIG. 10. That is, FIG. 11 is a waveform diagram showing an example of the output signal of the inverter INV in FIG. 10. As shown in FIG. 11, the output voltage Vinv of the inverter INV changes from high to low when the voltage Vinv exceeds the operating voltage range of the power supply Vdd used during normal operation to some extent and is lower than the AMR voltage. When the output voltage Vinv of the inverter INV changes in this manner, the bias vg1 from the bias circuit B1 to the amplifier unit 101 switches from high to low. This prevents the amplifier unit 101 from outputting an RF signal, thereby preventing damage to the downstream amplifier unit 201 or 202.

[0077] 12 is a diagram showing the input voltage and output voltage of a switch VddSW provided between a power supply Vdd and the amplifier unit 101. The solid line in Fig. 12 indicates the input voltage VddSWin to the switch VddSW. The dashed-dotted line in Fig. 12 indicates the output voltage VddSWout from the switch VddSW.

[0078] 12, the input voltage VddSWin to the switch VddSW rises within the range of the AMR voltage. In contrast, the output voltage VddSWout from the switch VddSW rises following the input voltage VddSWin, but drops at a voltage Voff that exceeds the operating voltage range of the amplifier unit 101 to some extent and is less than the voltage value corresponding to the withstand voltage of the amplifier unit 101. This is because the gate bias from the PMOS gate bias circuit PB drops, turning the switch TrP into the OFF state. Even when the switch TrP is in the OFF state, the switch TrN remains in the ON state. At this time, the output voltage VddSWout reaches a voltage level near the voltage VREG, which is the gate bias of the switch TrN.

[0079] If the switch VddSW is not provided, the withstand voltage (number of stacks) of the amplifier unit 101 must be designed to match the AMR voltage. In contrast, by employing the switch VddSW, a voltage greater than the voltage value of the power supply Vdd that turns the switch VddSW off is not applied to the amplifier unit 101. This allows the number of stacks in the amplifier unit 101 to be designed at a voltage lower than the AMR voltage, and the number of stacks can be reduced. Reducing the number of stacks improves the characteristics of the amplifier unit 101 within the operating voltage range.

[0080] 13 is a diagram showing the input voltage and gate bias of switch VddSW. Fig. 13 shows the input voltage VddSWin of switch VddSW, the gate bias Vgp of switch TrP, and the gate bias Vgn of switch TrN. While switch VddSW is in the on state, the gate bias Vgp to switch TrP is controlled so that the source-gate voltage of switch TrP does not exceed the element breakdown voltage due to a voltage rise in the power supply Vdd. After switch VddSW is turned off, switch TrP is set to the same potential as power supply Vdd and is turned off.

[0081] The voltage VREG is continuously applied to the switch TrN as the gate bias Vgn, regardless of the on / off state of the switch VddSW. This maintains the output voltage of the switch VddSW constant even after the switch TrP is turned off. For example, the output voltage of the switch VddSW is controlled to about 3 V, ensuring the withstand voltage of the switch VddSW. That is, regardless of the voltage value of the power supply Vdd, when the switch TrP is turned off, a gate bias Vgn is applied to the switch TrN such that the source potential of the switch TrN is less than a predetermined threshold (e.g., less than half the voltage of the AMR voltage as shown in FIG. 12). This causes the switch TrN to operate as a source follower, and the source potential of the switch TrN is maintained so as not to exceed the withstand voltage of the power amplifier circuit. That is, the voltage VREG is continuously applied to the gate of the NMOS switch TrN even when the PMOS switch TrP is turned off, thereby causing the switch TrN to operate as a source follower.

[0082] The voltage value of the power supply Vdd may be controlled. For example, in APT control, the voltage value of the power supply Vdd is controlled in accordance with the output power. In this case, the voltage value of the power supply Vdd varies over a wide range.

[0083] Fig. 14 is a diagram showing an example of changes in on-resistance. Fig. 14 shows a change curve S1 (dashed line in Fig. 14) of the on-resistance of the PMOS switch TrP, a change curve S2 (solid line in Fig. 14) of the on-resistance of the NMOS switch TrN, and a change curve S3 (dashed line in Fig. 14) of the on-resistance of the PMOS and NMOS switches. Note that Fig. 14 shows the on-resistance calculated without turning off the switch VddSW.

[0084] Fig. 15 is a diagram showing an example of a switch VddSWP formed solely by PMOS. The switch VddSWP in Fig. 15 has only a switch TrP formed by PMOS. Fig. 16 is a diagram showing an example of a switch VddSWN formed solely by NMOS. The switch VddSWN in Fig. 16 has only a switch TrN formed by NMOS. Fig. 17 is a diagram showing an example of a switch VddSW formed by both PMOS and NMOS.

[0085] 14, in the case of the switch VddSWP which has only the PMOS switch TrP (see FIG. 15), when the voltage of the power supply Vdd drops, the gate-source voltage Vgs of the switch VddSWP decreases, and the on-resistance increases. Also, in the case of the switch VddSWN which has only the NMOS switch TrN (see FIG. 16), since the gate bias is voltage VREG, when the voltage of the power supply Vdd increases, the gate-source voltage Vgs of the switch VddSWN cannot be secured, and the on-resistance increases. When the voltage of the power supply Vdd drops, the gate-source voltage Vgs can be increased, in contrast to the PMOS switch TrP, and the on-resistance decreases.

[0086] In the second and third embodiments described above, a configuration in which the switch TrP and the switch TrN are combined is adopted (see FIG. 17 ). This makes it possible to suppress an increase in the on-resistance of the switch VddSW over the entire operating range of the power supply Vdd.

[0087] 18 is a diagram illustrating an amplifier unit used in a power amplifier circuit according to a fourth embodiment. In the fourth embodiment, a variable resistor VR is used instead of the resistor R1 in the configuration of the third embodiment. The output signal of the comparator CMP may alternate between a high level voltage and a low level voltage near the threshold. This alternating high and low level voltage may cause the switch VddSW to alternate between an on state and an off state.

[0088] Therefore, in this embodiment, the output signal of the comparator CMP is given a hysteresis characteristic to prevent the above repetition. Specifically, the resistance value of the variable resistor VR is controlled by the output of the inverter INV, and the output signal of the comparator CMP is given a hysteresis characteristic.

[0089] 19 is a diagram illustrating the hysteresis characteristic of the output signal of the comparator CMP. When the power supply Vdd is at voltage Voff, the output signal of the comparator CMP transitions from high to low (arrow YD in FIG. 19). On the other hand, when the power supply Vdd is at voltage Von, the output signal of the comparator CMP transitions from low to high (arrow YU in FIG. 19). In other words, the output signal of the comparator CMP is a high-level voltage or a low-level voltage, and has hysteresis characteristics for the transition from high to low (arrow YD in FIG. 19) and the transition from low to high (arrow YU in FIG. 19).

[0090] 18 , in this embodiment, a switch SWin and a matching circuit MN1 are provided between the input terminal RFin and the amplifier unit 101. In addition, a matching circuit MN2 and a switch SWout are provided between the amplifier unit 101 and the output terminal RFout. Furthermore, a level shift circuit LVS is provided to convert the level of the output signal of the inverter INV.

[0091] The level of the output signal of the inverter INV may be converted by the level shift circuit LVS, and the output signal of the level shift circuit LVS may control the switches SWin and SWout. The output signal of the comparator CMP may be used to turn off the switches SWin and SWout at the timing when the switch TrP of the switch VddSW is turned off, thereby turning off the amplifier unit 101.

[0092] 20 is a diagram showing an example of the configuration of the variable resistor VR in FIG. 18. In FIG. 20, the variable resistor VR includes a resistor R11, a resistor R12, and an FET 19. One end of the resistor R11 is connected to a resistor R0. The other end of the resistor R11 is connected to one end of the resistor R12. The other end of the resistor R12 is connected to a reference potential. The drain of the FET 19 is connected to one end of the resistor R12. The source of the FET 19 is connected to the other end of the resistor R12. An output signal of the inverter INV (see FIG. 18) is applied to the gate of the FET 19.

[0093] When the output signal of the inverter INV is at a high level, the FET 19 is turned on. When the output signal of the inverter INV is at a low level, the FET 19 is turned off. Therefore, the voltage input to the comparator CMP differs depending on whether the output signal of the inverter INV is at a high level or a low level. Therefore, as described with reference to FIG. 19 , a hysteresis characteristic can be imparted to the transition of the output signal of the comparator CMP from a high level to a low level (arrow YD in FIG. 19 ) and a transition from a low level to a high level (arrow YU in FIG. 19 ). By providing a hysteresis characteristic, it is possible to prevent repetition of high-level voltages and low-level voltages near the threshold.

[0094] Fifth Embodiment FIG. 21 is a diagram illustrating the configuration of a power amplifier circuit 100c according to a fifth embodiment. In FIG. 21, the power amplifier circuit 100c, unlike the power amplifier circuit 100 described with reference to FIG. 3, has only a single-stage amplifier unit 101. That is, the power amplifier circuit 100c has the amplifier unit 101, which is a single-stage amplifier, and a switch VccSW provided corresponding to the amplifier unit 101. A voltage from a power supply Vcc is supplied to the amplifier unit 101 via the switch VccSW. The switch VccSW corresponds to the switch unit in the present disclosure. The amplifier unit 101 corresponds to the first amplifier unit in the present disclosure. The output unit of the amplifier unit 101 in this example is provided with a grounded-emitter transistor. Therefore, a voltage from the power supply Vcc is applied to the output side of the amplifier unit 101.

[0095] The switch VccSW is controlled to be turned on when the voltage from the power supply Vcc is equal to or lower than a predetermined threshold. The switch VccSW is controlled to be turned off when the voltage from the power supply Vcc exceeds a predetermined threshold. The predetermined threshold is, for example, the maximum drive voltage of the amplifier unit 101.

[0096] The amplifier unit 101 includes vertically stacked FETs (not shown), similar to the second embodiment described with reference to FIG. 8. The number of stacked FETs is determined so as to ensure a withstand voltage at the maximum voltage applied by the power supply Vcc. That is, the number of stacked FETs is determined so as not to cause breakdown even when the maximum voltage is applied. Similarly to the second embodiment described with reference to FIG. 8, the amplifier unit 101 includes a voltage-dividing resistor circuit (not shown) for generating a bias to be applied to the gate of the FET in each stage.

[0097] Therefore, the power amplifier circuit 100c includes an amplifier unit 101 that amplifies an input high-frequency signal and a switch VccSW provided in a power supply path to the amplifier unit 101. Power is supplied to the amplifier unit 101 via the switch VccSW, which turns on or off the power supply to the amplifier unit 101. As in the second embodiment described with reference to FIG. 8 , the amplifier unit 101 includes an input terminal to which a signal to be amplified is input, a first FET having a gate to which the signal input to the input terminal is applied, a second FET connected together with the first FET between a power supply and a reference potential, and an output terminal provided between the second FET and a load and from which an amplified signal is output, with the first FET and the second FET being stacked. Note that the relationship between the respective voltage values ​​is the same as that described with reference to FIG. 9 .

[0098] The operation of the power amplifier circuit 100c shown in Figure 21 is as follows. That is, in the power amplifier circuit 100c, when the switch VccSW is turned on, a voltage from the power supply Vcc is supplied to the amplifier unit 101. This causes the amplifier unit 101 to perform an amplification operation. The amplifier unit 101 amplifies a signal input to the input terminal Tin and outputs it from the output terminal Tout. When the switch VccSW is turned off, the voltage from the power supply Vcc is not supplied to the amplifier unit 101. At this time, the amplifier unit 101 does not perform an amplification operation.

[0099] In the power amplifier circuit 100c, the amplifier unit 101 may be formed on a silicon die. A silicon die refers to a die made of silicon, such as a die made of silicon-on-insulator (SOI) substrate. Even when the amplifier unit 101 is configured with multiple transistors stacked on a silicon die, it is possible to suppress the maximum voltage applied to the power amplifier circuit, ensure voltage resistance, and prevent deterioration of the characteristics of the power amplifier circuit.

[0100] (Communication Device) Here, a communication device including a power amplifier circuit 100c will be described. Fig. 22 is a diagram showing an example configuration of a communication device 1000a including a power amplifier circuit 100c. Unlike the communication device 1000 described with reference to Fig. 4, the communication device 1000a has only one output system to an antenna. That is, the communication device 1000a includes a power amplifier circuit M1a, a band select switch BS1, filters SF1 and SF2, an antenna switch AS1, an antenna ANT1, a power supply control unit 400, a baseband IC 500, and a switch VddSW. The switch VddSW corresponds to the switch unit of the present disclosure.

[0101] The power amplifier circuit M1a is a PA (Power Amplifier) ​​module and has a function as a power amplifier circuit. The power amplifier circuit M1a includes an amplifier unit 101 and a control circuit 301.

[0102] The output terminal of the amplifier unit 101 is input to the band select switch BS1 as the output of the power amplifier circuit M1a. The control circuit 301 is a circuit that outputs a control signal that controls the amplifier unit 101. For example, the control circuit 301 inputs a gate bias control signal SSW to the amplifier unit 101. The amplifier unit 101 and the control circuit 301 are realized by, for example, an SOI substrate 801a. The other configurations and operations in FIG. 22 are similar to those of the communication device 1000 described with reference to FIG. 4.

[0103] With regard to the recitation of the claims, the present disclosure may take the following forms. <1> A power amplifier circuit having a plurality of stages of amplifier units, comprising: a first amplifier unit that amplifies an input high-frequency signal; a second amplifier unit that amplifies an output of the first amplifier unit; and a switch unit provided in a power supply path to the first amplifier unit, wherein power is supplied to the first amplifier unit via the switch unit, and the switch unit sets power supply to the first amplifier unit to on or off, and the power is supplied directly to the second amplifier unit without passing through the switch unit. <2> The power amplifier circuit according to <1>, wherein the first amplifier unit is formed on a silicon die, and the second amplifier unit is formed on a die other than the silicon die. <3> The power amplifier circuit according to <1> or <2>, further including a power supply that supplies power to the first amplifying unit and the second amplifying unit, wherein the switch unit includes: a PMOS transistor having a source connected to the power supply; and an NMOS transistor having a drain connected to the power supply, wherein the drain of the PMOS transistor and the source of the NMOS transistor are connected, and power is supplied to the first amplifying unit from a connection point between the drain of the PMOS transistor and the source of the NMOS transistor, wherein the PMOS transistor is turned off when a voltage of the power supply exceeds a predetermined threshold, and is turned on when the voltage of the power supply is equal to or lower than the predetermined threshold, and wherein a gate bias is applied to the NMOS transistor such that a source potential of the NMOS transistor is less than the predetermined threshold when the PMOS transistor is turned off, regardless of the voltage value of the power supply. <4> The power amplifier circuit according to <3>, further comprising a bias circuit that applies a bias to the PMOS transistor, wherein the bias circuit applies a bias to a gate of the PMOS transistor that turns the PMOS transistor off when the voltage of the power supply exceeds a predetermined threshold and turns the PMOS transistor on when the voltage of the power supply is equal to or lower than the predetermined threshold.<5> The power amplifier circuit according to <4>, further including a comparator that compares the voltage of the power supply with a predetermined reference voltage, and the bias circuit applies a bias to the PMOS transistor based on a comparison result of the comparator. <6> The power amplifier circuit according to <5>, wherein the output signal of the comparator is a high-level or low-level voltage, and a hysteresis characteristic is imparted to a transition from the high level to the low level and a transition from the low level to the high level. <7> The power amplifier circuit according to any one of <1> to <6>, further including: a choke coil connected in series between the switch unit and the first amplifier unit; and a bypass capacitor provided between the choke coil and a reference potential. <8> The power amplifier circuit according to any one of <1> to <7>, wherein the first amplifier unit includes: an input terminal to which a signal to be amplified is input, a first FET having a gate to which the signal input to the input terminal is applied, a second FET connected together with the first FET between a power supply and a reference potential, an output terminal provided between the second FET and a load and for outputting the amplified signal, and a voltage dividing resistor circuit for generating a bias to be applied to the gate of the second FET, wherein the first FET and the second FET are connected in a cascade configuration by connecting adjacent drains and sources. <9> The power amplifier circuit according to any one of <1> to <8>, wherein a power supply voltage value changes depending on the output power of the power amplifier circuit.<10> A power amplifier circuit having only one stage of amplifier section, comprising: a first amplifier section that amplifies an input high frequency signal; and a switch section provided in a power supply path to the first amplifier section, wherein power is supplied to the first amplifier section via the switch section, and the switch section sets power supply to the first amplifier section to on or off, wherein the first amplifier section has: an input terminal to which a signal to be amplified is input; a first FET having a gate to which the signal input to the input terminal is applied; a second FET connected together with the first FET between a power supply and a reference potential; an output terminal provided between the second FET and a load, and which outputs an amplified signal; and a voltage dividing resistor circuit for generating a bias to be applied to the gate of the second FET, wherein the first FET and the second FET are connected in a cascade configuration by connecting adjacent drains and sources.

[0104] 11-17 FET 20 Voltage divider resistor circuit 21-26, 31-36, R0, R1, R11, R12, Rsw1, Rsw2 Resistor 41-46 Capacitor 100, 100a, 100b, 100c Power amplifier circuit 101, 201, 202 Amplifier section 1000, 1000a Communication device ANT1, ANT2 Antenna AS1, AS2 Antenna switch B1 Bias circuit BS1, BS2 Band select switch C11 Bypass capacitor CMP Comparator 500 Baseband IC INV Inverter L11 Choke coil LVS Level shift circuit M1, M1a Power amplifier circuit MN1, MN2 Matching circuit PB Gate bias circuit RFin Input terminal RFout Output terminal SF1-SF5 Filter SSW1, SSW2, SW1, SW2 Switches SWa, SWb, SWc Switches VR Variable resistor

Claims

1. A power amplifier circuit having multiple stages of amplifier sections, comprising: a first amplifier section that amplifies an input high frequency signal; a second amplifier section that amplifies the output of the first amplifier section; and a switch section that is provided in a power supply path to the first amplifier section, wherein power is supplied to the first amplifier section via the switch section, and the switch section sets the power supply to the first amplifier section to on or off, and the power is supplied directly to the second amplifier section without passing through the switch section.

2. The power amplifier circuit according to claim 1, wherein the first amplifier unit is formed on a silicon die, and the second amplifier unit is formed on a die other than the silicon die.

3. The power amplifier circuit according to claim 1 or 2, further comprising a power supply that supplies power to the first amplifying section and the second amplifying section, wherein the switch section comprises a PMOS transistor having a source connected to the power supply and an NMOS transistor having a drain connected to the power supply, the drain of the PMOS transistor and the source of the NMOS transistor are connected, and power is supplied to the first amplifying section from a connection point between the drain of the PMOS transistor and the source of the NMOS transistor, the PMOS transistor is turned off when the voltage of the power supply exceeds a predetermined threshold and is turned on when the voltage of the power supply is equal to or lower than the predetermined threshold, and a gate bias is applied to the NMOS transistor such that the source potential of the NMOS transistor is less than the predetermined threshold when the PMOS transistor is off regardless of the voltage value of the power supply.

4. The power amplifier circuit according to claim 3, further comprising a bias circuit for applying a bias to said PMOS transistor, said bias circuit applying a bias to a gate of said PMOS transistor for turning said PMOS transistor into an OFF state when the voltage of said power supply exceeds a predetermined threshold, and turning said PMOS transistor into an ON state when the voltage of said power supply is equal to or lower than said predetermined threshold.

5. The power amplifier circuit according to claim 4, further comprising a comparator for comparing the voltage of the power supply with a predetermined reference voltage, and wherein the bias circuit provides a bias to the PMOS transistor based on a comparison result of the comparator.

6. The power amplifier circuit according to claim 5, wherein the output signal of the comparator is a high-level or low-level voltage, and a hysteresis characteristic is provided for a transition from the high level to the low level and a transition from the low level to the high level.

7. The power amplifier circuit according to claim 1 or 2, further comprising: a choke coil connected in series between said switch section and said first amplifier section; and a bypass capacitor provided between said choke coil and a reference potential.

8. The power amplifier circuit according to claim 1 or 2, wherein the first amplifier section comprises: an input terminal to which a signal to be amplified is input; a first FET having a gate to which the signal input to the input terminal is applied; a second FET connected together with the first FET between a power supply and a reference potential; an output terminal provided between the second FET and a load and for outputting the amplified signal; and a voltage dividing resistor circuit for generating a bias to be applied to the gate of the second FET, wherein the first FET and the second FET are vertically stacked by connecting adjacent drains and sources.

9. The power amplifier circuit according to claim 1 or 2, wherein a power supply voltage value changes according to the output power of the power amplifier circuit.

10. A power amplifier circuit having only one stage of amplification section, comprising: a first amplification section which amplifies an input high frequency signal; and a switch section which is provided in a power supply path to the first amplification section, wherein power is supplied to the first amplification section via the switch section, and the switch section sets the power supply to the first amplification section to on or off, wherein the first amplification section comprises: an input terminal to which a signal to be amplified is input; a first FET having a gate to which the signal input to the input terminal is applied; a second FET connected together with the first FET between a power supply and a reference potential; an output terminal which is provided between the second FET and a load and which outputs an amplified signal; and a voltage dividing resistor circuit for generating a bias to be supplied to the gate of the second FET, wherein the first FET and the second FET are connected in a vertical stack manner by connecting adjacent drains and sources.

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