Method and apparatus for transmitting control frame

Abstract

The present application relates to the field of communications, and provides a method and apparatus for transmitting a control frame, which improves the bandwidth utilization rate of data transmission while improving the flexibility of control frame transmission. The method comprises: transmitting a control frame transmission position message, wherein the control frame transmission position message comprises control frame transmission position information, the control frame transmission position information is used for indicating that, upon the completion of transmission of the current logic block, a control frame is transmitted after a first number of logic blocks have been transmitted, and the first number refers to the number of logic blocks indicated by the control frame transmission position information; and upon the completion of transmission of the logic blocks containing the control frame transmission position message, transmitting the control frame after the first number of logic blocks have been transmitted.

Description

Method and device for transmitting control frame Technical Field

[0001] The present application relates to the field of communications, and in particular to a method and device for transmitting a control frame. Background Art

[0002] With the rapid development of communication technology, interconnected devices transmit business data through the links between them. To ensure the performance of the link, the devices at both ends control the link by exchanging control frames used to manage the link.

[0003] However, it is difficult to strike a balance between the flexibility of control frame sending and the accurate delimitation of the peer end.

[0004] Summary of the Invention

[0005] The method and device for transmitting control frames provided in the present application solve the problem of balancing the flexibility of control frame transmission and accurate delimitation by the opposite end, thereby improving the flexibility of control frame transmission while improving the accuracy of control frame delimitation by the opposite end.

[0006] To achieve the above objectives, the present invention adopts the following technical solutions:

[0007] In a first aspect, a method for transmitting a control frame is provided, which may include: sending a control frame sending position message, the control frame sending position message including control frame sending position information, the control frame sending position information being used to indicate that after the current logical block is sent, the control frame is sent after sending a first number of logical blocks; the first number is the number of logical blocks indicated by the control frame sending position information; after sending the logical block containing the control frame sending position message, the control frame is sent after sending the first number of logical blocks.

[0008] The solution provided by this application allows the specific sending location of a control frame to be indicated by a control frame sending location message before the control frame is sent. This allows the receiving end to delimit the control frame without configuring a dedicated character header, thereby improving bandwidth utilization for data transmission. Even if control frames are only sent when they are needed, accurate delimitation of the control frame can be guaranteed. Therefore, while increasing the flexibility of control frame transmission, bandwidth utilization for data transmission is also improved.

[0009] In a possible implementation, the current logic block may be a logic block containing a control frame sending location message.

[0010] In another possible implementation, the control frame is transmitted using an independent channel to ensure the integrity of its code type.

[0011] In another possible implementation, the control frame includes: a sequence frame used for clock locking in a channel training phase, or a logical layer training sequence 0.

[0012] In another possible implementation, the control frame includes: a sequence frame used for channel parameter tuning calculation in a channel training phase, or a logical layer training sequence 1.

[0013] In another possible implementation, the control frame includes: either a sequence frame for sending and receiving confirmation of synchronization status during the channel training phase, or a logical layer training sequence 2.

[0014] In another possible implementation, the control frame includes: a frame used to mark the end of channel data transmission, or a logical layer electrical idle frame.

[0015] In another possible implementation, the control frame includes: a frame used to mark the starting position of a new logical block, or a logical layer data start frame.

[0016] In another possible implementation, the control frame includes: a frame for delay detection, or a logical layer channel deviation elimination test frame.

[0017] In another possible implementation, the control frame includes: a frame for waking up, or a logical layer electrical idle exit frame.

[0018] In another possible implementation, the control frame includes: a frame for filling.

[0019] In another possible implementation, the code type of the control frame is fixed, that is, the content included in the control frame remains unchanged.

[0020] In another possible implementation, the control frame includes: the control frame includes one or more of the following: a frame header, or a payload.

[0021] The control frame is a sequence frame used for clock locking in the channel training phase, or a logical layer training sequence 0, and includes a payload.

[0022] Alternatively, the control frame is a sequence frame used for channel parameter tuning calculation in a channel training phase, or a logical layer training sequence 1, and the control frame includes a payload.

[0023] Alternatively, the control frame is a sequence frame used for sending and receiving confirmation of synchronization status during the channel training phase, or a logical layer training sequence 2. The control frame includes a frame header and a payload, and the frame header includes a frame type and a check field.

[0024] Alternatively, the control frame is a frame used to mark the end of channel data transmission, or a logical layer electrical idle frame. The control frame includes a frame header, and the frame header includes a frame type and a check field.

[0025] Alternatively, the control frame is a frame used to mark the start position of a new logic block, or a logical layer data start frame. The control frame includes a frame header, which includes a frame type and a check field.

[0026] Alternatively, the control frame is a frame used for delay detection, or a logical layer channel deviation elimination test frame. The control frame includes a frame header, and the frame header includes a frame type and a check field.

[0027] Alternatively, the control frame is a frame for waking up, or a logical layer electrical idle exit frame, and the control frame includes a payload.

[0028] Alternatively, the control frame is a frame used for padding, and the control frame includes a frame header and a payload, and the frame header includes a frame type and a check field.

[0029] In another possible implementation, the control frame is used to transmit link management and / or training sequence.

[0030] According to a second aspect, another method for transmitting a control frame is provided, which may include: receiving a logical block including a control frame sending position message; unpacking and deblocking the logical block to obtain control frame sending position information included in the control frame sending position message, wherein the control frame sending position information is used to indicate that after the current logical block is sent, the control frame will be sent after sending a first number of logical blocks; the first number is the number of logical blocks indicated by the control frame sending position information; and after the first number of logical blocks after the current logical block ends, parsing and obtaining the control frame.

[0031] It should be noted that the method for transmitting control frames provided in the second aspect is a receiving end method corresponding to the data transmission method provided in the above-mentioned first aspect or any possible implementation method. Its specific implementation can refer to the first aspect or any possible implementation method of the first aspect, and will not be repeated here.

[0032] In another possible implementation, the control frame is transmitted using an independent channel to ensure the integrity of its code type.

[0033] In another possible implementation, the control frame includes: a sequence frame used for clock locking in a channel training phase, or a logical layer training sequence 0.

[0034] In another possible implementation, the control frame includes: a sequence frame used for channel parameter tuning calculation in a channel training phase, or a logical layer training sequence 1.

[0035] In another possible implementation, the control frame includes: either a sequence frame for sending and receiving confirmation of synchronization status during the channel training phase, or a logical layer training sequence 2.

[0036] In another possible implementation, the control frame includes: a frame used to mark the end of channel data transmission, or a logical layer electrical idle frame.

[0037] In another possible implementation, the control frame includes: a frame used to mark the starting position of a new logical block, or a logical layer data start frame.

[0038] In another possible implementation, the control frame includes: a frame for delay detection, or a logical layer channel deviation elimination test frame.

[0039] In another possible implementation, the control frame includes: a frame for waking up, or a logical layer electrical idle exit frame.

[0040] In another possible implementation, the control frame includes: a frame for filling.

[0041] In another possible implementation, the code type of the control frame is fixed, that is, the content included in the control frame remains unchanged.

[0042] In another possible implementation, the control frame includes: the control frame includes one or more of the following: a frame header, or a payload.

[0043] The control frame is a sequence frame used for clock locking in the channel training phase, or a logical layer training sequence 0, and includes a payload.

[0044] Alternatively, the control frame is a sequence frame used for channel parameter tuning calculation in a channel training phase, or a logical layer training sequence 1, and the control frame includes a payload.

[0045] Alternatively, the control frame is a sequence frame used for sending and receiving confirmation of synchronization status during the channel training phase, or a logical layer training sequence 2. The control frame includes a frame header and a payload, and the frame header includes a frame type and a check field.

[0046] Alternatively, the control frame is a frame used to mark the end of channel data transmission, or a logical layer electrical idle frame. The control frame includes a frame header, and the frame header includes a frame type and a check field.

[0047] Alternatively, the control frame is a frame used to mark the start position of a new logic block, or a logical layer data start frame. The control frame includes a frame header, and the frame header includes a frame type and a check field.

[0048] Alternatively, the control frame is a frame used for delay detection, or a logical layer channel deviation elimination test frame. The control frame includes a frame header, and the frame header includes a frame type and a check field.

[0049] Alternatively, the control frame is a frame for waking up, or a logical layer electrical idle exit frame, and the control frame includes a payload.

[0050] Alternatively, the control frame is a frame used for padding, and the control frame includes a frame header and a payload, and the frame header includes a frame type and a check field.

[0051] In another possible implementation, the control frame is used to transmit link management and / or training sequence.

[0052] In a third aspect, a device for transmitting a control frame is provided, which may include: a determining unit and a sending unit.

[0053] a determining unit, configured to determine control frame sending position information, where the control frame sending position information is used to indicate that after the current logical block is sent, the control frame is sent after a first number of logical blocks are sent; the first number is the number of logical blocks indicated by the control frame sending position information;

[0054] The sending unit is used to send a control frame sending position message, which includes control frame sending position information; after sending the logic block containing the control frame sending position message, the control frame is sent after sending the first number of logic blocks.

[0055] The solution provided by this application allows the specific sending location of a control frame to be indicated by a control frame sending location message before the control frame is sent. This allows the receiving end to delimit the control frame without configuring a dedicated character header, thereby improving bandwidth utilization for data transmission. Even if control frames are only sent when they are needed, accurate delimitation of the control frame can be guaranteed. Therefore, while increasing the flexibility of control frame transmission, bandwidth utilization for data transmission is also improved.

[0056] In another possible implementation, the control frame is transmitted using an independent channel to ensure the integrity of its code type.

[0057] In another possible implementation, the control frame includes: a sequence frame used for clock locking in a channel training phase, or a logical layer training sequence 0.

[0058] In another possible implementation, the control frame includes: a sequence frame used for channel parameter tuning calculation in a channel training phase, or a logical layer training sequence 1.

[0059] In another possible implementation, the control frame includes: either a sequence frame for sending and receiving confirmation of synchronization status during the channel training phase, or a logical layer training sequence 2.

[0060] In another possible implementation, the control frame includes: a frame used to mark the end of channel data transmission, or a logical layer electrical idle frame.

[0061] In another possible implementation, the control frame includes: a frame used to mark the starting position of a new logical block, or a logical layer data start frame.

[0062] In another possible implementation, the control frame includes: a frame for delay detection, or a logical layer channel deviation elimination test frame.

[0063] In another possible implementation, the control frame includes: a frame for waking up, or a logical layer electrical idle exit frame.

[0064] In another possible implementation, the control frame includes: a frame for filling.

[0065] In another possible implementation, the code type of the control frame is fixed, that is, the content included in the control frame remains unchanged.

[0066] In another possible implementation, the control frame includes: the control frame includes one or more of the following: a frame header, or a payload.

[0067] The control frame is a sequence frame used for clock locking in the channel training phase, or a logical layer training sequence 0, and includes a payload.

[0068] Alternatively, the control frame is a sequence frame used for channel parameter tuning calculation in a channel training phase, or a logical layer training sequence 1, and the control frame includes a payload.

[0069] Alternatively, the control frame is a sequence frame used for sending and receiving confirmation of synchronization status during the channel training phase, or a logical layer training sequence 2. The control frame includes a frame header and a payload, and the frame header includes a frame type and a check field.

[0070] Alternatively, the control frame is a frame used to mark the end of channel data transmission, or a logical layer electrical idle frame. The control frame includes a frame header, and the frame header includes a frame type and a check field.

[0071] Alternatively, the control frame is a frame used to mark the start position of a new logic block, or a logical layer data start frame. The control frame includes a frame header, and the frame header includes a frame type and a check field.

[0072] Alternatively, the control frame is a frame used for delay detection, or a logical layer channel deviation elimination test frame. The control frame includes a frame header, and the frame header includes a frame type and a check field.

[0073] Alternatively, the control frame is a frame for waking up, or a logical layer electrical idle exit frame, and the control frame includes a payload.

[0074] Alternatively, the control frame is a frame used for padding, and the control frame includes a frame header and a payload, and the frame header includes a frame type and a check field.

[0075] In another possible implementation, the control frame is used to transmit link management and / or training sequence.

[0076] It should be noted that the device for transmitting control frames provided in the third aspect is used to implement the method for transmitting control frames provided in the above-mentioned first aspect or any possible implementation method. Its specific implementation can refer to the first aspect or any possible implementation method of the first aspect, and will not be repeated here.

[0077] In a fourth aspect, another apparatus for transmitting a control frame is provided, which may include a receiving unit and a decapsulation unit.

[0078] The receiving unit is configured to receive a logic block containing a control frame sending position message.

[0079] The decapsulation unit is used to unpack and deblock the logical block to obtain the control frame sending position information included in the control frame sending position message, where the control frame sending position information is used to indicate that after the current logical block is sent, the control frame is sent after sending a first number of logical blocks; the first number is the number of logical blocks indicated by the control frame sending position information; after the first number of logical blocks after the current logical block is sent, the control frame is parsed and obtained.

[0080] In another possible implementation, the control frame is transmitted using an independent channel to ensure the integrity of its code type.

[0081] In another possible implementation, the control frame includes: a sequence frame used for clock locking in a channel training phase, or a logical layer training sequence 0.

[0082] In another possible implementation, the control frame includes: a sequence frame used for channel parameter tuning calculation in a channel training phase, or a logical layer training sequence 1.

[0083] In another possible implementation, the control frame includes: either a sequence frame for sending and receiving confirmation of synchronization status during the channel training phase, or a logical layer training sequence 2.

[0084] In another possible implementation, the control frame includes: a frame used to mark the end of channel data transmission, or a logical layer electrical idle frame.

[0085] In another possible implementation, the control frame includes: a frame used to mark the starting position of a new logical block, or a logical layer data start frame.

[0086] In another possible implementation, the control frame includes: a frame for delay detection, or a logical layer channel deviation elimination test frame.

[0087] In another possible implementation, the control frame includes: a frame for waking up, or a logical layer electrical idle exit frame.

[0088] In another possible implementation, the control frame includes: a frame for filling.

[0089] In another possible implementation, the code type of the control frame is fixed, that is, the content included in the control frame remains unchanged.

[0090] In another possible implementation, the control frame includes: the control frame includes one or more of the following: a frame header, or a payload.

[0091] The control frame is a sequence frame used for clock locking in the channel training phase, or a logical layer training sequence 0, and includes a payload.

[0092] Alternatively, the control frame is a sequence frame used for channel parameter tuning calculation in a channel training phase, or a logical layer training sequence 1, and the control frame includes a payload.

[0093] Alternatively, the control frame is a sequence frame used for sending and receiving confirmation of synchronization status during the channel training phase, or a logical layer training sequence 2. The control frame includes a frame header and a payload, and the frame header includes a frame type and a check field.

[0094] Alternatively, the control frame is a frame used to mark the end of channel data transmission, or a logical layer electrical idle frame. The control frame includes a frame header, and the frame header includes a frame type and a check field.

[0095] Alternatively, the control frame is a frame used to mark the start position of a new logic block, or a logical layer data start frame. The control frame includes a frame header, and the frame header includes a frame type and a check field.

[0096] Alternatively, the control frame is a frame used for delay detection, or a logical layer channel deviation elimination test frame. The control frame includes a frame header, and the frame header includes a frame type and a check field.

[0097] Alternatively, the control frame is a frame for waking up, or a logical layer electrical idle exit frame, and the control frame includes a payload.

[0098] Alternatively, the control frame is a frame used for padding, and the control frame includes a frame header and a payload, and the frame header includes a frame type and a check field.

[0099] In another possible implementation, the control frame is used to transmit link management and / or training sequence.

[0100] It should be noted that the device for transmitting control frames provided in the fourth aspect is used to implement the transmission control frame method provided in the above-mentioned second aspect or any possible implementation method. Its specific implementation can refer to the first aspect or any possible implementation method of the first aspect, and will not be repeated here.

[0101] In a fifth aspect, a computing device is provided, which includes a memory and at least one processor, the memory being used to store a set of computer instructions; when the processor executes this set of computer instructions, the operations of the method described in the first aspect or the second aspect or any possible implementation method are performed.

[0102] In a sixth aspect, a data transmission system is provided, comprising a data transmitting device and / or a data receiving device. The data transmitting device is configured to execute the method for transmitting a control frame as described in the first aspect or any possible implementation of the first aspect, and the data receiving device is configured to execute the method for transmitting a control frame as described in the second aspect or any possible implementation of the first aspect. Alternatively, the data transmitting device includes the device for transmitting a control frame as described in the third aspect or any possible implementation of the third aspect, and the data receiving device includes the device for transmitting a control frame as described in the fourth aspect or any possible implementation of the fourth aspect.

[0103] In a seventh aspect, a chip is provided, comprising one or more interface circuits and one or more processors; the interface circuits are configured to receive signals from a memory of an electronic device and transmit the received signals to the processors, the signals comprising computer instructions stored in the memory. When the processors execute the computer instructions, the electronic device performs the steps of the method described in the first aspect, the second aspect, or any possible implementation.

[0104] In an eighth aspect, a computer-readable storage medium is provided, comprising: computer software instructions; when the computer software instructions are executed in a computer, the computer executes the operations of the method described in the first aspect or the second aspect or any possible implementation method.

[0105] In a ninth aspect, a computer program product, when running on a computer, enables the computer to execute the operating steps of the method described in the first aspect or the second aspect or any possible implementation method.

[0106] In a tenth aspect, a chip system is provided, which includes a processor and may also include a memory, for implementing the functions in the above method. The chip system can be composed of a chip or include a chip and other discrete devices.

[0107] The solutions provided in the third to tenth aspects are used to implement the methods provided in the first or second aspects, and therefore can achieve the same beneficial effects as the first or second aspects, and will not be repeated here.

[0108] It should be noted that various possible implementations of any of the above aspects can be combined under the premise that the solutions are not contradictory. BRIEF DESCRIPTION OF THE DRAWINGS

[0109] FIG1 is a schematic diagram of the architecture of a multimedia data transmission system provided in an embodiment of the present application;

[0110] FIG2 is a schematic diagram of the architecture of another multimedia data transmission system provided in an embodiment of the present application;

[0111] FIG3 is a schematic diagram of the structure of a computing device provided in an embodiment of the present application;

[0112] FIG4 is a schematic flow chart of a method for transmitting a control frame according to an embodiment of the present application;

[0113] FIG5 is a flow chart of another method for transmitting a control frame according to an embodiment of the present application;

[0114] FIG6 is a schematic diagram of a control frame structure provided by an embodiment of the present application;

[0115] FIG7a is a schematic diagram of a transmission bit sequence of data within a control frame provided by an embodiment of the present application;

[0116] FIG7 b is a schematic structural diagram of an LFSR provided in an embodiment of the present application;

[0117] FIG7 c is a schematic structural diagram of another LFSR provided in an embodiment of the present application;

[0118] FIG8 is a schematic diagram of an LLCF_PAD payload structure provided in an embodiment of the present application;

[0119] FIG9 is a schematic diagram of another LLCF_PAD payload structure provided in an embodiment of the present application;

[0120] FIG10 is a schematic structural diagram of an apparatus for transmitting a control frame according to an embodiment of the present application;

[0121] FIG11 is a schematic structural diagram of an apparatus for transmitting a control frame according to an embodiment of the present application;

[0122] FIG12 is a schematic structural diagram of a device for transmitting a control frame provided in an embodiment of the present application. DETAILED DESCRIPTION

[0123] In the embodiments of the present application, in order to clearly describe the technical solutions of the embodiments of the present application, words such as "first" and "second" are used to distinguish between identical or similar items with substantially the same functions and effects. Those skilled in the art will understand that words such as "first" and "second" do not limit the quantity or execution order, and words such as "first" and "second" do not necessarily mean different. There is no order of precedence or priority between the technical features described by "first" and "second".

[0124] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner to facilitate understanding.

[0125] In the embodiments of the present application, at least one can also be described as one or more, and multiple can be two, three, four or more, which is not limited in this application.

[0126] In addition, the network architecture and scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Ordinary technicians in this field can know that with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0127] Currently, control frames are usually sent periodically, and the receiving end delimits the control frames (i.e., determines which position is the control frame) based on the control frame period. This inevitably leads to the occupation of transmission bandwidth when there are no control frames to be transmitted, resulting in inflexible control frame transmission.

[0128] If control frames are sent only when needed, control frame transmission offers high flexibility. However, since control frames are not sent at fixed locations, a mechanism must be configured to support control frame delimitation on the receiving end. Therefore, a solution has emerged to distinguish service data from control frames using a header to support control frame delimitation on the receiving end. However, configuring a dedicated header still consumes data bandwidth, resulting in insufficient bandwidth utilization for data transmission.

[0129] Based on this, the present application provides a control frame transmission scheme that uses control frames to send location information to indicate the specific location of the next control frame to be transmitted. Based on this information, the peer end can delimit the control frame without configuring a dedicated header, thereby improving bandwidth utilization for data transmission. Even if control frames are only sent when they are needed, accurate delimitation of the control frame can be guaranteed. Therefore, while increasing the flexibility of control frame transmission, bandwidth utilization for data transmission is also improved.

[0130] The solutions provided by the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0131] FIG1 illustrates a multimedia data transmission system. As shown in FIG1 , the multimedia data transmission system may include a source device 101 and a sink device 102 .

[0132] The source device 101 and the sink device 102 may be connected directly or through a routing device (this scenario is not shown in FIG. 1 ).

[0133] In the multimedia data transmission system shown in FIG1 , a source device 101 transmits multimedia data to a sink device 102 .

[0134] In one scenario, source device 101 and sink device 102 are unified multimedia interconnect devices that deploy a unified multimedia interconnect interface. The multimedia data transmission system illustrated in Figure 1 implements data exchange between unified multimedia interconnect devices. For example, high-speed signal transmission between unified multimedia interconnect devices enables bidirectional audio and video transmission, meeting the audio and video transmission needs of devices such as televisions, computers, and mobile phones.

[0135] In one scenario, either the source device 101 or the sink device 102 is a unified multimedia interconnection device deployed with a unified multimedia interconnection interface, and the other is a third-party protocol device merged with the unified multimedia interconnection, realizing data interaction between the third-party protocol device and the unified multimedia interconnection device.

[0136] In one scenario, the source device 101 may be a set-top box device. The sink device 102 may be a device with a screen. For example, the set-top box device may obtain multimedia data from a data server via a network through a router, a switch, or other network devices.

[0137] Exemplarily, the set-top box device may also be called a digital video converter box (set top box, STB), or set-top box, or other. The set-top box device is a device that connects a multimedia player device and an external signal source. This application does not limit the specific product form of the set-top box device.

[0138] The sink device 102 may be a smart TV, tablet, smart screen, or other device for receiving and playing multimedia data. This application does not limit the specific product form of the sink device 102.

[0139] In one possible implementation, the internal architecture of the multimedia data transmission system shown in FIG1 may be as shown in FIG2 . As shown in FIG2 , the source device 101 and the sink device 102 include a router and a transceiver, and the router includes an adapter and a port.

[0140] The router uses the adapter to encapsulate the data generated by the external component into a unified multimedia interconnection message, forming a unified multimedia interconnection service flow and forwarding it to the port. The port then sends it to the router of the peer device. The peer device's router obtains the unified multimedia interconnection service flow restored by the port and forwards it to the adapter for processing. The adapter converts it into data and sends it to the external component.

[0141] For example, when the end device is a third-party protocol device, the adapter in the router can be a third-party protocol adapter. The third-party protocol adapter receives third-party protocol data from the third-party protocol component, encapsulates it into a tunnel message (specifically, a unified multimedia interconnection protocol message), forms a service flow, and sends it to the corresponding port, which then forwards it to the router of the opposite device. The router of the opposite device obtains the service flow restored by the port (such as the unified multimedia interconnection service flow) and forwards it to the corresponding third-party protocol adapter for processing. The third-party protocol adapter processes it into third-party protocol data and sends it to the third-party protocol component.

[0142] In one aspect, an embodiment of the present application provides a schematic structural diagram of a computing device 30. The computing device 30 can implement the functions of the source device 101 or the sink device 102 shown in FIG. 1 or FIG. 2 .

[0143] Exemplarily, the computing device 30 may implement the functions of the source device 101 or the sink device 102 illustrated in FIG. 1 or FIG. 2 at the logic layer.

[0144] 3 , the computing device 30 may include a processor 3010 , a bus 3020 , a memory 3030 , and a communication interface 3040 . The processor 3010 , the memory 3030 , and the communication interface 3040 are connected via the bus 3020 .

[0145] It should be understood that in this embodiment, the processor 3010 may be a central processing unit (CPU), or may be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0146] The processor 3010 may also be a graphics processing unit (GPU), a neural network processing unit (NPU), a microprocessor, an ASIC, or one or more integrated circuits for controlling the execution of the program of the present application.

[0147] The communication interface 3040 is used to implement communication between the computing device 30 and external devices or components.

[0148] The bus 3020 may include a path for transmitting information between the above-mentioned components (such as the processor 3010 and the memory 3030). In addition to the data bus, the bus 3020 may also include a power bus, a control bus, and a status signal bus. However, for the sake of clarity, various buses are labeled as bus 3020 in the figure. The bus 3020 may be a peripheral component interconnect express (PCIe) bus, an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a computer express link (CXL), a cache coherent interconnect for accelerators (CCIX), etc. The bus 3020 can be divided into an address bus, a data bus, a control bus, etc.

[0149] As an example, computing device 30 may include multiple processors. The processor may be a multi-core (multi-CPU) processor. A processor herein may refer to one or more devices, circuits, and / or computing units for processing data (e.g., computer program instructions).

[0150] It is worth noting that FIG3 only takes the computing device 30 including 1 processor 3010 and 1 memory 3030 as an example. Here, the processor 3010 and the memory 3030 are respectively used to indicate a type of device or equipment. In a specific embodiment, the number of each type of device or equipment can be determined according to business requirements.

[0151] Memory 3030 may be a volatile memory pool or a non-volatile memory pool, or may include both volatile and non-volatile memory. Non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0152] For example, the processor 3010 may perform the following functions by running or executing the software programs and / or modules stored in the memory 3030:

[0153] A control frame sending position message is sent, where the control frame sending position message includes control frame sending position information, where the control frame sending position information is used to indicate that after the current logical block is sent, the control frame will be sent after sending the first number of logical blocks; the first number is the number of logical blocks indicated by the control frame sending position information; after sending the logical block containing the control frame sending position message, the control frame will be sent after sending the first number of logical blocks.

[0154] On the other hand, an embodiment of the present application provides a method for transmitting a control frame, which is applied to a source device 101 or a sink device 102 in the multimedia data transmission system illustrated in FIG1 or 2 , or a chip in the source device 101 or a chip in the sink device 102, to implement the function of transmitting a control frame at a logical layer. The method can be executed by a computing device. The transmitting device described below can be the source device 101 or a chip therein, and the receiving device can be the sink device 102 or a chip therein.

[0155] The Logical Layer Control Frame (LLCF) is a code pattern used to implement link management functions such as link training and status update. It can also be called a Control Frame (CF).

[0156] For example, the control frame may be used to convey link management and / or training sequences.

[0157] In a possible implementation, the control frame is transmitted using an independent channel.

[0158] As shown in FIG4 , the method for transmitting a control frame provided in an embodiment of the present application may include:

[0159] S401. Send a control frame sending position message, where the control frame sending position message includes control frame sending position information. The control frame sending position information is used to indicate that the control frame should be sent after a first number of logic blocks are sent after the current logic block is sent.

[0160] The first number is the number of logic blocks indicated by the control frame sending position information.

[0161] Specifically, when link management is required through control frames, the upper layer of the logical layer of the computing device (which may be a transport layer or an adapter) determines the control frame sending position information to determine how many logical blocks after the current logical block the control frame is sent, that is, the control frame sending position information is used to indicate that after the current logical block is sent, the control frame will be sent after the first number of logical blocks are sent.

[0162] Afterwards, the logic layer constructs a control frame sending location message, which includes the control frame sending location information, fills the control frame sending location message into the logic block and sends it to the next layer in the protocol so that it can be transmitted to the receiving end, making it easier for the receiving end to obtain the control frame sending location information.

[0163] It should be understood that in S401, the computing device sends the control frame sending location message, which is to fill the control frame sending location message into the logic block and send it. The embodiment of the present application does not limit or elaborate on the filling process.

[0164] S402: After sending the logic block containing the control frame sending position message, send the control frame after sending the first number of logic blocks.

[0165] Specifically, the position where the control frame is sent must strictly match the position indicated by the control frame sending position information, that is, the control frame must be sent at the position indicated by the control frame sending position information.

[0166] For example, the control frame may be specifically designated by an upper layer of the logical layer. Different link management requirements correspond to different control frames.

[0167] Specifically, after sending the logic block containing the control frame sending position message in S401, the control frame indicated by the upper layer is sent after sending the first number of logic blocks.

[0168] The present application does not specifically limit the specific functions and names of control frames. For example, control frames may include but are not limited to any of the following:

[0169] 1) A sequence frame used for clock locking in the channel training phase, or a logical layer training sequence 0 (Control Frame, Training Sequence 0, LLCF_TS0).

[0170] 2) Sequence frame used for channel parameter tuning calculation in the channel training phase, or logical layer training sequence 1 (Control Frame, Training Sequence 1, LLCF_TS1)

[0171] 3) Used for sending and receiving sequence frames to confirm the synchronization status during the channel training phase, or logical layer training sequence 2 (Control Frame, Training Sequence 2, LLCF_TS2).

[0172] 4) A frame used to mark the end of channel data transmission, or a logical layer electrical idle (Control Frame, Electrical Idle, LLCF_EI) frame.

[0173] 5) A frame used to mark the starting position of a new logical block, or a logical layer data start (Control Frame, Data Start, LLCF_DS) frame.

[0174] 6) Frame used for delay detection, or logic layer channel deviation elimination test (Control Frame, De-Skew Test,) LLCF_DST frame.

[0175] 7) A frame used for wake-up, or a logical layer electrical idle exit (Control Frame, Electrical Idle, LLCF_EIE) frame.

[0176] 8) Frame LLCF_PAD used for padding.

[0177] Furthermore, the code type of the control frame is fixed.

[0178] Furthermore, the control frame structure may include one or more of the following: a frame header, or a payload.

[0179] Exemplarily, the control frame is a sequence frame used for clock locking in the channel training phase, or a logical layer training sequence 0, and the control frame includes a payload. Exemplarily, the payload of the control frame can be 0xAA of any length.

[0180] Alternatively, the control frame is a sequence frame used for channel parameter tuning calculation in the channel training phase, or a logical layer training sequence 1, and the control frame includes a payload. Exemplarily, the payload of the control frame can be a fixed sequence, and the embodiments of the present application do not limit the content of the sequence.

[0181] Alternatively, the control frame is a sequence frame used for transmitting and receiving synchronization confirmation during the channel training phase, or a logical layer training sequence 2. The control frame includes a frame header and a payload. The frame header includes a frame type and a checksum field. For example, the frame type field is 0x6C and the checksum field is 0x56. The payload may be a bit-flipped version of the logical layer training sequence 1.

[0182] Alternatively, the control frame is a frame used to mark the end of channel data transmission, or a logical layer electrical idle frame, and the control frame includes a frame header, which includes a frame type and a checksum field. For example, the frame type field is 0x65 and the checksum field is 0x69.

[0183] Alternatively, the control frame is a frame used to mark the start position of a new logical block, or a logical layer data start frame. The control frame includes a frame header, which includes a frame type and a checksum field. For example, the frame type field is 0x4B and the checksum field is 0xA3.

[0184] Alternatively, the control frame is a frame for delay detection, or a logical layer channel deviation elimination test frame, and the control frame includes a frame header, which includes a frame type and a checksum field. For example, the frame type field is 0x5A and the checksum field is 0xD4.

[0185] Alternatively, the control frame is a frame for waking up, or a logical layer electrical idle exit frame, and the control frame includes a payload.

[0186] Alternatively, the control frame is a frame used for padding, and the control frame includes a frame header, and the frame header includes a frame type and a checksum field. For example, the frame type field is 0xD2, and the checksum field is 0x65.

[0187] The solution provided by this application allows the specific sending location of a control frame to be indicated by a control frame sending location message before the control frame is sent. This allows the receiving end to delimit the control frame without configuring a dedicated character header, thereby improving bandwidth utilization for data transmission. Even if control frames are only sent when they are needed, accurate delimitation of the control frame can be guaranteed. Therefore, while increasing the flexibility of control frame transmission, bandwidth utilization for data transmission is also improved.

[0188] Furthermore, after the transmitting device executes the above-mentioned S401 and S402 to transmit the control frame, as shown in FIG5 , the method for transmitting the control frame provided in the present application may also include the process S403 to S405 of the receiving device receiving the control frame.

[0189] S403: The receiving device receives a logic block including a control frame sending position message.

[0190] Exemplarily, the logic block containing the control frame sending position message received by the receiving device in S403 may be the logic block sent by the transmitting device in S401, and details thereof will not be repeated here.

[0191] S404: The receiving end device unpacks and deblocks the logic block to obtain the control frame sending position information included in the control frame sending position message.

[0192] The control frame sending position information is used to indicate that after the current logic block is sent, the control frame is sent after sending a first number of logic blocks; the first number is the number of logic blocks indicated by the control frame sending position information.

[0193] The control frame sending position information has been described in detail in S401 and will not be repeated here.

[0194] S405 : After the first number of logical blocks after the current logical block ends, parse and obtain a control frame.

[0195] The current logic block refers to the logic block including the control frame sending position message received in S403.

[0196] Specifically, in S405, parsing and obtaining the control frame after the first number of logical blocks after the end of the current logical block can be understood as: starting from the position after the end of the current logical block and then parsing the first number of logical blocks, parsing and obtaining the control frame according to the frame structure of the control frame.

[0197] The following is an example of how the aforementioned control frame sends a location message.

[0198] The control frame send location message (CF Send Location Message, CFSLM) is an information parameter indicating the subsequent CF send location.

[0199] CFSLM can be used when the link is in the service transmission state. When the link state changes (such as link training, state switching, bandwidth adjustment, etc.), the sender needs to send CFSLM before sending CF. This allows the sender to send CF and the receiver to detect CF.

[0200] The communication between the sending end sending the CF and the receiving end detecting the CF refers to that the sending end sends the location of the CF to the receiving end through the CFSLM, so that the receiving end detects the CF according to the CFSLM.

[0201] Specifically, the location where the sender sends the CFSLM, the parameters within the CFSLM, and the subsequent CF sending location must match exactly. That is, after sending the LLB containing the CFSLM, and then sending the control frame send location information (CF Send Location, CF_SL) to specify the LLB, the CF must be sent.

[0202] Among them, CFSLM does not need to respond.

[0203] Specifically, CFSLM can only be transmitted through the main link (ML). Therefore, CFSLM is encapsulated as a logical layer main link management packet (LLMMP). For example, the arrangement format of the LLMMP corresponding to CFSLM (LLMMP obtained by encapsulating CFSLM) can be shown in Table 1.

[0204] Table 1

[0205] It should be noted that Table 1 is only an example to illustrate the arrangement format of LLMMP corresponding to CFSLM, and does not constitute a specific limitation.

[0206] The following is an example of the aforementioned control frame.

[0207] Control frames can be sent entirely on a single lane to convey information such as link management or training sequences. The logical layer management message CFSLM indicates the insertion position of a control frame. The control frame structure, as shown in Figure 6, includes the frame type, checksum, and optional payload.

[0208] The description of each field segment in the frame structure of the control frame can be shown in Table 2 below.

[0209] Table 2

[0210] In the control frame structure shown in FIG6 , the contents of frame header 1, frame header 2, and frame header 3 are identical, forming a repetitive code.

[0211] Unless otherwise specified, control frames (header + payload) are not scrambled or pre-coded.

[0212] For example, the control frames of the logic layer are summarized as shown in Table 3. Table 3 illustrates the specific fields of each domain segment in the frame structure of various control frames involved in the logic layer.

[0213] Table 3

[0214] For example, the transmission bit order of data within a control frame can be shown in Figure 7a. The transmission bit order of the control frame is consistent with the bit order on the line (link). The least significant bit (LSB) indicates the starting position of a byte in the control frame, and the most significant bit (MSB) indicates the ending position of a byte in the control frame.

[0215] For example, for a constant value, such as 0xABCD, 0xAB is the first byte received, that is, B0; 0xCD is the last byte received, that is, B1.

[0216] This application provides the following control frames, and examples of each control frame are given below.

[0217] 1. LLCF_TS0

[0218] LLCF_TS0 is used for clock locking during the training phase, and the payload is 0xAA of any length.

[0219] 2. LLCF_TS1

[0220] LLCF_TS1 is used for channel parameter tuning calculations during the training phase. The payload is a PRBS11 sequence of arbitrary length. The polynomial is G(x) = x 11 +x 2+1, seed: 00110011001b, the corresponding linear feedback shift register (LFSR) is shown in Figure 7b.

[0221] The PRBS sequence is continuously generated, and the generated bit sequence is consistent with the bit sequence sent on the line. The first few groups of 64-bit binary bit sequences are shown in Table 4 below.

[0222] Table 4

[0223] 3. LLCF_TS2

[0224] LLCF_TS2 is used to confirm the synchronization status of transmission and reception. The LLCF_TS2 length is fixed at 8 bytes, and the payload is the bit-reversed PRBS11 sequence.

[0225] The LLCF_TS2 polynomial is G(x) = x11 + x2 + 1, and the seed is 00110011001b. The corresponding LFSR is shown in Figure 7c. The PRBS sequence is continuously generated, and the generated bit sequence is consistent with the bit sequence sent on the line.

[0226] The binary bit sequences of the first several groups of 64 bits are shown in Table 5 below.

[0227] Table 5

[0228] 4. LLCF_EI

[0229] LLCF_EI is used to mark the end of transmission in this lane. The subsequent data should be discarded. The lane that stops receiving data will restart data reception after being re-enabled. This control frame has no payload.

[0230] It should be noted that the specific LLCF_EI sending time and lane restart control process are not limited in the embodiments of this application.

[0231] 5. LLCF_DS

[0232] LLCF_DS marks the start of a new LLB. LLB data is transmitted immediately following LLCF_DS. This control frame has no payload.

[0233] The transmitter should transmit LLCF_DS simultaneously on all valid lanes during the first transmission or when switching lane numbers (including due to low power consumption or other reasons). In non-delay correction scenarios, the skew of LLCF_DS on the line should be less than Ttx_skew (skew threshold).

[0234] LLCF_DS should be sent simultaneously on all valid lanes.

[0235] 6. LLCF_DST

[0236] LLCF_DST is used for delay measurement. This control frame has no payload.

[0237] 7. LLCF_EIE

[0238] LLCF_EIE is used by the transmitter to wake up the high-speed link. The payload length of LLCF_EIE can be configured according to actual needs.

[0239] 8. LLCF_PAD

[0240] This control frame is used for padding. It is allowed only after the link is established and before LLB transmission. It is not allowed after the LLB is transmitted. The receiving end discards this control frame upon receipt.

[0241] The LLCF_PAD payload is variable length, and its structure is shown in Figure 8. As shown in Figure 8, the LLCF_PAD payload begins with the padding byte 0x0F, continues to send these padding bytes until the end, sends the end indicator byte 0xF0 at the end of the padding, and finally sends the 2-byte CRC result calculated on the padding and end indicator.

[0242] Here, the CRC calculation method and the corresponding generator polynomial of CRC are: g(x)=x 16 +x 12 +x 5 +1.

[0243] In the payload check shown in FIG8 , excluding the payload check, the remaining payload length is less than 32 bytes.

[0244] The end indicator byte can be sent directly in LLCF_PAD without sending the padding byte. In this case, the CRC is calculated only for the end indicator byte. The frame structure of LLCF_PAD in the above case is shown in Figure 9, without the padding byte.

[0245] The LLCF_PAD control frame is used to adjust the skew deviation between different channels when both the sending and receiving negotiation support the delay measurement feature. In the link width adjustment scenario, it is sent on the channel where service transmission is restored to ensure that all channels send LLCF_DS synchronously.

[0246] The above mainly introduces the solution provided by the embodiment of the present invention from the perspective of the working principle of the computing device. It can be understood that in order to realize the above functions, the computing device, etc. includes hardware structures and / or software modules corresponding to the execution of each function. It should be easy for those skilled in the art to realize that, in combination with the units and algorithm steps of each example described in the embodiments disclosed herein, the present invention can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0247] In the embodiments of the present invention, computing devices, etc., can be divided into functional modules according to the above-described method examples. For example, functional modules can be divided according to respective functions, or two or more functions can be integrated into a single processing module. The above-described integrated modules can be implemented in the form of hardware or software functional modules. It should be noted that the module division in the embodiments of the present invention is illustrative and is merely a logical functional division. In actual implementation, other division methods may be used.

[0248] In the case of dividing each functional module according to each function, Figure 10 illustrates a device 100 for transmitting a control frame provided in an embodiment of the present application, and the device 100 for transmitting a control frame is used to implement the functions of the computing device in the above-mentioned method embodiment. As shown in Figure 10, the device 100 for transmitting a control frame may include: a determination unit 1001 and a sending unit 1002. The determination unit 1001 is used to control the frame sending position information; the sending unit 1002 is used to execute processes S401 and S402 in Figure 4. Among them, all relevant contents of each step involved in the above-mentioned method embodiment can be referred to the functional description of the corresponding functional module and will not be repeated here.

[0249] In the case of dividing each functional module according to each function, Figure 11 illustrates another device 110 for transmitting a control frame provided in an embodiment of the present application. The device 110 for transmitting a control frame is used to implement the function of the receiving device in the above-mentioned method embodiment. As shown in Figure 11, the device 110 for transmitting a control frame may include: a receiving unit 1101 and a decapsulation unit 1102. The determination unit 1001 is used to execute the process S403 in Figure 4; the decapsulation unit 1102 is used to execute the processes S404 and S405 in Figure 4. Among them, all relevant contents of each step involved in the above-mentioned method embodiment can be referred to the functional description of the corresponding functional module and will not be repeated here.

[0250] In another possible implementation, the control frame is transmitted using an independent channel to ensure the integrity of its code type.

[0251] In another possible implementation, the control frame includes: a sequence frame used for clock locking in a channel training phase, or a logical layer training sequence 0.

[0252] In another possible implementation, the control frame includes: a sequence frame used for channel parameter tuning calculation in a channel training phase, or a logical layer training sequence 1.

[0253] In another possible implementation, the control frame includes: either a sequence frame for sending and receiving confirmation of synchronization status during the channel training phase, or a logical layer training sequence 2.

[0254] In another possible implementation, the control frame includes: a frame used to mark the end of channel data transmission, or a logical layer electrical idle frame.

[0255] In another possible implementation, the control frame includes: a frame used to mark the starting position of a new logical block, or a logical layer data start frame.

[0256] In another possible implementation, the control frame includes: a frame for delay detection, or a logical layer channel deviation elimination test frame.

[0257] In another possible implementation, the control frame includes: a frame for waking up, or a logical layer electrical idle exit frame.

[0258] In another possible implementation, the control frame includes: a frame for filling.

[0259] In another possible implementation, the code type of the control frame is fixed, that is, the content included in the control frame remains unchanged.

[0260] In another possible implementation, the control frame includes: the control frame includes one or more of the following: a frame header, or a payload.

[0261] The control frame is a sequence frame used for clock locking in the channel training phase, or a logical layer training sequence 0, and includes a payload.

[0262] Alternatively, the control frame is a sequence frame used for channel parameter tuning calculation in a channel training phase, or a logical layer training sequence 1, and the control frame includes a payload.

[0263] Alternatively, the control frame is a sequence frame used for sending and receiving confirmation of synchronization status during the channel training phase, or a logical layer training sequence 2. The control frame includes a frame header and a payload, and the frame header includes a frame type and a check field.

[0264] Alternatively, the control frame is a frame used to mark the end of channel data transmission, or a logical layer electrical idle frame. The control frame includes a frame header, and the frame header includes a frame type and a check field.

[0265] Alternatively, the control frame is a frame used to mark the start position of a new logic block, or a logical layer data start frame. The control frame includes a frame header, and the frame header includes a frame type and a check field.

[0266] Alternatively, the control frame is a frame used for delay detection, or a logical layer channel deviation elimination test frame. The control frame includes a frame header, and the frame header includes a frame type and a check field.

[0267] Alternatively, the control frame is a frame for waking up, or a logical layer electrical idle exit frame, and the control frame includes a payload.

[0268] Alternatively, the control frame is a frame used for padding, and the control frame includes a frame header and a payload, and the frame header includes a frame type and a check field.

[0269] In another possible implementation, the control frame is used to transmit link management and / or training sequence.

[0270] In the case of adopting an integrated unit, as shown in Figure 12, the device 120 for transmitting control frames provided in an embodiment of the present application is used to implement the functions of the computing device or receiving device in the above-mentioned embodiment. The device 120 for transmitting control frames includes a processing module 1201 and a communication module 1202. The processing module 1201 is used to control and manage the actions of the device 120 for transmitting control frames, and the communication module 1202 is used to communicate with other devices. For example, the processing module 1201 is used to execute any of the processes S401-S405 in Figure 4; the communication module 1202 is used for the device 120 for transmitting control frames to interact with other devices. The device 120 for transmitting control frames may also include a storage module 1203 for storing program code and data of the device 120 for transmitting control frames.

[0271] The processing module 1201 may be the processor 3010 in the physical structure of the computing device 30 shown in FIG3 , and may be a processor or controller. For example, it may be a CPU, a general-purpose processor, a DSP, an ASIC, an FPGA, or other programmable logic device, a transistor logic device, a hardware component, or any combination thereof. It may implement or execute the various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this application. The processing module 1201 may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, and so on. The communication module 1202 may be the communication interface 3040 in the physical structure of the computing device 30 shown in FIG3 . The communication module 1202 may be a communication port, or may be a transceiver, a transceiver circuit, or a communication interface. Alternatively, the communication interface may communicate with other devices through the aforementioned transceiver components. The transceiver components may be implemented by antennas and / or radio frequency devices. The storage module 1203 may be the memory 3030 in the physical structure of the computing device 30 shown in FIG3 .

[0272] As mentioned above, the apparatus 100 for transmitting control frames, the apparatus 110 for transmitting control frames, and the apparatus 120 for transmitting control frames provided in the embodiments of the present application can be used to implement the functions of the computing device or the receiving device in the above-mentioned embodiments of the present application. For ease of explanation, only the parts related to the embodiments of the present application are shown. For specific technical details not disclosed, please refer to the embodiments of the present application.

[0273] On the other hand, an embodiment of the present application provides a data transmission system, including the above-mentioned device 100 for transmitting a control frame and / or the device 110 for transmitting a control frame.

[0274] On the other hand, an embodiment of the present application provides a data transmission system, including a data sending device and / or a data receiving device, the data sending device is used to perform the functions of the sending end device in the above method embodiment, and the data receiving device is used to perform the functions of the receiving end device in the above method embodiment.

[0275] As another form of this embodiment, a computer-readable storage medium is provided, on which instructions are stored. When the instructions are executed, the method for transmitting a control frame in the above method embodiment is executed.

[0276] As another form of this embodiment, a computer program product containing instructions is provided. When the computer program product is run on a computer, the computer is caused to execute the method for transmitting a control frame in the above method embodiment.

[0277] As another form of this embodiment, a chip is provided, comprising one or more interface circuits and one or more processors. The interface circuits are configured to receive signals from a memory of an electronic device and transmit the received signals to the processors, the signals comprising computer instructions stored in the memory. When the processors execute the computer instructions, the electronic device performs the operational steps of the method described in the first aspect or any possible implementation.

[0278] The embodiment of the present application further provides a chip system, which includes a processor for implementing the technical method of the embodiment of the present application. In one possible design, the chip system also includes a memory for storing the necessary program instructions and / or data of the embodiment of the present invention. In one possible design, the chip system also includes a memory for the processor to call the application code stored in the memory. The chip system can be composed of one or more chips, or can include chips and other discrete devices, which is not specifically limited in the embodiment of the present application.

[0279] Those skilled in the art will readily appreciate that, in conjunction with the various exemplary units and method steps described in the embodiments disclosed herein, this application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in hardware or in a hardware-driven manner by computer software depends on the specific application scenario and design constraints of the technical solution.

[0280] The above embodiments can be implemented in whole or in part by software, hardware, firmware or any other combination. When implemented using software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, the process or function described in the embodiment of the present application of the present invention is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more available media sets. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium. The semiconductor medium can be an SSD.

[0281] The above is only a specific embodiment of the present application, but the scope of protection of this application is not limited to this. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A method for transmitting a control frame, characterized in that, the method comprises: sending a control frame transmission position message, the control frame transmission position message including control frame transmission position information for indicating that after the current logical block transmission ends, the control frame is transmitted after transmitting a first number of logical blocks; the first number being the number of logical blocks indicated by the control frame transmission position information; after transmitting the logical block containing the control frame transmission position message, transmitting the control frame after transmitting the first number of logical blocks.

2. The method according to claim 1, characterized in that, the control frame is transmitted using an independent channel.

3. The method according to claim 1 or 2, characterized in that, the control frame includes one or more of the following: a sequence frame for clock locking in the channel training phase, or, logical layer training sequence 0; or, a sequence frame for channel parameter tuning calculation in the channel training phase, or, logical layer training sequence 1; or, a sequence frame for transceiver confirmation synchronization status in the channel training phase, or, logical layer training sequence 2; or, a frame for marking the end of channel data transmission, or, logical layer electrical idle frame; or, a frame for marking the start position of a new logical block, or, logical layer data start frame; or, a frame for delay detection, or, logical layer channel deviation cancellation test frame; or, a frame for wake-up, or, logical layer electrical idle exit frame; or, a frame for padding.

4. The method according to claim 3, characterized in that, the control frame includes one or more of the following: a frame header, or, a payload; wherein: when the control frame is a sequence frame for clock locking in the channel training phase, or, logical layer training sequence 0, the control frame includes a payload; or, when the control frame is a sequence frame for channel parameter tuning calculation in the channel training phase, or, logical layer training sequence 1, the control frame includes a payload; or, when the control frame is a sequence frame for transceiver confirmation synchronization status in the channel training phase, or, logical layer training sequence 2, the control frame includes a frame header and a payload, and the frame header includes a frame type and a check field; or, when the control frame is a frame for marking the end of channel data transmission, or, logical layer electrical idle frame, the control frame includes a frame header, and the frame header includes a frame type and a check field; or, when the control frame is a frame for marking the start position of a new logical block, or, logical layer data start frame, the control frame includes a frame header, and the frame header includes a frame type and a check field; or, when the control frame is a frame for delay detection, or, logical layer channel deviation cancellation test frame, the control frame includes a frame header, and the frame header includes a frame type and a check field; or, when the control frame is a frame for wake-up, or, logical layer electrical idle exit frame, the control frame includes a payload; or, when the control frame is a frame for padding, the control frame includes a frame header and a payload, and the frame header includes a frame type and a check field.

5. The method according to any one of claims 1-4, characterized in that, the control frame is used to transfer link management, and / or, training sequences.

6. A device for transmitting control frames, characterized in that, the device comprises: a determination unit, configured to determine control frame transmission position information, where the control frame transmission position information is used to indicate that after the current logical block is sent, the control frame is sent after sending a first number of logical blocks; the first number is the number of logical blocks indicated by the control frame transmission position information; a transmission unit, configured to transmit a control frame transmission position message, where the control frame transmission position message includes the control frame transmission position information; the transmission unit is further configured to, after sending the logical block containing the control frame transmission position message, send the control frame after sending the first number of logical blocks.

7. The device according to claim 6, characterized in that, the control frame is transmitted using an independent channel.

8. The device according to claim 6 or 7, characterized in that, the control frame includes: a sequence frame for clock locking in the channel training phase, or, logical layer training sequence 0; or, a sequence frame for channel parameter tuning calculation in the channel training phase, or, logical layer training sequence 1; or, a sequence frame for transceiver confirmation synchronization status in the channel training phase, or, logical layer training sequence 2; or, a frame for marking the end of channel data transmission, or, logical layer electrical idle frame; or, a frame for marking the start position of a new logical block, or, logical layer data start frame; or, a frame for delay detection, or, logical layer channel deviation cancellation test frame; or, a frame for wake-up, or, logical layer electrical idle exit frame; or, a frame for padding.

9. The device according to claim 8, characterized in that, the control frame includes one or more of the following: a frame header, or, a payload; where: the control frame is a sequence frame for clock locking in the channel training phase, or, logical layer training sequence 0, and the control frame includes a payload; or, the control frame is a sequence frame for channel parameter tuning calculation in the channel training phase, or, logical layer training sequence 1, and the control frame includes a payload; or, the control frame is a sequence frame for transceiver confirmation synchronization status in the channel training phase, or, logical layer training sequence 2, and the control frame includes a frame header and a payload, and the frame header includes a frame type and a check field; or, the control frame is a frame for marking the end of channel data transmission, or, logical layer electrical idle frame, and the control frame includes a frame header, and the frame header includes a frame type and a check field; or, the control frame is a frame for marking the start position of a new logical block, or, logical layer data start frame, and the control frame includes a frame header, and the frame header includes a frame type and a check field; or, the control frame is a frame for delay detection, or, logical layer channel deviation cancellation test frame, and the control frame includes a frame header, and the frame header includes a frame type and a check field; or, the control frame is a frame for wake-up, or, logical layer electrical idle exit frame, and the control frame includes a payload; or, the control frame is a frame for padding, and the control frame includes a frame header and a payload, and the frame header includes a frame type and a check field.

10. The method according to any one of claims 6 - 9, wherein, the control frame is used to transmit link management and / or training sequences.

11. A computing device, wherein, the computing device includes a memory and at least one processor, and the memory is used to store a set of computer instructions; when the processor executes the set of computer instructions, the operation steps of the method according to any one of claims 1 - 5 above are executed.

12. A data transmission system, wherein, the data transmission system includes a data sending device, and the data sending device is used to execute the method for transmitting data packets according to any one of claims 1 - 5.

13. A chip, wherein, it includes one or more interface circuits and one or more processors; the interface circuit is used to receive a signal from the memory of the electronic device and send the signal to the processor, and the signal includes computer instructions stored in the memory; when the processor executes the computer instructions, the electronic device is caused to execute the operations of the method according to any one of claims 1 - 5.

14. A computer - readable storage medium, wherein, it includes: computer software instructions; when the computer software instructions run on a computer, the computer is caused to execute the operation steps of the method according to any one of claims 1 - 5 above.

15. A computer program product, wherein, the computer program product contains a software program, and when the software program is executed by a computer or a processor, the computer or the processor is caused to execute the operation steps of the method according to any one of claims 1 - 5.

Images