Three-dimensional FPGA chiplet packaging structure

Abstract

The present application relates to the technical field of chip packaging, and particularly relates to a three-dimensional FPGA chiplet packaging structure. The three-dimensional FPGA chiplet packaging structure provided in the present application comprises: several FPGA packaging modules arranged in a stacked manner, wherein each FPGA packaging module is provided with FPGA chips and micro-bump structures for interconnection, the elements and micro-bump structures in each FPGA packaging module are in the same topological layout, in adjacent FPGA packaging modules, the layouts of at least some of the micro-bump structures overlap, and the FPGA chips in the adjacent FPGA packaging modules are interconnected by means of the micro-bump structures at overlapping positions; and a connecting substrate, which is used for the placement of the stacked FPGA packaging modules and is also used for implementing outward signal transmission of the FPGA packaging modules. By means of the three-dimensional FPGA chiplet packaging structure provided in the present application, the capacity of FPGA chiplets per unit area can be increased, and the performance of the FPGA chiplets is improved.

Description

A FPGA three-dimensional chip packaging structure

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on December 1, 2023, with application number 202311639166.3 and invention name “A Three-Dimensional FPGA Chip Packaging Structure”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of chip packaging technology, and in particular to a FPGA three-dimensional chip packaging structure. Background Art

[0004] The capacity of an FPGA (Field Programmable Gate Array) chip is limited by the number of Configurable Logic Blocks (CLBs). The number of CLBs in an FPGA chip of the same area is, in turn, limited by power consumption, area, pin count, and packaging process. Future high-performance applications will require FPGAs with high capacity to process more data. However, existing FPGA packaging structures are limited by the number of CLBs per unit area, preventing capacity expansion and, consequently, performance improvements.

[0005] Therefore, a solution is needed that can accommodate more CLBs per unit area of ​​FPGA chips, thereby achieving a breakthrough in capacity and improving performance.

[0006] Summary of the Invention

[0007] In order to solve the above problems, the present application provides an FPGA three-dimensional chip packaging structure to solve the problem that the FPGA chip capacity is limited by the number of CLBs, the capacity is difficult to break through, and the performance is difficult to improve.

[0008] The present application provides an FPGA three-dimensional core packaging structure, comprising: a plurality of stacked FPGA packaging modules, each of which is provided with an FPGA chip and a micro-bump structure for interconnection; the components and the micro-bump structure in each of the FPGA packaging modules have the same topological layout; in the FPGA packaging modules of adjacent layers, at least part of the micro-bump structure layout overlaps, and the FPGA chips in adjacent FPGA packaging modules are interconnected via the micro-bump structures in the overlapping positions; and a connecting substrate for arranging the stacked FPGA packaging modules and realizing external signal transmission of each of the FPGA packaging modules.

[0009] Optionally, the FPGA packaging modules are stacked in such a manner that the FPGA packaging modules are completely overlapped, and the projection patterns of the FPGA packaging modules of different layers on the connecting substrate are completely overlapped.

[0010] Optionally, the stacking manner of the FPGA packaging modules is: the FPGA packaging modules in adjacent layers are partially staggered and partially overlapped after being horizontally rotated 180°; the FPGA packaging modules in adjacent layers are interconnected through micro-bump structures at overlapping positions.

[0011] Optionally, the connecting substrate includes a main substrate and an elevated substrate; the elevated substrate is stacked on part of the main substrate; the FPGA packaging module that is not directly connected to the main substrate has a non-overlapping area; the elevated substrate at least partially corresponds to the non-overlapping area in the FPGA packaging module that is not directly connected to the main substrate, and is electrically connected to the FPGA packaging module at the corresponding position.

[0012] Optionally, the distance between the main substrate and the directly connected FPGA packaging module is a first distance; the distance between the elevated substrate and the not directly connected FPGA packaging module is a second distance; the first distance and the second distance are the same.

[0013] Optionally, the heightened substrate is provided with an I / O interface, and the I / O interface is electrically connected to the non-overlapping area.

[0014] Optionally, the FPGA packaging module includes a packaging substrate, which has an overlapping area for setting the overlapping interconnected micro-bump structure; the packaging substrate has a front connection opening facing the micro-bump structure and a back connection opening on the surface of the side facing away from the micro-bump structure at a position directly opposite the micro-bump structure below the overlapping area; the front connection opening and the corresponding back connection opening are electrically connected; the front connection opening is connected to the micro-bump structure, and the back connection opening is suitable for connecting to the micro-bump structure at a corresponding position in the FPGA packaging module below.

[0015] Optionally, the connecting substrate is provided with a connecting line and a docking interface, and the docking interface is used to connect with the stacked FPGA packaging modules to realize external signal transmission of each FPGA packaging module through the connecting line; the FPGA packaging module includes a first FPGA packaging module and a second FPGA packaging module; the second FPGA packaging module is stacked above the first FPGA packaging module, and in the first FPGA packaging module, the back connection opening located in the overlapping area is electrically connected to the docking interface at the corresponding position on the connecting substrate.

[0016] Optionally, the connecting substrate is provided with a substrate micro-bump structure, and the substrate micro-bump structure is provided corresponding to the docking interface, is connected one-to-one with the docking interface, and is suitable for electrical connection with the back connection opening in the FPGA packaging module above.

[0017] Optionally, the FPGA packaging module includes an Xbar interconnection switch, and the Xbar interconnection switches in the FPGA packaging modules of adjacent layers are interconnected through the micro-bump structure in the overlapping area.

[0018] The FPGA three-dimensional core packaging structure provided in this application includes several stacked FPGA packaging modules. The FPGA chips in adjacent layers of the FPGA packaging modules are interconnected via overlapping micro-bump structures. This enables interconnection between the stacked FPGA chips, enabling three-dimensional stacked packaging of FPGA chips, increasing the number of CLBs per unit area of ​​the FPGA core, increasing the capacity of the FPGA core per unit area, and improving the performance of the FPGA core. Compared with the method of packaging first and then stacking, in which different FPGA chips are stacked and packaged using wire bonding and TSV vias, the process has fewer steps. The wire bonding method is prone to problems such as wire breakage or uneven soldering, resulting in low yield. The micro-bump structure is more stable and has a higher yield. Compared with the wire bonding method, the wire bonding-TSV process product has more windings and is difficult to test when transmission problems occur. The micro-bump array connection method can more easily determine which specific layer of chip has a problem. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0020] FIG1 is a schematic structural diagram of an FPGA three-dimensional chip packaging structure according to an embodiment of the present application;

[0021] FIG2 is a schematic diagram of a first FPGA packaging module and a second FPGA packaging module in the FPGA three-dimensional core packaging structure of FIG1 ;

[0022] FIG3 is a schematic structural diagram of an FPGA three-dimensional chip packaging structure according to another embodiment of the present application;

[0023] FIG4 is a schematic diagram of a first FPGA packaging module and a second FPGA packaging module in the FPGA three-dimensional core packaging structure of FIG1 ;

[0024] FIG5 is a schematic diagram showing the connection relationship between the Xbar interconnection switch in the first FPGA packaging module and the Xbar interconnection switch in the second FPGA packaging module in the FPGA three-dimensional core packaging structure according to an embodiment of the present application. DETAILED DESCRIPTION

[0025] In order to solve the problem that the capacity of FPGA core particles is limited by the number of CLBs, which makes it difficult to increase the capacity and improve the performance, the present application provides an FPGA three-dimensional core particle packaging structure.

[0026] The present application provides an FPGA three-dimensional core packaging structure, comprising: a plurality of stacked FPGA packaging modules, each of which is provided with an FPGA chip and a micro-bump structure for interconnection; the components and the micro-bump structure in each of the FPGA packaging modules have the same topological layout; in the FPGA packaging modules of adjacent layers, at least part of the micro-bump structure layout overlaps, and the FPGA chips in adjacent FPGA packaging modules are interconnected via the micro-bump structures in the overlapping positions; and a connecting substrate for arranging the stacked FPGA packaging modules and realizing external signal transmission of each of the FPGA packaging modules.

[0027] The FPGA three-dimensional chip packaging structure provided in this application can effectively increase the number of CLBs in the FPGA chip per unit area, thereby increasing the capacity of the FPGA and improving the performance of the FPGA.

[0028] The following will clearly and completely describe the technical solution of this application in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0029] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this application and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0030] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0031] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0032] Example

[0033] With reference to FIG1-FIG5, the present application provides an FPGA three-dimensional chip packaging structure, including:

[0034] A plurality of stacked FPGA packaging modules are provided, each of which is provided with an FPGA chip and a micro-bump structure for interconnection; the topological layout of the components and the micro-bump structure in each of the FPGA packaging modules is the same.

[0035] In adjacent layers of the FPGA packaging modules, at least some of the microbump structures overlap. The FPGA chips in the adjacent FPGA packaging modules are interconnected via the overlapping microbump structures. The connecting substrate is used to arrange the stacked FPGA packaging modules and facilitate external signal transmission between the FPGA packaging modules. Each FPGA packaging module can be considered a CLB.

[0036] The FPGA three-dimensional core packaging structure provided in this embodiment includes several stacked FPGA packaging modules. The FPGA chips in adjacent layers of the FPGA packaging modules are interconnected via overlapping micro-bump structures. This enables interconnection between the stacked FPGA chips, enabling three-dimensional stacked packaging of FPGA chips, increasing the number of CLBs per unit area of ​​the FPGA core, increasing the capacity of the FPGA core per unit area, and improving the performance of the FPGA core. Compared with the method of packaging first and then stacking, in which different FPGA chips are stacked and packaged using wire bonding and TSV vias, the process has fewer steps. The wire bonding method is prone to problems such as wire breakage or uneven soldering, resulting in low yield. The micro-bump structure is more stable and has a higher yield. Compared with the wire bonding method, the wire bonding-TSV process product has more windings and is difficult to test when transmission problems occur. The micro-bump array connection method can more easily determine which specific layer of chip has a problem.

[0037] Specifically, referring to Figures 1-2 or Figures 3-4, the FPGA packaging module includes a packaging substrate (e.g., 211, 221 in Figure 1), and a micro-bump structure (e.g., 213, 223 in Figure 1) is connected to the FPGA chip through a connection line in the packaging substrate (not shown in the figure). The packaging substrate has an overlapping area for arranging the overlapping and interconnected micro-bump structures (black blocks in Figure 1 and circles in Figure 2). The packaging substrate located below the micro-bump structure in the overlapping area has a front connection opening facing the micro-bump structure (e.g., 2111, 2211 in Figure 1) and a back connection opening on the surface facing away from the micro-bump structure (e.g., 2112, 2212 in Figure 1, not shown in the figure); the front connection opening is electrically connected to the corresponding back connection opening; the front connection opening is connected to the micro-bump structure, and the back connection opening is suitable for connecting to the micro-bump structure at a corresponding position in the FPGA packaging module below.

[0038] Furthermore, the connection substrate 100 is provided with a connection line and a docking interface (not shown in the figure), and the docking interface is used to connect with the stacked FPGA packaging modules to realize external signal transmission of each FPGA packaging module through the connection line.

[0039] The electrical connection between the front connection opening and the corresponding back connection opening may be achieved through direct connection, for example, by means of a TSV through-hole, or may be achieved through a non-direct connection via a wiring inside the package substrate.

[0040] Furthermore, the connecting substrate is provided with a substrate micro-bump structure, and the substrate micro-bump structure is provided corresponding to the docking interface, is connected one-to-one with the docking interface, and is suitable for electrical connection with the back connection opening in the FPGA packaging module above.

[0041] With reference to Figures 1-2 or 3-4, the FPGA packaging module includes a first FPGA packaging module 210 and a second FPGA packaging module 220. The second FPGA packaging module 220 is stacked above the first FPGA packaging module 210. In the first FPGA packaging module 210, the back connection opening 2112 located in the overlapping area is electrically connected to the docking interface at the corresponding position on the connection substrate. In the embodiments of Figures 1-2 or 3-4, the stacked FPGA packaging module only includes the first FPGA packaging module 210 and the second FPGA packaging module 220. In other embodiments, more FPGA packaging modules stacked in this manner may also be included.

[0042] Furthermore, the connecting substrate is provided with a substrate micro-bump structure, and the substrate micro-bump structure is provided corresponding to the docking interface, is connected one-to-one with the docking interface, and is suitable for electrical connection with the back connection opening in the FPGA packaging module above.

[0043] In different embodiments, there are multiple options for stacking FPGA packaging modules.

[0044] For example, referring to Figures 1 and 2, in some embodiments, the FPGA packaging modules are stacked in such a manner that the FPGA packaging modules completely overlap, and the projections of the FPGA packaging modules of different layers on the connection substrate completely overlap. That is, the first FPGA packaging module 210 and the second FPGA packaging module 220 completely overlap, and the projections of the first FPGA packaging module 210 and the second FPGA packaging module 220 on the connection substrate 100 completely overlap. The A in Figure 2 is only for indicating the orientation of the packaging modules and is not intended to indicate a specific technical feature.

[0045] In this manner, the first FPGA packaging module 210 includes a first packaging substrate 211, on which is disposed a first FPGA chip 212 and a first microbump structure 213 arranged in an array for interconnection. Furthermore, a front connection opening 2111 facing the first microbump structure 213 and a back connection opening 2112 on the side facing away from the first microbump structure 213 are provided on the first packaging substrate 211, directly opposite the first microbump structure 213 on the first packaging substrate 211. The second FPGA packaging module 220 includes a second packaging substrate 221, on which is disposed a second FPGA chip 222 and a second microbump structure 223 for interconnection. At the same time, the second packaging substrate 221 below the second micro-bump structure 223 on the second packaging substrate 221 has a front connection opening 2211 facing the second micro-bump structure 223 and a back connection opening 2212 on the surface of the side facing away from the second micro-bump structure 223; the front connection openings 2111, 2211 and the corresponding back connection openings 2112, 2212 are electrically connected; the front connection openings 2111, 2211 are connected to the corresponding micro-bump structures 213, 223; the back connection opening 2212 on the second packaging substrate 221 is suitable for connecting to the first micro-bump structure 213 at the corresponding position in the first FPGA packaging module below.

[0046] The connecting substrate 100 is provided with a substrate micro-bump structure (the structural form is the same as the above-mentioned first micro-bump structure 213 and second micro-bump structure 223), and the substrate micro-bump structure is arranged corresponding to the docking interface and is connected one-to-one with the docking interface, and is suitable for electrical connection with the FPGA packaging module above, that is, the back connection opening in the first FPGA packaging module 210.

[0047] Different from the above stacking method, you can also choose a stacking method that does not completely overlap.

[0048] For example, referring to Figures 3 and 4, in some other embodiments, the FPGA packaging modules are stacked in such a manner that the FPGA packaging modules of adjacent layers are partially offset and partially overlapped after being horizontally rotated 180°; the FPGA packaging modules of adjacent layers are interconnected via micro-bump structures at overlapping positions. Referring to Figure 4, the first FPGA packaging module 210 and the second FPGA packaging module 220 are partially offset and partially overlapped after being horizontally rotated 180°. The A in Figure 4 is only for illustrating the orientation of the packaging modules and is not intended to indicate specific technical features.

[0049] Furthermore, referring to FIG4 , in this stacking arrangement, the connection substrate 100 includes a main substrate 110 and a heightened substrate 120. The heightened substrate 120 is stacked on a portion of the main substrate 110. The FPGA packaging module that is not directly connected to the main substrate, i.e., the second FPGA packaging module 220, has a non-overlapping area. The heightened substrate 120 corresponds at least partially to the non-overlapping area of ​​the FPGA packaging module that is not directly connected to the main substrate, i.e., the second FPGA packaging module 220, and is electrically connected to the FPGA packaging module, i.e., the second FPGA packaging module 220, at the corresponding position.

[0050] In this stacking method, on the one hand, the overlapping area is used to realize the interconnection between the first FPGA chip 212 and the second FPGA chip 222 in the first FPGA packaging module 210 and the second FPGA packaging module 220 of the adjacent layers, realizing the stacking connection of multiple chips within a unit area, and realizing external signal connection through the connection main substrate 110. At the same time, by rotating 180 degrees symmetrically, the second FPGA packaging module 220 can leave a considerable portion of non-overlapping micro-bumps, or an area for interconnection, that is, a non-overlapping area. This area is not blocked by the first FPGA packaging module 210 below, so that it can be connected to the connecting substrate, realizing more interface connections and more signal transmission. Not only does the chip capacity increase, but the signal transmission lines are also increased, so that the improvement of capacity and performance can be guaranteed. In addition, by increasing the setting of the substrate 120, the distance between the connecting substrate and the packaging module is shortened, which also ensures the stability of the structure and the stability of signal transmission.

[0051] The connection method can be selected by providing a docking interface on the main substrate 110 and providing a substrate micro-bump structure, which connects to the docking interface in a one-to-one correspondence and is connected to the back connection opening on the back side of the first packaging substrate 211 of the first FPGA packaging module 210. The heightened substrate 120 is also provided with a docking interface and provided with a micro-bump structure, which connects to the docking structure in a one-to-one correspondence and is connected to the back connection opening on the back side of the second packaging substrate 221 of the second FPGA packaging module 220. Alternatively, the connection can be made through other methods such as copper pillars and solder balls.

[0052] The elevated substrate 120 is provided with an I / O interface electrically connected to the non-overlapping area. In this embodiment, for example, the docking interface of the elevated substrate 120 is configured as an I / O interface. That is, since the overlapping area already enables external connections for the second FPGA packaging module 220, the non-overlapping area becomes a free interconnection area that can be used to implement more docking transmission lines, such as a DDR I / O connection interface.

[0053] Furthermore, the distance between the main substrate 110 and the directly connected FPGA packaging module is a first distance; the distance between the elevated substrate 120 and the not directly connected FPGA packaging module is a second distance; the first distance and the second distance are the same.

[0054] Specifically, in the embodiments of Figures 3 and 4 , the distance between the main substrate 110 and the directly connected first FPGA package module 210 is a first distance; the distance between the elevated substrate 120 and the not directly connected second FPGA package module 220 is a second distance; the first and second distances are the same. This ensures that the distances between different FPGA package modules and the connecting substrate are consistent, resulting in uniform structural specifications and greater overall structural stability.

[0055] In addition, the FPGA packaging module includes Xbar interconnect switches, and the Xbar interconnect switches in the FPGA packaging modules of adjacent layers are interconnected via the microbump structure in the overlapping region. For example, as shown in Figure 5, the first FPGA packaging module 210 of the adjacent layers includes a first Xbar interconnect switch array 214, and the second FPGA packaging module 220 includes a second Xbar interconnect switch array 224. The first Xbar interconnect switch array 214 and the second Xbar interconnect switch array 224 are also interconnected via the microbumps in the overlapping region, allowing for more flexible shared circuit connections, such as I / O connections, and enabling more data processing. The Xbar interconnect switch arrays of the upper and lower adjacent layers are connected in this way, expanding the Xbar connection from two dimensions to three dimensions. Furthermore, the Xbar interconnect switches can be interconnected to any node in the layer through FPGA programming, which is more flexible than the wire bonding-TSV method, which can only connect to fixed nodes.

[0056] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will readily appreciate that other variations or modifications based on the above descriptions are possible. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of this application.

Claims

1. A FPGA three-dimensional chip packaging structure, characterized in that: include: A plurality of stacked FPGA packaging modules, each of which is provided with an FPGA chip and a micro-bump structure for interconnection; The topological layout of the components and micro-bump structures in each of the FPGA packaging modules is the same; In the FPGA packaging modules of adjacent layers, at least part of the micro-bump structure layout overlaps, and the FPGA chips in the adjacent FPGA packaging modules are interconnected through the micro-bump structures at the overlapping positions; The connecting substrate is used to set up the stacked FPGA packaging modules and realize the external signal transmission of each FPGA packaging module.

2. The FPGA three-dimensional chip packaging structure according to claim 1, characterized in that: The stacking manner of the FPGA packaging modules is as follows: the FPGA packaging modules are completely overlapped, and the projection patterns of the FPGA packaging modules of different layers on the connecting substrate are completely overlapped.

3. The FPGA three-dimensional chip packaging structure according to claim 1, characterized in that: The stacking method of the FPGA packaging modules is: the FPGA packaging modules of adjacent layers are partially offset and partially overlapped after being horizontally rotated 180°; the FPGA packaging modules of adjacent layers are interconnected through micro-bump structures at overlapping positions.

4. The FPGA three-dimensional chip packaging structure according to claim 3, characterized in that: The connecting substrate includes a main substrate and an elevated substrate; the elevated substrate is stacked on part of the main substrate; the FPGA packaging module that is not directly connected to the main substrate has a non-overlapping area; the elevated substrate at least partially corresponds to the non-overlapping area in the FPGA packaging module that is not directly connected to the main substrate, and is electrically connected to the FPGA packaging module at the corresponding position.

5. The FPGA three-dimensional chip packaging structure according to claim 4, characterized in that: The distance between the main substrate and the directly connected FPGA packaging module is a first distance; the distance between the heightened substrate and the not directly connected FPGA packaging module is a second distance; the first distance and the second distance are the same.

6. The FPGA three-dimensional chip packaging structure according to claim 4, characterized in that: The heightened substrate is provided with an I / O interface, and the I / O interface is suitable for being electrically connected to the non-overlapping area.

7. The FPGA three-dimensional chip packaging structure according to any one of claims 1 to 6, characterized in that: The FPGA packaging module includes a packaging substrate, the packaging substrate has an overlapping area for arranging the overlapping interconnected micro-bump structures; the packaging substrate located under the micro-bump structure in the overlapping area has a front connection opening facing the micro-bump structure and a back connection opening on a surface on a side facing away from the micro-bump structure; The front connection opening is electrically connected to the corresponding back connection opening; The front connection opening is connected to the micro-bump structure, and the back connection opening is suitable for connecting to the micro-bump structure at a corresponding position in the FPGA packaging module below.

8. The FPGA three-dimensional chip packaging structure according to claim 7, characterized in that: The connection substrate is provided with a connection line and a docking interface, and the docking interface is used to connect with the stacked FPGA packaging modules to realize external signal transmission of each FPGA packaging module through the connection line; The FPGA packaging module includes a first FPGA packaging module and a second FPGA packaging module; the second FPGA packaging module is stacked above the first FPGA packaging module, and in the first FPGA packaging module, the back connection opening located in the overlapping area is electrically connected to the docking interface at a corresponding position on the connecting substrate.

9. The FPGA three-dimensional chip packaging structure according to claim 8, characterized in that: The connecting substrate is provided with a substrate micro-bump structure, and the substrate micro-bump structure is arranged corresponding to the docking interface, and is connected one-to-one with the docking interface, and is suitable for being electrically connected to the back connection opening in the FPGA packaging module above.

10. The FPGA three-dimensional chip packaging structure according to any one of claims 1 to 9, characterized in that: The FPGA packaging module includes an Xbar interconnection switch, and the Xbar interconnection switches in the FPGA packaging modules of adjacent layers are interconnected through the micro-bump structure in the overlapping area.

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