Command timing control circuit and memory

Abstract

Provided in the embodiments of the present disclosure are a command timing control circuit and a memory. The command timing control circuit comprises a decoding circuit and a shift circuit, wherein the decoding circuit is used for performing decoding processing on the basis of a frequency indication signal and a write preamble signal, so as to generate a control signal, which indicates a first duration for shifting a read-modify-write command signal; and the shift circuit is used for shifting the read-modify-write command signal by the first duration on the basis of the control signal, so as to generate a target command signal, so that the time interval between the target command signal and a write enable signal meets a preset timing condition.

Description

A command timing control circuit and memory

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on November 30, 2023, with application number 202311659153.2 and application name “A Command Timing Control Circuit and Memory”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of semiconductor technology, and in particular to a command timing control circuit and a memory. Background Art

[0003] When writing to a memory device such as Dynamic Random Access Memory (DRAM), the Error Checking and Correcting (ECC) operation requires a specific number of bits (e.g., 128 bits) for calculation. Therefore, if the number of bits of data to be written is less than this, data must be read from the memory to make up the number before writing. This results in a Read Modify Write (RMW) operation.

[0004] During a read-modify-write operation, after receiving an external write command, a read command must be generated at the appropriate time to perform the read operation, leaving sufficient time for intermediate operations (such as ECC) between the read and write commands. Choosing the right timing for generating the read command is a crucial issue when performing read-modify operations.

[0005] Summary of the Invention

[0006] Embodiments of the present disclosure provide a command timing control circuit and a memory.

[0007] In a first aspect, an embodiment of the present disclosure provides a command timing control circuit, including a decoding circuit and a shift circuit, wherein:

[0008] The decoding circuit is used to receive a frequency indication signal and a write preamble signal, perform decoding processing according to the frequency indication signal and the write preamble signal, and generate a control signal; the control signal indicates a first time length for shifting the read-modify-write command signal;

[0009] The shift circuit is used to receive the control signal and the read-modify-write command signal, shift the read-modify-write command signal by the first time length according to the control signal, and generate a target command signal so that the time interval between the target command signal and the write enable signal meets a preset timing condition.

[0010] In a second aspect, an embodiment of the present disclosure provides a memory, which at least includes the command timing control circuit as described in any one of the first aspects.

[0011] The embodiment of the present disclosure provides a command timing control circuit and a memory, wherein the command timing control circuit includes a decoding circuit and a shift circuit, wherein the decoding circuit is used to receive a frequency indication signal and a write preamble signal, and performs decoding processing according to the frequency indication signal and the write preamble signal to generate a control signal; the control signal indicates a first time length for shifting a read-modify-write command signal; and the shift circuit is used to receive a control signal and a read-modify-write command signal, and shift the read-modify-write command signal by the first time length according to the control signal to generate a target command signal, so that the time interval between the target command signal and the write enable signal meets a preset timing condition. In this way, the read-modify-write command signal is shifted to obtain the target command signal according to the control signal obtained by decoding the frequency indication signal and the write preamble signal, so that the shifted read-modify-write command signal meets the timing requirements, thereby the read-modify-write command signal can be generated at a reasonable time, and each step of the read-modify-write operation can be carried out smoothly. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] FIG1 is a timing diagram of a write operation in DDR5;

[0013] FIG2 is a second timing diagram of a write operation in DDR5;

[0014] FIG3 is a timing diagram of RMW command signals at different frequencies;

[0015] FIG4 is a timing diagram of different write preamble modes;

[0016] FIG5 is a schematic diagram of the structure of a command timing control circuit provided by an embodiment of the present disclosure;

[0017] FIG6 is a schematic diagram of the structure of a shift circuit provided in an embodiment of the present disclosure;

[0018] FIG7 is a first schematic diagram of the structure of a shift subcircuit provided in an embodiment of the present disclosure;

[0019] FIG8 is a second schematic diagram of the structure of a shift sub-circuit provided in an embodiment of the present disclosure;

[0020] FIG9 is a third structural diagram of a shift subcircuit provided in an embodiment of the present disclosure;

[0021] FIG10 is a fourth structural diagram of a shift subcircuit provided in an embodiment of the present disclosure;

[0022] FIG11 is a schematic diagram of the structure of a decoding circuit provided in an embodiment of the present disclosure;

[0023] FIG12 is a timing diagram of RMW command signals at different frequencies provided by an embodiment of the present disclosure;

[0024] FIG13 is a schematic diagram of the composition structure of a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0025] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It should be understood that the specific embodiments described herein are only used to explain the related applications and are not intended to limit the present disclosure. It should also be noted that for ease of description, only the portions relevant to the related applications are shown in the drawings.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0027] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0028] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0029] Before further explaining the embodiments of the present disclosure in detail, the nouns and terms involved in the embodiments of the present disclosure are explained first. The nouns and terms involved in the embodiments of the present disclosure are subject to the following interpretations:

[0030] Static Random Access Memory (SRAM);

[0031] Dynamic Random Access Memory (DRAM);

[0032] Synchronous Dynamic Random Access Memory (SDRAM);

[0033] Double Data Rate SDRAM (DDR SDRAM);

[0034] Double Data Rate (DDR);

[0035] Fourth-generation double data rate (Double Data Rate 4, DDR4);

[0036] Fifth-generation double data rate (DDR5);

[0037] Command (CMD);

[0038] Data (DQ);

[0039] Write (WR);

[0040] Read (RD);

[0041] Nanosecond (ns);

[0042] Read Modify Write (RMW);

[0043] Write Column Select (WCSL);

[0044] Data Strobe (DQS);

[0045] Preamble (PRE);

[0046] Write Preamble (WPRE);

[0047] Column Address Strobe (CAS);

[0048] Column address strobe write delay (CAS Write Latency, CWL);

[0049] Command / Address (CA);

[0050] Bank (BK);

[0051] Bank Group (BG);

[0052] Error Checking and Correcting (ECC);

[0053] Burst Length (BL);

[0054] Operation code (Operand, OP);

[0055] Million Times per second (MT / s);

[0056] Megabits per second (Mbps);

[0057] Picosecond (ps);

[0058] D flip-flop (Data Flip-Flop or Delay Flip-Flop, DFF);

[0059] Positive channel Metal Oxide Semiconductor field effect transistor (PMOS transistor);

[0060] N-type metal oxide semiconductor field effect transistor / N-type transistor (Negative channel Metal Oxide Semiconductor field effect transistor, NMOS tube).

[0061] Taking DDR5 DRAM as an example, during a write operation, the ECC operation requires a specific number of bits to perform calculations. For example, 128 bits of data are required to perform 8-bit error correction. When the write data is less than 128 bits, it is necessary to read data from the storage array through a read command signal to supplement the 128-bit data. The 128-bit data is modified with the write data, and then the modified 128-bit data is rewritten to the storage array through a write command signal (i.e., a overwrite operation).

[0062] Referring to Figure 1, Figure 1 shows a timing diagram of a write operation in DDR5. As shown in Figure 1, the write command signal (i.e., the EXT_WR command signal in Figure 1) generated after command decoding (CMD_DEC) will be shifted by the CWL time length (CWL Shift). During the CWL period, the earliest available shifted write command signal is used as the RMW command signal. After the memory receives the internal read command signal (i.e., the RMW_D command signal in Figure 1), it is necessary to latch information such as CA, BG, and BK and maintain it for a certain length of time (e.g., 5-6ns) to provide sufficient time to perform ECC decoding and correction on the data read from the storage array, as well as to merge and re-encode the write data and the read data. Then, when the write command (i.e., the WCSL signal in Figure 1) is valid, the latched information is transferred to perform the write operation. In other words, read ECC and write ECC need to be performed between the read operation and the write operation, so from the RMW command signal to the WCSL signal, the obtained RMW command signal needs to be released at the appropriate position. In Figure 1, the appropriate position refers to the position 5 to 6 ns before the WCSL signal, that is, the position of the RMW_D command signal. The RMW_D command signal is a signal obtained by shifting the RMW command signal. The read operation starts at the RMW_D command signal, and the write operation starts at the WCSL signal.

[0063] As shown in Figure 1, the time delay from the EXT_WR command signal to the first bit of input data (i.e., D0) is CWL. For DDR5 DRAM, CWL can be CWL-MR3, where MR3 is a value that can be set according to the mode register. After the clock signal CKT samples the EXT_WR command signal, it shifts through CWL to begin the data write operation. In addition, the WCSL signal is used to enable the column signal for data writing. The CA, BG, and BK information must be maintained until the WCSL signal is signaled for data writing.

[0064] It should be noted that Figure 1 illustrates the case where BL is 16. The DQ terminal transmits 16 data records (D0 to D15) at a time. The length of the clock signal CKT during data transmission is 8T, and the clock period of the clock signal CKT is T. Taking CWL0_CLK as the time origin, CWL4_CLK has elapsed 4T, and the WCSL signal has elapsed 8T. In Figure 1, CWL0_CLK is also the coordinate origin. The write preamble signal affects the distance of the RMW command signal relative to CWL0_CLK, which in turn affects the coordinate value of the RMW command signal.

[0065] Based on Figure 1, refer to Figure 2, which shows a second timing diagram of a write operation in DDR5, specifically a timing diagram under different write preamble signals. For example, as shown in Figure 2, the write preamble signal includes three write preambles, namely WPRE2, WPRE3, and WPRE4. WPRE2, WPRE3, and WPRE4 start receiving or writing data 2T, 3T, and 4T after the DQS valid edge respectively. That is, there is a 1T difference between WPRE2 and WPRE3, and a 1T difference between WPRE3 and WPRE4. In addition, the duration from the RMW command signal to the DQS valid edge is X. Because all signals are on the same path, and in order to obtain the RMW command signal as early as possible, CWL is fixed and X is also fixed under different write preambles. Because X is fixed and the write preambles are different, the coordinate values ​​of the RMW command signal relative to the coordinate origin (CWL0_CLK) will be different.

[0066] Based on the above background, the first shifted write command signal obtained after the write command signal is shifted is determined to be the RMW command signal. The RMW command signal needs to latch information such as CA, BG, and BK and maintain it for a certain length of time before being passed on when the WCSL signal is valid. However, the RMW command signal is far from the WCSL signal, and its timing cannot meet the requirements. That is, the RMW command signal to WCSL signal does not meet the 5-6ns requirement. As a result, there is not enough time for intermediate operations (such as ECC) between the read command signal and the write command signal. In addition, under different write preambles, the DQS valid edge starts to receive or write data at different times, resulting in different delay times for the RMW command signal.

[0067] As shown in Figure 3, HF_RMW_Shift is the position of the RMW_D command signal at high frequency, and LF_RMW_Shift is the position of the RMW_D command signal at low frequency. At different frequencies, the required shift length of the RMW command signal, that is, the delay time, is different. In addition, as shown in (a) of Figure 4, t WPRE is the length of time to write the preamble, t WPSTThe write preamble and write postamble are waveform settings for the start and end of the DQS signal. After the write preamble signal changes, the timing relationship between the RMW command signal and the WCSL signal will also change. Specifically, see Figure 4 (b), which is a partial enlarged view of the write preamble in the dotted box of Figure 4 (a). WPRE2 starts receiving or writing data 2T after the DQS valid edge, represented by 2T PRE; WPRE3 starts receiving or writing data 3T after the DQS valid edge, represented by 3T PRE; WPRE4 starts receiving or writing data 4T after the DQS valid edge, represented by 4T PRE. As shown in Figure 4 (a), because the time of the first input data D0 is fixed, that is, the time t0 is fixed, the position of the DQS valid edge (that is, the first falling edge) will be different under different write preambles, and the time when DQS starts to be valid will be different.

[0068] In summary, the timing of the read command signal (i.e., the RMW command signal) generated directly from the write command signal received by the memory cannot meet the requirements, so the read command signal needs to be shifted and adjusted. However, the delay time required for the read command signal varies under different frequency values ​​and different write preamble codes.

[0069] Based on this, an embodiment of the present disclosure provides a command timing control circuit, which includes a decoding circuit and a shift circuit. The decoding circuit is used to receive a frequency indication signal and a write preamble signal, and perform decoding processing according to the frequency indication signal and the write preamble signal to generate a control signal; the control signal indicates a first time length for shifting a read-modify-write command signal; the shift circuit is used to receive a control signal and a read-modify-write command signal, and shift the read-modify-write command signal by a first time length according to the control signal to generate a target command signal so that the time interval between the target command signal and the write enable signal meets a preset timing condition. In this way, according to the control signal obtained by decoding the frequency indication signal and the write preamble signal, the read-modify-write command signal is shifted to obtain the target command signal, so that a read operation is performed at the shifted read-modify-write command signal, information such as CA, BG and BK are latched and maintained for a certain length of time, and the latched information is transmitted when the write enable signal is valid to perform a write operation, so that the shifted read-modify-write command signal meets the timing requirements, the read-modify-write command signal can be generated at a reasonable time under different frequency values ​​and different write preambles, and each step of the read-modify-write operation can be carried out smoothly.

[0070] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0071] In one embodiment of the present disclosure, referring to FIG5 , a schematic diagram of the structure of a command timing control circuit provided by the present disclosure is shown. As shown in FIG5 , the command timing control circuit 10 may include a decoding circuit 11 and a shift circuit 12, wherein:

[0072] The decoding circuit 11 is used to receive the frequency indication signal and the write preamble signal, perform decoding processing according to the frequency indication signal and the write preamble signal, and generate a control signal; the control signal indicates a first time length for shifting the read-modify-write command signal;

[0073] The shift circuit 12 is used to receive the control signal and the read-modify-write command signal, shift the read-modify-write command signal by a first time length according to the control signal, and generate a target command signal so that the time interval between the target command signal and the write enable signal meets a preset timing condition.

[0074] Here, the frequency indication signal is used to indicate the current operating frequency value of the memory, and the write preamble signal is used to indicate the currently set write preamble. The frequency value and write preamble can be different in different situations. The present disclosure can use the frequency value and write preamble to control the shift length of the read-modify-write command signal.

[0075] It should be noted that the read-modify-write command signal is represented by RMW, the target command signal is represented by RMW_D; the control signal is represented by RMW_LT; the write enable signal can specifically be a write column select signal, represented by WCSL; the preset timing condition is that the time interval between the target command signal and the write enable signal meets the time required for intermediate operations (such as ECC) during the read and write operations. Exemplarily, this time meets 5-6ns. It can be understood that the target command signal is the shifted RMW command signal, the read operation starts at the target command signal, and the write operation starts at the write enable signal. The read and write operations require a 5-6ns interval to allow the read data to undergo ECC decoding, correction, data merging, and re-encoding.

[0076] In the disclosed embodiments, the command timing control circuit 10 is specifically a circuit related to RMW command signals in integrated circuit design, and more particularly, to a circuit for releasing RMW command signals in a DRAM chip. Furthermore, the command timing control circuit 10 can be applied to a circuit for releasing RMW command signals in a DRAM chip, or to circuits related to releasing other command signals at different frequencies, without specific limitation.

[0077] As shown in FIG5 , in the command timing control circuit 10, a control signal is generated according to the frequency indication signal and the write preamble signal by the decoding circuit 11, and the read-modify-write command signal is shifted by the shift circuit 12 to generate a target command signal, so that a read operation is performed at the target command signal and a write operation is performed at the write enable signal. The time interval between the target command signal and the write enable signal meets the preset timing conditions, which can provide sufficient time for ECC decoding, correction, data merging, re-encoding and other operations on the data read from the storage array, so that the read-modify-write command signals can be generated at a reasonable time under different frequency values ​​and different write preambles, and each step of the read-modify-write operation can be carried out smoothly.

[0078] In some embodiments, the command timing control circuit may further include a command processing circuit, wherein:

[0079] The command processing circuit is used to receive a write command signal, perform shift processing on the write command signal to obtain a shift write command signal, and determine the first shift write command signal during the column address strobe pulse write delay period as a read-modify-write command signal.

[0080] It should be noted that CWL is the time delay between the internal write command signal and the first bit of input data (D0), denoted by CWL. Specifically, for DDR5, CWL can be CWL-MR3, where MR3 is the mode register that controls write leveling operations and stores a variable delay amount. It can be understood that during CWL, the earliest available shift write command signal is used as the read-modify-write command signal.

[0081] Furthermore, in some embodiments, for the shift circuit 12, see FIG6 , which shows a schematic diagram of the composition structure of a shift circuit provided by an embodiment of the present disclosure. As shown in FIG6 , the shift circuit 12 may include S cascaded and identical shift sub-circuits 121 (only one number 121 is marked in FIG6 , and the remaining shift sub-circuits are not marked with numbers), the control signal includes S control sub-signals, and only one of the S control sub-signals is in an enabled state, S is an integer greater than 1; the input end of the first shift sub-circuit 121 is used to receive a read-modify-write command signal, the first output end of the i-th shift sub-circuit 121 is connected to the input end of the i+1-th shift sub-circuit 121, and the control end of the i-th shift sub-circuit 121 is used to receive the i-th control sub-signal, i is an integer greater than 0 and less than S; wherein:

[0082] The shift circuit 12 is used to shift the read-modify-write command signal by a first time length through the 1st to jth shift sub-circuits 121 when the jth control sub-signal is in an enabled state to obtain a target command signal, and output the target command signal through the jth shift sub-circuit 121, where j is an integer greater than 0 and less than S.

[0083] Here, only one of the S control sub-signals is in the enabled state, so only one bit of the output signal of the shift sub-circuit 121 is valid, and the output signal of the shift sub-circuit 121 corresponding to the control sub-signal in the enabled state is valid.

[0084] It should be noted that in the disclosed embodiment, the shift sub-circuit 121 may include a clock terminal (CK), an input terminal (D), a first output terminal (Q), a second output terminal (Z), an inverting output terminal (QN), and a reset terminal (RESET). In addition, a set terminal (SET) may also be included, but this is not shown in the figure. The first output terminal of the i-th shift sub-circuit 121 serves as the output terminal for the next stage and is connected to the input terminal of the next shift sub-circuit 121. The second output terminal of the i-th shift sub-circuit 121 serves as the output terminal for the shift amount, and is used to output the output signal of the corresponding shift sub-circuit 121.

[0085] As shown in FIG6 , the control sub-signal is represented by RMW_LT, and the mth control sub-signal is represented by RMW_LT <m>denoted by , the output signal of the corresponding shift sub-circuit 121 is denoted by RMWm (m is an integer greater than 0 and less than or equal to S). The RMW command signal selects an appropriate shift length under the control of the control sub-signal. Only one bit of the output signal of all shift sub-circuits 121 is valid, and after logical synthesis, it is output as the target command signal. In other words, the shift circuit 12 is composed of shift sub-circuits 121 that can control the shift length of the RMW command signal. This ensures that read operations performed on the shifted RMW command signal can proceed smoothly, achieving the normal function of the target command signal.

[0086] In some embodiments, as shown in FIG6 , the clock terminal of each shift sub-circuit 121 is used to receive a clock signal, and the shift sub-circuit 121 shifts the signal received at the input terminal based on the clock signal; wherein:

[0087] When i is equal to 1, the first shift sub-circuit 121 shifts the read-modify-write command signal by 2 clock cycles or 1 clock cycle;

[0088] When i is greater than 1, the 1st to i-1th shift sub-circuits 121 shift the signal received at the input terminal by 2 clock cycles, and the i-th shift sub-circuit 121 shifts the signal received at the input terminal by 2 clock cycles or 1 clock cycle;

[0089] The clock period is the period of the clock signal.

[0090] It should be noted that the clock signal is represented by CLK and the clock cycle is represented by T.

[0091] It should also be noted that the signal received at the input end is shifted according to the control sub-signal. When the first control sub-signal is in the enabled state, the first duration is 1T or 2T; when the jth control sub-signal is in the enabled state, the first duration is [2×(j-1)+1]T or [2×(j-1)+2]T.

[0092] In some embodiments, with respect to the shift sub-circuit 121, see FIG7 , which shows a schematic diagram of a structure of a shift sub-circuit provided in an embodiment of the present disclosure. As shown in FIG7 , the i-th shift sub-circuit 121 may include a first output circuit 1211, a second output circuit 1212, a control circuit 1213, and a selection circuit 1214, wherein:

[0093] A first output circuit 1211 is configured to shift a signal received at an input terminal by one clock cycle to generate a first shift amount signal. When i is equal to 1, the input terminal of the first output circuit 1211 receives a read-modify-write command signal. When i is greater than 1, the input terminal of the first output circuit 1211 receives a signal output by the (i-1)th shift sub-circuit.

[0094] The second output circuit 1212 is configured to receive the first shift amount signal, shift the first shift amount signal by one clock cycle, and generate a second shift amount signal;

[0095] The control circuit 1213 is configured to receive the second shift amount signal and the control sub-signal, and control whether to output the second shift amount signal to the (i+1)th shift sub-circuit 121 according to the control sub-signal;

[0096] The selection circuit 1214 is used to receive the first shift amount signal, the second shift amount signal, the control sub-signal and the preset write preamble code, and when the control sub-signal is in the enabled state, according to the preset write preamble code, select the first shift amount signal or the second shift amount signal to be output as the target command signal; the preset write preamble code instructs the i-th shift sub-circuit 121 to shift the signal received at the input end by 2 clock cycles or 1 clock cycle.

[0097] It should be noted that the first shift amount signal is represented by D1, and the second shift amount signal is represented by D2; the write preamble signal may include WPRE2, WPRE3, and WPRE4, and the preset write preamble is WPRE3. WPRE2, WPRE3, and WPRE4 begin receiving or writing data after the DQS valid edge has passed 2T, 3T, and 4T, respectively. One shift sub-circuit 121 can shift the signal received at the input end by a maximum of 2T. 2T and 4T require an even number of shift sub-circuits 121 shifts, and 3T requires (k+0.5) shift sub-circuits 121 shifts (k is a positive integer). Therefore, WPRE3 is used as the preset write preamble. In this way, when the control sub-signals corresponding to WPRE3 and WPRE4 are the same, by determining whether it is WPRE3 or WPRE4, WPRE3 is selected to be output from the first shift amount signal D1, or WPRE4 is selected to be output from the second shift amount signal D2, thereby enabling the last-stage shift sub-circuit 121 to shift the signal received at the input end by 1T or 2T.

[0098] Specifically, when WPRE3 is 1, the current shift subcircuit 121 outputs the first shift amount signal D1; when WPRE3 is 0, the current shift subcircuit 121 outputs the second shift amount signal D2. Logic "1" is a high level state, and logic "0" is a low level state.

[0099] Furthermore, in some embodiments, as shown in FIG7 , the first output circuit 1211 includes a first NOT gate a1 and a first transmission circuit a2, the second output circuit 1212 includes a second transmission circuit a3 and a second NOT gate a4, the control circuit 1213 includes a first AND gate a5, and the selection circuit 1214 includes a second AND gate a6, a third AND gate a7, a first OR gate a8, and a fourth AND gate a9, wherein:

[0100] The input end of the first NOT gate a1 serves as the input end of the shift sub-circuit 121; the output end of the first NOT gate a1 is connected to the input end of the first transmission circuit a2; the output end of the first transmission circuit a2 is connected to the input end of the second transmission circuit a3, for outputting a first shift amount signal;

[0101] The output end of the second transmission circuit a3 is connected to the input end of the second NOT gate a4; the output end of the second NOT gate a4 is connected to the first input end of the first AND gate a5, for outputting a second shift amount signal;

[0102] The second input terminal of the first AND gate a5 is used to receive the inverted control sub-signal, and the output terminal of the first AND gate a5 serves as the first output terminal of the shift sub-circuit;

[0103] A first input terminal of a second AND gate a6 is used to receive the first shift amount signal, a second input terminal of the second AND gate a6 is used to receive the preset write preamble code, and an output terminal of the second AND gate a6 is connected to the first input terminal of a first OR gate a8; a first input terminal of a third AND gate a7 is used to receive the second shift amount signal, a second input terminal of the third AND gate a7 is used to receive the inverted preset write preamble code, and an output terminal of the third AND gate a7 is connected to the second input terminal of the first OR gate a8; an output terminal of the first OR gate a8 is connected to a first input terminal of a fourth AND gate a9, a second input terminal of the fourth AND gate a9 is used to receive the control sub-signal, and an output terminal of the fourth AND gate a9 serves as a second output terminal of the shift sub-circuit;

[0104] The inverted preset write preamble is obtained by inverting the preset write preamble, and the inverted control sub-signal is obtained by inverting the control sub-signal.

[0105] It should be noted that the second input of the second AND gate a6 can also be used to receive the delayed preset write preamble, and the second input of the fourth AND gate a9 can also be used to receive the delayed control sub-signal, without specific limitation. The delayed preset write preamble is obtained by delaying the preset write preamble, and the delayed control sub-signal is obtained by delaying the control sub-signal. Here, the delayed control sub-signal is denoted by RMW_LT_T, the inverted control sub-signal is denoted by RMW_LT_B, the delayed preset write preamble is denoted by WPRE3_T, and the inverted preset write preamble is denoted by WPRE3_B.

[0106] It should be noted that the control sub-signal passes through an odd number of NOT gates to obtain an inverted control sub-signal, and the level state of the inverted control sub-signal is opposite to that of the control sub-signal; the control sub-signal passes through an even number of NOT gates to obtain a delayed control sub-signal, and the level state of the delayed control sub-signal is the same as that of the control sub-signal. It can be understood that the odd number of NOT gates can be composed of one NOT gate, or three, or five, seven, etc. NOT gates connected in series; the even number of NOT gates can be composed of two NOT gates, or four, or six, eight, etc. NOT gates connected in series, and the embodiments of the present disclosure do not specifically limit this. For example, in Figure 8, the specific implementation of the embodiment of the present disclosure is described in detail by taking the control sub-signal RMW_LT passing through a NOT gate to obtain the inverted control sub-signal RMW_LT_B, and the control sub-signal RMW_LT passing through two NOT gates to obtain the delayed control sub-signal RMW_LT_T as an example.

[0107] Similarly, the preset write preamble passes through an odd number of NOT gates to obtain an inverted preset write preamble, which has an opposite voltage level to the preset write preamble. The preset write preamble passes through an even number of NOT gates to obtain a delayed preset write preamble, which has the same voltage level as the preset write preamble. For example, in FIG8 , the specific implementation of the disclosed embodiment is described in detail using the example of the preset write preamble WPRE3 passing through one NOT gate to obtain the inverted preset write preamble WPRE3_B, and the preset write preamble WPRE3 passing through two NOT gates to obtain the delayed preset write preamble WPRE3_T.

[0108] In addition, as shown in FIG8 , the clock signal CLK is passed through a NOT gate to obtain the inverted clock signal CLKB. The clock signal CLK may also be obtained by a structure consisting of three, five, or seven NOT gates connected in series to obtain the inverted clock signal CLKB. This is not specifically limited.

[0109] It can be understood that when WPRE3 is 1, that is, WPRE3_T is 1, the signal received at the input end is shifted by half the shift sub-circuit 121, and the current shift sub-circuit 121 outputs the first shift amount signal D1; when WPRE3 is 0, that is, WPRE3_B is 1, the signal received at the input end is shifted by the entire shift sub-circuit 121, and the current shift sub-circuit 121 outputs the second shift amount signal D2.

[0110] In one embodiment, based on the shift sub-circuit 121 shown in FIG7 , refer to FIG9 , which shows a third schematic diagram of the structure of a shift sub-circuit provided in an embodiment of the present disclosure. As shown in FIG9 , the first transmission circuit a2 may include a first transmission gate u1 and a first drive circuit, the second transmission circuit a3 may include a second transmission gate u2 and a second drive circuit, the first drive circuit may include a third NOT gate u3, a fourth NOT gate u4, and a third transmission gate u5, and the second drive circuit may include a fifth NOT gate u6, a sixth NOT gate u7, and a fourth transmission gate u8, wherein:

[0111] The output end of the first NOT gate a1 is connected to the first end of the first transmission gate u1; the input end of the third NOT gate u3 and the second end of the third transmission gate u5 are both connected to the second end of the first transmission gate u1; the output end of the third NOT gate u3 and the input end of the fourth NOT gate u4 are both connected to the first end of the second transmission gate u2; the output end of the fourth NOT gate u4 is connected to the first end of the third transmission gate u5;

[0112] The input end of the fifth NOT gate u6 and the second end of the fourth transmission gate u8 are both connected to the second end of the second transmission gate u2; the output end of the fifth NOT gate u6 and the input end of the sixth NOT gate u7 are both connected to the input end of the second NOT gate a4; the output end of the sixth NOT gate u7 is connected to the first end of the fourth transmission gate u8.

[0113] It should be noted that a transmission gate is a controllable switching circuit that can transmit both digital and analog signals, exhibiting bidirectional signal transmission characteristics. A transmission gate consists of a PMOS transistor and an NMOS transistor connected in parallel. The gates of the PMOS and NMOS transistors serve as the two control terminals, each receiving a pair of mutually anti-phase signals. The sources of the PMOS and NMOS transistors are connected as the input terminals, while the drains are connected as the output terminals. Since the drains and sources of the PMOS and NMOS transistors are interchangeable, the input and output terminals of the transmission gate are also interchangeable.

[0114] As shown in Figure 9, each transmission gate is composed of a PMOS transistor and an NMOS transistor connected in parallel. The gate of the PMOS transistor is used to receive the clock signal CLK, and the gate of the NMOS transistor is used to receive the inverted clock signal CLKB. Based on this connection, clock edge transitions can be achieved. In addition, in the embodiment of the present disclosure, the first end is the input end, and the second end is the output end.

[0115] In another embodiment, as shown in FIG10 , the second AND gate a6 is replaced with a first NAND gate a10 and a seventh NOT gate a11, the third AND gate a7 is replaced with a second NAND gate a12 and an eighth NOT gate a13, the first OR gate a8 is replaced with a first NOR gate a14 and a ninth NOT gate a15, and the fourth AND gate a9 is replaced with a third NAND gate a16 and a tenth NOT gate a17. The specific connections are shown in FIG10 . Here, the second input terminal of the first NAND gate a10 is used to receive the delay preset write preamble code WPRE3_T, and the second input terminal of the third NAND gate a16 is used to receive the delay control sub-signal RMW_LT_T.

[0116] In addition, as shown in FIG10 , the i-th shift sub-circuit 121 may further include a reset transistor u9, which is an NMOS transistor. The gate of the reset transistor u9 is used to receive a reset signal RESET, the source of the reset transistor u9 is used to receive a ground signal VSS, and the drain of the reset transistor u9 is connected to the input of the fifth NOT gate u6, the second terminal of the fourth transmission gate u8, and the second terminal of the second transmission gate u2. Here, VSS represents a ground signal (also referred to as a "ground terminal"), which is used to provide a low-level signal (low level / low-level state in this embodiment refers to a logic "0").

[0117] Understandably, when the RMW_LT signal is high, the RMW_LT_B signal is low, the output value of the first output terminal Q of shift sub-circuit 121 is 0, and the RMW command signal no longer continues to shift. Simultaneously, the RMW_LT_T signal is high, outputted from the current shift sub-circuit 121, and the output of the second output terminal Z of shift sub-circuit 121 is turned on. Depending on the write preamble signal, the output port is selected as point D1 or point D2 to achieve different shift timings for WPRE2, WPRE4, and WPRE3. After the output of shift sub-circuit 121, all outputs are logically synthesized into the target command signal output, thereby accurately releasing the RMW command signal and ensuring that the RMW command signal meets timing requirements.

[0118] In some embodiments, a second time duration compensated for shifting the read-modify-write command signal is obtained by encoding according to the frequency value indicated by the frequency indication signal; a third time duration compensated for shifting the read-modify-write command signal is obtained by encoding according to the write preamble signal;

[0119] The second duration is equal to A times the clock period, the third duration is equal to B times the clock period, and the first duration is related to the second and third durations; A and B are both greater than 0, and A is less than B.

[0120] It should be noted that A and B can be integers, that is, the second duration and the third duration are equal to integer multiples of the clock cycle, but this is not specifically limited.

[0121] In some embodiments, the first duration is composed of the second duration and the third duration, for example, the first duration is the algebraic sum of the second duration and the third duration.

[0122] Table 1 shows the relevant provisions for OP[3:0] and data transmission rate (Data Rate) in MR13 (Mode Register 13) in DDR5. As shown in Table 1, the frequency indication signal is OP[3:0] (i.e., a combination of OP[3], OP[2], OP[1], and OP[0]). Specifically, the frequency indication signal is MR13_OP[3:0]. MR13 is a mode register that contains frequency information. When the value of MR13_OP[3:0] is different, the range of data transmission rate values ​​also varies. Here, the data transmission rate is the data transmission rate on the data bus and is proportional to the frequency value. When the data transmission rate changes, the frequency value also changes proportionally. Therefore, the frequency value can be indicated by the data transmission rate.

[0123] It should be noted that, as shown in Table 1, tCCD_L.min, tCCD_L_WR2.min, tCCD_L_WR.min, and tDLLK.min are all time intervals with fixed meanings in the DRAM field. When the frequency values ​​are different, the values ​​(nCK) representing the unit clock cycle multiples of these time intervals are also different.

[0124] Table 1

[0125] In some embodiments, the write preamble signal includes N write preambles, where N is an integer greater than 0; the frequency indication signal includes at least one operation code, where the at least one operation code corresponds to M logical combinations, each logical combination corresponds to a frequency value, and M is an integer greater than 0.

[0126] Table 2 shows a coding table provided by an embodiment of the present disclosure. As shown in Table 2, the units of the data transmission rate are consistent with those in Table 1; TCCD_L represents the longer time interval between CAS commands, specifically the time interval between CAS commands for the same memory bank; PREAMBLE2, PREAMBLE3, and PREAMBLE4 are the aforementioned WPRE2, WPRE3, and WPRE4, respectively, whose values ​​are stored in mode register MR8 and can be determined by reading mode register MR8; CWL0 is the aforementioned CWL0_CLK, representing the coordinate origin.

[0127] For example, as shown in Table 2, the write preamble signal includes three write preambles: WPRE2, WPRE3, and WPRE4. This embodiment uses three write preambles as an example, but is not limited to this. It should be noted that the write preamble is related to the frequency value. The memory selects the corresponding write preamble at different frequency values ​​based on the command sent by the host. When a certain frequency value corresponds to multiple write preambles, the host determines which write preamble to select. For the specific waveforms of the write preambles, refer to PRE2, PRE3, and PRE4 in Figure 2.

[0128] In addition, illustratively, as shown in Table 2, the frequency indication signal includes MR13_OP0 to MR13_OP3 (i.e., OP0 to OP3), a total of 4-bit operation codes. The frequency indication signal can also be represented by OP[3:0]. This embodiment takes the frequency indication signal including a 4-bit operation code as an example, but is not limited to this.

[0129] Table 2

[0130] It should be noted that in Table 2, X represents the starting point of the RMW command signal, excluding the compensation for the frequency value and the write preamble. This is the rising edge of the RMW command signal, and the pulse length of the RMW command signal is 2T. Because CWL0 is the coordinate origin, as shown in Figure 2, X is a negative value. Furthermore, because there is a 1T difference between WPRE2 and WPRE3, and a 1T difference between WPRE3 and WPRE4, the earliest position of the RMW command signal under WPRE2 is X. Therefore, when compensating for the time difference caused by the write preamble, the earliest position of the RMW command signal under WPRE3 is X-1, and the earliest position of the RMW command signal under WPRE4 is X-2. It can be understood that the second and third durations compensate for the same shift amount X under different frequency values ​​and different write preambles.

[0131] It should also be noted that the values ​​of -2, -4, -6, and -8 for the RMW_D command signal are calculated. This is to ensure that the time interval between the RMW_D command signal and the WCSL signal meets the preset timing condition of 5-6ns at different frequency values. Therefore, the RMW_D command signal is negatively offset according to the frequency value. For example, at a frequency of 3200Mbps, 1T is approximately 625ps, and 5-6ns is approximately 10T. Because the data DQ output occupies 8T, the offset of the RMW_D command signal is 2T at this frequency value. Furthermore, because -2, -4, -6, and -8 are all even numbers, the command timing control circuit 10 can be simplified. As shown in Table 2, the encoding values ​​corresponding to 3200MT / s and 3600MT / s are the same, thereby saving area in the command timing control circuit 10.

[0132] It should be noted that the code value represents the shift length from the RMW command signal to the RMW_D command signal. Here, the code value of WPRE3 is written as the code value of WPRE4, so the two remain consistent. Because WPRE3 and WPRE4 differ by 1T, they are output by the same shift subcircuit, specifically at the first shift amount signal D1 and the second shift amount signal D2, respectively. Therefore, WPRE3 is used as the default write preamble to distinguish the release positions of WPRE3 and WPRE4 under the same code value. For example, according to Table 2, when the frequency value is 3200 MT / s, the value of the RMW command signal under WPRE2 is -10, then the value of the RMW command signal under WPRE3 is -11, and the value of the RMW command signal under WPRE4 is -12; the value of the RMW command signal to the RMW_D command signal under WPRE2 is 8, the value of the RMW command signal to the RMW_D command signal under WPRE3 is 9, and the value of the RMW command signal to the RMW_D command signal under WPRE4 is 10. One shift sub-circuit can shift the signal received at the input end by a maximum of 2T, that is, under WPRE2, the signal received at the input end needs to be shifted by 4 shift sub-circuits; under WPRE3 and WPRE4, the signal received at the input end needs to be shifted by 5 shift sub-circuits, but it is necessary to determine in the fifth shift sub-circuit whether to output from D1 under WPRE3 or from D2 under WPRE4, to achieve a 1T or 2T shift of the last-level shift sub-circuit.

[0133] In summary, to ensure that the RMW command signal meets timing requirements from the WCSL signal to the RMW command signal at different frequencies and with different write preambles, the shift length of the RMW command signal must be encoded and controlled. Code information for different frequencies is encoded using the MR13 mode register. Assuming CWL0 is CLK0 (the time origin), the WCSL signal has passed 8T and is CLK8. Since the transition from the RMW command signal to the WCSL signal takes 5 to 6 ns, the release position of the RMW command signal can be obtained by shifting the WCSL signal by 5 to 6 ns based on the different frequency values. Assuming that the earliest time position of the RMW command signal after the write command signal shifts during the CWL period under WPRE2 is X, the shift length is the duration from the RMW command signal to the RMW_D command signal. According to the specification, the earliest positions of the RMW command signal under WPRE3 and WPRE4 are X-1 and X-2, respectively. As shown in Table 2, the same set of code values ​​is used in WPRE3 and WPRE4. The shift subcircuit performs further processing based on the write preamble signal. The code values ​​of WPRE3 and WPRE4 are increased by 2 compared to WPRE2.

[0134] In the prior art, the frequency range only includes a low frequency band, a mid-frequency band, and a high frequency band. The embodiment of the present disclosure narrows the frequency range, and the frequency range is more accurate than the prior art. Specifically, as shown in Table 2, the frequency value is accurately divided into 9 frequency bands from ≤3200MT / s to ≤6400MT / s according to the change of TCCD_L, and each frequency band is separated by 400MT / s. In addition, if the circuit develops to a higher frequency in the future, such as 6800MT / s, 7200MT / s and other frequencies, the corresponding coding value can continue to be implemented by adding coding according to the coding logic, and the application range is wider than the prior art. At the same time, the present disclosure encodes the control signal sent by the TCCD_L controller to realize the output of the RMW command signal at different positions, which is beneficial for the DRAM to know the operating frequency of the chip in real time, ensure the working timing of the chip at different frequencies, and improve stability.

[0135] According to Table 2, the control signal can be obtained through the decoding circuit 11. In some embodiments, for the decoding circuit 11, refer to Figure 11, which shows a schematic diagram of the structure of a decoding circuit provided by an embodiment of the present disclosure. As shown in Figure 11, the decoding circuit 11 may include a first decoding circuit 111, a second decoding circuit 112, and a third decoding circuit 113; wherein:

[0136] A first decoding circuit 111 is configured to receive at least one operation code bit, perform a first logic process based on the at least one operation code bit, and generate M frequency code signals, wherein the M frequency code signals correspond to M frequency values ​​in a one-to-one manner, and only one of the M frequency code signals is in an enabled state;

[0137] The second decoding circuit 112 is configured to receive M frequency code signals and N write preamble codes, and perform AND logic processing on each frequency code signal and each write preamble code to generate M×N initial control sub-signals;

[0138] The third decoding circuit 113 is configured to receive M×N initial control sub-signals and perform OR logic processing on several of the M×N initial control sub-signals to generate S control sub-signals.

[0139] For example, as shown in FIG11 , in the first decoding circuit 111, a total of 4-bit operation codes are included, including MR13_OP0, MR13_OP1, MR13_OP2 and MR13_OP3. MR13_OP0 passes through a NOT gate to obtain MR13_OP0B, and the level state of MR13_OP0B is opposite to the level state of MR13_OP0. MR13_OP0 passes through two NOT gates to obtain MR13_OP0T, and the level state of MR13_OP0T is the same as the level state of MR13_OP0. Similarly, MR13_OP1 passes through a NOT gate to obtain MR13_OP1B, and the level state of MR13_OP1B is opposite to the level state of MR13_OP1. MR13_OP1 passes through two NOT gates to obtain MR13_OP1T, and the level state of MR13_OP1T is the same as the level state of MR13_OP1. The same; MR13_OP2 passes through a NOT gate to obtain MR13_OP2B, and the level state of MR13_OP2B is opposite to the level state of MR13_OP2. MR13_OP2 passes through two NOT gates to obtain MR13_OP2T, and the level state of MR13_OP2T is the same as the level state of MR13_OP2; MR13_OP3 passes through a NOT gate to obtain MR13_OP3B, and the level state of MR13_OP3B is opposite to the level state of MR13_OP3. MR13_OP3 passes through two NOT gates to obtain MR13_OP3T, and the level state of MR13_OP3T is the same as the level state of MR13_OP3.

[0140] Here, MR13_OP0B represents the 0th opcode is 0, MR13_OP0T represents the 0th opcode is 1; similarly, MR13_OP1B represents the 1st opcode is 0, MR13_OP1T represents the 1st opcode is 1; MR13_OP2B represents the 2nd opcode is 0, MR13_OP2T represents the 2nd opcode is 1; MR13_OP3B represents the 3rd opcode is 0, MR13_OP3T represents the 3rd opcode is 1.

[0141] It should be noted that the opcode can obtain an inverted opcode with an opposite level state after passing through an odd number of NOT gates, and the opcode can obtain a delayed opcode with the same level state after passing through an even number of NOT gates. It is understandable that the odd number of NOT gates can be composed of one NOT gate, or three, or five, seven, etc. NOT gates connected in series; the even number of NOT gates can be composed of two NOT gates, or four, or six, eight, etc. NOT gates connected in series, and the embodiments of the present disclosure do not specifically limit this. For example, in Figure 11, the specific implementation of the embodiments of the present disclosure is described in detail by taking the example of the opcode passing through one NOT gate to obtain an inverted opcode and the opcode passing through two NOT gates to obtain a delayed opcode as an example.

[0142] As shown in Figure 11, there are a total of 9 frequency code signals, namely TCCD_L_8, TCCD_L_9, TCCD_L_10, ..., TCCD_L_16. According to Table 2, the corresponding MR13_OP[3:0] values ​​are 0000, 0001, 0010, ..., 1000, respectively. These 9 frequency code signals correspond to 9 MR13_OP[3:0] values, and also correspond to 9 frequency values.

[0143] It should also be noted that the value of MR13_OP[3:0] in Table 2 determines whether the inverted opcode or the delayed opcode is input into the first decoding circuit 111 to obtain the frequency code signal. For example, as shown in FIG11 , the value of MR13_OP[3:0] corresponding to TCCD_L_9 is 0001, so the frequency code signal TCCD_L_9 is obtained by inputting MR13_OP0T, MR13_OP1B, MR13_OP2B, and MR13_OP3B. In addition, as shown in FIG11 , in the first decoding circuit 111, MR13_OP0T, MR13_OP1B, and MR13_OP2B are inputted respectively through a three-input NAND gate, and MR13_OP3B is inputted through a NOT gate. Since the fourth-bit operation code MR13_OP3 is rarely used, it is taken out separately and is not involved in the calculation. However, two two-input NAND gates may also be used to input MR13_OP0T, MR13_OP1B, MR13_OP2B, and MR13_OP3B respectively. There is no specific limitation on this.

[0144] As shown in FIG11 , the second decoding circuit 112 includes nine frequency code signals TCCD_L_8, TCCD_L_9, TCCD_L_10, ..., TCCD_L_16, and three write preamble codes WPRE2, WPRE3, and WPRE4, resulting in a total of 27 initial control sub-signals, namely TCCD8_WPRE2, ..., TCCD16_WPRE2, TCCD8_WPRE3, ..., TCCD16_WPRE3, TCCD8_WPRE4, ..., TCCD16_WPRE4. For example, as shown in FIG11 , the frequency code signal TCCD_L_8 and the write preamble code WPRE2 are coupled together via a NAND gate and a NOT gate to generate the initial control sub-signal TCCD8_WPRE2. Alternatively, the initial control sub-signal TCCD8_WPRE2 can be derived via an AND gate, without specific limitation.

[0145] As shown in FIG11 , in the third decoding circuit 113 , 5 control sub-signals are obtained through 27 initial control sub-signals. Only one of the 5 control sub-signals is in a high-level state, that is, in an enabled state to control the aforementioned shift circuit 12 and determine from which level of the shift sub-circuit 121 the target command signal is output.

[0146] It should be noted that the third decoding circuit 113 corresponds to Table 2. As can be understood, since WPRE3 and WPRE4 have the same encoding, the input of the third decoding circuit 113 has both WPRE3 and WPRE4, which are then selected through the preset write preamble code in the shift subcircuit.

[0147] For example, as shown in FIG11 , taking the first sub-circuit in the third decoding circuit 113 as an example, in Table 2, when TCCD_L is 8 and 9, the shift amount under WPRE3 and WPRE4, that is, the Code value is X-2+2=X, so the initial control sub-signals input to the first sub-circuit in the third decoding circuit 113 are TCCD8_WPRE4, TCCD9_WPRE4, TCCD8_WPRE3 and TCCD9_WPRE3, respectively, and the output control sub-signal RMW_LT is <x>.

[0148] In addition, taking the second sub-circuit in the third decoding circuit 113 as an example, the control sub-signal is RMW_LT<X+2> , the shift amount is X+2. As shown in Table 2, when TCCD_L is 8 and 9, the shift amount under WPRE2 is X+2, and when TCCD_L is 10 and 11, the shift amounts under WPRE3 and WPRE4 are X-2+4=X+2. Therefore, the initial control sub-signals input to the second sub-circuit in the third decoding circuit 113 are TCCD8_WPRE2, TCCD9_WPRE2, TCCD10_WPRE3, TCCD11_WPRE3, TCCD10_WPRE4, and TCCD11_WPRE4, respectively, and the output control sub-signal RMW_LT is<X+2> .

[0149] That is, the decoding circuit 11 decodes MR13_OP[3:0] into a Code containing frequency information (i.e., a frequency code signal), combines the write preamble and the Code containing frequency information with logical processing to generate an initial control sub-signal, and finally encodes the Code with the write preamble information (i.e., the initial control sub-signal) into the control sub-signal RMW_LT according to the aforementioned Table 2. <x>~RMW_LT<X+8> .

[0150] Based on the aforementioned command timing control circuit 10, see Figure 12, which shows a timing diagram of RMW command signals at different frequencies provided by an embodiment of the present disclosure, specifically a diagram of the correct release of RMW command signals at different frequencies. As shown in Figure 12, regardless of whether it is a high-frequency or low-frequency case, the first RMW command signal obtained after the shift during the CWL period is shifted to the starting point of the RMW command signal (i.e., the point where the target command signal RMW_D is located) after coding control. At this time, the timing relationship between the shifted RMW command signal and the WCSL signal satisfies 5 to 6 ns, meeting the timing requirements.

[0151] In another embodiment of the present disclosure, referring to Figure 13, which shows a schematic diagram of the composition structure of a memory provided by an embodiment of the present disclosure, as shown in Figure 13, the memory 20 may include the command timing control circuit 10 according to any one of the aforementioned embodiments.

[0152] The memory 20 may be, for example, SRAM, DRAM, SDRAM, DDR SDRAM, etc., and is not specifically limited thereto.

[0153] Furthermore, in some embodiments, the memory 20 may include a DRAM chip. The DRAM chip may conform not only to memory specifications such as DDR, DDR2, DDR3, DDR4, DDR5, and DDR6, but also to memory specifications such as LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5, and LPDDR6, which are not specifically limited herein.

[0154] In the embodiment of the present disclosure, for the memory 20, the control signal obtained by decoding the frequency indication signal and the write preamble signal is used to shift the read-modify-write command signal to obtain the target command signal, so that the time interval between the target command signal and the write enable signal meets the preset timing conditions, so that the read-modify-write command signal can be generated at a reasonable time under different frequency values ​​and different write preambles, and each step of the read-modify-write operation can be carried out smoothly.

[0155] Details not disclosed in the embodiments of the present disclosure may be understood by referring to the description of the aforementioned embodiments.

[0156] The above description is merely a preferred embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure.

[0157] It should be noted that, in this disclosure, the terms "comprise," "include," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0158] The serial numbers of the above-mentioned embodiments of the present disclosure are for description only and do not represent the advantages or disadvantages of the embodiments.

[0159] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0160] The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0161] The features disclosed in several method or device embodiments provided in this disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0162] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.< / x> < / x> < / m>

Claims

1. A command timing control circuit (10), characterized in that: It comprises a decoding circuit (11) and a shift circuit (12), wherein: The decoding circuit (11) is used to receive a frequency indication signal and a write preamble signal, perform decoding processing according to the frequency indication signal and the write preamble signal, and generate a control signal (RMW_LT); the control signal indicates a first time length for shifting the read-modify-write command signal (RMW); The shift circuit (12) is used to receive the control signal and the read-modify-write command signal, shift the read-modify-write command signal by the first time length according to the control signal, and generate a target command signal (RMW_D), so that the time interval between the target command signal and the write enable signal (WCSL) meets a preset timing condition.

2. The command timing control circuit according to claim 1, characterized in that: The shift circuit comprises S cascaded shift subcircuits (121); the control signal comprises S control subsignals, and only one of the S control subsignals is in an enabled state, and S is an integer greater than 1; the input end of the first shift subcircuit is used to receive the read-modify-write command signal, the first output end of the i-th shift subcircuit is connected to the input end of the i+1-th shift subcircuit, and the control end of the i-th shift subcircuit is used to receive the i-th control subsignal, and i is an integer greater than 0 and less than S; wherein: The shift circuit is used to shift the read-modify-write command signal by the first time length through the 1st to the jth shift sub-circuit when the jth control sub-signal is in an enabled state, obtain the target command signal, and output the target command signal through the jth shift sub-circuit, where j is an integer greater than 0 and less than S.

3. The command timing control circuit according to claim 2, characterized in that: The clock terminal (CK) of each shift subcircuit (121) is used to receive a clock signal, and the shift subcircuit shifts the signal received at the input terminal based on the clock signal; wherein: When i is equal to 1, the first shift subcircuit shifts the read-modify-write command signal by 2 clock cycles or 1 clock cycle; When i is greater than 1, the 1st to i-1th shift subcircuits shift the signal received at the input end by 2 clock cycles, and the i-th shift subcircuit shifts the signal received at the input end by 2 clock cycles or 1 clock cycle; The clock period is the period of the clock signal.

4. The command timing control circuit according to any one of claims 1 to 3, characterized in that: encoding, according to the frequency value indicated by the frequency indication signal, a second time length compensated when the read-modify-write command signal is shifted; encoding, according to the write preamble signal, a third time length compensated when the read-modify-write command signal is shifted; Among them, the second duration is equal to A times the clock cycle, the third duration is equal to B times the clock cycle, and the first duration is related to the second duration and the third duration; A and B are both greater than 0, and A is less than B.

5. The command timing control circuit according to claim 2 or 3, characterized in that: The write preamble signal includes N write preambles, where N is an integer greater than 0; the frequency indication signal includes at least one operation code, where the at least one operation code corresponds to M logic combinations, where each logic combination corresponds to a frequency value, and M is an integer greater than 0; the decoding circuit (11) includes a first decoding circuit (111), a second decoding circuit (112), and a third decoding circuit (113); wherein: The first decoding circuit (111) is used to receive the at least one bit operation code and perform a first logic operation according to the at least one bit operation code. Processing is performed to generate M frequency code signals, wherein the M frequency code signals correspond to the M frequency values ​​one by one, and only one of the M frequency code signals is in an enabled state; The second decoding circuit (112) is used to receive the M frequency code signals and the N write preamble codes, and respectively perform AND logic processing on each frequency code signal and each write preamble code to generate M×N initial control sub-signals; The third decoding circuit (113) is used for receiving the M×N initial control sub-signals and performing OR logic processing on several of the M×N initial control sub-signals to generate S control sub-signals.

6. The command timing control circuit according to claim 3, characterized in that: The i-th shift subcircuit (121) comprises a first output circuit (1211), a second output circuit (1212), a control circuit (1213) and a selection circuit (1214), wherein: The first output circuit (1211) is used to shift the signal received at the input end by one of the clock cycles to generate a first shift amount signal (D1); wherein when i is equal to 1, the input end of the first output circuit receives the read-modify-write command signal, and when i is greater than 1, the input end of the first output circuit receives the signal output by the i-1th shift sub-circuit; The second output circuit (1212) is used to receive the first shift amount signal, shift the first shift amount signal by one of the clock cycles, and generate a second shift amount signal (D2); The control circuit (1213) is used to receive the second shift amount signal and the control sub-signal, and control whether to output the second shift amount signal to the (i+1)th shift sub-circuit according to the control sub-signal; The selection circuit (1214) is used to receive the first shift amount signal, the second shift amount signal, the control sub-signal and a preset write preamble code, and when the control sub-signal is in an enabled state, according to the preset write preamble code, select the first shift amount signal or the second shift amount signal to be output as the target command signal; the preset write preamble code instructs the i-th shift sub-circuit to shift the signal received at the input end by 2 clock cycles or 1 clock cycle.

7. The command timing control circuit according to claim 6, characterized in that: The first output circuit (1211) includes a first NOT gate (a1) and a first transmission circuit (a2), the second output circuit includes a second transmission circuit (a3) ​​and a second NOT gate (a4), the control circuit includes a first AND gate (a5), and the selection circuit includes a second AND gate (a6), a third AND gate (a7), a first OR gate (a8) and a fourth AND gate (a9), wherein: The input end of the first NOT gate (a1) is used as the input end of the shift sub-circuit (121); the output end of the first NOT gate (a1) is connected to the input end of the first transmission circuit (a2); the output end of the first transmission circuit (a2) is connected to the input end of the second transmission circuit (a3) ​​for outputting the first shift amount signal; The output end of the second transmission circuit (a3) ​​is connected to the input end of the second NOT gate (a4); the output end of the second NOT gate (a4) is connected to the first input end of the first AND gate (a5), and is used to output the second shift amount signal; The second input end of the first AND gate (a5) is used to receive the inverted control sub-signal, and the output end of the first AND gate (a5) serves as the first output end of the shift sub-circuit (121); The first input end of the second AND gate (a6) is used to receive the first shift amount signal, the second input end of the second AND gate (a6) is used to receive the preset write preamble code, and the output end of the second AND gate (a6) is connected to the first input end of the first OR gate (a8); the first input end of the third AND gate (a7) is used to receive the second shift amount signal, the second input end of the third AND gate (a7) is used to receive the inverted preset write preamble code, and the output end of the third AND gate (a7) is connected to the second input end of the first OR gate (a8); the output end of the first OR gate (a8) is connected to the first input end of the fourth AND gate (a9), and the second input end of the fourth AND gate (a9) is connected to the first input end of the fourth AND gate (a9). The end is used to receive the control sub-signal, and the output end of the fourth AND gate (a9) serves as the second output end of the shift sub-circuit; The inverted preset write preamble is obtained by inverting the preset write preamble, and the inverted control sub-signal is obtained by inverting the control sub-signal.

8. The command timing control circuit according to claim 7, characterized in that: The first transmission circuit (a2) includes a first transmission gate (u1) and a first drive circuit, the second transmission circuit (a3) ​​includes a second transmission gate (u2) and a second drive circuit, the first drive circuit includes a third NOT gate (u3), a fourth NOT gate (u4) and a third transmission gate (u5), the second drive circuit includes a fifth NOT gate (u6), a sixth NOT gate (u7) and a fourth transmission gate (u8), wherein: The output end of the first NOT gate (a1) is connected to the first end of the first transmission gate (u1); the input end of the third NOT gate (u3) and the second end of the third transmission gate (u5) are both connected to the second end of the first transmission gate (u1); the output end of the third NOT gate (u3) and the input end of the fourth NOT gate (u4) are both connected to the first end of the second transmission gate (u2); the output end of the fourth NOT gate (u4) is connected to the first end of the third transmission gate (u5); The input end of the fifth NOT gate (u6) and the second end of the fourth transmission gate (u8) are both connected to the second end of the second transmission gate (u2); the output end of the fifth NOT gate (u6) and the input end of the sixth NOT gate (u7) are both connected to the input end of the second NOT gate (a4); the output end of the sixth NOT gate (u7) is connected to the first end of the fourth transmission gate (u8).

9. The command timing control circuit according to any one of claims 1 to 8, characterized in that: The command timing control circuit also includes a command processing circuit, wherein: The command processing circuit is used to receive a write command signal, perform shift processing on the write command signal to obtain a shifted write command signal, and determine the first shifted write command signal during a column address strobe pulse write delay period as the read-modify-write command signal.

10. A memory (20), characterized in that: The memory comprises a command timing control circuit (10) as claimed in any one of claims 1 to 9.

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